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UCC20520
SLUSCN0 NOVEMBER 2016
UCC20520 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with Single Input
1 Features
3 Description
The UCC20520 is an isolated single input, dualchannel gate driver with 4-A source and 6-A sink
peak current. It is designed to drive power MOSFETs,
IGBTs, and SiC MOSFETs up to 5-MHz with best-inclass propagation delay and pulse-width distortion.
PACKAGE
DW SOIC (16)
16 VDDA
Driver
PWM
DIS
NC 2,7
DT
MOD
DEMOD
Reinforced Isolation
2 Applications
Disable,
UVLO
and
Deadtime
UVLO
15 OUTA
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
Driver
MOD
GND
DEMOD
UVLO
10 OUTB
VSSB
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC20520
SLUSCN0 NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
1
1
1
2
3
4
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
21
15
15
15
16
38
38
38
38
38
38
38
4 Revision History
DATE
REVISION
NOTES
November 2016
Initial Release.
UCC20520
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PWM
16
VDDA
NC
15
OUTA
VCCI
14
VSSA
GND
13
NC
DISABLE
12
NC
DT
11
VDDB
NC
10
OUTB
VCCI
VSSB
Not to scale
Pin Functions
PIN
NAME
DISABLE
NO.
5
I/O (1)
DESCRIPTION
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled
low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity.
Programmable dead time function.
Tying DT to VCCI disables the DT function with dead time 0ns. Leaving DT open sets the
dead time to <15 ns. Placing a 500- to 500-k resistor (RDT) between DT and GND adjusts
dead time according to: DT (in ns) = 10 x RDT (in k). It is recommended to parallel a
ceramic capacitor, 2.2nF or above, with RDT to achieve better noise immunity.
DT
GND
Primary-side ground reference. All signals in the primary side are referenced to this ground.
NC
No connection.
NC
No connection.
NC
12
No connection.
NC
13
No connection.
OUTA
15
Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase
with PWM input with a propagation delay
OUTB
10
Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always
complementary to output A with a programmed dead time.
PWM
PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if
left open.
VCCI
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
VCCI
VDDA
16
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
VDDB
11
Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL
capacitor located as close to the device as possible.
VSSA
14
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
UCC20520
SLUSCN0 NOVEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCCI to GND
0.3
20
VDDA-VSSA, VDDB-VSSB
0.3
30
0.3
VVDDA+0.3,
VVDDB+0.3
VVDDA+0.3,
VVDDB+0.3
0.3
VVCCI+0.3
VVCCI+0.3
VSSA-VSSB, VSSB-VSSA
(2)
1500
40
150
65
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
Electrostatic discharge
(1)
UNIT
4000
1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
MAX
UNIT
18
VCCI
VDDA,
VDDB
9.2
25
TA
Ambient Temperature
40
125
TJ
Junction Temperature
40
130
UCC20520
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DW-16 (SOIC)
UNIT
RJA
78.1
C/W
RJC(top)
11.1
C/W
RJB
48.4
C/W
JT
12.5
C/W
JB
48.4
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
PDI
PDA, PDB
VALUE
UNIT
1.05
0.05
0.5
UCC20520
SLUSCN0 NOVEMBER 2016
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VALUE
UNIT
TEST CONDITIONS
>8
mm
>8
mm
>21
> 600
CLR
CPG
External creepage
(1)
DTI
CTI
Material group
I-IV
I-III
AC voltage (bipolar)
2121
VPK
VIOWM
1500
VRMS
2121
VDC
VIOTM
VTEST = VIOTM
t = 60 sec (qualification)
t = 1 sec (100% production)
8000
VPK
VIOSM
8000
VPK
<5
qpd
<5
pC
test
(100%
production)
and
<5
RIO
1.2
> 1012
> 1011
> 109
Pollution degree
Climatic category
40/125/21
pF
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
UCC20520
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CSA
Certified according to
DIN VDE V 0884-10
(VDE V 0884-10):200612 and DIN EN 60950-1
(VDE 0805 Teil 1):201101
UL
CQC
Certified according to UL
1577 Component
Recognition Program
Reinforced Insulation
Maximum Transient
Isolation voltage, 8000
VPK; Maximum Repetitive Reinforced insulation per CSA 60950-107+A1+A2 and IEC 60950-1 2nd Ed.
Peak Isolation Voltage,
2121 VPK; Maximum
Surge Isolation Voltage,
8000 VPK
Reinforced Insulation,
Altitude 5000 m,
Tropical Climate,
400VRMS maximum working voltage
Certification number:
40040142
Certification number:
CQC16001155011
IS
TEST CONDITIONS
RJA = 78.1C/W, VDDA/B = 12 V, TA =
25C, TJ = 150C
TS
Safety temperature
MIN
TYP
MAX
UNIT
DRIVER A,
DRIVER B
64
mA
DRIVER A,
DRIVER B
31
mA
INPUT
50
DRIVER A
775
See Figure 3
DRIVER B
775
TOTAL
1600
See Figure 2
RJA = 78.1C/W, VDDA/B = 25 V, TA =
25C, TJ = 150C
PS
SIDE
150
mW
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a High-K test board for leaded surface mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
UCC20520
SLUSCN0 NOVEMBER 2016
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
DISABLE = VCCI
1.5
2.0
mA
IVDDA,
IVDDB
DISABLE = VCCI
1.0
1.8
mA
IVCCI
2.5
mA
IVDDA,
IVDDB
2.5
mA
2.55
2.7
2.85
VVCCI_OFF
2.35
2.5
2.65
VVCCI_HYS
Threshold hysteresis
0.2
VVDDA_OFF,
VVDDB_OFF
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
8
7.5
8.5
8.5
0.5
1.6
1.8
VPWML, VDISL
0.8
1.2
VPWM_HYS,
VDIS_HYS
Input hysteresis
VPWM
0.8
Not production tested, bench test
only
V
V
UCC20520
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IOA+, IOB+
IOA-, IOB-
ROHA, ROHB
ROLA, ROLB
0.55
VOHA, VOHB
11.95
VOLA, VOLB
5.5
mV
ns
15
ns
200
240
ns
Dead time
RDT = 20 k
160
TEST CONDITIONS
tRISE
COUT = 1.8 nF
tFALL
COUT = 1.8 nF
tPWmin
tPDHL
tPDLH
tPWD
tDM
f = 100 kHz
CMTI
MIN
TYP
MAX
16
ns
12
ns
20
ns
19
30
ns
19
30
ns
ns
ns
100
UNIT
V/ns
UCC20520
SLUSCN0 NOVEMBER 2016
www.ti.com
87.5%
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500
80
1800
70
60
50
40
30
20
10
0
1200
900
600
300
0
50
100
150
Ambient Temperature (qC)
200
D001
10
1500
50
100
150
Ambient Temperature (qC)
200
D001
UCC20520
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20
50
16
40
Current (mA)
Current (mA)
12
30
20
10
VDD=12v
VDD=25v
VDD= 12V
VDD= 25V
0
0
800
1600
2400
3200
Frequency (kHz)
4000
4800
5600
1000
1500
2000
Frequency (kHz)
2500
3000
D001
30
50kHz
250kHz
500kHz
1MHz
24
Current (mA)
500
D001
18
12
4
3
2
1
VDD= 12V
VDD= 25V
0
10
25
40
55
70
Frequency (kHz)
85
0
-40
100
20
1.6
1.8
1.2
0.8
0.4
40
60
80 100
Temperature (qC)
140
160
D001
1.6
1.4
1.2
VDD= 12V
VDD= 25V
0
-40
120
Current (mA)
Current (mA)
-20
D001
-20
20
40
60
80
Temperature (qC)
100
120
VCCI= 3.3V
VCCI= 5V
140
1
-40
-20
D001
20
40
60
80
Temperature (qC)
100
120
140
D001
11
UCC20520
SLUSCN0 NOVEMBER 2016
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10
20
8
Resistance (:)
Time (ns)
15
10
6
Output Pull-Up
Output Pull-Down
2
tRISE
tFALL
0
0
0
-40
10
Load (nF)
28
20
24
19
20
16
20
40
60
80
Temperature (qC)
12
140
D001
17
16
8
-40
-20
20
40
60
80
Temperature (qC)
100
120
140
12
15
VCCI (V)
D001
18
D001
5
Propagation Delay Matching (ns)
120
18
-1
-3
-5
-40
-20
20
40
60
80
Temperature (qC)
100
120
140
2.5
-2.5
Rising Edge
Falling Edge
-5
10
D001
12
100
-20
D001
13
16
19
VDDA/B (V)
22
25
D001
UCC20520
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530
2.5
Hysterisis (mV)
510
490
-2.5
470
Rising Edge
Falling Edge
-5
-40
-20
20
40
60
80
Temperature (qC)
100
120
450
-40
140
20
40
60
80
Temperature (qC)
100
120
140
D001
900
9
UVLO Threshold (V)
10
6
VVDDA_ON
VVDDA_OFF
5
-40
-20
20
40
60
80
Temperature (qC)
100
120
860
820
780
740
1.92
1.14
1.08
1.02
0.96
VCC=3.3V
VCC= 5V
VCC=12V
0
20
40
60
80
Temperature (qC)
100
120
140
20
40
60
80
Temperature (qC)
100
120
140
D001
-20
-20
D001
1.2
0.9
-40
VCC=3.3V
VCC=5V
VCC=12V
700
-40
140
-20
D001
1.84
1.76
1.68
1.6
-40
VCC=3.3V
VCC= 5V
VCC=12V
-20
D001
20
40
60
80
Temperature (qC)
100
120
D001
140
13
UCC20520
SLUSCN0 NOVEMBER 2016
www.ti.com
1500
1200
-6
900
-17
'DT (ns)
RDT= 20k:
RDT= 100k:
600
-28
-39
300
RDT= 20k:
RDT = 100k:
0
-40
-20
20
40
60
80
Temperature (qC)
100
120
-50
-40
140
-20
20
D001
40
60
80
Temperature (qC)
100
120
140
D001
18
14
Voltage (V)
10
6
2
-2
1 nF Load
10 nF Load
-6
0
100
200
300
400
500
Time (ns)
600
700
800
D001
14
UCC20520
www.ti.com
OUTA
90%
tPDHLA
tPDLHA
10%
90%
tPDLHB
tPDHLB
OUTB
80%
tRISE
90%
tFALL
20%
10%
PWM
DIS High
Response Time
DIS
DIS Low
Response Time
OUTA
90%
10%
10%
15
UCC20520
SLUSCN0 NOVEMBER 2016
www.ti.com
PWM
90%
OUTA
10%
tPDHL
90%
10%
OUTB
tPDHL
Dead Time
(with RDT1)
Dead Time
(with RDT2)
VDD
PWM
16
VCCI
GND
DIS
Input Logic
VCC
Reinforced Isolation
15
14
OUTA
OUTA
VSSA
Functional
Isolation
11
DT 6
VCCI
VDDA
10
VDDB
OUTB
OUTB
VSSB
GND
VSS
Common Mode Surge
Generator
Copyright 2016, Texas Instruments Incorporated
16
UCC20520
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8 Detailed Description
8.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC20520 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor
drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC20520 has many
features that allow it to integrate well with control circuitry and protect the gates it drives such as: resistorprogrammable dead time (DT) control, a DISABLE pin, and under voltage lock out (UVLO) for both input and
output voltages. The UCC20520 also holds its OUTA low when the PWM is left open or when the PWM pulse is
not wide enough. The driver input PWM is CMOS and TTL compatible for interfacing to digital and analog power
controllers alike. Importantly, Channel A is in phase with PWM input and Channel B is always complimentary with
Channel A with programmed deadtime.
16 VDDA
200 k:
MOD
VCCI
Driver
DEMOD
15 OUTA
UVLO
VCCI 3,8
4
DT
DIS
Reinforced Isolation
GND
UVLO
Deadtime
Control
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
200 k:
MOD
Driver
DEMOD
UVLO
PWM
10 OUTB
9
VSSB
NC 2,7
Copyright 2016, Texas Instruments Incorporated
17
UCC20520
SLUSCN0 NOVEMBER 2016
www.ti.com
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
18
UCC20520
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INPUT
OUTPUTS
PWM
OUTA
OUTB
INPUT
OUTPUTS
PWM
OUTA
OUTB
(1)
DISABLE
OUTPUTS
OUTA
OUTB
L or Left
Open
L or Left Open
L or Left Open
NOTE
Output transitions occur after the dead time expires. See Programmable
Dead Time (DT) Pin
-
19
UCC20520
SLUSCN0 NOVEMBER 2016
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VDD
ROH
Input
Signal
ShootThrough
Prevention
Circuitry
RNMOS
OUT
Pull Up
ROL
VSS
20
UCC20520
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VDDA
3,8
16
30 V
20 V
PWM
DIS
DT
20 V
30 V
GND
VSSB
15
OUTA
14
VSSA
11
VDDB
10
OUTB
21
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DT
OUTA
OUTB
Figure 33. Input and Output Logic Relationship with Dead Time
22
UCC20520
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VDD
VCC
HV DC-Link
RIN
PWM
CIN
VCCI
CVCC
PC
GND
Analog
or
Digital
DIS
Disable
RDIS
DT
2.2nF
16
15
14
VDDA
ROFF
RON
OUTA
CBOOT
SW
Functional
Isolation
VDD
11
10
VDDB
ROFF
RON
OUTB
CVDD
RDT
VCCI
CIN
RGS
VSSA
Reinforced Isolation
PWM
Input Logic
VCC
RBOOT
VSSB
RGS
9
VSS
23
UCC20520
SLUSCN0 NOVEMBER 2016
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VALUE
UNITS
Power transistor
C2M0080120D
VCC
5.0
VDD
20
0 3.3
100
kHz
DC link voltage
800
24
(2)
UCC20520
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2.
Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3.
Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4.
As mentioned in Output Stage, the UCC20520 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:
VDD VBDF
min 4A,
IOA
VDD
min 4A,
IOB
(3)
RGFET _ Int
where
In this example:
VDD VBDF
RNMOS || ROH RON RGFET _ Int
IOA
IOB
RNMOS || ROH
VDD
RON
RGFET _ Int
20V 0.8V
| 2.4A
1.47: || 5: 2.2: 4.6:
(5)
20V
1.47: || 5: 2.2:
(6)
4.6:
| 2.5A
Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
IOA
min 6A,
ROL
IOB
(7)
VDD VGDF
where
25
UCC20520
SLUSCN0 NOVEMBER 2016
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In this example,
IOA
ROL
IOB
ROL
(9)
(10)
Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
9.2.2.4 Estimate Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC20520 (PGD) and the power
losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in
PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC20520, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. Figure 4 shows the per output channel current consumption vs. operating frequency with
no load. In this example, VVCCI = 5 V and VVDD = 20 V. The current on each power supply, with PWM switching
from 0 V to 3.3 V at 100 kHz is measured to be IVCCI = 2.5 mA, and IVDDA = IVDDB = 1.5 mA. Therefore, the PGDQ
can be calculated with
PGDQ
VVCCI u IVCCI
VVDDA u IDDA
(11)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW
2 u VDD u QG u fSW
where
(12)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:
PGSW
26
240mW
(13)
UCC20520
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QG represents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change
with different testing conditions. The UCC20520 gate driver loss on the output stage, PGDO, is part of PGSW. PGDO
will be equal to PGSW if the external gate driver resistances are zero, and all the gate driver loss is dissipated
inside the UCC20520. If there are external turn-on and turn-off resistance, the total loss will be distributed
between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-up/down
resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be
non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
ROH || RNMOS
PGSW u
R || R
RON RGFET _Int
NMOS
OH
PGDO
ROL
ROL
R OFF || R ON
R GFET _Int
(14)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC20520
gate driver loss can be estimated with:
5: || 1.47:
240mW u
5: || 1.47: 2.2: 4.6:
PGDO
0.55:
| 60mW
0.55: 0: 4.6:
(15)
2 u fSW
PGDO
TR _ Sys
u 4A u VDD
0
TF _ Sys
VOUTA/B t dt
6A u
VOUTA/B t dt
where
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(16)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pulldown based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC20520,
PGD, is:
PGD
PGDQ
PGDO
(17)
TJ
TC
R TJC u PGD
where
TC is the UCC20520 case-top temperature measured with a thermocouple or some other instrument, RJC is
the Junction-to-case-top thermal resistance from the Thermal Information table. Importantly, RJA, the junction
to ambient thermal impedance provided in the Thermal Information table, is developed based on JEDEC
standard PCB board and it is subject to change when the PCB board layout is different.
(18)
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A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 F, should be placed in parallel with the MLCC.
9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
QTotal
QG
60nC
1.5mA
100kHz
75nC
where
(19)
QTotal
'VVDDA
CBoot
75nC
0.5V
150nF
where
(20)
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-F capacitor is chosen in this example.
CBoot
1 )
(21)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
NOTE
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and
VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal
command. Also during initial CBOOT charging cycles, the bootstrap diode has highest
reverse recovery current and losses.
28
UCC20520
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Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in
Figure 34) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current
for VDDA through the bootstrap diode. A 50-V, 10-F MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If
the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor,
with a value over 10 F, should be used in parallel with CVDD.
9.2.2.7 Dead Time Setting Guidelines
For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor
is important for preventing shoot-through during dynamic switching.
The UCC20520 dead time specification in the electrical table is defined as the time interval from 90% of one
channels falling edge to 10% of the other channels rising edge (see Figure 28). This definition ensures that the
dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.
However, this dead time setting may not reflect the dead time in the power converter system, since the dead time
setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as well as
the input capacitance of the load transistor.
Here is a suggestion on how to select an appropriate dead time for UCC20520:
DTSetting
DTReq
TF _ Sys
TR _ Sys
TD on
where
(22)
29
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SLUSCN0 NOVEMBER 2016
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15
VDDA
ROFF
CA1
RZ
OUTA
25 V
+
VA
RON
CIN
Input Logic
Reinforced Isolation
CA2
VSSA
14
VZ = 5.1 V
SW
Functional
Isolation
11
10
VDDB
OUTB
VSSB
Figure 35. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
30
UCC20520
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Figure 36 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
16
15
VDDA
CA1
OUTA
Input Logic
Reinforced Isolation
CA2
VSSA
14
HV DC-Link
ROFF
+
VA+
RON
CIN
+
VA
Functional
Isolation
SW
11
10
VDDB
OUTB
VSSB
31
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The last example, shown in Figure 37, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and
the bootstrap power supply can be used for the high side drive. This design requires the least cost and design
effort among the three solutions. However, this solution has limitations:
1.
The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias
voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency
resonant convertors or phase shift convertors which favor this solution.
2.
The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side
switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to
refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply
for the high side, like in the other two example circuits.
VDD
RBOOT
HV DC-Link
1
16
15
VDDA
Reinforced Isolation
Input Logic
VZ
OUTA
ROFF
RON
CBOOT
VSSA
3
CZ
RGS
14
SW
Functional
Isolation
VDD
11
10
VDDB
CZ
VZ
OUTB
ROFF
RON
CVDD
8
CIN
VSSB
RGS
9
VSS
Figure 37. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
32
UCC20520
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33
UCC20520
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34
UCC20520
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11 Layout
11.1 Layout Guidelines
One must pay close attention to PCB layout in order to achieve optimum performance for the UCC20520. Below
are some key points.
Component Placement:
Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the
source of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to place the dead time setting resistor, RDT, and its bypassing capacitor close to DT pin of
UCC20520.
Grounding Considerations:
It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSBreferenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
High-Voltage Considerations:
To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination
that may compromise the UCC20520s isolation performance.
For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could
operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB
layout between the high and low-side PCB traces.
Thermal Considerations:
A large amount of power may be dissipated by the UCC20520 if the driving voltage is high, the load is heavy,
or the switching frequency is high (Refer to Estimate Gate Driver Power Loss for more details). Proper PCB
layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance
(JB).
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended (See
Figure 41 and Figure 42). However, high voltage PCB considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind
that there shouldnt be any traces/coppers from different high voltage planes overlapping.
35
UCC20520
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36
UCC20520
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Figure 43 and Figure 44 are 3D layout pictures with top view and bottom views.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
37
UCC20520
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12.2 Certifications
UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate
Number: 20160516-E181974, (SLUQ001)
VDE Online Certifications Directory, "Certificate of Conformity with Factory Surveillance" Certificate Number:
40040142
CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate Number:
CQC16001155011
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
www.ti.com
17-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
UCC20520DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC20520
UCC20520DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC20520
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
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17-Nov-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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