Analog IC Design

Chapter 3. Single-Transistor Primitives

Outline
3.1. Two-Port Models
3.2. Frequency Response
3.3. Signal Flow
3.4. Common-Emitter/Source Transconductor
3.5. Common-Base/Gate Current Buffer
3.6. Common-Collector/Drain Voltage Follower
3.7. Summary

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Analog IC Design

3.1. Two-Port Models: Philosophy and Extraction

Purpose:

Model a device or complicated circuit with simple unloaded

two-component networks that can predict loaded response.

Philosophy: Avoid model redundancies.

Two-Port Models

with orthogonal components.

Extraction: When deriving a parameter,
nullify the effects
of the other.
Norton Equivalent:

Derive gain ANI when iR = 0 vN = 0: Short terminals.

Derive resistance RP when control signal sC = 0.

Thvenin Equivalent: Derive gain ATV when vR = 0 iR = 0: Remove load.

Derive resistance RS when control signal sC = 0.

Examples
Sample InputOutput Model

Sample Model:

Popular InputOutput Model

Derive RIN when iO = 0 Remove load.

Derive AG when iRIN = 0 vIN = 0: Short input.
Derive AV when vRO = 0 iO = 0: Remove load.
Derive RO when vIN = 0 Short input.

Popular Model:

Derive RIN as is No redundancies to consider.

Derive GM when iRO = 0 vO = 0: Short output.
Derive RO when vIN = 0 Short input.

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Analog IC Design

3.2. Frequency Response: A. Pole

Pole Signal decays (i.e., loses energy) as operating frequency climbs.
Parallel capacitors shunt energy away from nodes.
CSH shunts energy when 1/sCSH falls below parallel RSH, past pole pC.
!
i IN R SH
1 $
i R
v O = i IN # R SH ||
= IN SH
&=
s
sC
1+
sR
C
"
SH %
SH SH
1+
2p C

1
sCSH

f=

2R SH CSH

= R SH
pC

Capacitor voltage changes slowly.

Poles delay signals 0 to 90.
Lagging delay between two sinusoids
amounts to negative phase shift.
" f %
Phase Pole = tan 1 $ ' 0 to 90.
# pC &

Since ZC = 1/sCEQ 1/f, gain drops linearly with frequency.

Gain falls 10 with a 10 rise in frequency, which equates to 20 dB per decade.

B. Zeros: i. Feed-Forward Zeros

Zero Signal rises (i.e., gains energy) as frequency climbs Opposite of pole.
A feed-forward capacitor CFF:
Steers energy away from input vIN Contributes to input pole pIN.
Adds energy to output vO Introduces feed-forward zero zFF when iFF iGM.
Short-circuit transconductance (when vO = 0) incorporates a zero zFF:
i FF =

v IN v O
ZC

= v INsC FF
v O =0

z FF =

GM
2CFF

= i GM i RO

v O =0

= i GM = v IN G M

Since ZC = 1/sCEQ 1/f, gain climbs linearly with frequency.

Gain rises 10 with a 10 rise in frequency, which equates to +20 dB per decade.

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Analog IC Design

In-phase feed-forward capacitors do not oppose the amplifier.

Zero zLHP removes the effects of a pole Recovers 090 Left-half plane.
" f %
Phase LHP Zero = tan 1 $
'
# z LHP &

" f %
Phase RHP Zero = tan 1 $
'
# z RHP &

Out-of-phase feed-forward capacitors oppose the amplifier 180 = 90 (090).

Zero zRHP subtracts 090 Normally undesirable Right-half plane.

ii. Current-Limiting Zero

At Low Frequency: CSHUNT is open iO = iIN and vO = iINRO Flat response.

At Higher Frequency: CSHUNT shunts current energy away from RO.
iO and therefore vO drop past pole pSHUNT when 1/sCSHUNT RO + RLIMIT.
At High Frequency: Series RLIMIT limits CSHUNT's shunting current,
RLIMIT arrests (i.e., removes) the effects of pSHUNT past in-phase zero zLIMIT
when 1/sCSHUNT RLIMIT Response flattens to vO = iIN(RO || RLIMIT).
1
sCSHUNT

f=

2R LIMIT CSHUNT

= R LIMIT
z LIMIT

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Analog IC Design

C. Miller Split

iFF zRHP
C MI = (1+ A V ) C M A VC M
!
1 $
C MO = ##1+
&& C M C M
" AV %

As vIN rises, vO falls more vIN vO rises more than vIN:

(vIN vO)CM demands more current than vINCM, like higher capacitance would.
Z MI

v IN
v IN
v IN
1
1
=
=
=

iC ( v IN v O ) sC M ( v IN + v IN A V ) sC M s (1+ A V ) C M sC MI

vO rises when vIN hardly falls vO vIN rises nearly as much as vO.
(vO vIN)CM demands nearly as much current as vINCM.
Z MO

vO
vO
vO
1
1
=
=
=

#
sC MO
iC ( v O v IN ) sC M #
1 &
vO &
% vO +
( sC M s %1+
( CM
AV '
$
$ AV '

D. Analysis: Capacitors Shunt Resistors

Capacitors open at low frequencies: Capacitors are absent at low frequencies.
Capacitors shunt resistors past their 1/2REQCEQ frequencies.
Capacitors replace resistors Resistors disappear.
The lowest-frequency shunt corresponds to the highest REQCEQ product.
Note: Off-chip, intentional, load, and C/GS capacitors normally shunt first.
Frequency-Response Analysis
Low-frequency gain A0: Exclude all capacitors to determine A0.
f1: Determine which capacitor shunts its parallel resistance first.
Find highest REQCEQ when all other capacitors are still open.
f2: Replace REQ1 with CEQ1 and find the next highest REQCEQ.
fN: If N REQCEQ's are close, N capacitors short near fN

Page 5

1
.
2 Avg ( R EQ C EQ )

Analog IC Design

3.3. Signals and Terminals

Signal Composition
Bias (i.e., dc, steady state): All upper-case variables IC, VDS, etc.
Small-Signal Variations: All lower-case variables id, vbe, etc.
Entire Signal: Lower-case variables with

BJT

upper-case subscripts iS, vD, etc.

Terminal Roles in Transistors:
Bases and gates carry little to no current Bad outputs.
Collectors, emitters, drains, and sources carry almost
all the current: iC iE and iD = iS Good outputs.

MOS

iC/E and iD/S are sensitive to vBE and vGS.

Bases, emitters, gates, and sources are good inputs.
iC/E and iD/S are insensitive to vC and vD.
Collectors and drains are bad inputs.

A. Possible Transistor Configurations

Note common terminal is unused small-signal terminal.
Common Emitter/Source

Common Collector/Drain

Base and gate are bad outputs When in use, they should be inputs.

Common Base/Gate
Collector and drain are bad inputs When in use, they should be outputs.

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Analog IC Design

B. Signal Flow
Possible Signal-Flow Paths
Base Input: Higher vB (+) raises vBE iC rises (+) iC lowers vC () and raises vE (+).

Emitter Input: Lower vE () raises vBE iC rises (+) iC lowers vC ().

Polarity: Base/gate to emitter/source In phase.
Emitter/source to collector/drain In phase.
Base/gate to collector/drain Out of phase Only one that inverts.

3.4. Transconductor: A. Large-Signal Operation

Common-Emitter and -Source Configurations
Supply voltage VBIAS is constant.

VO(MAX) vCC VEC(MIN) or vDD because iD 0 and VO(MIN) = VCE(MIN) or IBIASRTRIODE.

ISOURCE(MAX) IBIAS

IPULL(MAX) = f(iB or vGST) IBIAS

Depends on bias.

Depends on base or gate drive and bias.

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Analog IC Design

B. Small-Signal Model
Equivalent Low-Frequency Two-Port Models

BJT

MOS

RIN:

r = 0/gm

RO when vin = 0:

ro = VA/IC

rds = 1/ID

GM when vo = 0:

gm = IC/Vt

gm = sqrt (2IDK'W/L)

Voltage Gain: A V0

v o v in G M ( R O || R LOAD )
=
= g m ( ro || R LOAD ) 50100 V/V
v in
v in

Example
Signal Propagation
v IN i D1 v O1 iC2 v O2 = v in id1 v o1 ic2 v o2

A V0

v o2 " i d1 %" v o1 %" i c2 %" v o2 %

= $ '$ '$ '$ '
v in $# v in '&$# i d1 '&$# v o1 '&$# i c2 '&

)(

)(

)(

= G M(CS) R O(CS) || R D1 || R IN(CE) G M(CE) R O(CE) || R C2

)(

)(

)(

= g m1 rds1 || R D1 || r2 g m2 ro2 || R C2

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Analog IC Design

C. Frequency Response
Wide-Spectrum Model

Load

Load

Source

Source

C feed-forwards energy to vo to produce a zero.

iC opposes igm Out of Phase In the right-half plane.
zRHP Location: When short-circuit gm inverts When iC igm.
When iC = igm, so vce = 0 and ro's and ZLOAD's currents = 0.
iC = ( v be v ce ) sC = ( v be 0 ) sC z

RHP =

gm
2C

igm + i ro ||Z LOAD = igm = v beg m

gm
Current

Feed-Forward
Current

CS, C, C and C, CLOAD shunt energy from vin and vo to establish poles.
Miller Split: Decompose C into CMI and CMO.
C MI = (1+ A V ) C = !"1+ G M ( R O || R LOAD )#$ C
'
*
!
1 $
1
C MO = #1+
, C
& C = )1+
)( G M ( R O || R LOAD ) ,+
" AV %

Case 1. If RS RLOAD ro and CLOAD C: RCICI is the highest REQCEQ.

First pole occurs when CI shunts RCI, when 1/sCI RCI.
1
s (CS + C + C MI ) p

IN =

1
2(CS +C +C MI )( R S ||R IN )

Page 9

R S || R IN

Analog IC Design

Past pIN, CS + C + CMI shunt and replace RS and RIN RS and RIN disappear.
1
1

#
%
s
C
+ C
s C LOAD + $C CS + C &
LOAD

)} (

( G C
+
M
*
* C +C +C ) S ,
pO
2 CLOAD +C

R GM || R O || R LOAD

iGM is a linear translation of vo.

R GM

(CS + C ) + C
G M C

vo
vo
vo
(C + C ) + C
=
=
= S
#
&
iGM # v o ( Z S || Z ) &
G M C
C
%
(G M vo %
(G M
Z
+
Z
||
Z
C
+
C
+
C
%$ ( S ) ('
$% ( S
'
)
(

Where GM is gm and RGM is moderately greater than 1/GM.

If C' CC + C >> CS + C C' shorts RGM 1/GM.

Case 2. If RS 1/gm, RLOAD ro, and CLOAD C: RCOCO can be the highest REQCEQ.
First pole occurs when CO shunts RCO, when 1/sCO RCO.
1
s (C MO + C LOAD ) p

O'

R O || R LOAD

2( R O ||R LOAD )(C MO +C LOAD )

Past pO', CMO + CLOAD shunt and replace RO and RLOAD RO and RLOAD disappear.
1
1

#
%
s
C
+
C
s$CS + C + (C C LOAD )&
( S + C )

Page 10

p IN'

1
2(CS +C +C )( R S ||R IN )

R S || R IN

Analog IC Design

Example
Objective: If RS = 100 k, vBS = 0, IC = ID = 25 A, 0 = 100, KN' = 100 A/V2,
VA = 1/ = 50 V, C = CGS = 100 fF, C = CGD = 10 fF, W = 20 m, L = 2 m,
RL = 100 k, and CL = 200 fF, determine AV0, fT, pIN, pO, and zRHP.
Solution:
BJT

gm = 980 S, 1/gm = 1.0 k, r = 100 k, and ro = 2 M.

AV0 93 V/V and fT 1.4 GHz.
CMI 930 fF CIN = CMI + C = 1 pF.
pIN 3.2 MHz, pO 77 MHz, and zRHP 1.4 GHz.

MOS

gm = 224 S, 1/gm = 4.5 k, and rds = 2 M.

AV0 21 V/V and fT 320 MHz.
CMI 220 fF CIN = CMI + CGS = 320 fF.
pIN 5.0 MHz, pO 23 MHz, and zRHP 324 MHz.

BJT's r shunts RS and higher gm raises CMI in pIN, so BJT's pIN MOS's pIN.

D. Emitter and Source Degeneration

Resistance RDEG in series with emitter and source.

RDEG raises input resistance RIN.

RDEG raises output resistance RO.
vbe and vgs drop a fraction of vin RDEG degenerates gm.

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Analog IC Design

i. Small-Signal Model
BJT:
GM when vo = 0 RDEG || ro.
v be g m

ve
ro

v be g m

v be g m R DEG || ro

ro
i
GM
o =

v =0
v in
v be + v e
v be + v be g m R DEG || ro

!
$
ro
g m ##
&&
" ro + R DEG %
=
=
1+ g m R DEG || ro

)
igm >> iro

gm
gm

gm
!1
$
1+ g m R DEG
1+ ## + g m && R DEG
" ro
%

igm >> i
Where

"1
%
v e = v be $ + g m ' ( R DEG || ro ) v beg m ( R DEG || ro )
# r
&

BJT:

igm >> iro

R IN =

RDEG reduces GM.

( )

#
%
v in v be + v e i b r + i e R DEG i b r + $i b + i b r g m & R DEG
=

= r + 1+ r g m R DEG
i in
ib
ib
ib

RO when vin = vb = 0 RDEG || r.

RO v

in =0

v o ( io + v eg m ) ro + v e #$io + io ( R DEG || r ) g m %& ro + io ( R DEG || r )

=
=
io
io
io
50100

= ro + g m ro ( R DEG || r ) + ( R DEG || r )

RDEG raises RIN and RO.

Voltage gain from equivalent two-port model:
A V0

When RO >> RLOAD.

'
v o v in G M ( R O || R LOAD ) $ g m
=
&
) R LOAD
v in
v in
% 1+ g m R DEG (

Page 12

Analog IC Design

MOS: Remove r and include gmb, where vbs = vs.

RIN
GM when vo = 0: igmb = vsgmb vs/RGMB.
1/gmb shunts rds.
igm, igmb >> iro
GM

v o =0

io
=
v in

gm
gm
gm

(" 1
+
%
1+ g mb + g m R DEG
1+ *$$ + g mb '' + g m - R DEG
*)# rds
-,
&

gmb reduces GM.

RO without r when vin = vg = 0 vgs = vs = vbs gm eff = gm + gmb.
R O = rds + (g m + g mb ) rds R DEG + R DEG

Example
Signal Propagation: v IN v B iC v O = v in v b ic v o
A V0

" 1 %
r
v o " v b %" ic %" v o %
'' ( rds(PL) ) ds(PL)
= $ '$ '$ ' (1) $$
v in # v in &# v b &# ic &
rds(ND)
# rds(ND) &

r + (1+ g m r ) R D
R IN(DCE)
vb
=

v in R S + R IN(DCE) R S + r + (1+ g m r ) R D

=
ic
G M(DCE)
vb

r + 1+ g m r rds(ND)

R S + r + 1+ g m r rds(ND)

0 rds(ND)
R S + 0 rds(ND)

g m
g m
1
=

$
$
rds(ND)
1'
1'
1+ & g m + ) R D 1+ & g m + ) rds(ND)
ro (
ro (
%
%

If RIN(DCE) >> RS.

vo
R L || R O(DCE) = rds(PL) || #$ro + g m ( r || R D ) ro + ( r || R D )%& rds(PL) || 0 ro rds(PL)
ic

Page 13

Analog IC Design

3.5. Current Buffer: A. Large-Signal Operation

Common-Base and -Gate Configurations: Notice iO iIN Current buffer.
Supply voltage VBIAS P is constant.

VO(MAX) vCC VEC(MIN) or vDD because iIN 0.

VO(MIN) = vIN + VCE(MIN) or vIN + iINRTRIODE.
ISOURCE(MAX) IBIAS

IPULL(MAX) = iIN(MAX) IBIAS f(VBIAS N vIN(MIN) and vBS)

Depends on bias.

Depends on input drive and bias.

Raising iIN corresponds to lowering vIN.

B. Small-Signal Model

v e = ( i i v eg m ) ro + i i R LOAD

" r + R LOAD % 1
R IN = r || R I = r || $ o
'>
# 1+ g m ro & g m
v r + R LOAD 1
>
RI e = o
1/gm if RLOAD << ro.
gm
ii
1+ g m ro

Non-degenerated
CE Load

RLOAD
Cases

Degenerated
CE Load

Equivalent Low-Frequency
Two-Port Model

ii

BJT

High

Bulk effect shifts vT.

RI =

RI =

ro + R LOAD
1+ g m ro

ro + R LOAD
1+ g m ro

R LOAD =ro

2
Still Low
gm
Moderate to High

R LOAD g m ro ( r ||ro )

g m ro ( r || ro )
r || ro r
1+ g m ro

RIN is a loaded 1/gm resistance Often near 1/gm << r << ro and generally low.

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Analog IC Design

RO when vin = 0 vegm = 0 and RO = ro.

GM when vo = 0:
"v %
v eg m + $ e '
i
1
# ro &
G M v =0 o =
= gm + gm
o
ro
v in
ve

MOS: Remove r and include gmb.

Same, but since vg = 0, vgs = vbs = vs.
gm eff = gm + gmb

Gains:
A V0

A I0

i gm
i in

v o v in G M R O || R LOAD "
1%
=
= $$ g m + '' ro || R LOAD
ro &
v in
v in
#

)
"r +R
%,"
" v %" i %
1%
LOAD
= $$ in ''$$ gm '' = R S || R IN G M = +R S || r || $$ o
''.$$ g m + '' 1
ro &
+*
# i in &# v in &
# 1+ g m ro &.-#

A R0

v o " i gm %" v o % (
= $ '$ ' = R || R IN G M *+ R O || R LOAD ro || R LOAD
i in $# i in '&$# i gm '& ) S

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Analog IC Design

Example
Approach: Using two-port models.
Signal Propagation:
i IN v G i D v E iC v O = i in v g id v e ic v o
A R0

v o " vg %" id %" v e %" ic %" v o %

= $ '$ '$ '$ '$ '
i in # i in &$# v g '&# id &# v e &# ic &

" r
+ RL %
v e id ( rds(CS) || R IN(CB) )
''
=
= rds(CS) || r(CB) || $$ o(CB)
id
id
# 1+ g m(CB)ro(CB) &
" r
%
+r
2
= rds(CS) || r(CB) || $$ o(CB) ds(PL) ''
# 1+ g m(CB)ro(CB) & g m(CB)
# 2 &#
1 &
((%% g m(CB) +
( ( ro(CB) || R L ) = 2R Sg m(CS) ( ro(CB) || rds(PL) )
A R0 ( R S ) (g m(CS) ) %%
ro(CB) ('
$ g m(CB) '$

i. Direct Translation
Norton two-port models are short-circuit translations.
Direct translations do not impose test conditions.
Direct translations for the current buffer:
(
" r + R LOAD %+
v in = v e = i in R IN(EQ) = i in ( R S || r || R GM(LD) ) = i in *R S || r || $ o
'# 1+ g m ro &,
)

Of RS, r, and RI, only RI's current io reaches RLOAD.

io = ic =

! 1+ g m ro $
ve
= ve #
&
R GM(LD)
" ro + R LOAD %

ic = igm + iro ic flows through RLOAD.

v o = v c = ic R LOAD

! 1 $
! v $! i $! v $
&& R LOAD
A R0 = # in &# o &# o & = ( R S || r || R GM(LD) ) ##
" i in %" v in %" io %
" R GM(LD) %

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Analog IC Design

C. Frequency Response
CI CS || C
RCI RS || RIN

Wide-Spectrum Model

Load
CO C || CLOAD
RCO RLOAD || RC

Source

Note: Equivalent shunt resistances do not correspond to short-circuit resistances.

RC Dominance: Equivalent C's, but RCO >> RCI Loaded 1/gm pO << pIN.
Response: C and CLOAD shunt energy from vo to establish output pole pO.
1
s C + C LOAD

R C || R LOAD = #$ro + g m ( r || R S ) ro + ( r || R S )%& || R LOAD

pO =

1
2 R C ||R LOAD C +CLOAD

)(

RC is equivalent shunt resistance,

not short-circuit output resistance.

CS and C shunt energy from vin to establish input pole pIN.

1
s ( CS + C ) p

IN

1
#
1 &
2% R S || ((CS +C )
gm '
$

# r + Z LOAD &
1
R S || R IN = R S || r || % o
( R S ||
gm
$ 1+ g m ro '

But since pO << pIN RLOAD disappears near pIN.

Z LOAD

1
<< R LOAD
s (C + C LOAD )

Base Degeneration: With resistance RB in series with the base,

vbe drops an r fraction of vin RB base-degenerates ve's gm.
gm' is a voltage-divided translation of gm: g m' =

Page 17

g mr
< gm .
r + R B

Analog IC Design

Example
Objective: If RS = 100 k, vBS = 0, IC = ID = 25 A, 0 = 100, KN' = 100 A/V2,
VA = 1/ = 50 V, C = CGS = 100 fF, C = CGD = 10 fF, W = 20 m, L = 2 m,
RL = 100 k, and CL = 200 fF, determine AI0, pO, and pIN.
Solution:
gm = 980 S, 1/gm = 1.0 k, r = 100 k, and ro = 2 M.

BJT

Shunt collector resistance RC(DEG) 100 M.

AI0 +0.98 A/A, pO 7.6 MHz, and pIN 1.6 GHz.
MOS

gm = 224 S, 1/gm = 4.5 k, and rds = 2 M.

Shunt drain resistance RD(DEG) 45 M.
AI0 +0.96 A/A, pO 7.6 MHz, and pIN 370 MHz.
RS and r steer current away from input.

Dominant low-frequency pole is usually at the output.

3.6. Voltage Follower: A. Large-Signal Operation

Common-Collector and -Drain Configurations

VBIAS is constant.
VO(MIN) = VCE(MIN) or zero

and

VO(MAX) BJT = vIN vBE.

Note Bulk Effect in vTN: VO(MAX) MOS = vIN vGS = vIN [vTN(f(vBS)) + VDS(SAT)]
ISOURCE(MAX) = f(iB or vIN vO and vBS) IBIAS

IPULL(MAX) IBIAS

Depends on base and gate drive and bias.

Depends on bias.

Since IBIAS is nearly constant, vBE is constant vO "follows" vIN Voltage Follower.

Page 18

Analog IC Design

B. Small-Signal Model

Equivalent Two-Port Model

BJT
MOS and BJT are similar, but r is absent and 1/gmb shunts ro.
vbs = vs = vo R GMB

vo
vo
1
=
=
i gmb v o g mb g mb

RIN: RLOAD || ro raises RIN like degenerating RDEG in CE BJT.

R IN = R B(DEG) = r + (1+ g m r ) ( R LOAD || ro )

GM when vo = 0 iro = iLOAD = 0.

v be
+ v beg m
i
1
r
G M v =0 = o =
= + gm gm
o
r
v in
v be

RO when vin = 0 Unloaded and undegenerated 1/gm.

vE vBE igm Large iE Low RO.
And
RO

v in =0

Where
R GM =

= ro || R GM || r = ro ||

1
1
|| r
gm gm

vo
ve
v
1
=
= e =
i gm v be g m v eg m g m

Voltage Gain:
A V0

&
#
v o v in G M R O || R LOAD #
1 &#
1
1 &
=
= %% g m + ((%% ro ||
|| r || R LOAD (( g m %% R LOAD || ((
r '$
gm
gm '
v in
v in
'
$
$

Page 19

Analog IC Design

Example
Approach: Using two-port models.
Signal Propagation:
i IN v B i E v O = i in v b ie v o
A R0

v o " v b %" i e %" v o %

= $ '$ '$ '
i in $# i in '&$# v b '&$# i e '&

vb
= R S || R IN(CC) = R S || "#r + (1+ g m r ) ( R L || ro )$% = R S || "#r + (1+ 0 ) ( rds(NL) || ro )$% R S
i in
ie
1
G M(CC) = + g m g m
r
vb

If RS << RIN(CC).

"
%
vo
1
1
= R O(CC) || R L = $$ r ||
|| ro '' || rds(NL)
g
g
ie
#
&
m
m
A R0

" 1 %
v o " v b %" i e %" v o %
= $ '$ '$ ' R S g m $$ '' R S
i in $# i in '&$# v b '&$# i e '&
# gm &

( )( )

i. Direct Translation
A voltage follower outputs ie io = ie.
Current vbe/r reinforces vbegm gm(EFF) = 1/r + gm.
RLOAD degenerates gm(EFF) GM(DEG) = GM(DCE) with gm(EFF).
ie
= G M(DEG) =
vb

g m(EFF)

!
1$
1+ # g m(EFF) + & R LOAD
ro %
"

1
+ gm
r
=
!1
1$
1+ # + g m + & R LOAD
ro %
" r

ie = ir + igm + iro = ir + ic flows through RLOAD.

v o = v e = ie R LOAD

,
)
1
.
+
+ gm
v
r
.R
A V0 o = G M(DEG) R LOAD = +
. LOAD
+ #1
v in
1&
+1+ % + g m + ( R LOAD .
ro '
* $ r

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Analog IC Design

C. Frequency Response
Wide-Spectrum Model

Source

Source

Load

Load

MOS and BJT are similar, but r is absent and 1/gmb shunts rds because vbs = vo.
C feed-forwards energy to vo to produce a zero.
iC reinforces igm In Phase In the left-half plane.
zLHP Location:

When iC ir + igm.

$1
'
i r + igm = v be & + g m ) v beg m
% r
(
C shunts vbe ZIN falls with frequency Capacitive effect.
iC = v besC z

LHP

gm
2C

igm falls and ZO 1/gm rises Inductive effect.

CS, C, C and C, CLOAD shunt energy from vin and vo to establish poles.
Miller Split: Decompose C across non-inverting stage into CMI and CMO.
*, $
.,
'
gm
C MI = (1 A V ) C +1 &
)( R O || R LOAD )/ C << C
,- &%1+ g m ( ro || R LOAD ) )(
,0

"
1 %
C MO = $1
' C << C
# AV &

C has negligible effects on pIN and pO.

Case 1. Normally, RS || RB(DEG) >> RGM(DEG) || ro || RLOAD CI shunts first.

1
s (CS + C )

p IN

1
2R S (CS +C )

R S || R B(DEG) = R S || %&r + (1+ 0 ) ( R LOAD || ro )'( R S

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Analog IC Design

Past pIN, RS disappears RGM(DEG)'s degeneration lightens.

AV is still nearly 1 C is still negligible.
CO shunts RLOAD || (r + ZCI) || RGM(DEG) || ro:

sC LOAD

pO

gm'
2C LOAD

R LOAD || ( r + Z CI ) || R GM(DEG) || ro

1 r + Z CI
=
g m'
g m r

Case 2. If RS RGM CO and CI both shunt at high frequency:

1
sC LOAD

gm
pO'
2C LOAD

1
s (CS + C )

R LOAD || r || R GM(DEG) || ro R GM(DEG)

g m(S)
p IN'
2(CS +C )

R S || R B(DEG) R S

1
gm

1
g m(S)

Note pO is usually high and normally precedes zLHP's gm/C Polezero pair.

Example
Objective: If RS = 100 k, vBS = 0, IC = ID = 25 A, 0 = 100, KN' = 100 A/V2,
VA = 1/ = 50 V, C = CGS = 100 fF, C = CGD = 10 fF, W = 20 m, L = 2 m,
RL = 100 k, and CL = 200 fF, determine AV0, pIN, pO, and zLHP.
Solution:
BJT

gm = 980 S, 1/gm = 1.0 k, r = 100 k, and ro = 2 M.

Shunt input resistance RB 10 M.
AV0 +0.99 V/V, pIN 160 MHz,
pO 810 MHz, and zLHP 1.6 GHz.

MOS

gm = 224 S, 1/gm = 4.5 k, and rds = 2 M, and RG .

AV0 +0.96 V/V, pIN 160 MHz,
pO 185 MHz, and zLHP 360 MHz.
Polezero pair pOzLHP zLHP recovers pO's phase.
MOS's lower gm reduces AV0, pO, and zLHP.

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Analog IC Design

3.7. Summary: A. Primitives

Transconductor

Possible Transistor Configurations

Common Emitter (Source)
Base to collector: ic = vbGM Transconductor.
Common Collector (Drain)

Voltage Follower

Base to emitter: vb ve Voltage Follower.

Common Base (Gate)
Emitter to collector: ie ic Current Buffer.
Relative Magnitudes:

Current Buffer

gm

>>

1/r, gmb

>> go, gds

1/gm

<<

r, 1/gmb

<< ro, rds << gmrro, gmrdsrds

C, CGD << C, CGS(SAT) << CINTENTIONAL << COFF-CHIP

Low

<<

Moderate

<<

High

<< Very High

B. Expressions
Small-Signal Translations:
RE/S and gmb degenerate vbe/gs's gm.
ic/d/s
G M(EQ) =
v b/g

gm

1
1+ g m + g mb + R E/S
ro

ie's vbe/r
reinforces vbegm.

1
gm +
r
ie

v
1
1
b
RE/S loads RB(EQ) and RC/D(EQ):
1+ g m + + g mb + R E/S
r
ro

vb
R B(EQ) r + (1+ g m r ) R E = r + (1+ 0 ) R E
ib

v c/d
R C/D(EQ) = ro + (g m' + g mb ) ro R E/S' + R E/S'
ic/d

R E/S' = R E/S || ( r + R B )

RC/D loads RE/S's 1/gm, r + RB shunts RE, and gmb reinforces gm:
r +R

v e/s
o
C/D
R E/S(EQ) =
|| ( r + R B )
ie/s
1+ (g m' + g mb ) ro

v eg m' =

v eg mr
r + R B

RB degenerates veb's gm.

RGM

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Analog IC Design

Emitter/Source Resistance
Emitter/source's RGM resistance is a 1/gm translation.
r and RB shunt emitter's RGM.
Plain

Base Degeneration

Loading Effect

R GM || ( r + R B )

R GM || ( r + R B )

R GM || ( r + R B )

1
|| ( r + R B )
gm

r + R B

|| ( r + R B )
g m r

ro + R C

|| ( r + R B )
1+ g m ro

Plain RGM.

Degenerated RGM.

Loaded RGM.

Loaded RGM reduces to 2/gm when RC ro and to rX when RC gmrorX >> ro.

C. Small-Signal Analysis
Approach: Trace small-signal path and track voltagecurrent conversions.
Insightful Approach: Use direct translations.
Example: iin vg(CS) id(CS) ve(CB) ic(CB) vo1 ie(CC) vo
1
v o1
( rdsPL || R B(CC) ) R Sg mCSrdsPL
= ( R S ) (g mCS ) ( rdsCS || rCB || R GM(CB) )
i in
R GM(CB)

g mCC +
vo
rCC
r
=
1
dsNL
v o1
1
1
+
1+ g mCC +
rdsNL
rCC roCC

Where: R GM(CB) =

roCB + ( rdsPL || R B(CC) )

1+ g mCBroCB

2
g mCB

R B(CC) = rCC + (1+ 0CC ) ( rdsNL || roCC )

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Analog IC Design

D. Noise Analysis
Refer measured non-degenerated noise current iN* to base or gate vB/G* with gm.
Translate forward vB/G* to collector/drain current iC/D*.
v B/G =
*

iN
gm

iC/D = v B/G G M
*

Degenerated Transistors:
Translate vB/G* to degenerated iC/D* with degenerated gm.
*
" i * %"
%
gm
iN
*
*
iC/D = v B/G G M $ N '$
'=
# g m &# 1+ g m R DEG & 1+ g m R DEG

Emitter/source resistors degenerate noise contributions.

Multiple Noise Sources:
Random and uncorrelated Use rootsquare sum.
v TOTAL =
*

* 2

* 2

* 2

* 2

(v ) + (v ) + (v ) +... + (v )
N1

N2

N3

N(K)

Statistical sum magnifies effects of dominant terms Others fade.

Example
Every component contributes noise to input-referred noise voltage vIN*.
v IN =
*

* 2

* 2

* 2

* 2

* 2

* 2

(v ) + (v ) + (v ) + (v ) + (v ) + (v )
NRS

* 2

NCS

* 2

NCB

* 2

NPL

NCC

NNL

v NCS =
*

iCS
g mCS
*

* 2

(v ) + (v ) + (v ) + (v )
NRS

NCS

NPL

NNL

+! 1 $
!i *$
! 1 $ ! i * $(
g mCB
*
-#
v NCB = # CB &G MCB #
& = # CB &*
&
" g mCS % " g mCB %*)1+ g mCB ( rCB || rdsCS ) -," g mCS %
" g mCB %

v NPL =
*

*
*
*
i PL R O1 i PL ( rdsPL || R B(CC) || R C(CB) ) i PL

A V1
g mCS ( rdsPL || R B(CC) )
g mCS

i * 1 i *
1
*

v NCC = CC
CC
g mCC A V1 g mCC g mCS ( rdsPL || R B(CC) )

First gain stage

suppresses
i * 1

1
*
* 1+ g mCC ( rdsNL || roCC )

v NNL = NL
i NL

g mCC

g mCS ( rdsPL || R B(CC) ) output noise.

G M(CC) A V1

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Analog IC Design

E. Offset Analysis
Collector/drain voltage difference vC/D produces a small offset current iC/D.
Measured non-degenerated current mismatches iM* are usually 5%15%.
iM* and vC/D are small Treat as small signals.
Refer iM* to base or gate vB/G* with gm.
vC/D is systemic and iM* is random.
Linear and rootsquare sum: iOS = iOS(S) iOS*.
Degenerated Transistors:
Translate gate offset vB/G* to degenerated iC/D* with gm(DEG).
%I g m12
%I12
*
*
iOS = i12 12
=
g m12 1+ g m12 R 34 1+ g m12 R 34

vC/D into drain resistance RD produces iOS(S).

i v D
v D
iOS(S) = v D d =
=
v d R D12 rds12 + R 34 + g m12 rds12 R 34

Emitter/source resistors degenerate mismatch effects.

Page 26