Analog IC Design

Chapter 4. Analog Building Blocks

Outline
4.1. Cascode Transistor
4.2. Current Mirror
4.3. Base/Gate-Coupled Pair
4.4. Emitter/Source-Coupled Pair
4.5. Differential Stage
4.6. IC Design

Page 1

Analog IC Design

4.1. Cascode Transistor

Origin of "Cascode": Contraction for "cascade" and "triode" from cascaded triodes.
A cascode transistor is a common base/gate current-buffer transistor.
Basic Transconductor

Gain: vin id1 vo.

A V = (g m1 ) ( rds1 || rds2 )

Input Pole: M1 Miller-multiplies CGD1.

C IN CGS1 + g m1 ( rds1 || rds2 ) CGD1

Output Pole: When CIN shunts first,

RIN disappears,
igm is a linear gm translation of vo: Rgm, and
vg is a voltage-divided fraction of vo
pO

1 g m1CGD1
1
=
> p IN

2CO R gm 2CO CGS1 + CGD1

A. Cascoded Transconductor

Cascoded Transconductor

Gain: MC1 current-buffers M1.

2 g mC1
A V (g m1 ) rds1 ||

rds2
2
g

mC1
Similar AV.
Input Pole: MC1 reduces CGD1's Miller gain.

2
C IN CGS1 + 1+ g m1
C DS1
g mC1

Input pole pIN is at higher frequency.

Output Pole: No gm translation from vo: no Rgm.
R O rds2 || R DC1 rds2 || (g mC1rdsC1rds1 ) rds2

Output pole pO is at lower frequency.

Intermediate Pole: CD1 shunts energy, but pO's CO shunts RGM(C1)'s load first
g mC1
1
p D1
> pO
2CO R O
2CGSC1

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Analog IC Design

B. Cascoded Amplifier

Cascoded Amplifier

Gain: MC2 increases load resistance.

1
A V (g m1 ) ( rds1 || rds ) (g mC2 rdsC2 rds2 )
rds
Higher AV.
Input Pole: MC2 increases MC1's RGM(C1)'s load.
C IN CGS1 + g m1 ( rds1 || rds ) C DS1

Input pole pIN is back to lower frequency.

Output Pole: MC2 increases load resistance.
R O (g mC1rdsC1rds1 ) || (g mC2 rdsC2 rds2 )

Output pole pO is at even lower frequency.

Intermediate Pole: CD1 shunts energy, but pO's CO shunts RGM(C1)'s load first
p D1

g mC1
1
> pO
2CO R O
2CGSC1

4.2. Current Mirror: A. Theory of Operation

Basic Operation:
iC and iD are very sensitive to vBE and vGS.
iC and iD are insensitive to vCE and vDS.
vBE's and vGS's match iO iIN.
(
(
! v $ +! v $
!v $ +
iC = IS *exp # BE & 1-#1+ CE & IS *exp # BE & 1- i IN i O
" Vt % ," VA %
" Vt % ,
)
)

W
W
2
2
i D = K'( v GS v T ) (1+ v DS ) K'( v GS v T ) i IN i O
L
L

vIN = vBE = vDIODE Q1 is said to be a diode-connected transistor.

By translation, M1 is also said to be a diode-connected transistor.
Voltage Limits:

vIN = vBE or vGS

and

Page 3

vO VCE(MIN) or VDS(SAT).

Analog IC Design

Mirror Translations

"i %
iO = 2iC 2 $ IN '
# 3&

iO = 2i D 2i IN

Relative BJT emitter areas and MOS widthlength aspect ratios set gain.
Integers and fractions are possible.
Tip for Analysis: Distribute into equal current segments.

B. Small-Signal Response
Q1's Diode-Connected Resistance:
1
1
R D = ro || R GM || r = ro ||
|| r
gm
gm
igm1 is a linear translation of vbe RGM1 is a 1/gm resistor.
Two-Port Parameters: RIN = RD1 || r2 1/gm1, GM = gm2, and RO = ro2.
Gain: Source resistance RS "steals" current from input RIN and output resistance
RO "steals" from load RLOAD Higher gain if RS >> RIN and RLOAD << RO.
A I0

i load " v in %" i gm2 %" v o %" i load %

'$
'$
= $ '$
' = R S || R IN G M R O || R LOAD
i in $# i in '&$# v in '&$# i gm2 '&$# v o '&

)(

)(

"

%
''
LOAD &

) $$# R 1

r || R LOAD

g
1
IV
A
= R S || ro1 ||
|| r1 || r2 (g m2 ) o2
m2 = 2 t 2
g m1
g m1
Vt I1
A1

R LOAD

if RS >> RIN and RLOAD << RO.

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Analog IC Design

C. Errors
Base-Current Error: iO = AIiC1 AIiIN.
i 1 i

iO = A I iC1 = A I ( i IN i E ) A I i IN O + O
A I 0 0

Voltage VA Error:
vO vIN vCE2 vCE1 and vDS2 vDS1 iO iIN.

i
A I = C2
i C1

( ! v $ +! v $
!
v
IS2 *exp ## BE && 1-#1+ O &
# 1+ O
*) " Vt % -," VA % ! A E2 $#
VA
=
=#
&
( ! v $ +! v $ #" A &%# v BE
E1
IN
BE
# 1+
IS1 *exp ##
&& 1-#1+
&
VA
"
*) " Vt % -," VA %

$
&
&
&
&
%

!W$
2
# & K'( v GS v T ) (1+ v O ) ! $!
i D2 iO " L %2
S
1+ v O $
AI =
=
=
= # 2 &#
&
i D1 i IN ! W $ K' v v 2 1+ v
" S1 %" 1+ v GS %
# & ( GS T ) (
)
IN
" L %1

W
Si
L i

D. Error Correction: i. Base-Current Correction

Compensation:
Increase iO by iE by raising vBE2.
iE is small Small-signal model predicts translation:
Raise vBE2 by dropping iE/gm2 across R above vBE1.
iO v Rg m2 = ( i B1R ) g m2

Reduction:

1+A I
R
g m2

i E = i B1 + i B2 = i B1 (1+ A I )

Diode-connect with follower QB

to reduce error by 0.
Pull IBIAS to raise QB's gmB
so emitter pole is higher.
i IN iO
+ + I BIAS
i (1+ A ) I
0
iE 0
IN 2 I + BIAS
1+ 0
0
0

Elimination: If FETs are available, replace QB with MB to eliminate base error.

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Analog IC Design

ii. Voltage-Correcting Cascodes

Voltage VA Error:
vO vIN vCE2 vCE1 iO iIN.
Fix:
Impress vCE1 on vCE2 vCE's match.
How:
Q3 passes iIN and drops one vBE3 above vCE1.
Q4 buffers iO and drops Q3's vB3 down one vBE4.
vCE2 = vCE1 + vBE3 vBE4 vCE1 = vBE1.
Drawbacks: Higher input and output voltages vIN and vO.
vIN = 2vBE

or

2vGS.

vO vCE2 + VCE4(MIN) vBE1 + VCE4(MIN)

or

vO vDS2 + VDS4(SAT) vGS1 + VDS4(SAT).

Small-Signal Resistances
Equivalent Shunt Resistances Assume AE1 = AE2 and AE3 = AE4.
RIN: Two diode-connected transistors.
R IN = R D31 || R B4 R D31 || (0 R D31 ) R D31

Where Q1Q2 mirrors ie3: R B4

1
1
+
g m3 g m1

v in
v in 0 0 R D31
i b4
ie3

RO: Q2 and Q4's r4 path emitter-degenerate Q4.

R O = ro4 + R DEG4' + g m4 ro4 R DEG4' g m4 ro4 R DEG4' g m4 ro4 ( r4 || r4 || ro2 ) 0.504 ro4

Where Q1Q2 mirrors i4 in RDEG4' igm2 ir4 Rgm2 r4.

!
1
1 $
v
R DEG4' = # r4 +
+
& || R GM2 || ro2 r4 || e4 || ro2 r4 || r4 || ro2
g m3 g m1 %
i r4
"

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Analog IC Design

Low-Voltage Cascodes
Reduce Minimum Voltages: Another circuit biases cascode bases and gates.
Input: Q3 current-buffers iC1 and diode-connects Q1.

vIN = vBE1 or vGS1.

vO > 2VCE(MIN)
or 2VDS(SAT).
vGSX shifts with VDS(SAT)
across temp. and
fab. corners
vDS2 can be near VDS(SAT).
vB/G34 f(iIN).

RB: QX matches cascodes v CE1 = v CE2 = v R + v BEX v BE4 v R = I BIASR B > VCE(MIN)
MX: MX matches cascodes, VGSX(SAT) > VGS34(SAT), and vT's cancel with low bulk effects.
v DS1 = v DS2 = v GSX v GS34 VDSX(SAT) v DS34(SAT) > v DS1(SAT) v DS2(SAT)
Design Objective

Self-Biasing Cascodes
Self Bias: iIN and RB drop a level-shifting bias voltage vR = iINRB.
Q3 and M3 diode-connect Q1 and M1.
If Q1234 and M1234 match and
bulk effects are low:
v CE2 = v BE1 + v R v BE4 v R > VCE(MIN)
v DS2 v DS1(SAT) + v R v DS4(SAT) > v DS2(SAT)

Design Objective
Design Note: vR = iINRB, VCE(MIN), and vDS(SAT) (iIN/K')
do not track well across iIN, temperature, or fabrication corners.
Design for worst case: vCE and vDS > Highest VCE(MIN) and vDS(SAT).

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Analog IC Design

4.3. Base/Gate-Coupled Pair: A. Large-Signal Operation

Q1 drops a constant VEB1 vB2 follows vI1 and ic2 = (vi2 vb2)gm2 = (vi2 vi1)gm2.

ICMR: BJT v IC > v EE + VQB1(MIN) + v EB1 = v EE + VCEB1(MIN) + v EB1

ICMR: MOS v IC > v SS + VMB1(MIN) + v SG1 = v SS + VDSB1(SAT) + v TP + VSD1(SAT)
Output Swing: v EE + VCEB2(MIN) < v O < v IC VEC2(MIN)
vID's Linear Range: v ID(MAX) =

Slew Rate:

iO
I
BIAS = Vt
G D g m(BJT)

v ID(MAX) =

V
iO
I
BIAS = DS(SAT)
G D g m(MOS)
2

Maximum possible rising and falling rates of vO.

iO(MAX) and CLOAD limit dvO/dt.
SR

v O dv O
iO
i I
=
=
= 2 BIAS
t
dt C LOAD + C EQ C LOAD + C EQ

Shift SR dominance:
Fold and mirror i2.
Q3Q4.
Mirror i1.
Q1Q1'.
ISOURCE(MAX) = IBIAS

ISOURCE(MAX) = i2(MAX) IBIAS

IPULL(MAX) = i2(MAX) IBIAS

IPULL(MAX) = IBIAS

SR can be >> SR+.

SR+ can be >> SR.

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Analog IC Design

B. Small-Signal Response

Approx.

Small-Signal
Model

The voltage-divider drop across Q1's 1/gm1 is negligible vb2 vi1.

v b2 =

v i1 roB1 || R B2
R I1

)=

v i1 roB1 || R B2

1
+ roB1 || R B2
g m1

v i1 roB1 || R B2
roB1 || R B2

)=v

i1

ic2 = (vi2 vb2)gm2 (vi2 vi1)gm2 vidgm2 ic2 is a differential output current.
Q2 is a differential transconductor.

Model: R I1 =

1
+ roB1 || R B2 roB1 || R B2 = roB1 || #$r2 + 1+ g m2 r2 R SI2 %&
g m1

.0
(
" 1
%+20
r +r
2
R I2 = /r2 + *roB1 || $
+ R SI1 '-3 || R GM2 R GM2 = o2 oB2
g
g
1+
g
'r
# m1
&,40
)
m2 o2
m2 '
10

R O = roB2 || R C2
A D0

Gain:

GD

vo
= G D R O || R LOAD
v id

io
io
=
= g m2
v id v i2 v i1

Can be high.

Frequency Response: RSI1 is usually low pI1 is at high freq.

ROCLOAD >> RI2CI2 pO << pI2.
1
s C LOAD + C EQ

R O || R LOAD
pO

)(

2 R O ||R LOAD C LOAD+CEQ

Page 9

1/gm1 and RSI1

base-degenerate
RGM2 to gm2'.

Analog IC Design

C. Electronic Noise
Every component contributes noise.
2

2
2
2
i * i * i * g i *
*
v N = 1 + 2 + B1 mB2 + B2
g m1 g m2 g mB1 g m2 g m2

For low VOS, use JFETs, vertical BJTs,

and PFETs and raise gm12.

D. Input-Referred Offset
VOS = VOS(S) VOS
*

# i & # i &
v C
% 12 ( + % B12 (
A D0
$ g m2 ' $ g m2 '

For low VOS, use BJTs, match

Q1Q2 and QB1QB2, and raise AD0 and gm12.
Recall that BJT's gm translation suppresses offsets more than FET's gm.

4.4. Emitter/Source-Coupled Pair: A. Large-Signal Operation

iC12:

Insensitive to vIC.
Sensitive to vID.

iC12(MAX) = ITAIL.
vO(MAX) depends on load:
vCC or vDD.
vO(MIN) depends on input:
Differential Input Voltage: vID vI1 vI2.

vI12 vBE + VCE(MIN).

Common-Mode Input Voltage: Average input voltage vIC 0.5(vI1 + vI2).

Each input carries vIC and opposite halves of vID: vI1 = vIC + 0.5vID, vI2 = vIC 0.5vID.
Input Common-Mode Range (ICMR): All transistors remain in high-gain mode.
When biased and with negative feedback, vI1 vI2 vBE1 vBE2 and IC1 IC2.
High vIC "crushes" diff. pair against load.
Low vIC "crushes" tail transistor.
v EE + VTAIL(MIN) + v BE1 < v IC < v CC v LOAD VCE1(MIN) + v BE1

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Analog IC Design

B. Small Differential Signals

Small-Signal Transformation: vIC and steady-state signals are 0.
Small-Signal

Model
Small-Signal Model: Equal, but opposite io's drop zero volts across RTAIL.
Circuit reduces to two CE/CS transistors.
R ID

GD

v id
v id
=
= 2r
#
i id
0.5v id &
%
(
$ r '

R OD

v od
v od
=
= 2ro
"
iod
0.5v od %
$
'
# ro &

io1 io2 io1 io2 (0.5v idg m ) ( 0.5v idg m )

=

= g m
v id
v id v id
v id
v id

Linear Range vID(MAX):

v ID(MAX) BJT

Vt
iOD
I
TAIL = I TAIL
= 2Vt
GD
gm
0.5I TAIL

v ID(MAX) FET

iOD
I
TAIL =
GD
gm

I TAIL

W
2 ( 0.5I TAIL ) K'
L

2 ( 0.5I TAIL )
= VDS(SAT)
W
K'
L

Gains:
A D10

v o1
= 0.5 (g m ) ( ro || R LOAD )
v id

A D20

v o2
= 0.5 (g m ) ( ro || R LOAD ) = 0.5g m ( ro || R LOAD )
v id

A DD0

v od v o1 v o2

= 0.5g m ( ro || R LOAD ) 0.5g m ( ro || R LOAD ) = g m ( ro || R LOAD )

v id
v id
If transistors match.

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Analog IC Design

C. Small Common-Mode Signals

Small-Signal Transformation: vID and steady-state signals are 0.
Small-Signal

Model

Small-Signal Model: io's add to drop twice the voltage of one across RTAIL.
Circuit reduces to two degenerated CE/CS transistors.
R IC R B1 || R B2 = 0.5R B = 0.5$%r + (1+ 0 ) ( 2R TAIL )&' 0 R TAIL

R OC1 = R OC2 = ro + ( 2R TAIL || r ) + g mro ( 2R TAIL || r ) g m ro ( 2R TAIL || r ) 0 ro

G C1 = G C2

io1 io2
gm
=

v ic v ic 1+ 2R TAILg m

G CD

iod io1 io2 io1 io2

= G C1 G C2 = 0
v ic
v ic
v ic v ic
If transistors match perfectly.

Common-Mode Gains:
A C10

v o1 v o2
gm
=
A C20
( R OC1 || R LOAD )
v ic v ic
1+ 2R TAILg m

A CD0

v od v o1 v o2 v o1 v o2

= 0 If transistors
v ic
v ic
v ic v ic
match perfectly.

Common-Mode Rejection Ratio (CMRR)

Definition: How much a circuit favors differential over common-mode signals.
Common-mode noise is typical Low AC and high CMRR are desirable.
A D10
CMRR10

v o1
= 0.5 (g m ) ( ro || R LOAD )
v id

If transistors match perfectly.

1+ 2R TAILg m
A
A
A D10
A
= D20 = 0.5 ( ro || R LOAD )
CMRR D0 DD0 DD0
A CD0
0
A C10
A C20
R OC || R LOAD

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Analog IC Design

D. Emitter/Source Degeneration

Emitter and source

Small-Signal

degeneration lowers

Model

transconductance.

0.5ITAILRDEG raises vIC(MIN) ICMR suffers.

Usually, RDEG << RTAIL RDEG degenerates GD more than GC CMRR can suffer.
A lower GD extends the vID's linear range vID(MAX):
v ID(MAX)'

I
iOD(MAX)
(1+ gm R DEG ) = v
TAIL
ID(MAX) (1+ g m R DEG )
G D'
gm

Splitting ITAIL
similarly

Small-Signal

degenerates GD.
Model

vID appears across vE's Junction of RDEG's is 0 V.

Usually, RDEG << 2RTAIL ie's flow into RDEG's, not RTAIL's.
vIC raises both vE's RDEG's current is 0 A and no degeneration in GC.
RDEG degenerates GD, but not GC CMRR suffers.
0.5ITAIL does not flow through RDEG ICMR does not suffer.
Mismatch in 0.5ITAIL's produces offset QT1 should match QT2.

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Analog IC Design

CMOS Implementations

Input-Common Mode Range (ICMR):

v IC > v SS + VTAIL(MIN) + v GS1 = v SS + VDST(SAT) + ( v TN1 + VDS1(SAT) )

v IC < v DD v LOAD VDS1(SAT) + v GS1 = v DD v LOAD + v TN1

Bulk
Effect

Well to source No vT shift, but substrate noise couples to source.

Well to supply No sub. noise, but vT shifts ICMR shifts.
Bulk is the substrate Sub. noise and vT shifts ICMR shifts.

E. Summing Transconductor
Matched differential pairs project input voltages to matched currents:
If MAT matches MBT.
If MA12 matches MB12.
gmA = gmB GM.
iOD = (vA + vB)GM.
iOD = ( v AP v AN ) g mA + ( v BP v BN ) g mB v Ag mA + v Bg mB

Equivalent translations when GM gmA12 gmB12:

iOD = ( v AP v AN + v BP v BN ) G M

= ( v AP + v B v AN ) G M

= (v A + v B ) G M

Analog
Summer
g mB
MB12 produces a programmable offset that MA12 refers to vA as v OS = v B
.
g mA

Page 14

Analog IC Design

4.5. Differential Stage: A. Large-Signal Operation

Purpose of Mirror:
Convert two half differential signals to one full differential signal.
M3M4 mirrors i1 to vO iO = i1 i2 = iDIFF iOD.

Commonly known as double- to single-ended differential conversion.

ICMR: v IC > v SS + VTAIL(MIN) + v GS1 = v SS + VDST(SAT) + v TN1 + VDS1(SAT)

v IC < v DD vSG3 VDS1(SAT) + v GS1 = v DD v TP3 VSD3(SAT) + v TN1

Output Swing: v IC v GS2 + VDS2(SAT) = v IC v TN2 < v O < v DD VSD4(SAT)

Slew Rate: SR

dv O iO(MAX)
I TAIL
=
=
dt
CO
C LOAD + C EQ
2

2
2
!i*$ !i *$ !i*$ !i *$
*
1
& +# 2 & +# 3 & +# 4 &
Noise: v N = #
" g m1 % " g m2 % " g m1 % " g m2 %

*
Offset: VOS = VOS(S) VOS =

" i % " i %
v D
$ 12 ' + $ 34 '
A D0
# g m1 & # g m1 &

For low VOS and vN*, match M1M2 and M3M4 and
raise AD0 and gm12's W12 towards subthreshold.
Polarity: A rise in vI2 pulls vO down vI2 is the inverting input.

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Analog IC Design

B. Small Differential Signals: i. Low Frequency

Model:

R IN
GD

Gain:

R O = rds2 || rds4

i o i1 i 2 i1
0.5v id g m1 0.5v id g m2
i
=
=
2 =

= g m1 = g m2
v id
v id
v id v id
v id
v id

A D0

vo
= G M R O || R LOAD = g m2 rds2 || rds4 || R LOAD
v id

Example: Determine AD0 of PMOS pair into

NMOS mirror when vTN = |vTP| = 0.6 V,
KN' = 100 A/V2, KP' = 40 A/V2, 1/ = 50 V,
W's = 2 m, L's = 2 m, and ITAIL = 10 A.
Solution: A D0 = g m2 ( rds2 || rds4 ) = g m2 ( 0.5rds2 )
2 m 50 V
= 2(5 A) ( 40 A/V 2 )
0.5
= 100 V/V = 40 dB
2 m 5 A

Offset Example
Objective: Determine VOS of a PMOS differential pair loaded
with a basic NMOS mirror when vTN = |vTP| = 0.6 V,
KN' = 100 A/V2, KP' = 40 A/V2, 1/ = 100 V,
W's = 4 m, L's = 4 m, ITAIL = 10 A,
iMOS* = 5%, and vD = 1 V.
Solution:
VOS(S) =

v D
=
g m2 ( rds2 || rds4 )

1V
1V
=
= 5 mV

200
V/V

100 V
4 m
2(5 A) ( 40 A/V 2 )
0.5

4 m 5 A
2

VOS

2
2
i i
5%( 5 A )
18 mV
= 12 + 34 = 2

2
g m2 g m2
2( 5 A )( 40 A/V )( 4 m 4 m )

VOS = VOS(S) VOS 5 18 mV

*

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Analog IC Design

ii. Frequency Response

Pole Locations: At every node in the
small-signal path pIN, pM, and pO.
Pole dominance: pO << pM << pIN
if rds24CO >> (1/gm3)CG34 >> RSCG12.
1
s C LOAD + C GD2 + C DB2 + C GD4 + C DB4

R O || R LOAD = rds2 || rds4 || R LOAD

pO

2 R O||R LOAD C EQO

GD's io falls past mirror pole pM: Since pO << pM CEQO replaces RLOAD and
M4 has little gain with which to Miller-multiply CGD4 CGD4 CEQO CGD4.
1
1

s (C GS3 + C GS4 + C GD4 + C GD1 + C DB3 + C DB1) s ( 2C GS3) p

g m3
2( 2C GS3)

1
1
|| rds3 || rds1
g m3
g m3

Past pM, GD drops until i4 << i2 GD falls 2 to 0.5gm2 Freq. rises 2 to zM 2pM.
+
(
"
%
s
- g $1+ s '
g m1 *1+
m1
*) 2 2p M -,
0.5g m1
# 2z M &
GD =
+ 0.5g m2 =

"
%
"
%
"
s
s
s %
$1+
'
$1+
'
$1+
'
# 2p M &
# 2p M &
# 2p M &

zM follows pM, and only by 2 zM recovers some of pM's phase shift.

CIN shunts RS to establish pIN.

Page 17

Analog IC Design

Example
Parameters: ITAIL = 20 A, CGS = 100 fF, CGD = 10 fF, CL = 1 pF, W's = 20 m,
L's = 2.4 m, KN' = 100 A/V2, KP' = 40 A/V2, and 1/ = 100 V.
Solution: gmN 130 S, gmP 80 S, rds 10 M, AD0 gmN(rdsN || rdsP) = 56 dB,
pO 1/2(2CGD + CL)(rdsN || rdsP) = 31 kHz,
pM gmP/2(2CGS + 2CGD) = 58 MHz, and zM = 2pM 116 MHz.

C. Small Common-Mode Signals: i. Low Frequency

If transistors match perfectly.
i4 = i2 iO = 0 and AC0 = 0.
vDS mismatches produce mirror error E.
i4 i2 iO 0 and AC0 0.
R OC = rds4 || R D2 = rds4 || ( rds1 + 2R TAILg m1rds1 + 2R TAIL ) rds4
GC =

, i )# 1+ v &# 1+ v & ,
iO i 4 i 2 # 1 &) # i1 &# i 4 &
DS1
SD4
=
= % (+i 2 % (% ( i 2 . = 2 +%
(%
( 1.
v ic
v ic
$ v ic '* $ i 2 '$ i3 '
- v ic *$ 1+ v DS2 '$ 1+ v SD3 ' -

"
%
g m2
= G C2 E = $
'E
1+
2R
g
#
TAIL m2 &
A C0

$
'
vo
g m2
= G C ( R OC || R LOAD ) = E G C2 ( R OC || R LOAD ) E &
) ( rds4 || R LOAD )
v ic
% 1+ 2R TAILg m2 (

Random mismatches in vT, K', and raise AC0.

Page 18

Analog IC Design

ii. Frequency Response

Pole dominance: If rds4CO >> (1/gm3)CM >> RSCS pO' << pM << pIN.
1
s (C LOAD + C GD2 + C DB2 + C GD4 + C DB4 )

pO'

1
2( R OC||R LOAD)C EQO

R OC || R LOAD rds4 || R LOAD

Mirror: Error i4 i2 climbs and begins to flatten when i4 is 3 dB below i2 At pM.

GC2E climbs past zM' to GC2 at pM pM is 1/E times higher than zM'.
#
s &
sG E
G C = G C2 E %1+
C2
(
2z M'
$ 2z M' ' f>>zM'

f=p M

G C2 zM' EpM.

Since mirror error E << 1:

zM' = EpM << pM
zM' is at low frequency.

RTAIL is normally high CTAIL shunts RTAIL at moderate to low frequency.

CTAIL removes RTAIL's degenerating effects GC2 rises past zD.
1
s ( 0.5C TAIL ) z

1
2R TAIL C TAIL

2R TAIL

0.5CTAIL shunts M2's 1/gm2 past pD.

1
s ( 0.5C TAIL ) p

g m2
2( 0.5C TAIL )

1
g m2

GC2 rises past zD and flattens to gm2 at pD, when degenerating effects disappear.
!
$!
!
$! s $
s $
g m2
g m2
G C2 = #
#
g m2
&#1+
&
&#
&
" 1+ 2R TAILg m2 %" 2z D % f>>zD " 1+ 2R TAILg m2 %" 2z D % pD =(1+2R TAILgm2 )zD

CTAIL raises GC past zD and flattens GC past pD, well after zD << pD.

Page 19

Analog IC Design

Summary
CLOAD lowers AC past pO'.
CTAIL raises GC, and as a result, AC past zD.
Mirror's 2CGS3 raises iO from i2E past zM'.
2CGS3 shunts 1/gm3 past pM i4 disappears and iO levels to i2.
0.5CTAIL shunts 1/gm2 past pD after pM GC levels to gm2.

Example
Same Parameters: ITAIL = 20 A, CGS = 100 fF, CGD = 10 fF, CL = 1 pF, W's = 20 m,
L's = 2.4 m, KN' = 100 A/V2, KP' = 40 A/V2, 1/ = 100 V, and E = 4%.
Solution: gmN 130 S, gmP 80 S, rds 10 M, rdsT 5 M,
AC0 E(rdsP/2rdsT) 28 dB, pO' 1/2(2CGD + CL)rdsP = 16 kHz,
pM gmP/2(2CGS + 2CGD) = 58 MHz, zM' = EpM 2.3 MHz,
zD 1/2rdsTCGDT = 3.2 MHz, and pD gmN/2(0.5CGDT) = 4.1 GHz.

Page 20

Analog IC Design

iii. Common-Mode Rejection Ratio

pO and pM in AC roughly match those in AD They cancel in CMRR.
)
#
s &#
s &,
s &#
s & ,) #
+ A D0 %1+
(%1+
(%1+
(.
( .+ %1+
A
$ 2z M ' .+ $ 2p O' '$ 2p M '$ 2p D ' .
CMRR D = +
#
AC +#
s & .
s &#
s &#
s & .+
A C0 %1+
+ %1+
(%1+
(%1+
( .
( .+
2z
2z
$
* $ 2p O '$ 2p M ' -*
D '$
M' '
#
s &
s &#
g m2 ( rds2 || rds4 || R LOAD ) %1+
(%1+
(
$ 2z M '$ 2p D '

* E g m2 ( rds4 || R LOAD ) -#
s &
s &#
(%1+
(
,
/%1+
+ 1+ 2R TAILg m2 .$ 2z D '$ 2z M' '

zD and zM'

#
s &
s &#
2R TAILg m2 %1+
(%1+
(
$ 2z M '$ 2p D '

#
s &
s &#
E %1+
(%1+
(
$ 2z D '$ 2z M' '

are at moderate
frequencies.

D. Power-Supply Rejection
Power-supply rejection (PSR) is the ability to reject supply noise, or rather,
inability to amplify supply noise vSUPPLY in the output signal sO.
PSR

1
v
SUPPLY
ASUPPLY
sO

Power-supply rejection ratio (PSRR) is a measure of how much a circuit

favors processed input signals sI over supply noise vSUPPLY in sO.
PSRR

A FWD # sO &# v SUPPLY &

=%
( = A FWD PSR
(%
A SUPPLY $ sI '$ sO '

Analysis: Derive forward gain AFWD and supply gain ASUPPLY

and use AFWD and ASUPPLY to determine PSR and PSRR.

Page 21

Analog IC Design

i. P-Type Mirrors: Positive Supply Gain

Current mirrors reproduce noise currents.
Small-Signal Model: Positive supply gain AVDD when vid 0, vic 0, and vss 0.

P-type mirrors reinforce positive-supply noise.

v dd R B v dd R BR M
v dd R B

+ igm ( R B || R M )
R B + R M R B R B + R M
v
R + RM
A VDD o = B

=1
v dd
v dd
v dd

P-type mirrors with balanced loads reproduce positive-supply noise PSRR+ AD/1.
For more accurate results, include the effect of 1/gm3 in igm.

Negative Supply Gain

Small-Signal Model: Negative supply gain AVSS when vid 0, vic 0, and vdd 0.

P-type mirrors subtract negative-supply noise.

v ss R M v ss R B'R M
v ss R M

igm ( R B' || R M )
R B' + R M R B' R B'+R M
v o R B' + R M
A VSS
=

=0
v ss
v ss
v ss

P-type mirrors with balanced loads cancel negative-supply noise PSRR AD/0 .
For more accurate results, include the effects of M12's 1/gm12 in RB' and 1/gm3 in igm.

Page 22

Analog IC Design

ii. N-Type Mirrors

Small-Signal Model: Supply gains AVDD and AVSS when vid 0 and vic 0.

N-type mirrors subtract positive-supply noise.

If balanced, they cancel positive-supply noise: AVDD 0 PSRR+ AD/0 .
N-type mirrors reinforce negative-supply noise.
If balanced, they reproduce negative-supply noise: AVSS 1 PSRR AD/1.

E. Folding Cascodes: i. Performance

vIC(MAX) in Differential Stage: Differential pair crushes against mirror.
Raise vIC(MAX) by reducing mirror's vSG to VSD(SAT).
How: Use current buffers to fold differential currents into opposite mirror.

ICMR+: v IC < v DD vSD9 VDS1(SAT) + v GS1 = v DD vSD9 + v TN1

Higher vIC(MAX).

Output Swing: vSS + VDS4(SAT) < v O < v DD vSD10 VSD6(SAT)

Lower vO(MAX).

Note: v SD9/10 = VBIAS3 VSG6 = VBIAS3 v TP6 VSD6(SAT) VSD9/10(SAT)

Design Aim

Page 23

Lower vO(MIN).

Analog IC Design

Offset and Electronic Noise: More devices contribute VOS and vN* are higher.
Current sources M1,2,9,10 counter M5,6's effects rds1||9,2||10 degenerate v56 and vG5,6*.
VOS = VOS(S) VOS

2
2
2
1
i i i i
v
g m5
D 12 + 9/10 + 34 + 56

A D0
g m1 g m1 g m1 g m5 1+g m5 ( rds9 ||rds1 ) g m1

Output Resistance: R O = rds4 || R D6 = rds4 || !"rds6 + g m6 rds6 ( rds10 || rds2 ) + ( rds10 || rds2 )#$ rds4
Raise RO and AD0 by cascoding M4.

vO(MIN) is higher.

ii. Folded-Cascode Amplifier

SRO+ = (I6(MAX) I8(MIN))/CL = ITAIL/CL

Bias: Ensure I9 and I10

SRO = (I8(MAX) I6(MIN))/CL = ITAIL/CL

are high enough to feed

RO [gm6rds6(rds10 || rds2)] || (gm8rds8rds4) High

M56 when M12 peaks to ITAIL.

AD0 GDRO gm12(0.3gmrdsrds) High

I9 I10 > ITAIL E.g.: 1.5ITAIL.

pS5 and pS6 each lower half of AD.

Together they constitute one pole.
ROCO >> RMCM, RS56CS56 pO << pM, pS56
pO = 1/2ROCO
pM gm3/2(2CGS3)
zM = 2pM when i8 << i6.
Past pO, M6's 1/gm6 is lightly loaded.
pS56 gm6/2CGS6.

Page 24

Analog IC Design

Example
Objective: Assume I18 = 50 A, CGS = 100 fF, CGD = 10 fF, CL = 1 pF,
W's = 5 m, L's = 2.5 m, KN' = 100 A/V2, KP' = 40 A/V2, and 1/ = 50 V.
Determine RO, AD0, pO, pM, zM, and pS56.
Solution:
gmN = 140 S, gmP = 89 S,
rds18 = 1.0 M, and rds9/10 = 0.5 M.
RO 25 M
AD0 3.5 kV/V = 71 dB
pO 6.2 kHz
pM 101 MHz
zM 202 MHz
pS56 118 MHz

iii. Power-Supply Gain

Equivalent to differential stages:
Mirrors with symmetrical loads cancel and reproduce power-supply ripples.

M3M4 is an N-type mirror.

M3M4 is an P-type mirror.

M5M6 is a symmetrical load to M3M4.

M5M6 is a symmetrical load to M3M4.

M3M4 cancels vdd.

M3M4 reproduces vdd.

M3M4 cancels vss.

M3M4 reproduces vss.

Page 25

Analog IC Design

Example
Objective: Determine ICMR, output
swing limits vO(MAX), AVDD, and
AVSS of the amplifier on the right.
Solution:
vSS + v DS9 v TP1 < v IC < v DD VSDT(SAT) v TP1 VSD1(SAT)
vSS + v DS10 + VDS6(SAT) < v O < v DD VSD4(SAT)

Design Aim

Where: v DS9/10 = VBIAS3 v GS56 = VBIAS3 v TN56 VDS56(SAT) VDS9/10(SAT)

v dd R D6 v dd R D6 rds4
v dd R D6

+ igm ( R D6 || rds4 )
r + R D6 R D5 rds4 + R D6
r + R D6
A VDD = ds4
ds4
1
v dd
v dd
v ss rds4 v ss R B6'rds4
v ss rds4

igm ( R B6' || rds4 )

R B6' + rds4 R B5' R B6' + rds4
R '+r
A VSS = B6 ds4

0
v ss
v ss

iv. Design Flexibility

N- and P-type pairs can fold into N- or P-type mirrors.
M5 current-buffers M3's i3
M5 diode-connects M3.
M5 current-buffers M1's i1 into
current mirror M3M4.
M4's igm4 mirrors i1.
M6 current-buffers i1 i2 to vO.
N- and P-type pairs can cancel or reproduce either supply ripple,
but normally, not cancel or reproduce both supply ripples.

Page 26

Analog IC Design

4.6. IC Design: i. Process

Use specification targets to:

Design architecture.
Derive parametric constraints.

Justify every design choice, even if just to save silicon area.

ii. Margin
Add margin to each design choice to reduce:
Design iterations within first cycle.
Design iterations across temperature and fabrication corners.
Margin nearly always trades advantages for disadvantages.
Excessive margin can keep circuit from meeting other specifications.
And ultimately require more design iterations.

iii. Example
Objective: Design an amplifier with VDD = +3 V, VSS = 3 V, IBIAS = 1 uA,
CLOAD = 5 pF, 1.5 V < vIC < 2.5 V, 2.6 V < vO < 2.2 V, AV > 40 dB,
AVDD < 30 dB, SR > 4.5 V/s, IVDD < 100 A, vTN = |vTP| = 0.6 V,
KN' = 100 A/V2, KP' = 40 A/V2, and 1/ = 50 V when L = 3 m.
Architectural Design:
vIC(MAX) is close to VDD.
Fold N-type differential pair.
AVDD is very low.
Fold into N-type mirror.
vO(MIN) is close to VSS and
AV is not very high.
No cascodes in the mirror.

Page 27

Analog IC Design

Parametric Design:
SR

Designed:

IT
I
= T > 4.5 V/s IT > 22.5 A IT 27 A.
C LOAD 5 pF

IT 27 A

I9/10 1.5IT = 40.5 A I9/10 40 A and I3456 = I9/10 0.5IT 27 A.

50 V
A V g m12 ( rds4 || R D6 ) g m12 rds4 = g m12
> 100 V/V
13.5 A

I9/10 40 A
I3456 27 A

g m12 2 ( 0.5I T ) K N'S12 = 2 (13.5 A) (100 A/V 2 ) S12 > 27 S

S12 5
S34 10

S12 > 0.27, but for good matching S12 5.

v O(MIN) = VSS + VDS4(SAT) VSS +

2I 4
3 V +
K N'S34

2 ( 27 A )

(100 A/V ) S
2

34

< 2.6 V

S34 > 3.4 S34 10.

v O(MAX) = VDD v SD10 + VSD6(SAT) 3 V VSD10(SAT) VSD6(SAT) > 2.2 V

VSD6(SAT) =

2I 6

K P'S56

2 ( 27 A )

( 40 A/V ) S
2

56

< 0.4 V

2I 9/10
=
K P'S9/10

I3456 27 A

2 ( 40 A )

( 40 A/V ) S
2

IT 27 A
I9/10 40 A

S56 > 8.4 S56 15.

VSD9/10(SAT) =

Designed:

9/10

< 0.4 V

S12 5
S34 10

S9/10 > 12.5, but letting IB1 = IB9/10 2 A means I9/10 = 20IB9/10:

S56 15

WB9/10 LB9/10 SB9/10 1.

SB9/10 1

W9/10 20WB9/10 = 20L9/10 S9/10 20 > 12.5.

S9/10 20

Page 28

Analog IC Design

VOS should be low.

Designed:

M12, M9/10 (and MB9/10), and M34 should match well L 6 m.

M56 should match L 3 m.

IT3456 27 A

Response should be predictable Low channel-length modulation effects.

MB, MB1, MB2, and MT should match L 3 m.

I9/10 40 A
S12 5

v IC(MIN) = VSS + VDST(SAT) + v TN + VDS12(SAT)

= 3 V +

2 ( 0.5I T )
2I T
+ 0.6 V +
< 1.5 V
K N'ST
K N'S12

S34 10
S56 15
SB9/10 1
S9/10 20

ST > 1.40, but since IT = 27IBIAS:

WB WMIN 3 m = LB SB 1.
WT 27WB = 27LT ST 27 > 1.40.

L12349B9/10B10 6 m
L56BB1B2T 3 m
SB 1, ST 27

IVDD = IB + IB1 + IB2 + IT + I3 + I4 = 1 A + 2 A + IB2 + 3(27 A) < 100 A.

Designed:

IB2 = IB56 2 A
WB1 WB2 2WB = 2LB1 = 2LB2 SB1/B2 2.
v SD9/10 = VSDPC(SAT) VSD56(SAT)

2I B2
2I3456

0.4 V
K P'SB56
K P'S56

1/SB56 4.9

IT3456 27 A
I9/10 40 A
S12 5
S34 10
S56 15

LB56 5WB56 5WMIN 5(3 m) 15 m.

SB9/10 20
L12349B9/10B10 6 m

Design Check:

L56BB1B2T 3 m

vIC(MAX) = VDD vSD9/10 + vTN

SB 1, ST 27

3 V 0.4 V + 0.6 V = 3.2 V > 2.5 V

Page 29

SB1/B2 2, SB56 3/15

Analog IC Design

iv. Simulations
Simulate only when you believe you know what to expect.
To verify and tweak performance only, not to design.
Meet worst-case conditions plus margin with nominal models.
Across supply voltages, input range, load range, temperature, etc.
Meet worst-case conditions across fabrication corners.
With combinations of weak, strong, and nominal
transistor, diode, resistor, and capacitor models.
Common Term: PVT Worst-case simulations across
process, voltage (but more generally, conditions), and temperature.

Bias
Bias in unity-gain configuration when VIN is within its ICMR.
Monitor all dc node voltages and currents.
Ensure all transistors are in the
desired region of operation.

Static Parameters
Quiescent Power PQ: Bias the same way and
monitor iVDD(vDD vSS).
Input-Referred Offset VOS: Bias the same way.
VOS vIN vO.
Output Swing vO(MAX): Fix VIC within its ICMR,
sweep vIN slowly below and above vIC, and monitor vO's swing limits.

Page 30

Analog IC Design

Input Common-Mode Range ICMR:

Bias in unity-gain configuration.
Sweep vIN slowly.
Monitor vO and iTAIL.
ICMR when vO vIN and
iTAIL is nearly unchanged.
Valid only when vO is within vO(MAX).

Dynamic Parameters
Open-Loop Gain AV: Bias in unity-gain
when VIN is within ICMR, nil ac feedback with LDC 1 kH
and CAC 1 kF, inject ac signal with vin 1, and monitor vo = vinAV AV.

Open-Loop Gain AV: Simulated Response

ACL0 1 and A CL0 = 0
LDC opens
CAC shorts

ACL rises +40 dB/dec.

past pLC when ZL = ZC.

AV0 later limits gain ACL AV.

! Z +Z $
A CL = A V || # L C &
" ZC %
If AV limits ACL past
AV's first pole p1,
raise LDC and CAC
until AV's AV0 limits ACL.

If RDC replaces LDC: ACL rises past pRC +20 dB/dec. when ZL = RDC.
RDC loads AV when CAC shorts RDC should be high.

Page 31

Analog IC Design

Power-Supply Gain AVDD/VSS:

Bias in unity-gain configuration.
Nil ac feedback with LDC and CAC.
Inject ac signal with vdd 1 or vss 1.
Monitor vo = vddAVDD AVDD or vssAVSS AVSS.
Power-Supply Rejection Ratio PSRR:
Bias in unity-gain configuration.
Inject ac signal with vdd 1 or vss 1.
Monitor vo vddAVDD/AV 1/PSRR+.
or

vssAVSS/AV 1/PSRR.

Approximation up to f0dB.

Common-Mode Gain AC:

Bias in unity-gain configuration.
Nil ac feedback with LDC.
Inject ac signal with vin 1
to both inputs through CAC.
Monitor vo = vicAC AC.
Common-Mode Rejection Ratio CMRR:
Bias in unity-gain configuration.
Inject equal ac signals to inputs with vin 1.
Monitor vo vicAC/AV 1/CMRR.
Approximation up to f0dB.

Page 32

Analog IC Design

Slew Rate SR:

Bias in unity-gain configuration.
Inject fast and
high-amplitude pulses with vIN.
Example: 2 V with 1-ps rise and fall times.
Monitor rising and falling vO in V/s or V/ns.
Stability Test:
Bias in unity-gain configuration.
Inject fast and high-amplitude pulses
with vIN, vDD, vSS, and/or load iLD.
Monitor vO: vO should settle within 1%5% of target with less than 34 rings.

Page 33