Analog IC Design

Analog IC Design
An Intuitive Approach
Gabriel Alfonso Rincn-Mora
Georgia Institute of Technology
Rincon-Mora.gatech.edu

CONTEXT

Chapters
1. Microelectronic Systems

3. Single-Transistor Primitives
4. Analog Building Blocks
5. Negative Feedback

APPLICATION

U
D

FOUNDATION

2. Microelectronic Devices

6. Operational Amplifiers
7. Comparators
8. Reference Circuits
Final Notes on Analog IC Design

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Analog IC Design

1.1. Emerging Applications

Applications: Bio-monitors, micro-sensors, pacemakers, cochlear processors,
10200 W

defibrillators, hearing aids, reconnaissance, micro-robots, remote meters,

Peak to 510 W

0 22 mW

110 mW

Micro-sensor

neural recorders/stimulators, retinal implants, and others.

1100 mW

40250 mW

Requirements: Useful, unobtrusive, and economical.

Lightweight
Self-powered (with onboard power source)
Self-sustained (with ambient energy)
Silicon microchip (i.e., on-chip, in-package,
and on-package integration)

Bio-monitor

Portable (i.e., small and compact)

Micro-robot

Smart (e.g., low-power sensor, processor, transmitter, etc.)

1.2. Technological Constraints

Portable and Unobtrusive

Small Footprint: 1 Microchip

Low Breakdown Voltages

Low Supply Voltages: 11.8 V

High Integration

Diverse Power Levels: nW's to W's

Diverse Supply Voltages: 0.52 V

Low Filter Density

Low CMAX/m2 15 fF/m2

E.g.: 1 nF requires 260 260 m2
LMAX 40100 nH

Noise-Sensitive (analog) Blocks

Accurate and Fast Supplies:

vSUPPLY(DCRIPPLEDUMPS) 10100 mV

High Silicon (wafer) Density

Digital VLSI (CMOS) and

Mixed-Signal (BiCMOS) Microchips

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Analog IC Design

Parameter

1.3. System
Requirements

Linear Regulator
Vout (overall accuracy)
Line Regulation
Load Regulation
Short Ckt. Current

Specifications
Min.
Typ.
2.85

Max.
3

Simulated Perf.
Min.
Typ.
Max.

3.15
10
50

2.87
3
190

Meas. Perf.
Mean Sigma

3.1
7
42
250

3.05
10
45
225

0.1
2
5
30

Un

V
m
m
m

Reference

Low breakdown voltage and low battery voltage Low supply headroom (margin).
Long life, little board space, and no heat sinks Low power consumption.
Accurate and high performance, but with low dynamic range (low signal/noise ratio).
On chip High power-packing density, low exposure to high voltages, and
low interface power (i.e., less parasitic capacitance to charge and discharge).
Cross-coupled, substrate-injected, and electronic noise Suppress noise.
Noisy supply Reject supply noise High power-supply rejection.
I.e.: Highly functional: complex, fast, accurate, low cost: CMOS and few components,
small: SoC/SiP/SoP, long life: low power, reliable: few transistors, etc.

1.4. Objectives
Present, discuss, and show how to understand, develop, and use
semiconductor devices to design analog integrated circuits (ICs).
Develop and illustrate how to model, analyze, and design analog ICs
using bipolar, CMOS, and biCMOS technologies.
Develop basic understanding and critical-thinking skills, in other words,
insight and intuition for how semiconductor devices work
individually and collectively in microelectronic circuits.
Furnish a physical and insightful view of solid-state circuits that
transcends rigorous mathematical and algebraic formulations
to empower the engineer with the tools necessary
to design practical, high-performance, and innovative ICs.

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Analog IC Design

Chapter 2. Microelectronic Devices

Outline
2.1. Resistors
2.2. Capacitors
2.3. PN-Junction Diodes
2.4. Bipolar-Junction Transistors
2.5. MetalOxideSemiconductor Field-Effect Transistors
2.6. Junction Field-Effect Transistors
2.7. Practical Considerations

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Analog IC Design

2.1. Resistors: A. Theory of Operation

Materials (diffusion, poly-silicon, etc.) offer resistance to charge carriers.
Resistance rises with length LX and falls with cross-sectional area AX (i.e., WXTX).
L
L
RX = X X = X X
AX
TX WX

Sheet Resistance

RS = X
TX

!L $
R X = R S # X & = R SN X
" WX %

(of one square)

WX and LX are design variables.

X Resistivity

NX Number of Squares

Parasitics
PR = i R v R

v R = iR R X

A dielectric isolates resistors from substrate Parasitic CPAR in all R's.

B. Physical Layout:
i. Unmatched
Dog-Bone Structure

RX 7RS

For high resistances,

use narrow
serpentine resistors
Approximation:
10 corners can be
roughly equivalent
to 5 squares.
Usually, RS is 20500 /Square and tolerance is 20%.

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Analog IC Design

ii. Matched
Eliminate
corner

No Corners

mismatch.
Reduce
gradient

Close Array
(square)

effects.
Reduce
edge
mismatch.

Wide Strips
Dummy Strips

RA = 2RB

Average and match effects

Common Centroid

of two-dimensional gradients.

Interdigitated Strips and Statistical Spread

This way, resistors can match within 0.5% to 1%.

Cross-coupling components into a modular/square array

reduces maximum distance dMAX and related nonlinear spread effects.
No corners
Close Array
Wide Strips
Dummy Strips
Common Centroid

RA RA1 + RA2 + RA3 + RA4 = RB1 + RB2 + RB3 + RB4 RB

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Analog IC Design

2.2. Capacitors: A. Theory of Operation

An electric field FLD induces charge flow (i.e., current iC)
and disconnected parallel plates accumulate charge qC,
so the field (i.e., voltage vC) across the plates rises.

Capacitance CP is how much charge qC the device holds

(i.e., permits) with a voltage vC.
CP =

qC
vC

q C = CP vC

iC

and

" dv %
dq C
= CP $ C '
# dt &
dt

I.e.: An electric field FLD across parallel plates

holds (i.e., stores) charge (i.e., energy).

Larger surface areas AP = WPLP collect more charge and

less separation dP intensifies the field and attracts more charge,
CP rises with higher WP and LP and lower dP.
!A $
!W L $
C P = # P & P = # P P & k P0 = WP L P C "
" dP %
" dP %

Permitivity
WP and LP are design variables.

iC causes vC Capacitors offer impedance:

ZC

dv C dt
1
=

sC P
di C C P

Parasitics

Plates offer resistance Parasitic RP in all C's.

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Analog IC Design

B. Physical Layout: Matched

Top View

CA = CB
Overlap bottom plate to reduce edge variation to that of one plate Top place sets C.
Improve Matching Performance:
Large Area and Dummy Strips (shown)

Common Centroid (not shown)

Statistical Spread (not shown)

Cross-Coupled Devices (not shown)

Typical tolerance is 20% and matching can be within 0.5% to 1%.

Thin oxide (TOX) separates topbottom capacitor plates.

Capacitor sits on thick field oxide (FOX).
The same layers of dissimilar structures do not always align.
Capacitor

Matching Top Plate

Misaligned

To minimize mismatches from dissimilar peripheries

like "etching effects", ensure peripheries match and align.

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Analog IC Design

(3)

2.3. PN-Junction Diodes:

A. Theory of Operation
(4) iDIFF = iDRIFT iD = 0.

(2)

(1)

Energy-Band
Diagram
Conduction Energy EC: Electrons e above EC are loosely bound Available.
Valence Energy EV: e below EV are tightly bound Only holes h+ are available.
No charge carriers across the "band-gap" energy EBG.
Fermi Energy EF: Highest probability of finding a charge carrier at 50%.
Probability of finding a charge carrier falls exponentially away from EF.
Lightly doped regions are easier to deplete Depletion width 1/NDOPANTS.

Forward-biasing junction with vD > 0 reduces barrier iD exp(vD).

Raising vP pushes holes toward depletion region dDEP shortens.
iDvD Curve

v
i D = IS exp D 1 A J
Vt

Reverse-biasing with vD < 0 raises barrier iD IS Junction Area AJ Near 0.

Lowering vP pulls holes away from depletion region dDEP lengthens.

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Analog IC Design

Breakdown when vD << 0: Avalanche and tunneling conduction, so iD < 0.

Tunneling: Energized electrons tunnel

across short depletion region.
Avalanche: Energized electrons crash
into and free bounded electrons.
Highly doped junctions exhibit thinner depletion regions Tunneling is more likely.
Wider depletions require more energy (higher voltages) to tunnel than to avalanche.
Tunneling saturates highly doped junctions and avalanche lightly doped junctions.

B. Physical Structure and Layout

Immerse P+ into an N well in the P substrate.

Well-in-substrate diode DPAR junction-isolates DX from the substrate and other devices.
Top View
N+-in-

P+-in-

P Base

N Well

Diode

Diode
P-Type Substrate

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Analog IC Design

C. Small-Signal Model
Analog Strategy: First, bias. Then, vary small signals about bias.
Linear projection of small signals about bias is a reasonable approximation.

Slope is first derivative of iD evaluated at VD.

Parasitics

"I
"I %
" di %
v
V %
i d = v D $$ D '' = v d $$ S exp D '' v d $$ D '' v d g d d
dv
V
V
V
rd
# D&
# t
# t&
t &

CDEP:

Parallel plates across the depletion region also hold charge CDEP.
Plates separate with higher reverse voltage CDEP falls with vD.
Model zero-bias junction capacitance per unit area with CJ0"
C DEP =

CDIF:

A J C J0 ''
A
J
WDEP
vD
1
VBI

Peripheral sidewall depletion region

also holds charge Higher CDEP.

Recall capacitance is how much charge a device holds with voltage.

Charge qC crosses in forward transit time F vD holds in-transit qC.
C DIF =

dq C ! dq C $ ! 1 $ ! di D $
=#
&=#
& = gd F
& #
dv D " dt % F #" dv D &% #" dv D &% F

F Forward Transit Time

C D = C DIF + C DEP

In reverse bias, qC(DIF) << qC(DEP) CD(REV) CDEP.

In forward bias, qC(DIF) >> qC(DEP) CD(FWD) CDIF >> CDEP.

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Analog IC Design
Emitter e's diffuse into such

2.4. Bipolar-Junction Transistors:

a short base that field

sweeps them to

A. Theory of Operation
iE = iC + iB iC

the collector.

because NE >> NB.

(2)

(1)

iC = f(vBE) = iD(BE) exp vBE.

(3

(1) Fwd-bias baseemitter.

(2) Rev-bias basecoll.

Energy-Band
Diagram

(3) Short base WB.

(1)

WB' shortens with higher vC

iC collects more electrons e,
iC vCE, but only slightly Base-width modulation.

v v

v v
iC IS exp BE 11+ CE IS exp BE 1+ CE A E
Vt VA
Vt VA

VA Early Voltage

iC N E

iC F0iB and i E = i C + i B = F0i B + i B = i B F0 +1

iB NB

B. Large-Signal Model

Symbol

AE Emitter Area

iCvCE Curve

Exponential

Emitter "emits" charge carriers, collector "collects" them,

and base was the "physical base" of the first prototyped transistor.
Forward Active: Small iC produces large vCE High gain.
Saturation: When basecollector junction forward biases, junction steals some iB.
BJT is symmetrical Transistor also has a reverse active region,
except emitting doping concentration is lower than that of base R < F.

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Analog IC Design

C. PNP BJT
With a forward-biased emitterbase junction vEB > 0.
Emitter holes diffuse into the base Emitter receives current iE.
Base electrons diffuse into the emitter Base outputs current iB.
With a short base and a reverse-biased collectorbase junction vBC 0.
Diffused emitter holes in base drift to collector Collector outputs iC.
Since emitter concentration is much higher than base concentration:
iC's h+'s is F times higher than iB's e's iC = FiB.
A lower vC further reverses the basecollector junction, so
Depletion region extends and base width shortens.
I.e., Base-width modulation raises iC.

v v

v v
iC IS exp EB 11+ EC IS exp EB 1+ EC A E
Vt VA
Vt VA

D. Physical Structure and Layout

Vertical NPN BJT

Immerse N+ into a P base inside an N well in the P substrate.

Parasitics
Well-in-substrate diode junction-isolates vertical NPN from substrate and other devices.
Top View

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Analog IC Design

Immerse two close P+ regions into an N well in the P substrate.

Lateral PNP BJT
Parasitics

Current Mirror
Top View

iC1 = iC2 0.5iC

Immerse P+ into an N well in the P substrate.

Substrate PNP BJT

Parasitics

Because the well region is lightly doped, depletion region is:

Wide Base width can be narrow SUB can be high.
Sensitive to vEC Base-width modulation can be high VA is typically low.
Collector/substrate terminal is always connected to a supply rail Not flexible.
Substrate BJTs feed current into the substrate They generate substrate noise.

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Analog IC Design

E. Small-Signal Model
Linearize at bias point in forward active or lightly saturated region, where
iE = iB + iC

iB = f(vBE)

and

Currents

iC = f(vBE, vCE).

Simplified

Model

iBE = f(vBE) r

Complete Model

iCE = f(vCE) ro

Note that a current that is a linear translation of its voltage behaves like a resistor.

Currents:

#I &
# i &
gm ic vce =0 v be % C ( v beg m v be % C (
$ v BE '
$ Vt '
#g & v
# i & v # i &
r i b v be % B ( = be % C ( = v be % m ( be
$ v BE ' 0 $ v BE '
$ 0 ' r
# i &
#I & v
ro ic vbe =0 v ce % C ( v ceg o v ce % C ( ce
$ VA ' ro
$ v CE '

CBE is in forward bias

C C BE = C DIF + C DEP q

DIF >>q DEP

C DIF =

dq DIF iC F
=
= gm F
dv BE v BE

CBC is in reverse bias

C C BC = C DIF + C DEP q

DIF <<q DEP

C DEP =

+ Peripheral Sidewall Capacitance

A BCC JBC0 "

v
1+ R(BC)
VBI

Normally, igm >> ir >> iro 1/gm << r = 0/gm << ro.

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Analog IC Design

Maximum Bandwidth:

ic

ib

Transistor is useful as an amplifier only when short-circuit current gain AI ic/ib 1.

Except, C and C steal current from r AI falls with frequency.
Highest useful bandwidth (i.e., speed) is when AI ic/ib 1 at vce = 0.
iro = 0
ic
ib

(test condition for AI's two-port model)

=
v ce =0

v beg m
ib

"
%( g + "
%
1
r
= i b $r ||
'* m - = $
'g m
$# (C + C )s '&) i b , $#1+ r (C + C )s '&
v ce =0
fT

gm
2(C +C )

at Transitional Frequency fT Faster with higher current and a smaller geometry.

2.5. MetalOxideSemiconductor Field-Effect Transistors:

A. Theory of Operation
Profile View of N-Channel MOSFET

(of holes)

! v $(
! v $+
!W$
i D(SUB) = # & IST exp # GS &*1 exp # DS &"L%
" nVt %)
" Vt %,

(of holes)

v DS >4Vt

!v $
!W$
# & IST exp # GS &
"L%
" nVt %

n 1.53 and iD(DIF) saturates when vDS > VDS(MIN) 4Vt.

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Analog IC Design

(Channel)
Inverted Channel Resistance RChannel: Ohm's Law
i D(TRI) =

v DS

R CHANNEL

vTN N-Type Threshold Voltage

!W$
!W$
= v DS # & N q CHANNEL = v DS # & N COX"()( v GS v TN ) 0.5v DS *+
"L%
"L%

"W%
$ ' K N' ( v GS v TN ) v DS
#L&

v DS <VDS(SAT)

N Mobility of Electrons
Transconductance Parameter KN' = NCOX"

Raising vD pulls charges back to drain qCHANNEL falls, RCHANNEL rises, and iD falls.
Triode or ohmic region when vCHANNEL = vDS iD = f(vGS, vDS).
Note that extending channel length L raises the barrier that source and drain
carriers must overcome to connect Threshold vTN L (slightly).

Raising vD pulls charges back to drain.

q C = COX v OX = COX ( v GD v TN ) v

G v D =v TN

= 0 VDS(SAT) VDS Pinch = v GS v TN

When vDS(X) = vGS vTN VDS(SAT), q(X) = 0 and vCHANNEL = Constant = VDS(SAT).
iD saturates at vDS(X) = VDS(SAT), vD field sweeps charges across depletion region.
vD effectively shortens L, which results in slight channel-length modulation.
i D(SAT) =

"W%
VDS(SAT)
VDS(SAT) $ ' K N')*( v GS v TN ) 0.5VDS(SAT) +,(1+ N v DS )
#L&
R CHANNEL
VDS(SAT)

"W%
2
2i D
0.5$ ' K N'( v GS v TN ) (1+ N v DS ) VDS(SAT) v GS v TN
W
#L&
K N'
L
Channel-Length Modulation Parameter 1/V
A

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Analog IC Design

Bulk Effect: Lowering the bulk voltage vB below the source vS

pushes electrons back to the source.
RCHANNEL rises when vBS < 0 V Model as rise in vT.
v TN = VTN 0 + N

2 v BS 2

VTN0 Zero-Bias Threshold

N Bulk-Effect Parameter 0.40.6 V

Note vTN = VTN0 when vBS = 0 V.

2 Surface Potential 0.6 V

B. Large-Signal Model

Symbol

iDvDS Curves

Square Law

Source "sources" charge carriers

and drain "drains" them.
In Saturation: Small iD produces large vDS High gain.
MOSFET are normally symmetrical devices They are reversible:
Symmetrical reverse saturation and reverse triode regions.
Nomenclature: VDS(SAT) vGS vT vGST Overdrive or gate drive.

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Analog IC Design

C. Capacitances
Oxide Capacitances: Gate-to-Source/Drain/Bulk COX"WOXLOX.
Oxide Capacitances across Regions

Gatesource/drain overlap length LOL can be 48 lower than LMIN.

Depletion Capacitances
CSB =

A SBC JSB0 "

v
1+ R(SB)
VBI

C DB =

A DBC JDB0 "

v
1+ R(DB)
VBI

+ Peripheral Sidewall Capacitance

D. P-Channel MOSFET

Raising vG accumulates electrons underneath the gate.

Lowering vG depletes the region underneath the gate of electrons.
Lowering vG a threshold |vTP| below vS and vD pulls holes
from source and drain to invert the channel.
Lowering vD pulls holes away from channel to the point channel pinches.
i D(SAT) =

"W%
2
VSD(SAT)
0.5$ ' K P'( v SG v TP ) (1+ P v SD )
#L&
R CHANNEL

Raising vB pushes holes back to source to lower iD vSB < 0 raises |vTP|.
v TP = VTP0 + P

2 v SB 2

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Analog IC Design

E. Transistor Variations

F. Physical Structure

Symbols illustrate physical traits.

Substrate N-Channel MOSFET

Parasitics

Welled P-Channel MOSFET

Parasitics
If MOSFET is large, IS in reverse-biased wellsubstrate junction
can be large enough to de-bias well (drop a voltage) and activate QS.
Substrate current iSUB through QS injects noise
and produces possible latch-up conditions.
The drain's low vD usually shuts QD QD is usually less problematic.

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Analog IC Design

G. Physical Layout and Matching

Top Views:
Gate overlaps source/drain terminals to ensure channel connects to terminals.
Overlap Length LOL
Effective Length LEFF
LEFF = LDRAWN 2LOL

Matching Techniques:
Close

Same Orientation

Modular Square Array

Common Centroid

Large Gate Areas

Cross-Coupled

Dummy Gate Strips

Statistical Spread

Field-oxide (FOX) dummy Passive dummy.

Thin-oxide (TOX) dummy Active dummy.

MOSFETs surrounded by active dummies match better.

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Analog IC Design

H. Small-Signal Model
Linearize at bias point in saturation, where
iG = 0

and

iD = iS = f(vGS, vBS, vDS).

Currents

Simplified

Model

Complete Model

iDS = f(vDS) rds

Note that a current that is a linear translation of its voltage behaves like a resistor.

Currents:

# i &
# I &
#W&
gm id vds =0,vbs =0 v gs % D ( v gsg m v gs 2I D K N' % ( or v gs % D (
$L'
$ nVt '
$ v GS '
Inversion

gmb i d v

ds =0,v gs =0

Subthreshold

# i &
# i &# dv &
# i &# dv &
v bs %% D (( = v bs %% D ((%% TN (( = v bs %% D ((%% TN ((
$ v BS '
$ v TN '$ dv BS '
$ v GS '$ dv BS '
(
(
%
%

g m
** = v bs ''
** v bsg mb
v bsg m ''
& 2 2 VBS )
& 2 2 VBS )

# i &
v
rds id vgs =0,vbs =0 v ds % D ( v dsg ds v ds ( N I D ) ds
rds
$ v DS '

Normally, igm >> igmb >> irds 1/gm << 1/gmb << rds.
Bandwidth: Highest useful bandwidth is at fT when AI id/iin 1 at vds = 0 irds = 0.
id v gsg m
=
ig
ig

g
ig
=
m
(CGS + CGD ) s ig
v ds =0
fT =

gm
2(CGS +CGD )

Page 22

Higher fT with
higher current and
a smaller geometry.

Analog IC Design

Current: iD carries diffusion and drift currents iD = iD(DIF) + iD(FLD).

gm: Exponential gm(BJT) > n-Suppressed exponential gm(SUB) > Square-law gm(INV).

IDL
VDS(SAT) = 2nVt VDS(SUB).
2
2n 2 Vt K '
Weak Inversion: 50 mV of transition VDS(SAT) vGS vT 2nVt 50 mV.

Transition: At gm(SUB) = gm(INV) WCH(SUB) =

Warning: Models usually do not emulate weak inversion well.

gm rises with W in strong inversion and peaks in subthreshold.
fT falls with 1/W in strong inversion and with 1/W in subthreshold.

gmfT
Tradeoff

For high gm, edge subthreshold WCH should not exceed WCH(SUB) by much.

I. MOS Capacitor
PolyChannel/Bulk MOS Capacitor

If vC vSG > |vTP|, channel inverts CMOS CINV 2COL + CTOX.

If 0 < vC < |vTP|, channel depletes CMOS CDEP 2COL + (CTOX CDPL).
If vC < 0, electrons accumulate CMOS CACC 2COL + CTOX CINV.
Note CINV CACC > CDEP, except CINV's series resistance is lower than in CACC.

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Analog IC Design

J. Channel Resistor
Bias MOSFET in triode and use channel as resistor.
Resistance:
Increases with resistivity X and length LX.

RX =

Decreases with width WX and thickness TX.

X L X X L X
=
AX
WX TX

For high resistance:

High resistivity Lightly doped channel.
In strong inversion for M's.

Low gate drive vGST.

In subthreshold for G's.

Shallow channel Lightly inverted channel.
Long channel LLONG.
Short width WSHORT.

Note LX and WX are well-defined in triode Moderate tolerance.

2.6. Junction FETs: A. Theory of Operation Profile View of N-Channel JFET

vGS enhances channel and vDS pinches channel.

Triode: iD = vDS/RCHANNEL and RCHANNEL L/W and 1/vGS
i D(TRI) =

!W$
v DS
= v DS # & K JN ()( v GS + VPN ) 0 5v DS *+
"L%
R CHANNEL

"W%
v DS $ ' K JN ( v GS + VPN )
#L&
v DS <VDS(SAT)

Saturation: Channel pinches iD = VDS(SAT)/RCHANNEL f(vDS)

q C = C DEP v DEP = C DEP ( v GD + VPN )
i D(SAT) v

DS >VDS(SAT)

v G v D = VPN

= 0 VDS(SAT) VDS Pinch = v GS + VPN

"W%
VDS(SAT)
2
0.5$ ' K JN ( v GS + VPN ) (1+ N v DS )
#L&
R CHANNEL

VPN N-Channel Pinch-Off Voltage < 0

Channel-Length Modulation Parameter

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Analog IC Design

B. Physical Structure
Profile View of P-Channel JFET

vSG enhances channel and vSD pinches channel.

Parasitics
Substrate
JFET

Welled
JFET

C. Layout
Top Views
Substrate JFET

Welled JFET

P-Type Substrate
Overhang of top gate over channel ensures entire channel pinches.

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Analog IC Design

D. Small-Signal Model
Linearize at bias point in saturation, where
iG 0

and

Currents

iD = iS = f(vGS, vDS).
Simplified

Model

Complete Model

iDS = f(vDS) rds

Note that a current that is a linear translation of its voltage behaves like a resistor.

# i &
#W&
Currents: gm id vds =0 v gs % D ( v gsg m v gs 2I D K JN % (
$L'
$ v GS '
# i &
v
rds id vgs =0 v ds % D ( v dsg ds v ds ( N I D ) ds
rds
$ v DS '

Capacitances:

C DEP =

A J C J0 "
v
1+ R
VBI

+ Peripheral Sidewall
Capacitance

Bandwidth: Highest useful bandwidth is at fT when AI id/iin 1 at vds = 0 irds = 0.

id v gsg m
=
ig
ig

!
$' g *
ig
=#
&)) m ,,
C
+
C
s
#
&%( ig +
(
)
"
GS
GD
v ds =0
fT =

gm
2(CGS +C DG )

Higher fT (i.e., faster) with higher current and a smaller geometry.

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Analog IC Design

2.7.A. Electronic Noise

Thermal Noise:
Thermally charged carriers collide randomly to produce thermal (white) noise.
Norton
Equivalent

4kT
i NT

RX
f
2

Thvenin
Equivalent

2
2
v NT " i NT % 2
=$
' R X 4kTR X
f # f &

Where k Boltzmann constant and T Temperature.

MOS channel carriers similarly generate thermal noise:
" 1 %
R EQ K X $ '
# gm &

Shot Noise:

!
3
#
Long Channel
Where K X = "
2
# 2 to 3 Short Channel
$

Discrete carriers diffuse and recombine randomly

2
i
across PN junctions to produce shot noise: NS 2qI D .
f

Flicker 1/f Noise:

Random gate-surface imperfections (i.e., traps) alter charge flow to
produce (pink) noise that diminishes when operating frequency climbs.
K F ID
i NF

f COX"L X 2f
2

Gate-Voltage
Referral

2
2
KF
v NF " i NF %" 1 %
=$
'$ 2 '
f # f &# g m & 2WX L X N/P COX"2 f

JFETs and vertical BJTs conduct current well below the surface.
They produce less flicker noise than MOSFETs.
Noise Data:
iN is usually measured with the emitter and source terminals grounded.
Empirical data shows that PMOSFETs generate less noise than NMOSFETs.
Noise current is usually in pA/Hz Can treat as small signals.

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Analog IC Design

B. Absolute and Relative Accuracies: Passive Devices

Tolerance Matching
Absolute
Accuracy

Relative
Accuracy

Temperature
Coefficient

Voltage
Coefficient

20%

0 5%1%

+20 ppm/C

50 ppm/V

20%

0 5%1%

+25 ppm/C

10 ppm/V

Base Diffused R

100200 /sq

20%

2%

+1750 ppm/C

Emitter Diffused R

210 /sq

20%

2%

+600 ppm/C

S/D Diffused R

10100 /sq

20%

2%

+1500 ppm/C

200 ppm/V

Components

Range of Values

MOS C

0 315 fF/m

PolyPoly C

0 315 fF/m

N-Well R

110 k/sq

40%

5%

+8000 ppm/C

10 kppm/V

Pinched Base R

210 k/sq

50%

10%

+2500 ppm/C

Poor

Pinched Epitaxial R

25 k/sq

50%

7%

+3000 ppm/C

Poor

Implanted R

0 52 k/sq

20%

2%

+400 ppm/C

800 ppm/V

Poly R

30500 /sq

20%

0 5%1%

+1500 ppm/C

100 ppm/V

Thin-Film R

0 12 k/sq

5%20%

0 2%2%

+10200 ppm/C

Costly

Passive and Active Devices

Three-Sigma (3) Matching Performance
Resistors/Capacitors: R* and C* can be 0.5% Best.
Transistors:

iC/D* can be 5%15%.

BJT's exponential gm = IC/Vt suppresses %IC to vBE %Vt 14 mV.

MOS's subthreshold gm = IC/nVt suppresses %ID to vGS %nVt n(14 mV).
MOS's square-law gm suppresses %ID* to:
Matching Hierarchy

v GS

%VDS(SAT)
%
%I D
2I D
=
=
5 15 mV
K'(W/L)
2
2
2I D K'(W/L)

Critical Matching: Close, modular (i.e., square), same orientation, cross-coupled,

common centroid, dummy devices, and statistical spread, and for low piezo
effects, no metal routes above, uniform sheets of top-level metals above, etc.
Good Matching: Close, modular (i.e., square), and same orientation.
Nominal Matching: Close.

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Analog IC Design

C. Fabrication: Process Flow

Start with silicon wafer: substrate, grow silicon epitaxially, ion-implant (fire) dopants
on or below surface, diffuse gaseous dopants thermally, grow oxide regions,
deposit materials (e.g., poly-silicon, metal, etc.), and etch away undesired materials.
TEOS: TetroEthyl
Ortho Silicate

Sample
0.8-m CMOS

RPoly

Thicknesses:

CPolyPoly
CMtlMtl

Metal 1 0.5 m
FOX 1 m
TOX 14 nm
Anti Punch-Through

SOG: Silicon On Glass

BPSG: BoronPhosphorous doped Silicate Glass

N+/P+ 0.2 m
Process Flow

Threshold
Adjust

+ RDiff, RMOS,
CMOS, DPN

Well 2 m
Epitaxy 20 m

ND/A usually higher near surface. ND/A epitaxial layers can be grown on ND/A+ substrates.

Page 29