Chp7 CountersRegisters Part2

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Chp 7 Counters & Registers
Content
1.
Introductory Concepts
2.
Numbering Systems
3.
Boolean Algebra
4.
Combinational Logic
5.
Flip-Flops
6.
Digital Arithmetic
7. Counters & Registers Part 2

8.
IC Logic Families
9.
MSI Logic Circuits
Counters & Registers Part 2

1.
Asynchronous (ripple) Counters
2.
Counters with MOD number < 2N
3.
IC Asynchronous Counters
4.
Asynchronous Down Counter
5.
Propagation Delay in Ripple Counters
6.
Decoding a Counter
7.
Decoding Glitches
8.
IC Registers
7.4 Asynchronous Down Counters
Asynchronous Down Counter

QC
QB
CLK
QA
CLK
J
CLK
All J, K, PRESET and CLR = 1

Note:
For down counter, we connect /Q to next CLK,
but the output is still taken from Q.
Down Counter
State Transition Diagrams
000
CBA
001
111
010
110
011
101
100
Asyn Down Counter - waveform

1
10
11
12
13
14
15
16
17
CLK
CBA 000
110
111
100
101
010
011
000
001
110
111
100
101
010
011
000
001
7.11 Decoder
Design a circuit to turn on an LED for 1 s once every 13

s to signal an assembly line worker to perform some
manual operation. Assume that you have a 1 Hz clock
available.
7.11 Decoder
Design a circuit to turn on an LED for 1 s once every 13 s

to signal an assembly line worker to perform some manual
operation. Assume that you have a 1 Hz clock available.
Solution
CLK
= 1 Hz
every count last for 1 s

Need a divide-by-13 counter, i.e. Mod 13
7.11 Decoder
Design a circuit to turn on an LED for 1 s once every 13 s to

signal an assembly line worker to perform some manual
Solution, cont
CP1
CP0
mod 13 counter
74LS293
MR1 MR2
Q 3 Q 2 Q1 Q0
7.11 Decoder
Design a circuit to turn on an LED for 1 s once every 13 s to

signal an assembly line worker to perform some manual
Solution, cont
0000
0001
1011
1100
0000
(0)
(1)
Q 3Q 2Q1Q 0
decoder
(11)
(12)
(0)
every count last for 1 s
10
7.1 Asynchronous counters
Draw the output waveforms for the

following counter?
C
CLK
CLK
J
CLK
fCLK= 1MHz
tpd = 50ns
TCLK = 1/fCLK = 1us = 1000ns
11
7.5 Propagation Delay in Ripple Counters
Output waveforms for the counter on the previous slide

1
CLK
1000ns
A
50ns
B
100ns
C
150ns
3 FFs, max delay = 3 times FF tpd

12
Whats wrong with this counter?
CLK
CLK
J
CLK
fCLK= 10MHz
tpd = 50ns
TCLK = 1/fCLK = 0.1us = 100ns
13
Effect of Propagation Delay missing count

1
CLK
100ns
A
50ns
50ns
50ns
50ns
B
50ns
50ns
50ns
150ns
000
001
010
011
101
100 did not occur
14
How do you get round the problem?
15
Propagation Delay in Ripple Counter

Propagation delays tpd of the FFs add up
For Nth FF, the total delay will be N x tpd
If clock pulses are applied at high frequency,
missing state(s) may occur.
To avoid this problem, Tclock >= N x tpd
Max frequency Fmax <= 1 / (N x tpd)
16
A 4-bit ripple counter is constructed using 74LS11 JK

FFs. The FF has tPLH = 16ns and tPHL = 24ns (from CLK
to Q). Calculate fmax.
17
A 4-bit ripple counter is constructed using 74LS11 JK

FFs. The FF has tPLH = 16ns and tPHL = 24ns (from CLK
to Q). Calculate fmax.
Use worst case tpd = 24 ns

fmax. = 1/(4 x 24ns) = 10.4MHz
18
Another possible problem with counter

Decoding Glitches
tpd = 50ns
C
CLK
A
B
C
fCLK= 1MHz
A
CLK
J
CLK
X2
e.g. this is a
decoder decoding
count 2, i.e. 010
19
Decode Output Waveform

1
CLK
1000ns
A
B
C
50ns
(010)
decoder
This unwanted
output is called
a Glitch
20
To overcome glitches, apply strobe signal

tpd = 50ns
C
CLK
Strobe
(enable)
signal
A
B
C
fCLK= 1MHz
A
CLK
J
CLK
X2
21
To overcome glitches, apply strobe signal

1
CLK
A
strobe
Notice the glitch

did not occur
(010)
docoder
22
7.11 Decoding a Counter
Decoder
A decoder generates a unique output for each state
of the counter
Decoder output can be ACTIVE HIGH or
ACTIVE LOW
23
Decoder (cont)
At any one time only ONE output is ACTIVE
e.g.
Can
come
from
counter
outputs
3-bit
inputs
23
outputs
X0
QA
X1
Decoder X2
X3
X4
QB
X5
X6
X7
Q
C
24
Decoder e.g. at work

ACTIVE HIGH outputs
0
0
0
X0
QA
X1
Decoder X2
X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X0
1
0
0
0
0
0
0
0
25

ACTIVE HIGH outputs
1
0
0
X0
QA
X1
Decoder X2
X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X1
0
1
0
0
0
0
0
0
26

ACTIVE HIGH outputs
0
1
0
X0
QA
X1
X2
Decoder X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X2
0
0
1
0
0
0
0
0
27

ACTIVE HIGH outputs
1
1
0
X0
QA
X1
Decoder X2
X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X3
0
0
0
1
0
0
0
0
28

ACTIVE HIGH outputs
0
0
1
X0
QA
X1
Decoder X2
X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X4
0
0
0
0
1
0
0
0
29

ACTIVE HIGH outputs
1
0
1
X0
QA
X1
X2
Decoder X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X5
0
0
0
0
0
1
0
0
30

ACTIVE HIGH outputs
0
1
1
X0
QA
X1
Decoder X2
X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X6
0
0
0
0
0
0
1
0
31

ACTIVE HIGH outputs
1
1
1
X0
QA
X1
Decoder X2
X3
QB
X4
X5
X6
X7
QC
QA
QB
QC
X7
0
0
0
0
0
0
0
1
32

ACTIVE LOW outputs
0
0
0
/X0
QA
/X1
Decoder /X2
/X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X0
0
1
1
1
1
1
1
1
33

ACTIVE LOW outputs
1
0
0
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X1
1
0
1
1
1
1
1
1
34

ACTIVE LOW outputs
0
1
0
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X2
1
1
0
1
1
1
1
1
35

ACTIVE LOW outputs
1
1
0
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X3
1
1
1
0
1
1
1
1
36

ACTIVE LOW outputs
0
0
1
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X4
1
1
1
1
0
1
1
1
37

ACTIVE LOW outputs
1
0
1
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X5
1
1
1
1
1
0
1
1
38

ACTIVE LOW outputs
0
1
1
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X6
1
1
1
1
1
1
0
1
39

ACTIVE LOW outputs
1
1
1
/X0
QA
/X1
/X2
Decoder /X3
QB
/X4
/X5
/X6
/X7
QC
QA
QB
QC
/X7
1
1
1
1
1
1
1
0
40
Decoding Application
BCD Counter
BCD counter
counts from
0000 to 1001
BCD-to-7 seg
Decoder (7447)
g fedcba
a
f
e
b
g
d
41
BCD Counter Decoding

BCD Counter
0
BCD-to-7 seg
Decoder (7447)
g fedcba
0111111
a
f
c
d
42

BCD Counter
0
BCD-to-7 seg
Decoder (7447)
g fedcba
0000110
b
c
43

BCD Counter
0
BCD-to-7 seg
Decoder (7447)
g fedcba
1011011
a
b
e
g
d
44

BCD Counter
0
BCD-to-7 seg
Decoder (7447)
g fedcba
1001111
a
b
g
d
45

BCD Counter
0
BCD-to-7 seg
Decoder (7447)
b
g
g fedcba
1100110
and so on
46
7.18 IC Registers
IC Registers
Registers are used to store data

temporarily - while the data
awaits further operations.
47
7.18 IC Registers
IC Registers
Registers can be classified according

to the manner data is :(i) entered for storage
(ii) Output from the register
48
7.18 IC Registers
IC Registers
Different registers are:(i) Parallel in /parallel out

(ii) Serial in / serial out
(iii) Parallel in / serial out
(iv) Serial in / parallel out
49
7.18 IC Registers
IC Registers
D0
D1
D0
D0
CP
D0
CP
D1
Serial in serial out

illustration
D0
parallel in parallel out

illustration
50
The next few slides show one e.g. IC from

each category of the registers.
Refer to the text book or web site link for
detail description of each e.g. IC.
51
7.19 Parallel In / Parallel Out
Parallel in / Parallel out

D5 D4 D3 D2 D1 D0
CP
MR
74ALS174
Q5 Q4 Q3 Q2 Q1 Q0
http://www.philipslogic.com/products/als/pdf/74als174.pdf
http://www.fairchildsemi.com/ds/DM/DM74ALS174.pdf
52
7.20 Serial In / Serial Out
Serial in / Serial out

D63
Ds
CP
4731B
http://www.datasheet4u.com/download.php?id=550899
(Quad)
53
7.21 Parallel In / Serial Out
Parallel in / Serial out

P0 P1 P2 P3 P4 P5 P6 P7
Ds
Q7
CP
74ALS165
CP INH
Q7
SH/ LD
SH/ LD 0 CP, CP INH = X
parallel load (asyn)
SH/ LD 1
shift
CP INH = 0
CP
http://www.fairchildsemi.com/ds/DM/DM74ALS165.pdf
54
7.22 Serial In / Parallel Out
Serial in / Parallel out

A
B
CP
&
74ALS164
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
http://www.philipslogic.com/products/als/pdf/74als164.pdf
55
7.3 IC Asynchronous Counters
End of Counters and Registers
56

Chp7 CountersRegisters Part2

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Instructions for using the PowerPoint slides:

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Chp 7 Counters & Registers

7. Counters & Registers Part 2

MSI Logic Circuits

Chp 7 Counters & Registers

Counters & Registers Part 2

Asynchronous (ripple) Counters

Counters with MOD number < 2N

Asynchronous Down Counter

Propagation Delay in Ripple Counters

Chp 7 Counters & Registers

7.4 Asynchronous Down Counters

Asynchronous Down Counter

All J, K, PRESET and CLR = 1

Chp 7 Counters & Registers

7.4 Asynchronous Down Counters

Chp 7 Counters & Registers

7.4 Asynchronous Down Counters

Asyn Down Counter - waveform

Chp 7 Counters & Registers

Design a circuit to turn on an LED for 1 s once every 13

Chp 7 Counters & Registers

Design a circuit to turn on an LED for 1 s once every 13 s

every count last for 1 s

Chp 7 Counters & Registers

Design a circuit to turn on an LED for 1 s once every 13 s to

Chp 7 Counters & Registers

Design a circuit to turn on an LED for 1 s once every 13 s to

every count last for 1 s

Chp 7 Counters & Registers

7.1 Asynchronous counters

Draw the output waveforms for the

Chp 7 Counters & Registers

7.5 Propagation Delay in Ripple Counters

Output waveforms for the counter on the previous slide

3 FFs, max delay = 3 times FF tpd

7.1 Asynchronous counters

Whats wrong with this counter?

Chp 7 Counters & Registers

7.5 Propagation Delay in Ripple Counters

Effect of Propagation Delay missing count

100 did not occur

Chp 7 Counters & Registers

7.1 Asynchronous counters

How do you get round the problem?

Chp 7 Counters & Registers

7.5 Propagation Delay in Ripple Counters

Propagation Delay in Ripple Counter

Chp 7 Counters & Registers

7.5 Propagation Delay in Ripple Counters

A 4-bit ripple counter is constructed using 74LS11 JK

Chp 7 Counters & Registers

7.5 Propagation Delay in Ripple Counters

A 4-bit ripple counter is constructed using 74LS11 JK

Use worst case tpd = 24 ns

Chp 7 Counters & Registers

7.1 Asynchronous counters

Another possible problem with counter

Chp 7 Counters & Registers

7.5 Propagation Delay in Ripple Counters

Decode Output Waveform

Chp 7 Counters & Registers