Progress

report

:1

Reporting period: Week 10

Submitting date: 26/11/2014

Project Objectives:
The objective of this project is to design 8-bit signed number digital
multiplier using Booth Multiplier Algorithm in VHDL.
Introduction:
In this report, we will write about the project planning: first of all, we
include the project scope and then Gantt chart that illustrates the schedule
of this project. Then, we present an overview of booth multiplier and its
algorithm in VHDL.
Next, we include the overall design of 8-bit booth multiplier project including
block diagram, step by step operation flow chart, list of inputs and outputs
signal.

1. Gantt chart
Table 1: Gant chart of project planning
Week

Week 10

Week 11

Week 12

Week 13

Week 14

Task
Project planning
Overview of
booth multiplier
Flow chart of project
Overall
design
block
diagram
Booth Multiplier
VHDL design
Booth Multiplier
VHDL Testbench
Functional Simulation
LCD driver design
Testing on FPGA board
Displaying result on LCD
(X * Y)= C
1

Final Report and

interview Session

2. Project Scope
The input will be in 8 bits multiply by 8 bits which will produce 16 bits of
accurate multiplied answer.
The input and output of the system will only process and produce fixed point
value.
The system also accepts negative value which is called signed number.
VHDL (Very high speed integrated circuit Hardware Description Language) is
used as the language for the system.
All the process will be running using Quartus II 9.1 sp2 Web Edition then
implement it on Altera DE1 FPGA board to display the multiplication result.

3. Overall Project methodology

This project starts with introduction or overview of Booth
Multiplier and its algorithm rules. Then the project will continue with
VHDL designing process using Quartus II 9.1 software. Once the VHDL
design is finished and compiled successfully, then the design need to
be tested by designing the testbench VHDL code. The undesired output
resulting that the design process needs to be tested again. After that,
testbench code runs successfully then we simulate our design using
functional simulation. The flowchart of overall methodology of the
project is shown in figure 3.1 below.

Start

Project
Introduction

Booth Algorithm

VHDL

Design VHDL

Booth multiplier
VHDL

LCD Driver
design
NO

Test & simulation

Yes

Display results on
LCD
End

Figure 2: Flowchart of overall methodology of this project

4.

Booth Multiplier Overview

As we know, digital system has been used in daily life or industrial field
nowadays because of the benefits compared with analog system. Due to
crucial developing of digital system, many new complex digital devices
had been design. Some of the devices are called microprocessor,
microcontroller or microchip. It is very important to have a very high
speed performance in all the devices.
Multiplier is one of the most important parts in the devices which can
affect the performance of the devices. So, the high speed and efficient
multiplier system is important for the designers of microprocessor,
microcontroller and others digital devices. As we know, multiplication
operation is not hard to do in decimal number. But, to do the operation in
binary number (which used in digital system) is very complex operation.
This project is being done to help create a prototype of digital system
design

that

can

operate

as

multiplier

operation

that

would

be

implemented into FPGA board, microprocessor, microcontroller and other

digital devices.
4.1. Booth multiplier algorithm

Table 2 show that the Booth Multiplier Algorithm Rules, that is very
important for this project. The algorithm rules give a procedure for
multiplying binary integers in signed 2s complement representation.
Table 2: Booth Multiplier Algorithm Rules

Xi
0
0
1
1

Xi-1
0
1
0
1

OPERATION
SHIFT ONLY
ADD (Y) & SHIFT
ADD (-Y )& SHIFT
SHIFT ONLY

The table above shows the rules of booth Multiplier where X and Y
are 8-bits inputs to be multiplied. [1]

4.2 Booth Multiplier Algorithm flowchart

Start

Input

Identify
Operation
N

Ye
s

O
i + 1,
0 i 7

Xi =

Xi-1=1

Shift

Xi =

O Xi-1=0

Add -Y
then Shift

Xi = 1
Xi-1=0

Add Y
then Shift
5

Output
END

Figure 3: flowchart of booth multiplier algorithm

Figure 3 helps to understand the flow of the process easier. As we can

see, there are three main operations (shift, add Y then shift, and add Y then
shift) which are repeatedly used depends on the Value of X. The looping
process (I + 1) will loop until i is equal to the maximum number of bits in X.
After the looping process is finished, the exact Value of multiplication value is
produced booth multiplier in algorithm way for I is an integer from (0 to 7)
where the operations repeat till get the result of multiplication of X * Y 8-bits
inputs.
From figure 3 the main components can be identified as Shifter, Adder,
and Negative (change Y to negative value in 2s complement). [1]

4.3 Procedure and Example

Booth multiplier works procedure as follows:
1. If number of bits of multiplicand is u, and that of multiplier is v.
2. Firstly, draw a three row grid each with columns for u+v+1 bit. The name
is given as A (add), S (subtract), and P (product).
3. The first u bits of each row are filled i.e. for row A: the multiplicand, for row
S: the 2s compliment of multiplicand and for row P: zeroes.
6

4. The next v bits of each row are given with:

1. A: zeroes
2. S: zeroes
3. P: the multiplier
5. The last bit of each row is given with a zero.
Example: Find 2 4 with u = 4 and v = 4:
A = 0010 0000 0
S = 1110 0000 0
P = 0000 0100 0
Execution these steps v times, and do accordingly as the last two bits of
product P are obtained.
00 or 11: only arithmetic shifting.
01: P = P + A. Ignore any overflow and shift it arithmetically.
10: P = P + S. Ignore any overflow and shift it arithmetically.
LSB is ignored rest bits are the final product of multiplication of two signed
numbers. [2]
5. Overall Block Diagram
After the main component had been identified, basic block diagram is
designed as shown
in figure 4 below. This block diagram is used to get the basic idea to design
the whole system. The process contain only three main components (shifter,
adder, and negative) which will be used repeatedly depends on the value of
X. Control Unit component is added to the system to control the stability of
data and the functionality of the main components when process is running .
The main components (shifter, adder, and negative) are placed in Data Path
Unit because all the input data will be processed in this section until the
output result is produced.
7

Y(0-7)
Data Path Unit

Shifter

X(0-7)

Control
Unit

Adder
Negative

Output(0-15)

Figure 4: Overall block diagram

6. List of inputs and outputs signals

X: input with 8 bits
Y: input with 8 bits
Output: out with 16 bits as a result of (X * Y) Multiplication

7. Summary of Work Completed To Date

Overall project methodology

Booth Multiplier overview
Booth Multiplier algorithm with flowchart
Overall design block diagram
List of inputs and outputs signal
8

8. Next work to Be Done

Booth multiplier VHDL design

Flowchart of VHDL design
Block diagram of VHDL design
Booth multiplier VHDL design
Functional simulation
LCD driver design
Testing on FPGA board and debugging
Final Report

9. References
1. Meyer-Baese, U. and U. Meyer-Baese, Digital signal processing with field
programmable gate arrays. Vol. 65. 2007: Springer.
2. Akanksha Sharma, Akriti Srivastava, Anchal Agarwal, Divya Rana and Sonali
Bansal, Design and Implementation of Booth Multiplier and Its Application Using
VHD,IJSET, vol. 3 Issue No.5, pp : 561-563, 1 May 2014.
3. Brown, S.D. and Z.G. Vranesic, Fundamentals of digital logic with VHDL design.
Vol. 70125910. 2000: McGraw-Hill New York.