A LNA

Design for
O.

8um

WCDMA

Application

In

Process

CMOS

Xiao-dong Wang, Jia-you Song

School of Information Engineering, Zhengzhou University, Zhengzhou 450052, China
Abstract- This paper presents a design and optimization

CMOS Process with its operating frequency at 2.14GHz.

With given Vdd of 1.8V, Id of 5.36mA and matched
input and output, the LNA behaves good with NF of
0.655dB, gain of 16.64dB, P-1dB of -12dBm and IIP3 of
6dBm.The LNA can be used for the third wireless
communication system and other wireless transceiver.

method for low noise amplifiers (LNAs), based on the

minimization of the noise figure for a given power

consumption. The LNA design is realized through the
0.18um CMOS process with the operating frequency at
2.14GHz. Simulation results show that the amplifier draws
5.36 mA from a given 1.8 V supply voltage while keeping
the input/output impedance matched to 50Q. Furthermore,

2. Analysis for the MOSFET noise model

the circuit behaviors with 0.655 dB noise figure, gain of

The noise of MOSFET mainly gives rise to the

channel thermal noise and induced gate noise. Their
effects can be modeled by drain and gate current noise
generators[2]. These currents are partially correlated with
each other because they share a common origin, and
possess spectral power given by the following equations:

16.64dB,ldB compression point of about -12dBm and 11P3

of 6dBm.
1. Introduction

With the rapid development of wireless

communication and the coming of 3G times, the RFIC
design is now becoming a more and more attractive
subject. The silicon on insulator(SOI) CMOS technology
comes to be the top choice for the RFIC designers
because of its lower lost, lower power consumption,
higher integration and better compatibility with the
baseband digital circuit process. The SOC will finally
come true by Si CMOS Process. As a consequence, it has
recently become a hotter spot for researchers to design
the RFIC in Si CMOS Process.
Being the first block of the RF receiver system, the
low-noise amplifier(LNA) plays a crucial role for the
whole receiver performance[1]. It must satisfy the
requirements of higher gain, low NF, good linearity and
impedance matching etc. Higher gain can suppress the
noise from the following stages; The noise performance
of LNA nearly determines that of the entire receiver
directly. Good linearity permits the system working well
in a large dynamic range. This is the key problem in the
design for us to compromise between them to meet the
needs. The LNA in the paper is designed in 0.18um

(1)

4kTygdoAf

id

(2)

ig4kTggA
=

Co 2c
C 2

(3)

gg=-5gdO
1g

4f

4kT&g(d12)+4kT&gjL

wheregd0 is the drain

c_jO.395

(4)

output conductance under zero

drain bias, gg is the real part of input admittance, y is
the channel thermal noise factor, 8 is induced gate noise
factor , c stands for the correlated factor between the
two noise. See Fig 1.
For the cascode LNA we will used in the design, the
equivalent noise circuit architecture of its input stage is
shown in Fig.2.
VL2 ' Vg2 in the circuit are the noise voltage sources
generated respectively by parasitic resistor RL of the
inductor Lg and the gate resistor Rg. Here we directly
give out the noise expressions for the circuit in Fig 1.

stage ,reduce the effect between the input and the output
ports and make the impedance match much easier.
Vdd

Pi

Fig. 1 Mosfet Cross-section diagram

=-*

T7

Vt

77T

-1~~CbL

Fig.3 The Circuit Schematic of LNA

By reason that the noise matching and the power

matching are usually difficult to reach at the same time,
with a given power consumption, the capacitor Cex is
added between the gate and the source of the
transconductance mosfet MI so that the Zopt for noise
matching and the Zin for power matching become much
closer with each other. By tuning the value of Cex, NF
can be improved but gain will be drop off slightly. We
have to compromise between them to get what we want.
When doing the simulation, we found that the NFmin is
achieved while Zopt and Zin are much close but not
while they are matched at the same point. The possible
reason is the effect of the additional Cex on NF.
The L-degenaration architecture is adopted for the
input matching, because of the best advantage that it
provides a resistive component but not a real resistor
(Otherwise, the NF will be deteriorated). In this way the
noise matching is achieved with the NF not deteriorated.
As shown in Fig.3, the input impedance is expressed in
formula (8) at the resonant frequency [4]:

L,
Fig.2 The Equivalent Noise Circuit

RgRg++ / 0090
F=1+ L+
R, R, a Q, ct)T
1
OO(L, +Lg)
F R1

Rs

=1+2Ic

(5)

(6)

OoRsCgs
+ 8a

(1+Q2)

(7)

Rs is the source impedance; c)T and co are

respectively the cutoff frequency and the operating
frequency. Obviously, there is an optimum Qs for the
minimal NF, which determining the dimension of MI.
Generally its value is between 3.5 and 5.5.
All of them are institutive for our noise optimization
of the LNA. From (5), The multi-finger MI and hign Q
Lg can be selected to reduce the parasitic gate resistors
for less Noise figure.
3. LNA schematic and layout design

The paper presented a LNA with the cascode

architecture by the power-constrained simultaneous noise
and input matching technology(PCSNIM)[3]. Fig.3
shows the circuit schematic. The cascode architecture
behaviors with good isolation between the input and
the output, which can rejects the inverse leakage of the
signal appearing at the input port of the following

Zin = s(LS + Lg)+ Cgs'+ K:g:l Ls ';:ZTLS

(8)

The resonant frequency is:

=0

(L5

+ Lg gs

(9)

o-~.=> l~ine=4.832t1

Fig.4 shows the layout of LNA with the area of

0.37mm*0.575mm. In order to reduce the parasitic
resistor of MOSFET, the gate finger number can selected
a bit larger. The number of Vias for the substrate
grounded around the devices should be as larger as
possible to reduce the value of the parasitic back-gate
resistor.

Where
gmi is the transconductance of
M1 ;C gs =C gs //Ce,
C g is the parasitic capacitor
x
of MI between the gate and the source, Cex is
additional capacitor in parallel with Cgs .Here the effect
of C gdl is ignored, but its Miler effect should be
considered in fact.
Because the input impedance Zin equals to 50Q at the
input matching point, the values of Lg and Ls can be
decided as long as the MOSFET and operating frequency
are selected. When the power consumption and the
biasing voltage is determined, the gate width of MI is
also a certain value. The gate width of M2 is usually
selected between half the gate width of MI and the gate
width of MI. Of course it can be optimized for the total
NF and linearity. In order to save the power, the biasing
transistor size is about one tenth of the size of the MI.
Out of consideration for the power consumption,
linearity etc. ,the total width of MI and M2 are finally
designed as 100um and 50um respectively. The Vdd is
1.8V, Id is 5.34mA. By calculated by formulae (8) (9),
the Lg and Ls is respectively 13.3nH and 0.7nH.
Considerating the lower Q and larger dimension of
inductor in the CMOS Process library, the inductor Lg is
realized with off-chip device(Produced by Murata) and
Ls is realized with the bolding wire inductor. Ld, Cl, C2
makeup the output matching network resonating at
2.14GHz and they are on-chip devices.

4. simulated results

The LNA is designed in 0.18um CMOS Process. The

simulated results are listed in Fig 5-Fig8 and Table 1.
sn

10-

Forward Transmission, dB
~~~m4

m4

freq=2.1 40GHz
dB(S(2,1))=16541

freq=2.1 40Hz

10-

dB(S(2,2))

30 004

~m9

-20

freq=2.1 40GHz
dB(S(1 1))=- 43
mrl 0
freq=2.1 40GHz

-3p . . . . . ........=

~40-

-501.2

1.4

1-6

1-8 20

dB(S(1.2))=-32 552

28 3C1)

22 24 26

freq, GHz

Fig.5 S Parameters

Minimum NF and NF with

50 ohm terminations

4.0o

24-

3.2- ..
2.0

16-

i/{

mO

freq=2 140GHz
nf(2)=0. 65

.M
.m5
freq=2.140GHz

NFmin=0 .637

0.4
0.0

1.2

1.4

1.

1.0

2.0 2.2
freq, GHz

2.6

2.4

2.8

3.0

Fig.6 NF and NFmin

20 -.

10
,=
g1 -10-

mI

m2+ 6 4

Q.SRFpower=-12.000
~~~~~~~~~~m l

b .

71

20

RFpower=-1 2.000

-dbm out=3.350

-30- ....<...................dmotE.5

-40_
-5 3

-4,5

-40

-35

-30

-25

-20

-1l5

-1l0

RFpower

Fig.7 PIdB

FO

m ~~~~~~~I i1

RF;oer

Fig.4 Layout of LNA

Fig.8 IIP3

4Th

Table t Summary of LNA Measurements

Vdd

1.8V

NF

0.655dB

Power dis.

<10mW

NFmin

0.637dB

S21

16.64dB

IIP3

6dBm

S 12

-32.66dB

PIdB

-12dB

From the results ,we can see that the LNA has
achieved fairly good perfornance and can be used in the
wireless communication system, especially in the third
generation mobile communication system.
5. Conclusion

The paper presents a single-stage cascode LNA in the

0.18um CMOS Process. With the help of capacitor Cex,
the simultaneous noise and power matching is achieved
with the NF only 0.018dB larger than the NFmin. With
constraint of given power consumption, good input and
output match, lower NF ,higher gain and better linearity
are reached for the LNA simultaneously .
Reference
[1] T.H.LEE ,The design of CMOS Radio Frequency Integrated

Circuits Cambridge, U.K.: Cambridge Univ.Press,2004 :209-212

[2]Bing Wang, James R. Hellums and Charles G. Sodini, "MOSFET

thermal noise modeling for analog integrated circuits," IEEE Journal of
Solid State Circuits, vol. 29, no. 7, pp. 833-835, July 1994.
[3] Trung-Kien Nguyen, "CMOS Low-Noise Amplifier Design

Optimization Techniques," IEEE Transactions On Microwave Theory

and Techniques, VOL. 52, NO. 5, MAY 2004: 1433-1442
[4] D. K. Shaeffer, et al, "1.5-V, 1.5-GHz CMOS Low Noise

Amplifier",Solid-State Circuits, IEEE Journal of, Volume: 32, May

1997, pp.745-759