UNIT 3

Semiconductor Memory Interfacing:

Semiconductor memories are of two types: RAM and ROM. The semiconductor
memories are arranged as arrays of memory locations. For example, 1K X 8 memory chip
contains 1024 locations and each of them is one byte wide. i.e. 1024 bytes of information can
be stored in that chip. Each location should have an address. So, there has to be certain
number of address lines on the memory chips. If we designate it as n, then n = log2N, where
N is the number of locations that could be addresses in that chip. For 1K chip n would be 10,
for 2K it is 11, for 4k it will be 13 etc.
If a microprocessor has x address lines and if a RAM/EPROM IC is to be interfaced
which has y lines (x > y), then we connect y lines from microprocessor to those of memory
chip. Remaining x-y lines of microprocessor are used for address decoding. Main aim of this
decoding circuit is to select one location for the address sent from microprocessor.
Memory Organization:
Let us consider an example to interface two 4K 8 EPROMs and two 4K 8 RAM
chips with 8086.
The address of the RAM may be selected anywhere in the 1 MB address space of
8086, but to make the address space continuous we would follow the given procedure. After
reset the IP and CS are initialized to for address FFFF0H. Now first calculate the total
number of address lines required for 8K bytes of EPROM which is 13.
213 = 8K
The memory system here contains in total four 4K 8 memory chips. The two 4K 8 chips
of RAM and ROM are arranged in parallel to obtain 16-bit data bus width. As RAM and
ROM are 8K, 13 address lines are required from A0 to A12. The remaining address lines are
used for address decoding circuitry.

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Memory Mapping:
Since the first instruction is fetched from FFFF0H after the microprocessor is reset, it make
that address to be present in EPROM and write the memory map as follows. Locations having
addresses from FFFFFH to FE000H are allocated to EPROM 1 and 2. Immediate address
map FDFFFH to FD000H is allocated to RAM 1 and 2. The line which is differentiating
to identify odd and even
EPROM from RAM is A13. Let us use it along with A0 and BHE
banks.
If A0 is 0 i.e. the address is even, then the RAM chip is selected indicating 8-bit
transfer at an even address.
is 0, i.e. the address is odd, then the RAM chip is selected indicating that the
If BHE
8-bit transfer is at an odd address.

Since there is continuous address map, decoder is used to decode the chip select signals. The
.
inputs for the decoder would be A13, A0 and BHE

As the table shows, when the decoder output O0 is enabled it selects both even and odd banks
can be used accordingly to select only even or only odd bank.
in RAM. Then A0 and BHE
Similarly, EPROM is selected by O4.
Matrix Keyboard Interfacing:
Fig. below shows a matrix keyboard with 16 keys connected to the 8086 microprocessor
using 8255. A matrix keyboard reduces the number of connections, thus the number of
interfacing lines. In this example the keyboard with 16 keys, is arranged in 4 x 4 (4 rows and
4 columns) matrix. This requires eight lines from the microprocessor to make all the
connections instead of 16 lines if the keys are connected individually. The interfacing of
matrix keyboard requires two ports: one input port and one output port.
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Rows are connected to the input Port (return lines) and columns are connected to the Output
Port (scan lines). When all keys are open row and column do not have any connection. When
any key is pressed, it shorts corresponding row and column. If the output line of this column
is low, it makes corresponding row line low; otherwise the status of row line is high. The key
is identified by data sent on the output port and input code received from the input port. The
following explains the steps required to identify pressed key.

Check 1: Whether any key is pressed or not

l. Make all column lines zero by sending low on all output lines. This activates all
keys in the keyboard matrix. (Note: When scan lines are logic high, the status on the
return lines do not change, it will remain logic high.)
2. Read the status of return lines. If the status of all lines is logic high, key is not
pressed; otherwise key is pressed.
Check 2:
l. Activate keys from any one column by making any one column line zero.
2. Read the status of return lines. The zero on any return line indicates key is pressed
from the corresponding row and selected column. If the status of all lines is logic
high, key is not pressed from that column.
3. Activate the keys from the next column and repeat 2 and 3 for all columns. In Fig.
the scan lines are connected to the port CL of 8255 and returns lines are connected to
the port CU of 8255.

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Interfacing LCD Display

The liquid crystals are one of the most fascinating material systems in nature, having
properties of liquids as well as of a solid crystal. Liquid crystal displays do not emit or
generate light, but rather alter externally generated illumination. Their ability to modulate
light when electrical signal is applied has made them very useful in flat panel display
technology.
Now-a-days, many LCD modules are available which have built-in drivers for LCD and
interfacing circuitry to interface them to microprocessor/microcontroller systems. These LCD
modules allow display of characters as well as numbers. They are available in 162, 201,

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202, 204 and 402 sizes. Here the following is the pin configuration of 162 module has
14-pins the display is organized as two lines, each of 20 characters.

The figure shows the interfacing of a 20 character 2 line LCD module with the 8086. The
and E are drive by
data lines are connected to the port A of 8255 and control lines RS, R/W
PC0, PC1 and PC3 of port C, respectively. The voltage at VEE pin is adjusted by a
potentiometer to adjust the contrast of the LCD.

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