Department of Electrical and Computer Engineering

University of Debre Tabor, Faculty of Technology

Course Title

Microcomputers and Interfacing

Program

Regular

Course Code

ECEg4161

Degree Program

B.Sc. in Electrical and Computer Engineering

Course Instructor

Achamie A.

ECTS

Students workload

32 Lecture hrs, 16 Tutor, 48 Laboratory hrs and 64 Home study hrs

Target Group

IV Year Computer, Control & Communication Engineering students

Year/Semester

4th/I

Prerequisites

ECEg3143- Computer Architecture and Organization

Status of the course

Core Electrical Engineering

Course Objective and Competency

After successfully completed this course, the student should be able to :

Get knowledge of the internal architecture of a microprocessor.

Write efficient codes in both assembly language.
Understand and handle interrupts
To interface Microprocessors with peripheral devices
Use microprocessors to develop controllers and computers
Design and implement microcomputers

Course description
The Microcomputers and interfacing course intends in getting the concepts to the mastering of basic
microcontroller and microcomputers. The discussion of the course will be based around the 8086 Intelmicroprocessor. However, this is not stiff and could be subjected to change. The fact that the 8086 is the
considered basic processor architecture, only for those matters will the discussion is based on the
microcontroller. The discussion of the course will begin by introducing the microcontroller evolution in
their historical background. The art of bringing hardware and software together will be explored. The two
most common computer architectures, the Reduced Instruction Set Computing (RISC) and the Complex
Instruction Set Computing (CISC) will also be explained. The overall 8086/8088 architecture with a close
look at the register, memory, bus, and IO organization will be covered. Having discussed the concept of
the architecture, the course will then pass to getting to know with the instruction sets of the 8086. The
most important instruction set will be given emphasis and soon after that, hardware programming will be
taught. The hardware programming or the storing of a program will take two tours. The first will be
assembly language programming route and the second will be high level hardware programming. The
high level language programming can take various languages into the programming task. C and C++ are
the most common ones. Subroutines and interrupts shall be handled in programming to enable students
get the art of real time applications. Next shall be the skill of interfacing microcontrollers with various
peripherals devices that help bring up real applications. Finally bringing all things together, students will
be made able to design microcomputers for various devices. This will help them in developing hardware
based controllers in embedded concepts.

Unit objectives: At the end of this unit,

Content

students will be able to:

Delivery
Method

Domain
&
Hierary

Delivre
y
weeks

1.1. KL1

Weeks
(1-2)

CHAPTER ONE: INTRODUCTION TO MICROPROCESSORS & COMPUTERS

1.1 Identify evolution of the Intel
processors
1.2 Identify history of Microprocessors

1.1. Evolution of the Intel

processors
1.2. History of Microprocessors

brain storming,
interactive
lecture, group
discussion
CHAPTER TWO: THE 8086 MICROCONTROLLER ARCHITECTURE
brain storming,
2.1. Identify features of 8086
2.1. Features of 8086
interactive
2.2. Explain architecture of 8086
2.2. Architecture of 8086
2.2.1. Explain Bus Interface Unit
2.2.1. Bus Interface Unit (BIU) lecture,
group
(BIU)
discussion,
2.2.2. Summerize Execution Unit (EU) 2.2.2. Execution Unit (EU)
(1)home taken
2.3. Explaint Register Organization
2.3. Register Organization
2.3.1. Explain General purpose
2.3.1. General purpose registers individual
assignment,
registers

Weeks
1.1. KL1 (3-5)
1.2. KL2
1.3. KL2

2.3.2. Describe Segment Registers

2.3.2. Segment Registers
1.4. KL2
2.3.3. Describe Pointers and Index
2.3.3. Pointers and Index
Registers
Registers
1.5. KL2
2.3.4. Describe Flag Registers
2.3.4. Flag Registers
2.4. Bus Operation
2.4. Explain Bus Operation
2.5. Explain Memory Segmentation
2.5. Memory Segmentation
CHAPTER THREE: 8086 MICROPROCESSOR PROGRAMING & INSTRUCTION SETS
brain storming,
Weeks
3.1. Explain 8086 Addressing Modes 3.1. 8086 Addressing Modes
interactive
3.1. KL2 (6-10)
3.1.1. Describe data Addressing
3.1.1. Data Addressing Modes
lecture,
group
3.1.2. Program Memory
Modes
discussion,
3.2. KL2
Addressing Modes
3.1.2. Describe Program Memory
(2)home taken
3.1.3. Stack Memory Addressing
Addressing Modes
group
Modes
3.1.3. Describe Stack Memory
assignment,
Addressing Modes
3.2. Explain instruction Set of 8086 3.2. Instruction Set of 8086
3.2.1. Data Movement instrucn
3.2.1. Data Movement instrucns
3.2.1.1. MOV instrucns
3.2.1.1. Explain MOV instrucns
3.2.1.2. PUSH/POP instructions
3.2.1.2. Explain PUSH/POP
instructions
3.2.1.3. Load effective address
3.2.1.3. Explain Load effective
3.2.1.4. String Data transfer
address
instructions
3.2.1.4. Explain String Data
transfer instructions
3.2.1.5. Explain Miscellaneous
Data Transfer Instructions
3.2.2. Explain Arithmetic and

3.2.1.5. Miscellaneous Data

Transfer Instructions
3.2.2. Describe Arithmetic and
Logic instruction

3.3. KL2

Logic instruction
3.2.3. Addition
3.2.4. Subtraction
3.2.5. Comparison
3.2.6. Multiplication
3.2.7. Division
3.2.8. BCD and ASCII Arithmetic
3.2.8.1. BCD Arithmetic
3.2.8.2. ASCII Arithmetic
3.3. Explain Basic Logic Instructions
3.3.1. Shift
3.3.2. Rotate
3.4. Explain String Instructions
3.5. Describe program Control Transfer
Instructions
3.6. Describe CALL and RET Instructions
3.7. Describe JMP Instruction
3.8. Describe Conditional Jump
3.9. Iteration Control Instructions
3.9.1. Prepare Process Control instrns
3.9.2. Demonstrate External Hardware
Synchronization Instructions
3.10. Demonstrate Interrupt Instructions
3.11. Writing Assembly Language
Programming
3.11.1. Write Some Assembly
Language Programs
3.12. Explain Programming with
Assembler
3.12.1. Explain Assembling Process
3.12.2. Explain Linking Process
3.12.3. Explain Debugging Process
3.13. Explain Timings and Delays
3.13.1. Explain Timer Delays using
NOP instruction
3.13.2. Explain Time Delay using
COUNTERS
3.13.3. Explain Timer delays using
NESTED Loops
3.14. 8086 System Configuration
3.14.1. Identify Signal Description
of 8086
3.14.2. Explain Minimum Mode of
Operation

3.4. KL2
3.2.3. Addition
3.2.4. Subtraction
3.2.5. Comparison
3.2.6. Multiplication
3.2.7. Division
3.2.8. BCD and ASCII Arithmetic
3.2.8.1. BCD Arithmetic
3.2.8.2. ASCII Arithmetic
3.3. Basic Logic Instructions
3.3.1. Shift
3.3.2. Rotate
3.4. String Instructions
3.5. program Control Transfer
Instructions
3.6. CALL and RET Instructions
3.7. JMP Instruction
3.8. Conditional Jump
3.9. Iteration Control Instructions
3.9.1. Process Control instructions
3.9.2. Describe External Hardware
Synchronization Instructions
3.10. Interrupt Instructions
3.11. Assembly Language
Programming
3.11.1. Some Assembly
Language Programs
3.12. Programming with Assembler
3.12.1. Assembling Process
3.12.2. Linking Process
3.12.3. Debugging Process
3.13. Timings and Delays
3.13.1. Timer Delays using NOP
instruction
3.13.2. Describe Time Delay using
COUNTERS
3.13.3. Describe Timer delays using
NESTED Loops
3.14. 8086 System Configuration
3.14.1. Signal Description of
8086
3.14.2. Minimum Mode of
Operation

3.5. KL3
3.6. KL3
3.7. KL3
3.8. KL3
3.9. KL3
3.10.KL
3
3.11.KL
3
3.12.KL
3
3.13.KL
2
3.14.KL
3

3.14.3. Explain Maximum Mode opn

3.14.3. Maximum Mode operation
CHAPTER FOUR: INTERFACING
4.1. Explain Basic IO Interfacing
4.1. Basic IO Interfacing
4.1.1. Explain Parallel I/O
4.1.1. Parallel I/O
4.1.2. Explain Programmed I/O
4.1.2. Programmed I/O
4.1.3. Demonstrate I/O Port Address
4.1.3. I/O Port Address
Decoding
Decoding
4.2. Demonstrate Programmable
4.2. Programmable Peripheral
Peripheral Interface (PPI)
Interface (PPI)
4.2.1. Demonstrate Programming
4.2.1. Programming 8255
8255
4.2.2. Operation Modes of the
4.2.2. Demonstrate Operation Modes
8255
of the 8255
4.3. Timer Interfacing
4.3. Identify Timer Interfacing
4.3.1. The 8254 Programmable
Interval Timer (PIT)
4.3.1. Demonstrate The 8254
Programmable Interval Timer
4.4. Serial I/O Interface
(PIT)
4.4.1. Asynchronous
4.4. Demonstrate Serial I/O Interface
Communication
4.4.1. Demonstrate Asynchronous
4.4.2. Programmable
Communication
Communication Interface
4.4.2. Demonstrate Programmable
UART 8251
Communication Interface UART
4.5. Interrupts
8251
4.5.1. Interrupt Driven I/O
4.5. Identify Interrupts
4.5.2. Software and Hardware
4.5.1. Explain Interrupt Driven I/O
4.5.2. Explain Software and Hardware
Interrupts
Interrupts
4.5.3. Interrupts vectors and
4.5.3. Explain Interrupts vectors and
Vector tables
Vector tables
4.5.4. The 8259A Programmable
4.5.4. Explain The 8259A
Interrupt Controller (PIC)
Programmable Interrupt Controller 4.6. Direct Memory Access (DMA)
(PIC)
4.6. Explain Direct Memory Access
4.6.1. Basic DMA Operations
(DMA)
4.6.1. Describe Basic DMA
4.6.2. DMA Controlled I/O
Operations
4.6.3. The 8237 DMA Controller
4.6.2. Describe DMA Controlled I/O
4.6.3. Describe The 8237 DMA
Controller

brain storming,
interactive
lecture, group
discussion,
home taken
group
assignment,
(3) Case study
project

4.1. KL2
4.2. KL4
4.3. KL4
/5
4.4. KL4
/5
4.5. KL2
4.6. KL2

Weeks
(1116)

Course policy

Class activities will vary day to day, ranging from lectures to discussions. Students will be active
participants in the course.
Active participation in class is essential and it will have its own value in your grade
Academic dishonesty, including cheating, fabrication, and plagiarism will not be tolerated.
You are required to submit and present the assignments provided according the due time
allocated.
80 % of class attendance and 100% of the lab attendance is mandatory! Please try to be on time
for class.
Cell phones MUST be turned off before entering the class.

Assessment
Assignment .10%
Quiz .....5% to 10%
Group work.10% (if no lab)
Lab activity..20%
Test...25% to 30%
Final Exam..40%

References
1. .Douglas V Hall, Microprocessors and Interfacing-Programming and Hardware, 2nd Edition,
Tata McGraw-Hill Publishing Company Limited, NewDelhi-2002.
2. Ramesh S Gaonkar, Microprocessor Programming and Interfacing using 8085, Penram
Publications, 4th Edition, 2003
3. A.K.Ray, K.M.Bhurchandy, Intel Microprocessors-Architecture, Programming and Interfacing,
McGraw-Hill International Edition, 2004
4. Microprocessors and Interfacing, first Edition, 2009. A.P Douglas and D.A Douglas

Course Title

Department of Electrical Engineering

University of Debre Tabor, Faculty of Technology
Database Systems

Program

Regular

Course Code

ECEg4172

Degree Program

B.Sc. in Electrical and Computer Engineering

Course Instructor

Achamie A.

ECTS

Students workload

32 Lecture hrs ,16Tutor hrs, 32 Laboratory hrs and 64 Home study hrs

Target Group

IV Year Computer Stream students

Year/Semester

4th/I

Prerequisites

ECEg3142 Object Oriented Programming

Status of the course

Core Electrical Engineering

Course Objective and Competency

After successfully completed this course, the student should be able to:
Introduce the concept of database systems and modeling techniques
Provide a profound ground for the analysis, design and implementation of database systems
Discuss advanced database types and issues related to storage and security

Course description
This course is designed to provide students a working knowledge of Fundamental concepts of a
database systems, functionality of a database system, types of models, steps of database design,
Structured query language (SQL), and introduction them to distributed and parallel databases

Unit objectives: At the end of this unit,

students will be able to:

Content

CHAPTER ONE: INTRODUCTION

1. Identify historical perspective
1. historical perspective
2. Identify Components and functionality 2. Components and functionality of a
of a database system
database system
3. Define types of models
3. types of models
4. Identify steps of database design
4. steps of database design

Delivery
method

Domain & Delivre

Hierarchy y weeks

brain
1. KL1
storming,
interactive 2. KL1
lecture,
group
3. KL1
discussion
4. KL1

Weeks
(1-2)

CHAPTER TWO: CONCEPTUAL LEVEL DESIGN

1. E/R model:
1.1. Define Entities and
relationships
1.2. Identify attribute types
1.3. Describe key types, types of
constraints
1.4. Describe multiplicity and
participation
1.5. Describe symbols
1.6. Describe design guidelines
2. ODL model
2.1. Define Syntax
2.2. Define OO concepts
2.3. Describe ODL diagram
2.4. Comparison with E/R

1. E/R model:
1.1. Entities and relationships
1.2. attribute types
1.3. key types, types of constraints
1.4. multiplicity and participation
1.5. symbols
1.6. design guidelines
2. ODL model
2.1. Syntax
2.2. OO concepts
2.3. ODL diagram
2.4. Comparison with E/R

brain
1. KL2
storming,
interactive 2. KL2
lecture,
group
discussion
,
home
taken
individual
assignmen
t,

CHAPTER THREE: RELATIONAL DATABASE DESIGN

1. Define Relations
1. Relations
brain
1. KL1
storming,
2. Define Dependencies
2. Dependencies
interactive 2. KL1
3. Describe Normal forms
3. Normal forms
lecture,
3. KL2
4. Describe Normalization steps
4. Normalization steps
group
5. Describe Overall design process
5. Overall design process
discussion 4. KL3
, case
5. KL2
study
CHAPTER FOUR: RELATIONAL ALGEBRA
1. Identify Simple operations and symbols 1. Simple operations and symbols
brain
1. KL1
storming,
2. Describe complex operations
2. complex operations
interactive 2. KL2
3. Describe introduction to relational
3. introduction to relational calculus
lecture,
3. KL2
calculus
group
discussion
CHAPTER FIVE: STRUCTURED QUERY LANGUAGE (SQL)
1. Introduction
1. Introduction
brain
1. KL1
storming, 2. KL2
2. Describe Constructs and their syntax
2. Constructs and their syntax
interactive 3. KL2
3. Describe Subqueries
3. Subqueries
lecture,
4. KL2
4. Describe Views
4. Views
group
5. KL2
5. Describe Embedded and Dynamic SQL 5. Embedded and Dynamic SQL
discussion
CHAPTER SIX: DATA STORAGE AND QUERY EVALUATION
1. Define File structure
1. File structure
brain
1. KL1
storming,
2. KL2
2. Describe indexing and hashing
2. indexing and hashing
interactive 3. KL2
3. query evaluation
3. Describe query evaluation
lecture
CHAPTER SEVEN: SECURITY AND INTEGRATION
1. Describe Assertions
2. Describe Triggers

1. Assertions
2. Triggers

brain
storming,

1. KL1
2. KL2

Weeks
(3-5)

Weeks
(6-8)

Weeks
(9-10)

Weeks
(11-14)

Weeks
(15)

Weeks
(16)

interactive 3. KL2
lecture,
4. KL2
group
discussion
CHAPTER EIGHT: INTRODUCTION TO DISTRIBUTED AND PARALLEL DATABASES

3. Describe security and authorization

4. Describe encryption and authentication

3. security and authorization

4. encryption and authentication

1. Introduction to distributed and parallel

databases

1. Introduction to distributed and parallel

databases

Group
discussion

KL1

Course policy

Academic dishonesty, including cheating, fabrication, and plagiarism will not be tolerated.
Class activities will vary day to day, ranging from lectures to discussions. Students will be active
participants in the course.
You are required to submit and present the assignments provided according to the time table
indicated.
80 % of class attendance and 100% of the lab attendance is mandatory! Please try to be on time
for class.
Active participation in class is essential and it will have its own value in your grade
Cell phones MUST be turned off before entering the class

Assessment
Assignment .10%
Quiz.....5%
Lab activity..20% to 25%
Test...20% to 25 %
Final Exam..40%

Text
Elmasri, Navathe: Fundamentals of Database Systems

References
1. Silbershatz, Korth, Sudarshan: Database system concepts
2. Raghu Ramakrishnan, Johannes Gehrke: Database management systems
3. H.C. Mollina, J.D. Ullman, J. Widom: Database system, the complete book
4. Pervasive Software Inc., Database design guide