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MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Intelligent
<Intelligent
Power
Power
Module>
Module>
PS21246-E
PS21246-E
TRANSFER-MOLD
TRANSFER-MOLD
TYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE
PS21246-E
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Dimensions in mm
272.8(=75.6)
TERMINAL CODE
12 13
14 15 16 17 18 19 20 21
.2
24
25
26
A
100.3 100.3 100.3
200.3
3.80.2
14
15
16
17
18
19
20
21
22
23
24
25
26
VN1
VNC
CIN
CFO
FO
UN
VN
WN
P
U
V
W
N
0.50.2
(71)
HEAT SINK SIDE
Detail A
1.90.05
10.2
3.25MAX
Detail B
(t=0.7)
1.75MAX
0.80.2
0.60.5
80.5
790.5
670.3
0.60.5
23
UP
VP1
VUFB
VUFS
VP
VP1
VVFB
VVFS
WP
VP1
VPC
VWFB
VWFS
45
22
11.50.5
280.5
9 10 11
21.40.5
7 8
310.5
5 6
1
2
3
4
5
6
7
8
9
10
11
12
13
13.40.5
3 4
161 or
12.81
1 2
3~5
2.80.3
Detail C
(t=0.7)
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
CBW
CBW+
CBU+
CBV+
CBV
CBU
Bootstrap circuit
C4
C3
Protection
circuit (UV)
(Note 6)
Protection
circuit (UV)
DIP-IPM
Drive circuit Drive circuit Drive circuit
Inrush current
limiter circuit
AC line input
H-side IGBTS
(Note 4)
Fig. 3
U
V
W
M
AC line output
N1
VNC
N
L-side IGBTS
CIN
Drive circuit
Protection
circuit
Fo logic
Control supply
Under-Voltage
protection
FO CFO
Low-side input (PWM)
(5V line)
(Note 1, 2) Fault output (5V line)
(Note 3, 5)
Note1:
2:
3:
4:
5:
6:
VNC
VD
(15V line)
To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6)
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 6)
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1k resistance.
(see also Fig. 6)
The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to
these P and N1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
DIP-IPM
Drive circuit
IC (A)
H-side IGBTS
SC Protection
Trip Level
U
V
W
L-side IGBTS
Shunt Resistor
(Note 1)
VNC
C R
Drive circuit
CIN
B
C
Collector current
waveform
Protection circuit
(Note 2)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0s.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
0
2
tw (s)
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
IC
ICP
PC
Tj
Parameter
Condition
Applied between P-N
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Ratings
450
500
600
25
50
59.5
20~+150
Unit
V
V
V
A
A
W
C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ TC 100C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ TC 100C).
Parameter
Control supply voltage
Condition
Applied between VP1-VPC, VN1-VNC
VDB
VCIN
Input voltage
VFO
IFO
VSC
Ratings
20
Unit
V
20
0.5~+5.5
0.5~VD+0.5
15
0.5~VD+0.5
V
mA
V
Ratings
Unit
400
20~+100
40~+125
C
C
1500
Vrms
TOTAL SYSTEM
Symbol
Parameter
VCC(PROT) Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
TC
Tstg
Storage temperature
Viso
Isolation voltage
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125C, non-repetitive, less than 2 s
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Control Terminals
DIP-IPM
Tc
Tc
Power Terminals
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
Parameter
Rth(j-c)Q
Rth(j-c)F
Rth(c-f)
Limits
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
Case to fin, (per 1 module)
thermal grease applied
Unit
Min.
Typ.
Max.
2.1
3.0
C/W
C/W
0.067
C/W
Limits
Typ.
Max.
1.55
1.65
2.50
0.80
0.10
0.30
1.50
0.80
2.15
2.25
3.40
1.30
0.70
2.60
1.70
1
10
Condition
Parameter
IC = 25A, Tj = 25C
VD = VDB = 15V
VCIN = 0V
IC = 25A, Tj = 125C
Tj = 25C, IC = 25A, VCIN = 5V
VCE(sat)
Collector-emitter saturation
voltage
VEC
ton
trr
tc(on)
toff
tc(off)
Switching times
ICES
Collector-emitter cut-off
current
VCE = VCES
Min.
0.10
Tj = 25C
Tj = 125C
Unit
V
V
s
s
s
s
s
mA
Parameter
VD
VDB
ID
Circuit current
VFOH
VFOL
VFOsat
tdead
VSC(ref)
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Limits
Condition
Applied between VP1-VPC, VN1 -VNC
Applied between VUFB-VUFS, VVFB-VVFS , VWFB-VWFS
VD = VDB = 15V Total of VP1-VPC, VN1 -VNC
VUFB-VUFS, VVFB-V VFS, VWFB-VWFS
VCIN= 5V
VSC = 0V, FO = 10k 5V pull-up
VSC = 1V, FO = 10k 5V pull-up
VSC = 1V, IFO = 15mA
Relates to corresponding input signal for blocking arm
shoot-through.
20C TC 100C
Tj = 25C, VD = 15V
Trip level
Reset level
T j 125C
Trip level
Reset level
CFO = 22nF
(Note 3)
(Note 4)
Min.
13.5
13.5
Unit
4.9
Typ.
15.0
15.0
Max.
16.5
16.5
8.50
1.00
0.8
0.8
1.2
1.2
1.8
V
V
V
2.5
0.45
10.0
10.5
10.3
0.5
10.8
1.0
0.8
2.5
1.8
1.4
3.0
0.55
12.0
12.5
12.5
13.0
2.0
4.0
V
V
V
V
V
ms
V
V
mA
V
V
Note 3 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 42.5 A.
4 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 10-6 tFO [F].
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Condition
Parameter
Mounting torque
Terminal pulling strength
Bending strength
Weight
Heat-sink flatness
Mounting screw : M4
Weight 19.6N
Weight 9.8N. 90deg bend
EIAJ-ED-4701
EIAJ-ED-4701
(Note 5)
Min.
0.98
10
2
50
Limits
Typ.
1.18
54
Max.
1.47
100
Min.
Limits
Typ.
Max.
Unit
Nm
s
times
g
m
(Note 5)
DIP-IPM
Measurement point
3mm
Place to contact
a heat sink
Heat sink
Heat sink
Parameter
VCC
VD
VDB
VD, VDB
tdead
fPWM
VCIN(ON)
VCIN(OFF)
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Input ON threshold voltage
Input OFF threshold voltage
Condition
Applied between P-N
Applied between VP1-VPC, VN1 -VNC
Applied between VUFB-VUFS, V VFB-VVFS , VWFB-VWFS
Relates to corresponding input signal for blocking arm shoot-through
TC 100C, Tj 125C
Applied between UP, VP, WP-VPC
Applied between UN, VN, WN-VNC
0
13.5
13.5
1
2.5
300
15.0
15.0
5
0~0.65
4.0~5.5
400
16.5
16.5
1
Unit
V
V
V
V/s
s
kHz
V
V
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
VUFB
VUFS
VP1
UP
HVIC 1
VB
VCC
IGBT1
Di1
HO
IN
VS
COM
VVFB
VVFS
VP1
VP
HVIC 2
VB
VCC
IGBT2
Di2
HO
IN
VS
COM
VWFB
VWFS
HVIC 3
VP1
VCC
WP
IN
VPC
COM
VB
IGBT3
Di3
HO
VS
W
IGBT4
LVIC
Di4
UOUT
VN1
VCC
IGBT5
Di5
VOUT
UN
UN
VN
VN
WN
WN
Fo
Fo
IGBT6
Di6
WOUT
VNO
CIN
VNC
GND
CFO
CFO
CIN
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (N-side only)
(For the external shunt resistor and CR connection.)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. Hard IGBT gate interrupt.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the F O signal is set by the external capacitor CFO.
a6. Input H : IGBT OFF state.
a7. Input L : IGBT ON state.
a8. IGBT OFF state.
a6
a7
SET
RESET
a3
a2
SC
a4
a1
a8
SC reference voltage
Error output Fo
a5
Control input
RESET
SET
UVDr
UVDt
a5
a2
a1
a3
a6
Error output Fo
a4
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
[C] Under-Voltage Protection (P-side, UVDB)
a1. Control supply voltage rises : After the voltage level reachs UVDBr, the circuits start to operate when the next input is applied.
a2. Normal operation : IGBT ON and carrying current.
a3. Under voltage trip (UVDBt).
a4. IGBT OFF in spite of control input condition, but there is no FO signal output.
a5. Under-voltage reset (UVDBr).
a6. Normal operation : IGBT ON and carrying current.
Control input
RESET
SET
RESET
UVDBr
Control supply voltage VDB
a1
UVDBt
a2
a5
a3
a4
a6
5V line
DIP-IPM
5.1k
4.7k
UP,VP,WP,UN,VN,WN
CPU
Fo
1nF
1nF
VPC, VNC(Logic)
Note : RC coupling at each input (parts shown dotted) may change depending on the
PWM control scheme used in the application and on the wiring impedances of
the applications printed circuit board.
Sep. 2001
PS21246-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1: Tight tolerance temp - compensated electrolytic type; C2,C3: 0.22~2 F R-category ceramic capacitor for noise filtering
5V line
C2
VUFB
C1
VUFS
DIP-IPM
P
VP1
C3
UP
VCC
VB
IN
HO
COM
VS
VCC
VB
IN
HO
COM
VS
VCC
VB
IN
HO
C2
VVFB
C1
VVFS
VP1
C3
VP
C2
VWFB
C1
C
P
U
VWFS
VP1
C3
WP
VPC
U
N
I
T
COM
VS
UOUT
C3
VN1
VCC
5V line
VOUT
UN
VN
WN
Fo
UN
VN
WOUT
WN
Fo
VNO
CIN
VNC
GND
CFO
C
CFO
CIN
C4(CFO )
15V line
A
The long wiring of GND might generate
noise on input signals and cause IGBT to
be malfunctioned.
R1
C5
Shunt
resistor
N1
Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short
as possible. (Less than 2cm)
2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
5.1k resistance.
4 : FO output pulse width should be decided by connecting an external capacitor between CFO and VNC terminals (C FO). (Example : CFO
= 22 nF tFO = 1.8 ms (typ.))
5 : Each input signal line should be pulled up to the 5V power supply with approximately 4.7k resistance (other RC coupling circuits at
each input may be needed depending on the PWM control scheme used and on the wiring impedances of the systems printed circuit
board). Approximately a 0.22~2F by-pass capacitor should be used across each power supply connection terminals.
6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
7 : In the recommended protection circuit, please select the R1C5 time constant in the range 1.5~2s.
8 : Each capacitor should be put as nearby the pins of the DIP-IPM as possible.
9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approximately a 0.1~0.22F snubber capacitor between the P&N1 pins is recommended.
Sep. 2001