Vaagdevi College of Engineering

UGC Autonomous
CMOS MIXED SIGNAL CIRCUIT DESIGN(Code: A925703)
Answer Key

Part A: Answer all Short answer questions

1a) Characterize the basic building blocks of a switched capacitor circuit.
Ans: A switched-capacitor circuit is realized with the use of some basic building blocks such as opamps, capacitors,
Switches, and non-overlapping clocks
Opamps: The basic principles of switched-capacitor circuits can be well understood assuming ideal opamps.
However, some important opamps no idealities in practical switched capacitor circuits are dc gain, unity-gain
frequency and phase-margin, slew-rate, and dc offset. Opamps input impedance is generally capacitive assuming
MOSFET input stages are used. The dc gain of opamps in a MOS technology intended for switched-capacitor
circuits is typically on the order of 40 to 80 dB. Low dc gains affect the coefficient accuracy of the discrete-time
transfer function of a switched-capacitor filter.
Capacitors: A highly linear capacitance in an integrated circuit is typically constructed from two closely-spaced
conducting layers. The desired capacitance, , is formed as the intersection of area between the two conductive
layers, layer 1 and layer 2.
Switches: The requirements for switches used in switched-capacitor circuits are that they have a very high off
resistance (so little charge leakage occurs), a relatively low on resistance (so that the circuit can settle in less than
half the clock period), and introduce no offset voltage when turned on (as does a bipolar switch whose on voltage
equals ). The use of MOSFET transistors as switches satisfies these requirements, as MOSFET switches can have
off resistances up to the range, have no offset on voltages, and have on resistances of or much less depending on
transistor sizing.
Non-overlapping Clocks: At least one pair of no overlapping clocks is essential in switched-capacitor circuits.
These clocks determine when charge transfers occur and they must be no overlapping in order to guarantee charge
is not inadvertently lost.
1b) what are the Non ideal effects in PLL? Explain.
Ans: Explain at least 4 non-ideal effects-4 Marks
1c) Define resolution, INL, DNL, and full scale voltage of DAC.

Resolution: The resolution of a converter is defined to be the number of distinct analog levels corresponding to the
different digital words. Thus, an -bit resolution implies that the converter can resolve 2 N distinct analog levels.
Resolution is not necessarily an indication of the accuracy of the converter, but instead it usually refers to the number of
digital input or output bits.
Integral Nonlinearity (INL) Error After both the offset and gain errors have been removed, the integral nonlinearity
(INL) error is defined to be the deviation from a straight line. However, what straight line should be used? A
conservative measure of nonlinearity is to use the endpoints of the converters transfer response to define the straight
line.
Differential Nonlinearity (DNL) Error In an ideal converter, each analog step size is equal to 1 LSB. In other words, in a
D/A converter, each output level is 1 LSB from adjacent levels, whereas in an A/D, the transition values are precisely 1
LSB apart. Differential nonlinearity (DNL) is defined as the variation in analog step sizes away from 1 LSB (typically,
once gain and offset errors have been removed).
1d)Explain the issued in designing the Flash ADC.
Ans: Issues in Designing Flash A/D Converters:
Input Capacitive Loading: The large number of comparators connected to Vin results in a large parasitic load at the
node Vin . Such a large capacitive load often limits the speed of the flash converter and usually requires a strong and
power-hungry buffer to drive Vin .
Resistor-String Bowing: Any input currents to the comparators cause errors in the voltages of the nodes of the resistor
string. These errors usually necessitate the bias current in the resistor string being two orders of magnitude greater
than the input currents of the comparators. This is particularly significant if bipolar comparators are used. The errors
are greatest at the center node of the resistor string and thus considerable improvement can be obtained by using
additional circuitry to force the center tap voltage to be correct.
Comparator Latch-to-Track Delay: Another consideration that is often overlooked is the time it takes a comparator
Latch to come from latch mode to track mode when a small input signal of the opposite polarity from the previous
period is present. This time can be minimized by keeping the time constants of the internal nodes of the latch as small
as possible. This is sometimes achieved by keeping the gain of the latches small, perhaps only two to four. In many
cases, the differential internal nodes might be shorted together temporarily as a reset just after latch time.
Signal and/or Clock Delay: Even very small differences in the arrival of clock or input signals at the different
comparators can cause errors.

Substrate and Power-Supply Noise: This power-supply noise can easily couple through the circuitry or substrate,
resulting in errors. To minimize this problem, the clocks must be shielded from the substrate and from analog
circuitry.
Flashback: An additional source of error is flashback. Flashback is caused by clocked comparators, which are almost
always used. When clocked comparators are switched from track to latch mode, or vice versa, there is major charge
glitch at the inputs to the latch. If there is no preamplifier, this will cause major errors due to the unmatched
impedances at the comparator inputs (one input goes to the resistor stringthe other to the input signal). To minimize
this effect, most modern comparators have one or two stages of continuous-time buffering and/or preamplification
1e) Discuss the advantages of sampling higher than the Nyquist rate.
Ans: The advantage of sampling at higher than the Nyquist rate is that an extra dynamic range can be obtained by spreading
the quantization noise power over a larger frequency range. However, we shall see that the increase in dynamic range is
only 3 dB for every doubling of the sample rate. To obtain much higher dynamic-range improvements as the sampling
rate is increased; noise shaping through the use of feedback can be used.
Oversampling A/D and D/A converters are popular for high-resolution medium-to-low-speed applications such
as high-quality digital audio and baseband signal processing in some wireless systems. A major reason for their
popularity is that oversampling converters relax the requirements placed on the analog circuitry at the expense of more
complicated digital circuitry. This tradeoff became desirable with the advent of deep submicron CMOS technologies as
complicated high-speed digital circuitry became more easily realized in less area, but the realization of high-resolution
analog circuitry was complicated by the low power-supply voltages and poor transistor output impedance caused by
short-channel effects.
With oversampling data converters, the analog components have reduced requirements on matching tolerances
and amplifier gains. Oversampling converters also simplify the requirements placed on the analog anti-aliasing filters for
A/D converters and smoothing filters for D/A converters.

Part B
Answer one question from each unit. Each question carries 8 marks.
2.

Parasitic Insensitive Inverting Integrator: The parasitic-insensitive integrator was a critical development that allowed the
realization of high-accuracy integrated circuits. The development of the parasitic-insensitive inverting integrator allowed the
complete filter to be insensitive, which greatly decreased second-order errors. To obtain an inverting discrete-time integrator
that is also parasitic insensitive, the same circuit as the parasitic-insensitive non Inverting integrator can be used, but with the
two switch phases on the switches near the opamp input side of C 1(that is, the top-plate of C 1) interchanged as shown in
following Figure.

The transfer function of the same can be calculated to,

3. Realize active RC general continuous time low Q-biquad filter with switched capacitor and explain.
Ans:
A switched-capacitor biquad based on this active-RC circuit can be realized as shown in following figure. Here, all
positive resistors were replaced with delay-free feed-in switched-capacitor stages while the negative resistor was replaced
with a delaying feed-in stage. The switched-capacitor circuit has redundant switches, as switch sharing has not yet been
applied.
The input capacitor K1C1 is the major signal path when realizing low-pass filters; the input capacitor K 2C2 is the major
signal path when realizing bandpass filters; whereas, the input capacitor K3C 2 is the major signal path when realizing highpass filters.

It is worth mentioning that while this switched-capacitor filter is a natural result when using single-ended circuits,
the use of fully differential circuits could result in quite a few other circuits, some of which could have poor performance
properties. For example, all the positive resistors could be replaced with delay-free feed-in stages as before, but in addition, the
negative resistor could also be replaced with a delay-free feed-in stage where the differential input wires are interchanged.
Such a circuit would have a delay-free loop around the two integrators and may have an excessive settling time behavior. As
another example, all resistors might be replaced with delaying feed-in stages where positive resistors are realized by
interchanging the input wires of those stages.
In this case, settling time behavior would not suffer as there would be two delays around the two-integrator loop, but
coefficient sensitivity would be worse for filters having high-Q poles. In summary, what is important is that the two-integrator
loop has a single delay around the loop. Such an arrangement is referred to as using lossless discrete integrators (LDI).
4. Draw the circuit diagram of CMOS VCO and explain its operation.
5. Draw the block diagram of a DLL and explain its operation.
6. Draw and explain the thermo meter code converter.
Ans: THERMOMETER-CODE CONVERTERS: Simplest method for realizing a D/A converter is to digitally recode the
input value to a thermometer-code equivalent. A thermometer code differs from a binary one in that a thermometer code has
2N-1digital inputs to represent 2N different digital values. Clearly, a thermometer code is not a minimal representation since a
binary code requires only N digital inputs to represent 2N input values.
However, as we will see, a thermometer-based converter does have advantages over its binary counterpart, such as low
DNL errors, guaranteed monotonicity, and reduced glitching noise.
Typically, in a thermometer-code representation, the number of 1s represents the decimal value.One method to realize a
D/A converter with the use of a thermometer-code input is to build 2 N-1equal-sized resistors and switches attached to the
virtual ground of an opamp, as shown in following figure.

Note that monotonicity is guaranteed here since, when the binary input changes to the next higher number, one more
digital value in the thermometer code goes high, causing additional current to be drawn out of the virtual ground and forces
the opamp output to go some amount higher (never lower). This is not necessarily the case for a binary-array D/A converter
since mismatches between elements may cause the output to go lower even though the digital input value is increased.
Perhaps more importantly, a D/A converter based on a thermometer code greatly minimizes glitches, as compared to
binary-array approaches, since banks of resistors are never exchanged at slightly different times when the output should
change by only 1 LSB. It should also be mentioned here that latches can be used in the binary-to-thermometer code
conversion such that no glitches occur in the digital thermometer-code words and pipelining can be also used to maintain a
high throughput speed. It is also of interest to note that the use of a thermometer code does not increase the size of the analog
circuitry compared to a binary-weighted approach. In a 3-bit binary-weighted approach, the resistor values of R,2R,, and
4Rare needed for a total resistance of 7R .
This total value is the same as for the 3-bit thermometer-code approach shown in figure and since resistors are created on
an integrated circuit using area that is proportional to their size, each approach requires the same area (ignoring interconnect).
The same argument can be used to show that the total area required by the transistor switches is the same since transistors are
usually size-scaled in binary-weighted designs to account for the various current densities. All transistor switches in a
thermometer-code approach are of equal sizes since they all pass equal currents.
7. Explain qualitatively the architecture and working of a charge scaling DAC,s
Ans:
Charge scaling DACs: Charge-redistribution switchedcapacitor D/A converters sample a fixed reference voltage onto a
binary-weighted capacitor array whose effective capacitance is determined by the input digital code. The sampled charge is
then applied to a switched-capacitor gain stage to produce the analog output voltage. The basic idea here is to simply replace
the input capacitor of an SC gain amplifier by a programmable capacitor array (PCA) of binary-weighted capacitors, as
shown in following figure.

As in the SC gain amplifier, the shown circuit is insensitive to opamp input offset voltage, 1/f noise, and finite-amplifier
gain. Also, an additional sign bit can be realized by interchanging the clock phases (shown in parentheses) for the input
switches. It should be mentioned here that, as in the SC gain amplifier, carefully generated clock waveforms are required to
minimize the voltage dependency of clock feed-through, and a deglitching capacitor should be used. Also, the digital codes
should be changed only when the input side of the capacitors is connected to ground, and thus the switching time is
dependent on the sign bit, which requires some extra digital complexity.
8.Describe the successive approximation ADC with a neat diagram.
Ans:
Successive-approximation A/D converters are one of the most popular approaches for realizing A/D converters due to
their amazing versatility. Successive-approximation A/D converters are very versatile, capable of moderately high speed or
accuracy with relatively low power. They are relatively simple circuits, in the simplest cases requiring only a single
comparator, a bank of capacitors and switches, and a small digital logic circuit.
Their biggest drawback is that they operate iteratively and therefore require many clock cycles to perform a single
conversion. They can provide reasonably quick conversion time, or they can be used for relatively high accuracy, and can
operate with very low power in either case. Fundamentally, these benefits arise because successive-approximation converters
require only modest circuit complexity, in the simplest cases requiring only a single comparator, a bank of capacitors with
switches, and a small amount of digital control logic.
To understand the basic operation of successive-approximation converters, knowledge of the search algorithm referred to
as a binary search is helpful. As an example of a binary search, consider the game of guessing a random number from 1 to
128 where one can ask only questions that have a yes/no response. The first question might be, Is the number greater than
64? If the answer is yes, then the second question asks whether the number is greater than 96. However, if the first answer is
no, then the second question asks whether the number is greater than 32. The third question divides the search space in two
once again and the process is repeated until the random number is determined. In general, a binary search divides the search
space in two each time, and the desired data can be found in N steps for a set of organized data of size 2N.

The flow graph for a unipolar conversion is only slightly different and is left as an exercise for the reader. The major
drawback of successive-approximation converters is that, because their principle of operation is an iterative search, they
require multiple clock cycles for each input conversion. This limits their conversion frequency to far below the circuits
maximum clock frequency, particularly when high resolution is sought since more iterations are required.
9. Briefly explain the block diagram of a 2 step flash ADC and its working.
Ans:
Two-step A/D converters: Two-step (or sub ranging) converters are used for high-speed medium-accuracy A/D
converters. They offer several advantages over their flash counterparts. Specifically, two-step converters require less
silicon area, dissipate less power, have less capacitive loading, and the voltages the comparators need to resolve are less
stringent than for flash equivalents. The throughput of two-step converters approaches that of flash converters, although
they do have a larger latency. The block diagram for a two-step converter is shown in following figure.

In fact, a two-step converter may be thought of as a special case of a pipelined converter with only two pipeline stages.
The example of figure shows two 4 bit stages with no redundancy resulting in a 8-bit output. The 4-bit MSB A/D determines
the first four MSBs. To determine the remaining LSBs, the quantization error (residue) is found by reconverting the 4-bit
digital signal to an analog value using the 4-bit D/A and subtracting that value from the input signal. To ease the requirements
in the circuitry for finding the remaining LSBs, the quantization error is first multiplied by 16 using the gain amplifier, and
the LSBs are determined using the 4-bit LSB A/D. With this approach, rather than requiring 256 comparators as in an 8-bit
flash converter, only 32 comparators are required for a two-step A/D converter. However,this straightforward approach would
require all components to be at least 8-bit accurate. To significantly ease the accuracy requirements of the 4-bit MSB A/D
converter, digital error correction is commonly used.
Two-step converters may be considered a special case of pipelined converters where only 2 pipelined stages are needed.
As with pipelined converters, digital error correction greatly relaxes the requirements on the first stage.
10. Briefly explain the role of decimating filters in ADC.
Decimation filter: "decimation" is the process of reducing the sampling rate. In practice, this usually implies lowpassfiltering a signal, then throwing away some of its samples."Down sampling" is a more specific term which refers to just the
process of throwing away samples, without the low pass filtering operation. Throughout this FAQ, though, we'll just use the
term "decimation" loosely, sometimes to mean "down sampling".
(Requires some more Explanation)
11.Draw the architecture of delta sigma D/A converter and explain.
Delta Sigma D/A Converter: A high-resolution oversampling D/A converter using a 1-bit converter can be realized as
shown in the block diagram in Following figure.

Oversampling D/A converters require a very linear but low-resolution internal D/A converter, and an analog smoothing
filter whose order should be at least one greater than that of the noise shaping and must have sufficient dynamic range to
accommodate both signal and large quantization noise power at its input. While oversampling allows the use of a 1-bit D/A
converter, which can have excellent linearity, the use of oversampling also relaxes some of the analog-smoothing filter
specifications