AAiT

Lecture 02
The 8086 Microprocessor Architecture

[Register level organization]

ECEg - 4501

Daniel D. DECE

In this Lecture:

AAiT

Review of the Basic Comp. Arch.

The 8086 internal architecture
 The Execution Unit
 The Bus Interface Unit
 Physical Address Generation

ECEg - 4501

The Basic Arch.

AAiT

The simplest microprocessor at least contains:

Program and data address bus (separate or unified)
Address decoder and generator
Instruction decoder
Arithmetic and Logic Unit (ALU)
A set of basic registers
 Program Counter (PC)
 Instruction Register (IR)
 Accumulator or Working Register (AC)
 Flag register (FR)
 Input and output registers
 General purpose (temporary)registers (GPRs)
(to hold data operands and intermediate results)
ECEg - 4501

The Basic Arch. graphically

Data Reg.

AAiT

Address
decoder

To
Memory

Stack Pointer

ALU
Program counter

Flags
-Carry
- Zero
- Overflow
- Interrupt

Accumulator
Counting Reg.
Input Reg.

Instruction Reg.

Instruction
decoder &
execution unit

Output Reg.
ECEg - 4501

The Basic Arch instruction set

AAiT

Assume we have only 16 instructions:

1. MOV A B
2. LDA [D]
3. STA [D]
4. ADD D
5. AND D
6. OR D
7. NOT
8. SHR
9. SHL
10. IN
11. OUT
12. JMP X
13. JZ X
14. JC X
15. CALL sub
16. RETURN

ECEg - 4501

Move data from B to A (A any register; B reg. or immediate)

Load data to Accumulator from memory (address is in D)
Store data in accumulator to memory (address in D)
Add data D to accumulator (D register or immediate)
Bitwise AND data in accumulator with data in D >>
Bitwise OR data in accumulator with data in D >>
Negate data in accumulator
Shift right data in accumulator
Shift left data in accumulator
Read data from input port to accumulator (port address immediate)
Write data from accumulator to output port (port address immediate)
Unconditional jump to program address x
Jump to address X if the previous operation result was zero
Jump to address X if the previous operation resulted in a carry
Call a subroutine labeled sub
Return from subroutine or interrupt

The Basic Arch data format

AAiT

Let our machine be an 8-bit microprocessor

i.e. The basic data width is 8-bit
Also assume:
- All registers except A and D are 8-bit, A and D are 16-bit
- The ALU is 8-bit wide
- internal data/prog bus is 10-bit wide
- Memory is accessed with byte address
- Thus, max address space is 210 = 1KBytes
- we have unified memory model
- I/O devices are memory mapped
- Stack is the first 10 bytes of memory
- Reset vector is at 10 and interrupt vector is at 20
ECEg - 4501

The Basic Arch instruction format

AAiT

We only need 4-bits to decode all instructions

i.e. 0000 = MOV
0001 = LDA
0010 = STA
.
.
1111 = RETURN
The complete Opcode, there fore, is 12 bits including
an 8-bit immediate data.
11

Instruction

8 bit immediate data

Instruction opcode
ECEg - 4501

AAiT

The 8086 Microprocessor

Architecture

ECEg - 4501

Internal Architecture
AAiT

ECEg - 4501

The Execution Unit (EU)

AAiT

the EU contains control circuitry, which directs internal

operations.
 A decoder in the EU translates instructions fetched from
memory into a series of actions which the EU carries out.
The EU has a 16-bit arithmetic logic unit which can add,
subtract, AND, OR, XOR, increment, decrement,
complement, or shift binary numbers.

ECEg - 4501

The Execution Unitcntd

AAiT

Flag Register

ECEg - 4501

10

Flag Register
AAiT

Carry Flag (C)

This flag is set when there is a carry out of MSB in case of
addition or a borrow in case of subtraction.
Zero Flag (Z)
This flag is set when the result of an arithmetic operation is
zero.
Sign Flag (S)
This flag is set when the result an arithmetic operation is
negative.
For signed computations, the sign flag equals the MSB of the
result.
ECEg - 4501

11

Flag Register

cntd
AAiT

Parity Flag (P)

This flag is set when the lower byte of the result contains even
number of 1s.
Overflow Flag (O)
This flag is set, if an overflow occurs, i.e. if the result of a signed
operation is large enough to be accommodated in a destination
register.
Direction Flag (D)
This is used by string manipulation instructions.
If this flag bit is '0 the string is processed beginning from the
lowest to the highest address (auto-incrementing mode).
Otherwise, the string is processed from the highest to the lowest
address (auto-decrementing mode).
ECEg - 4501

12

Flag Register

cntd
AAiT

Interrupt Flag (I)

If this flag is set, the maskable interrupts are acknowledged by
the CPU, otherwise they are ignored.
Trap Flag (T)
If this flag is set, the processor enters the single step execution
mode.
In other words, a trap interrupt is generated after execution of
each instruction. The processor executes the current instruction
and the control is transferred to the Trap interrupt service
routine.
Auxiliary Cary Flag (AC)
This is set if there is a carry from the lowest nibble, i.e. bit three,
during addition or borrow for the lowest nibble, i.e. bit three,
during subtraction.
ECEg - 4501

13

General Purpose Registers (GPR)

AAiT

 The EU has 8 GP registers

AH, AL, BH, BL, CH, CL, DH, DL
AL Accumulator
 Certain pairs of these general-purpose registers can be
used together to store 16-bit data words. The acceptable
register pairs are AH-AL, BH-BL, CH-CL, and DH-DL.
 The AH-AL pair is referred to as the AX register, the BH-BL pair is
referred to as the BX register, the CH-CL pair is referred to as the CX
register, and the DH-DL pair is referred to as the DX register.
Usually used as: A - accumulator, B - base, C - counter, D - data

ECEg - 4501

14

The Bus Interface Unit (BIU)

AAiT

Instruction Queue
oWhile the EU is decoding or executing an instruction, which does
not require use of the buses, the BIU fetches up to six instruction
bytes for the following instructions.
oThe BIU stores these pre-fetched bytes in a first-in-first-out register
set called a queue. When the EU is ready for its next instruction, it
simply reads the instruction byte(s) for the instruction from the
queue in the BIU.
oFetching the next instruction while the current instruction
is being executed is called pipelining.

ECEg - 4501

15

The Bus Interface Unit cntd

AAiT

Segment Registers
oThe four segment registers are the code segment (CS)
register, the data segment (DS) register, the stack segment
(SS) register, and the extra segment (ES) register.
o A segment register is used to hold the upper 16 bits of the
starting address for each of the segments.
oThe four segments can be separated or for small programs,
which do not need all 64 Kbytes in each segment, they can
overlap.

ECEg - 4501

16

The Bus Interface Unit cntd

AAiT

Physical address generation

Therere two types of address generation
Real Mode (8086 can only operate in this mode)
Allows the P to address the first 1MB of memory only
The first 1MB of memory is called real or physical memory
Protected Mode (80286 , 80386, )
Uses the segment register contents (called selector) to access a
descriptor from the descriptor table.
The descriptor describes the memory segments location,
length and access rights.
ECEg - 4501

17

The Bus Interface Unit cntd

AAiT

The 8086 addresses a segmented

memory. The complete physical
address, which is 20-bits long, is
generated using segment and
offset registers, each 16-bits long.
The content of a segment
register is shifted left bit-wise
four times and to this result,
content of an offset register is
added, to produce a 20-bit
physical address.

The Bus Interface Unit cntd

AAiT

For example, if the segment address is 1005h and the

offset is 5555h, then the physical address is calculated as
below.
Segment address --------- 1005h
Offset address------------- 5555h
Segment address--------- 1005h --------- 0001 0000 0000 0101
Shifted by 4 bit positions---------- 0001 0000 0000 0101 0000
Offset address---------------------

0101 0101 0101 0101

Physical address --------------------- 0001 0101 0101 1010 0101

1
ECEg - 4501

h
19

The Bus Interface Unit cntd

AAiT

Instruction Pointer
 The IP contains the distance or offset from the base address in Code
Segment (CS) to the next instruction byte to be fetched.
 The 16-bit offset in IP is added to the 16-bit segment base address in
CS to produce the 20-bit physical address.
 Location of the next instruction in memory is, therefore
address of next instruction. = (CS << 4) + IP;

ECEg - 4501

20

The Bus Interface Unit cntd

AAiT

Instruction Pointer
Example: Let CS holds 348Ah,
and IP holds 4214h
Now the actual address in the
physical memory space is
given by CS:IP and calculated
as:
CS is first shifted left four times
16*CS = 348A0h
Then the offset in IP is added
348A0h
+ 4214h
Actual address 38AB4h
ECEg - 4501

21

Other registers in the EU

AAiT

Stack Pointer
 A stack is a section of memory set aside to store addresses and data
while a subprogram is executing.
 The 8086 allow you to set aside an entire 64KB segment as a stack.
The upper 16 bits of the starting address for this segment are kept in
the stack segment register (SS).
 The stack pointer (SP) register holds the 16-bit offset from the start
of the segment to the memory location where a word was most
recently stored on the stack (Top of stack).

ECEg - 4501

22

Other registers in the EU cntd

AAiT

Example: Let SS hold 5000h,

and SP hold FFE0h
Now the actual address in the
physical memory space is
given by SS:SP and calculated
as:
SS is first shifted left four times
16*SS = 50000h
Then the offset in SP is added
50000h
+ FFE0h
Top of stack 5FFE0h
ECEg - 4501

23

Other registers in the EU cntd

AAiT

Base Pointer and Index Registers

 In addition to the SP, the EU contains a 16-bit base pointer (BP)
register, a 16-bit source index (SI) register and a 16-bit destination
Index (DI) register.
 The base pointer can be used to hold the 16-bit offset of a data
word in one of the segments. Index registers are very useful in
string manipulation.
 These three registers can be used for temporary storage of data just
as the general-purpose registers described above.

ECEg - 4501

24

Summary of 8086 registers

AAiT

AX [Accumulator]

AH:AL

BX [Base Register]

BH:BL

CX [Count Register] CH:CL

DX [Data Register]

DH:DL

CS [Code Segment]
DS [Data Segment]
SS [Stack Segment]
ES [Extra Segment]
IP [Instruction pointer]
SP [Stack pointer]
BP [Base pointer]
SI [Source Index]
DI [Destination Index]
ECEg - 4501

General Purpose
Registers

Segment Registers
Base address of segments

Pointer Registers
Offset within a segment

Index Registers
x x x x O D I

Flags

T S Z x A x P x C

25

Summary Address generation

AAiT

Real mode memory addressing

 Memory addresses consist of segment address plus offset address in
the segment.
 A segment address defines the start of a 64KB block of memory
 The offset address points to the location within the 64KB block
 Memory locations are often written as:
Segment : offset
eg. 03C1h : 38A0h
This notation is referred to as logical address

ECEg - 4501

26

Summary Address generation..II

Segment

AAiT

Offset

<< 4
Segment

0000
Adder

-The segment-offset scheme

allows programs to be
relocated in memory on
16byte boundaries

Physical Address

-Memory segments may

overlap

ECEg - 4501

27

Summary Address generation..III

AAiT

Rule of thumb
The P has a set of rules that apply whenever memory is addressed,
which defines the segment-offset register combinations used by
certain addressing modes
Segment

offset

Special Purpose

CS

IP

Instruction Address

DS

BX, BP, DI or SI

Data Address

SS

SP or BP

Stack Address

ES

SI/DI

String source/destination

ECEg - 4501

28

Next lecture: 8086 External View

8086 Datasheet

Pin layout and signal descriptions

Physical memory organization

General bus operations

I/O addressing capabilities

Special processor activities