Serial No.

: A__Analog Electronics_080716_EE_CH1

CLASS TEST - 2016

Electrical Engineering

Analog Electronics

EE

Date : 08/07/2016

ANSWERS
1.

(b)

7.

(b)

13.

(c)

19.

(c)

25.

(b)

2.

(d)

8.

(a)

14.

(d)

20.

(a)

26.

(b)

3.

(a)

9.

(b)

15.

(d)

21.

(c)

27.

(a)

4.

(a)

10.

(d)

16.

(a)

22.

(c)

28.

(c)

5.

(b)

11.

(a)

17.

(d)

23.

(b)

29.

(c)

6.

(c)

12.

(c)

18.

(c)

24.

(d)

30.

(d)

ELECTRICAL ENGINEERING

Explanation
1.

(b)

2.

(d)
The given configuration is a current shunt feedback configuration.
So, the input impedance decreases

Rif =

Ri
1 + KAi

and the output impedance increases, Rof = R0 (1 + KAi)

3.

(a)

4.

(a)

5.

(b)
For unbypassed RE

R i = re + (1 + ) RE and
Av =

6.

AI RL
Ri

(c)
dAf
Af

1 dA
A A

1
(20%) = 0.2%
0.1( 1000)

for A >> 1

The improvement is 100 times. Thus, where as the amplifier gain changes from A = 1000 by 20%, the
gain with feedback changes from Af = 100 by only 0.2%
7.

(b)
Diode resistance

rd =

VT
25mV
=
1 mA
ID

rd = 25
8.

(a)
More the base doping, more the recombination of the electrons diffusing from emitter to collector smaller
is the common emitter current gain.

9.

(b)
Width of depletion region in a PN junction diode decreases with rise in temperature.

10.

(d)
Since the amplifier senses current at input therefore it need low input impedance and it produce voltage at
output therefore it need low output impedance.

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CTEE16 | Analog Electronics

11.

(a)
1 k

II

IL
Iz

20 - 30 (V)

5.8 V

Load

VL = 5.8 V
Maximum load current will be when
Vi = Vmax
= 30 V

30 5.8
= IL + IZ
1k
24.2 mA = IL + IZ
IL = 24.2 mA 0.5 mA
= 23.7 mA
12.

(c)
I =

10 2.1
= 7.9 mA
1000

Incremental resistance,

rd =

VT
2 25 10 3
=
I
7.9 10 3

rd = 6.32
Total incremental resistance = 3 rd
= 3 6.32
= 18.98

13.

(c)
The current Ix is
Ix = IE +

14.

I Ix =

3 IE + 3
=
IE ; IE

VCC VBE
6 0.7
=
= 4.08 mA
Rx
1.3 103

(d)

R1 = 25 k, R2 = 8 k
RTH = 25 8 = 6.06 k

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ELECTRICAL ENGINEERING

8
VTH =
(24) = 5.82 V
25 + 8

Thus the circuit is as follows

+ 24 V

3 k
6.06 k
+5.82 V

1 k

5.82
5.82 0.7
IBQ
IEQ
ICQ
VCEQ

15.

=
=
=
=
=
=
=

(6.06 k) (IBQ) + VBE + ( + 1) IB (1 k)

(6.06 k + 76 k) IBQ
62.4 A
( + 1) IBQ = 4.74 mA
IBQ = 4.68 mA
24 ICQRC IEQRE
24 (4.68) (3) (4.74) (1) = 5.22 V

(d)
3R

V1

V2

V0

2R

By applying KCL at node, we get

V2 V1 V2 V2 V0
= 0
+
+
R
2R
3R
6 V2 6 V1 + 3 V2 + 2 V2
= V0
2

V0 = 3 V1 +
16.

11
V2
2

(a)
From the figure given in the question,
1
R
sC
V0 = Vi 1 + Vi
1
R1
+R
sC

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R1
1 +

R1

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11

CTEE16 | Analog Electronics

2 (1 + RsC )
1
V0
2 =
= 1 +
+
1
RsC
1 + RsC
Vi

=
17.

(d)
For case - i

1 RsC
1 + RsC

Vi < 1.7
D1 ON
D2 OFF
R
+

+
0.7 V
Vi

Vo
1 V

Vo = 1.7 V
For case-ii
1.7 < Vi < 2.7
D1 OFF
D2 OFF

R
+

Vi

Vo

V0 = Vi
18.

(c)
+

Ro1
Vin

Rin

AVo Vin
1

Ro
V2

Rin

AVo V2
2

RL

Vo

RL
V0
=
RL + Ro2
AVo 2 V2

where,

V2 =

...(i)

Avo1 Vin Rin2

...(ii)

Rin2 + Ro1

From equations (i) and (ii), we get

Rin2
RL
V0

= Avo Avo
2
1
RL + R o2 Rin2 + Ro1
Vin

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V0
1k
5k
= 5 10

Vin
1k + 0.2k 5k + 1k

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ELECTRICAL ENGINEERING
V0
= 34.72
Vin

19.

(c)
VCC = +12 V

R1

5 k

R2

10 k

1 F
vi
1 F
vo
RE

1 k

DC analysis
(VB) Q =

VCC R2 12 10 k
=8V
=
15 k
R1 + R2

(VE)Q = VB 0.7 = 8 0.7 = 7.3 V

(VCE)Q = (VC)Q (VE )Q = 12 7.3 = 4.7 V
4.7 V
VCE = Vo

(VCE) Q
4.7 V

Vo(p p) = 2 4.7 = 9.4 V

20.

(a)
By KCL at the node,
0 Vo 0 Vi
+
Z2
Z1

where

= 0
1
Cs
Z1 = R1 = 1 k

Z2 = R2

R2
Z
R2
V
Cs =
or o = 2 =
Z
R
R
(
R
V1
1
1
1 2Cs + 1)
cut-off frequency

1+ R2 Cs

21.

= 0

or

R2 Cs = 1

or

R2 =

1
1
= 3184.7 or 3.18 k
=
Cs
2fC

(c)
When early affect is considered then the IC - VCE plot is approximated by a straight line so from the given
data we get slope of line equal to

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13

2.4 1.8
1
mA / V
=
14 2
20

So the equation of the straight line (relation between IC - VCE)

VCE

+ C mA
IC =
20

value of C can be found by putting (1.8 mA, 2V) in the above equation,
V

IC = CE + 1.7 mA
20

Hence,

Early voltage is the magnitude of value of VCE where IC = 0

So from above equation we get
VA = 34 V
22.

(c)
With all the parameter we draw the small signal model of the circuit, then we will find equivalent resistance
seen across the capacitor. The cut off frequency will be

1
2ReqC

The small signal model is

V0
20 k
gm Vbe

2 k

10 k

+
Vbe

re =

r
+1

2 k

C = 5 F

The base resistance when seen from emitter get multiplied with

So,

1
( + 1) .

r
10k P 2k
+
Req = (2 k ) P

+1
+1

= (2000) || (26.40)
Req = 26.05
So,

23.

f =

1
= 1197 Hz
2 ReqC

(b)
The given circuit work as a simple current mirror,
Since, area of
Q2 = two times area of Q1

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ELECTRICAL ENGINEERING
Therefore,

I0 = 2 collector current of Q1
IC1 =

10 0.7
= 1 mA
9.3 k

I0 = 2 mA
24.

(d)
The input impedance Rin will be

Vin
Iin
20 k
Iin 10 k

Vin

V0

B +
10 k

20 k

Since the circuit has negative feedback, so using virtual short concept
VA = VB
By applying KVL between A and B, we get:
Vin = 20 k . Iin
So
Rin = 20 k
25.

(b)
The gain bandwidth product of the amplifier is constant,
So,
105 10 = 100 fH

fH = 104 Hz

26.

(b)
Since the two port network is symmetric thus conveting it into T network we get the circuit as shown below.
10 k

10 k
I3
1 k

I2
1k I
1

Vi

I1 = I2 =

10Vi
1k

I3 =

and

I4 = I2 + I3 =

or,

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V0

Vi
1k

and

I4

11Vi
1k

V0 = 120 Vi
V0
= 120
Vi

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CTEE16 | Analog Electronics

27.

(a)

165 k

ID

Vi

V0

+
gmVGS

VGS

35 k

7 k

S
RS = 0.5 k
gmVGS

V0 = gm VGS RD
Vi = VGS + gm VGS RS
Vi = VGS (1 + gm RS )
Voltage gain =
=
28.

1.4 7
= 5.76
1 + 1.4 0.5

(c)
Duty cycle =

=
29.

V0
gmVGS RD
gmRD
=
=
Vi VGS (1 + gmRS ) 1 + gmRS

R1 + R2
100%
R1 + 2R2
7.5
2.5k + 5k
100 = 60%
100 =
12.5
2.5k + 5k 2

(c)
I0R + VBE3 = VBE1 + VBE2
I0 =
Since

So,
30.

VBE 1 + VBE 2 VBE 3

R

VBE1 = VBE2 = VBE3

I0 =

VBE
R

R =

0.7
= 70 103 = 70 k
10 10 6

[given : I0 = 10 A]

(d)
Applying KCL at inverting terminal of op-amp,
V0

1 103

= C

Vc =

dVc
dt
V dt

Vt

0
C 01000 = C 1000

From the given data we get,

9=

V0 103

1 106 103
V0 = 9 V

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