2017

WORKBOOK
Detailed Explanations of
Try Yourself Questions

Electrical Engineering
Digital Electronics
 1 Number Systems and Codes

T1 : Solution

Converting into decimal number system

x2 + 3x + 5 + 82 + 4 8 + 4 = 2(x+2)2 + x + 2 + 4
x2 + 3x + 105 = 2x2 + 8 + 8x + x + 6
x2 + 5x 91 = 0
(x + 13) (x 7) = 0
x = 13, 7
base cant be negative
x=7

T2 : Solution

(36)7 = (27)10
(67)8 = (55)10
(98)10 = (98)10
(Z )5 = (Z)5
(241)9 = (199)10
(Z )5 = (199)10 (27)10 (55)10 (98)10
(Z )5 = (19)10
Z = 34

T16 : Solution

Binary No. Gray Code

0000 0000
0001 0001
0010 0011
0011 0010

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 Workbook 3

0100 0110
0101 0111
0111 0100
1000 1100
1010 1101
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000

T3 : Solution

Given that,
(110)r = 4r
so, r2 + r = 4r
r2 = 3r
r = 3
so, (010)3 = 3
so, the answer is 3 and 3.

T4 : Solution

(d)
Given that,
(10)x (10)x = (100)x
x x = x2
and (100)x (100)x = (10000)x
x2 x2 = x4
so, above conditions are valid for all values of x.

T5 : Solution

Since, (123)5 = (x8)y

38 = xy + 8y
so, the equation has 3 solution.

T6 : Solution

(d)
Given that,
73x = 54y
7x + 3 = 5y + 4
from the above equation we can see that option (d) is correct.

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4 Electrical Engineering Digital Electronics

T8 : Solution

(b)
So, the input to adder is y and 1s complement x since carry input in 1.
So, output is complement of x + 1, so output is y x.

T11 : Solution

The 1s complement representation of 127 is 10000000 and 2s complement representation of 127 is

10000001 so the answer is 2/1.

T13 : Solution

Let number N is given to the system.

Output after 1s complement = 15 N
Output after 2s complement = 16 15 + N = N + 1
3 such systems are connected in cascade.
So, Final output = Input + (3)10 = 1010 + 0011
= 1101

T14 : Solution

(d)
From the figure we can see that,
O3 = I3
O2 = I2 I3
O1 = (I2 + I3) (I2 I3) I1
= I 2 I 3 I1
O0 = (I1 + (O2 (I2 + I3))) O1 I0
= I0 I1 I2 I3
From this we can see that, if input is gray code then output is its binary.

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 2 Boolean Algebra & Logic Gates

T1 : Solution

f1 = m(0, 1, 3, 5)
f2 = m(4, 5)
f3 = ?
f = m(1, 4, 5)
and f = ((f1 + f2) + f3)
f = (f1 + f2) f3
so, m(1, 4, 5) = (m(0, 1, 3, 5) + m(4, 5)) f3
m(1, 4, 5) = (m(0, 1, 3, 4, 5)) f3
so, f3 has to be zero for 0, 3 and should be 1 for 1, 4, 5 and dont care for 2, 6, 7.
So, answer is (c).

T2 : Solution

From the figure,

f = (f1 f2 + f 3)
since, f1 = w x z + yz + xz
so, f1(w, x, y, z) = m(2, 4, 6, 9, 10, 11, 12, 14)
and f = m(1, 3, 5, 6, 9, 12, 13)
since, f = f1 f2 + f 3
so, f3 has to be 1 for 0, 2, 4, 7, 8, 10, 11, 14, 15 and dont care for 6, 9, 12.

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6 Electrical Engineering Digital Electronics

T3 : Solution
(b)
(x 1) = x
1 xx=1
1
2
3
x

Output of odd XOR is x .

Output of even XOR is 1.

T5 : Solution

(a)
EXNOR gate on logic in called coincidence logic.
So, f = AB + AB
so option (a) is correct.

T6 : Solution

1 s

8 s
1
Frequency of output = = 125 kHz
8 s

T7 : Solution

(a)
Y from the figure is AB + A(B + C ) + AC + BC

Y = AB + AB + AC + AC + BC

= B + A + BC
= B+A+C

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 Workbook 7

T8 : Solution

[Ans. : (b)]

T9 : Solution

(d)
x y f y
x 0 1
0 0 1
0 1 1 0 1 1
=
x+y
1 0 0
1 1
1 1 1
Since complements are not available.
y

x
x

2 units.

T11 : Solution

(d)
Y = a + a b + a b c + ....
= a + a (b + b c) + ....
= a + a (b + b ) (b + c) + ....
= a + a b + a c + ....
= (a + a ) (a + b) + (a + a ) (a + c)....
= a + b + c...

T12 : Solution

Y = x y z +w y z +w xz

YZ
WX 00 01 11 10
so,
00 1

01 1 1

11 1

10

Y = w yz + xy z
so, Gate (3) is redundant.

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8 Electrical Engineering Digital Electronics

T13 : Solution

(b)
D will be 1 majority of input is 1, so
D = ABC

T14 : Solution

(d)
BC
AB 00 01 11 10

00 0 0 1 0
f =
01 0 0 0 1

so, f = B(A + C) (A + C)

T15 : Solution

Let the 3 locks are A, B, C

0 - key not inserted
1 - key inserted
A B C Y
0 0 0 0
0 0 1 0 BC
A 00 01 11 10
0 1 0 0 0 1
0 1 1 1 1 1 X 1
1 0 0 0
1 0 1 1 Y = AB + BC + AC
1 1 0 1
1 1 1 X
The expression for Y is similar to carry in full adder circuit.
So, Number of NAND Gates required are = 6.

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 Workbook 9

T16 : Solution

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 F
CD
0 1 0 1 0 AB 00 01 11 10
0 1 1 0 1
00 1 1
0 1 1 1 1
1 0 0 0 1 01 1 1
1 0 0 1 1
1 0 1 0 0 11 1 1
1 0 1 1 0
1 1 0 0 1 10 1 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0

A
F = AC + AC = A C C
F

T17 : Solution

(b)
f = A + BC
BC
A 00 01 11 10

0 1
so, f =
1 1 1 1 1

so, f = m(1, 4, 5, 6, 7)

T18 : Solution

(a)
Function f is 1 when x and y are different.
Clearly we can say that,
f = x y = xy + xy

T19 : Solution

The function Y will be 1 when majority of inputs A, B, C is 1 thus

Y = ABC

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 3 Combinational Logic Circuits

T1 : Solution

Y = AB
EXNOR gate find equality between two bits.

T2 : Solution

To generate square of 2 bit input.

A B W X Y Z
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 1 0 0
1 1 1 0 0 1

Input Output

So, input is 2 bit and output is 4 bit

W = AB, X = AB
Y = 0, Z=B

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 Workbook 11

T3 : Solution

(a)
Z = PRS + PQRS + PRS + (P + Q ) RS
Mapping above terms in Karnaugh map
RS
PQ 00 01 11 10

00 1

01

11 1 1 1 1

10 1 1 1

Z = PQ + PQS + QRS

T4 : Solution

(b)
P1 P2 a b c d e f g
0 0 1 1 1 1 1 1 0
0 1 1 0 1 1 0 1 1
1 0 1 1 0 1 1 0 1
1 1 1 0 0 1 1 1 1
a= 1
b = P2 ...1 (NOT)
c = P1 ...1 (NOT)
d= 1 = c + e
e = P1 + P2 ...1 (OR)
f = P1 + P2 ...1 (OR)
g = P1 + P2 ... 1 (OR)
g = P1 + P2
d= 1 = c + e

T5 : Solution

(d)
2 NOT gates
3 OR gates

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12 Electrical Engineering Digital Electronics

T6 : Solution

64 8
+ = 8 +1= 9
8 8

T7 : Solution

(c)
Since the delay is of 1 sec the output will a square wave with time period of 2 sec.
So, frequency = 0.5 MHz

T8 : Solution

The look ahead block has delay of 2 logic gates but input ot the block is given through XOR gate and for
sum we need one gate delay so answer is 4.

T9 : Solution

(b)
Redrawing the circuit

D0
D1
A
D2

B 3x8 f
Decoder D4
A B C D f
C D5
X X X 0 0
D6
0 0 0 1 1
D7
0 0 1 1 0 Enable

0 1 0 1 1
D
0 1 1 1 0
1 0 0 1 0 BC
A BC BC BC BC
1 0 1 1 1
A 1 1
1 1 0 1 0
1 1 1 1 1 A 1 1

f = D (AC + AC )

T10 : Solution

[Ans. (c)]

T11 : Solution

(c)
S1 = A B
C 1 = AB
S = (A B) AB = (A B) AB + (A B ) AB

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 Workbook 13

= (AB + AB) (A + B) + (AB + AB) (A, B)

= AB + AB ) + AB = A + B
C = (A B) AB
= (AB + AB) AB
= 0

T12 : Solution

(a)
D0 X
0 0
1 x 4 D1 F
I0 De MUX 1
D2 Z 2x4
Decoder
D3 2
Y
1 0 C 1 3

A B

X = D0D1 I 0 = (D0 + D1)I0

= (AB + AB) I 0 = A I 0

Y = D2 D3 I 0 = (D2 + D3)I0
= (AB + AB)I 0 = A I 0
Z = (X Y ) = X + Y
= A I0 + A I0 = I0
F = (ZC + ZC) = C(I 0 + I 0 )
= C

T13 : Solution

(b)
To check the output of the adder we need checking circuit that should give output 1 when sum is greater
than 1001 and when ever Co = 1.
So,. Y = Co + S3S2 + S2S1

T14 : Solution

So, Y = ABC I0 + ABC I1 + ABC I2 + ABC I3

+ ABC I 4 + ABC I 5 + ABC I 6 + ABC I7

So, Y = ABC D + ABCD + ABC D + ABC + ABCD + ABC D

= ABD + AC D + ABC + ABC D + ABD + AC D + ABC + ABD

= AD + ACD + ABC

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 4 Sequential Circuits

T1 : Solution

0/0

0/0
1/0
0/0
0/0
0/0 b c

1/0 1/0
0/0
g 1/0 d e

1/1
1/1
0/0 f

1/1

Considering the input sequence 01010110100 starting from the initial state a. Each input of 0 or 1 produces
an output of 0 or 1 and causes the circuit to go the next state. From the state diagram, we obtain the output
and state sequence for the given input sequence as follows. With the circuit in initial state a, an input of 0
produces an output of 0 and circuit remains in state a. With present state at a and input of 1 and the output
is 0 and the next state is b. With present state b and an input of 0, the output is 0 and the next state is c.
Continuing this process, we find the complete sequence to be as follows:

State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0

In each column, we have the present state, input value and output value. The next state is written on top of
the next column.

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 Workbook 15

We now proceed to reduce the number of states. Two states are said to be equivalent if, for each
member of the set of inputs, they give exactly the same output and send the circuit either to the same
state or to an equivalent state. When two states are equivalent one of them can be removed
without altering the input-output relationship.

State Table:
Table:

Present state Next state Output

x = 0 x =1 x = 0 x = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

Now apply the statement written above under inverted comma, we look for two present states that go
to the same next state and have the same output for both input combinations. Such states are g and e.
They both go to states a and f and have outputs of 0 and 1, for x = 0 and x = 1 respectively. Therefore
states g and e are equivalent, and one of these states can be removed. The row with present state g
is removed, and state g is replaced by state e.

Reducing State Table:

Table:

Present state Next state Output

x = 0 x =1 x = 0 x = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1

Present state f now has next states e and f and outputs 0 and 1 for x = 0 and x = 1, respectively. The
same next states and outputs appear in the row with present state d. Therefore states f and d are
equivalent, and state f can be removed and replaced by d. The final reduced table is shown below:

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16 Electrical Engineering Digital Electronics

Reduced State Table:

Table:

Present state Next state Output

x = 0 x =1 x = 0 x = 1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
The state diagram for the reduced table consists of only five states. This state diagram satisfies the
original input-output specifications and will produce the required output sequence for any given input
sequence.

State a a b c d e d d e d e a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0
Reduced state diagram:

0/0

0/0 1/0 0/0

0/0
b c
1/1
e 1/0
1/0
0/0
d

1/1

T2 : Solution

All the counters are positive edge triggered. In 10 clock pulses MSB of counter C1 goes from low to high
once. LSB of counter C1 goes from low to high 5 times.
Output of C1
0 0 0 0 C3
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
C2
1 0 0 0
1 0 0 1

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 Workbook 17

After 17 clock pulse

Count of C2 = 9
Count of C3 = 9
Minimum 17 clock pulses are required to make A = B high again.

T3 : Solution

Set Clear Q(n) Q (n + 1)

Set
Q 1 1 0 0
Qn
1 1 1 1
1 0 0 0
0
1 0 1 0
Q
Clear
0 1 0 1
1
0 1 1 1

Input waveform and output Q waveform.

Let us take initial [Q = 1]

Set 1

Clear 1

Waveform of
'Q'

T4 : Solution

+ + +
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 1 0 0 x 1 x 0 x
0 0 1 0 0 0 0 x 0 x x 1
0 1 0 1 0 1 1 x x 1 1 x
0 1 1 0 0 0 0 x x 1 x 1
1 0 0 0 0 0 x 1 0 x 0 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 0 0 0 x 1 x 1 0 x
1 1 1 0 0 0 x 1 x 1 x 1

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18 Electrical Engineering Digital Electronics

From the above table

For J1 : Q1Q0 Q1Q0 Q1Q0 Q1Q0 For K1 : Q1Q0 Q1Q0 Q1Q0 Q1Q0

Q2 1 X X Q2 X X 1 1
J1 = Q2 Q0 + Q2Q 0
K1 = 1
= Q2 Q0
Q2 1 X X Q2 X X 1 1

T5 : Solution

(d)
The expression of Q+ = S + RQ
S = AB
R = B
so, Q+ = A  B + BQ
= AB + AB + BQ

T6 : Solution

(a)
When A =1 and B = 1
X =Y
Y =X
Now A =1 and B = 0
Y = 1
X = 0
Now A =1 and B = 1
X =Y = 0
Y =X =1
So, the outputs x and y will be fixed at 0 and 1 respectively.

T7 : Solution

(a)
Given that,
if X = Y = 1 then Q+ = 1
X = Y = 0 then Q+ = 0
X = Y = 0 then Q+ = Q
X = Y = then Q+ = Q

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 Workbook 19

so, +
X Y Q Q
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

YQ
X 00 01 11 10

0 0 0 0 1
Q+ =
1 1 1 1 1

Q+ = X + YQ

T8 : Solution

(d)
A B Ci S Co
st
After 1 CP 1 1 0 0 1
nd
After 2 CP 1 1 1 1 1

T9 : Solution

Truth table Excitation table

J K Q (n + 1) Q (n) Q (n + 1) J K
0 0 Q (n)
0 0 0 x
0 1 0 0 1 1 x
1 0 1 1 0 x 1

1 1 Q (n) 1 1 x 0

Design of synchronous counter using J-K flip-flop.

State diagram State assignment

0 00000
9 10001
1 20010
8 30011
2 40100
50101
7 60110
3 70111
81000
6 91001
4
5

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20 Electrical Engineering Digital Electronics

Present stage Next stage

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x
1 0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
2 0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
3 0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1
4 0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x
5 0 1 0 1 0 1 1 0 0 x x 0 1 x x 1
6 0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x
7 0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
8 1 0 0 0 1 0 0 1 x 0 0 x 0 x 1 x
9 1 0 0 1 0 0 0 0 x 1 0 x 0 x x 1

J3 K3
Q1 Q0 Q1 Q0
Q3 Q2 00 01 11 10 Q3 Q2 00 01 11 10

00 0 0 0 0 00 x x x x

01 0 0 1 0 01 x x x x
J3 = Q2 Q1 Q0
11 x x x x K3 = Q0 11 x x x x

10 x x x x 10 0 1 x x

J2 K2
Q1 Q0 Q1 Q0
Q3 Q2 00 01 11 10 Q3 Q2 00 01 11 10

00 0 0 1 0 00 x x x x

01 x x x x 01 0 0 1 0
J2 = Q1 Q0 K2 = Q1 Q0
11 x x x x 11 x x x x

10 0 0 x x 10 x 1 x x

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 Workbook 21

J1 K1
Q1 Q0 Q1 Q0
Q3 Q2 00 01 11 10 Q3 Q2 00 01 11 10

00 0 1 x 0 00 x x 1 0

01 0 1 x 0 01 x x 1 0
J1 = Q3 Q0 K1 = Q0
11 x x x x 11 x x x x

10 0 0 x x 10 x x x x

J0 K0
Q1 Q0 Q1 Q0
Q3 Q2 00 01 11 10 Q3 Q2 00 01 11 10

00 1 x x 1 00 x 1 1 x

01 1 x x 1 01 x 1 1 x
J0 = 1 K0 = 1
11 x x x x 11 x x x x

10 1 x x x 10 x 1 x x

Q1 Q0 Q1
Q2 Q0
Q3 Q0

Q0 Q1 Q2 Q3

1 J0 J1 J2 J3

1 K0 K1 K2 K3

Q0
CLK

Q0

Q1 Q0 Q1 Q0

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22 Electrical Engineering Digital Electronics

T10 : Solution

Excitation table of (S-R) Flip-Flop.

Truth table
S R Qn +1 Q(n) Q(n + 1) S R

0 0 Qn 0 0 0 x

0 1 0 0 1 1 0
1 0 1 1 0 0 1

1 1 x 1 1 x 0

Design of mod-6 counter state diagram.

State diagram

1 2

5
3

State transition table:

Present stage Next stage

Q2 Q1 Q 0 Q2 Q1 Q0 S2 R2 S1 R1 S0 R0
0 0 0 0 0 1 0 0 x 1 0 0 x
2 0 1 0 0 1 1 0 x x 0 1 0
3 0 1 1 1 1 0 1 0 x 0 0 1
6 1 1 0 1 0 1 x 0 0 1 1 0
5 1 0 1 0 0 1 0 1 0 x x 0
1 0 0 1 0 0 0 0 x 0 x 0 1

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 Workbook 23

R2
S2
Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 0 1 0 0 x x 0 x

1 x 0 x x 1 x 1 x 0

S2 = Q1 Q0 R2 = Q1

R2
S2
Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 1 0 x x 0 0 x 0 0

1 x 0 x 0 1 x x x 1

S1 = Q 1 Q 0 R1 = Q2

R2
S2
Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10
0 0 0 0 1 0 x 1 1 0

1 x x x 1 1 x 0 x 0

S0 = Q 1 Q 0 R0 = Q2 Q0

Q0 Q1 Q2

S0 = Q1 Q0 S0 S1 S2

S-R S-R S-R

Q1 Q2
R0 Q0 R1 R2

CLK
Q2

Logic diagram

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24 Electrical Engineering Digital Electronics

T11 : Solution

Excitation table of T flip-flop:

Present Next
state state
Q(t) Q( t 1) T
0 0 0

0 1 1

1 0 1

1 1 0

Present Next
state state
L M Q(t) Q(t 1) T (Based on Q(t) & Q(t 1)
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1

Getting the value of T interms of L, M and Q(t):

F M Q(t)
L 00 01 11 10
2 1
0 1 1 1

1 1 3 1 1

T = M + LQ + LQ = M + (L Q)

M
T Q
L
CLK
Q

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 Workbook 25

T15 : Solution

Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0
0

511 0 1 1 1 1 1 1 1 1 1
512 1

999 1

999 511
Duty cycle of MSB = 100
1000
= 48.8%

T17 : Solution

(c)
For NAND gates: Inputs [(0,1); (1,1)]
Output [(1, 0) ; (1, 0)]
For NOR gates : Inputs [(0, 1); (1,1)]
Output [(1,0); (0,0)]

T18 : Solution

Clock Q3 Q2 Q1 Q0
0 1 0 1 0
1 1 1 0 1
2 0 1 1 0
3 0 0 1 1
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 1 0 1 0

So, after 7 clock we get 1010

T19 : Solution

(b)

Q2Q1Q0 = 011
1st Clk Q2Q1Q0 = 100
Q0 = 1 (triggers T1)
Q1 = 1(triggers T2)

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26 Electrical Engineering Digital Electronics

T21 : Solution

(c)
This is a 3-bit Johnsan counter so it has 6 states.

T22 : Solution

[Ans. : (d)]

T23 : Solution

(a)
If we draw the state diagram of the system we get,
1/0
0/0
0/1
01
00
0/1
1/0
1/1 10

11 0/1
1/0

To reach 11 from 00 we need 111 input sequence. So answer is (a).

T24 : Solution

(a)
10 flip-flops initially at 0.
After 2048 clocks all flip-flop will be 0 again so after 2060 clock count will be 12 i.e. 1100.

\ T25 : Solution

The frequency of output will be clock frequency i.e. 5 kHz.

T26 : Solution

8-bit up counter has initial value

(10101100)2 =(172)10
and to reach (00100111)2 = (39)10
so it need 122 clocks.

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 5 Memories

T1 : Solution

X3 X2 X1 X 0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 0 1 1 0 1 1
0 1 1 0 1 1 0 0
0 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0
1 0 0 1 1 1 1 1
Clearly Y3 Y2 Y1 Y0 is a 2421 code.

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28 Electrical Engineering Digital Electronics

T2 : Solution

ROM has a decodes and OR gate

D0
D1

A D2

B 38 D3

C Decodes D
4

D5
D6
D7

Y3 Y2 Y1 Y0

T3 : Solution

BCD to excess 3 converter

X3 X2 X1 X0 Y3 Y2 Y1 Y0
D0
0 0 0 0 0 0 1 1 D1
0 0 0 1 0 1 0 0 X3 D2
0 0 1 0 0 1 0 1
D3
0 0 1 1 0 1 1 0
X2 D4
0 1 0 0 0 1 1 1
D5
0 1 0 1 1 0 0 0
X1 D6
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 4 16 D7
X0 Decodes D8
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0 D9
D10
D11
D12
D13
D14
D15

Y3 Y2 Y1 Y0

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 6 Integrated-Circuit Logic
Families

T1 : Solution

I IH
Fanout is min OL ,
I IL IOH

16 40
min ,
1.6 8
min {10, 5} = 5

T2 : Solution

(c)
I = IC = 1 mA ( BJT is in saturation)
VBE = 0.75
sat

0.75 = IR .1 k
IR = 0.75 mA

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 7 ADC and DAC

T1 : Solution

(b)

C/P 1 2 3 4 5 6 7

Counter 001 010 011 100 101 110 1000

Decoder
0001 0010 0011 1000 1001 1010 0000
1 2 3 8 9 10 0

D2 is connected to ground and Q2 to D3.

T2 : Solution

(a)
8-bit ADC have full scale value of 2.56 V.
So, LSB = Resolution = 0.1 V
So, 1 V will be equal to (100)10
i.e. (1100100)2

T3 : Solution

Input 110011
Gray code 101010
Input to Digital to Analog converter 010101 = 21
10.5
Analog voltage = 21 = 3.45 V
26

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 Workbook 31

T4 : Solution

(c)
S1 = A B
C 1 = AB
S = (A B) AB = (A B) AB + (A B ) AB
= (AB + AB) (A + B) + (AB + AB) (A, B)
= AB + AB ) + AB = A + B
C = (A B) AB
= (AB + AB) AB
= 0

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