Matlab Project

Sayed Abdullah Sadat

A. Design a controller, Gc(s), that will satisfy the performance specifications given below
due to a step input. Simulate the system using SIMULINK to verify the system perfor-
mance.
P.O. 5%
ts 0.1 tsol (tsol is the open loop settling time)
ess 0 (Steady State Error)

Ans: First we need

to find , for that we have,
P.O. = 100e / 1 2 , as we have P.O.=5

p p
ln(0.05) = / 1 2 , 0.9536 = / 1 2 , = 0.6901

Similarly using the 2% time settling, we run the Simulink block diagram shown in figure one (i.e. without
the control block) and using the plot (Figure 2) we find the open loop settling time.
As can be seen in figure 2, the settling time at 2% is tSOL = 40265.783.

Figure 1: Open-loop block diagram for the given system in Simulink

Using the tSOL = 40265.783 we find tS , the ratio tS /tSOL is given in the question as 0.1.

4
Therefore, ts is 40265.783 0.1 = 4026.5783. We know that tS = n ,
Substituting and tS values we find the n as,

n = 1.4395 104 (r/s)

 Figure 2: unit step response of open-loop system

We have the standard second order form as,

2
n 2.0722106
2,
s2 +2n s+n
which in our case should be, S(s) = s2 +0.002s+2.0722106

In order to obtain the step unit response, a PID controller is used. Using the "Tune" option in mat-
lab PID block we adjust the parameters to get the desired peak overshoot and settling time. These
parameters are obtained as P = 0.0992,I = 0.000272,D = 727.26979, and N = 0.4155738. Figure 3
shows the simulink block digram for the given system with PID continuous-time controller. The unit step
frequency response is also plotted as shown in figure 4.

Figure 3: closed-loop block diagram for the given system in Simulink with PID controller.

Figure 4: Unit step response of the closed loop system shown in figure 3.

B. Determine the closed loop bandwidth of the system above.

Ans: The closed loop bandwidth can be calculated as given below,
 q p
Bandwidth = n (1 2 2 ) 4 4 4 2 + 2

Substituting the n and values in the formula, we get;

Bandwidth = 0.0015

C. Replace the continuous-time controller, Gc(s), with a discrete equivalent, Gc(z), using
the zero order hold" method for the sampling period of 25 x bandwidth. Determine the
percent overshoot, settling time, and steady state error of the system due to a unit step
input. Verify your result by using Simulink. Please, Show all your work and provide a
HARDCOPY of your design procedures. Simulink block diagram, Simulink simulation
output.
The GC (S) is converter to GC (z) using zero-order hold and the sampling period is given as
TS = 25 Bandwidth = 25 0.0015 = 0.0375. The system is simulated and shown in figure 5. The unit

Figure 5: closed-loop block diagram for the discrete time system using zero-order hold with PID con-
troller.

step response for the system in figure 5, is shown in figure 6. The settling time tS is found to be 4068,

Figure 6: Unit step response of the closed loop discrete time system shown in figure 6.

the percent overshoot (P.O) is 4.9% and the steady state error eSS = 0