Sample Final Solutions

ECE 4242/5242 Department of Electrical and Computer Engineering
Advanced Digital Design Methodology University of Colorado at Colorado Springs

Sample Final Solutions "Engineering for the Future"
Dr. Greg Tumbush, gtumbush@uccs.edu
Sample Final Solutions Total of 600 points
1. Minimize the following expression and then check your answer using a Karnaugh Map.
30pts.
(, , ) = + + +
2 solutions both by the Absorption theorem
f(a, b, c) = a bc + cb + a b + b f(a, b, c) = a b c + cb + a b + b
absorption rearrange
f(a, b, c) = a bc + cb + a b f(a, b, c) = a bc + a b cb + b
rearrange OR absorption absorption
f(a, b, c) = a bc + a cb b
absorption absorption f(a, b, c) = a b b
absorption
f(a, b, c) = a b
f(a, b, c) = a b
bc
a 00 01 11 10
0 0 0 1 1
1 1 1 1 1
a
ab a bc cb b
Greg Tumbush Page 1 of 17 Sample Fall Solutions Version 1.0

2. Using a synchronizer design a circuit in gates that will de-bounce a switch with 3ms of bounce.
When the switch is bouncing it only stays at 0 or 1 for a maximum of 500us. See the figure
below for an example of the input. Be sure to clearly denote the clock speed that the de-bounce
circuit will operate at. 30pts
3ms 3ms
async_in
500us 500us
Solution:
A synchronizer is only affected by the total bounce time so the clock speed for a
synchronizer to debounce an input that bounces for 3ms is 1/3ms = 333Hz. The circuit is
below.
async_in q1 sync_out
D Q D Q
clk
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3. Design in Verilog a module that will implement the synchronizer from problem 2. 30pts
Solution:
`default_nettype none
module debounce_sync(
input wire clk,
input wire reset,
input wire async_in,
output reg sync_out

);
These always block can be combined:
always @(posedge clk or posedge reset)
reg reg1_q; begin
if (reset) begin
//First register reg1_q <= 1'b0 ;
always @(posedge clk or posedge reset) begin sync_out <= 1'b1;
end
if (reset)
else begin
reg1_q <= 1'b0 ; reg1_q <= async_in;
else sync_out <= reg1_q;
reg1_q <= async_in; end
end end
//Second register
always @(posedge clk or posedge reset) begin
if (reset)
sync_out <= 1'b0;
else
sync_out <= reg1_q;
end
endmodule

4. Suppose the following circuit has been designed:
a
or2x1
b and2x1
or2x1 out
c
d
The delay through a gate in ns is equal to its number of inputs. The timing constraint (i.e. the
maximum delay on the longest path from input to output) on this circuit is 5.25ns.
a. Does this circuit meet the timing constraint? Explain. 25pts
No this circuit does not meet timing because the delay from input a or b to output out is
2ns+2ns+2ns = 6.0ns
b. What can be done to achieve the same functionality and meet timing? Explain and if a
new circuit is the solution, draw it. 25pts
The timing constraint can be met by reducing the levels of logic to output out. The
resulting circuit is below. The delay from path a or b to output out is now 2.0ns+3.0ns =
5ns
a
and2x1
c
or2x1 out
and2x1
b

5. Write a Verilog procedure (task or function) that will accept two 8-bit inputs, data_in,
and address, and print out the values in hex. 30pts
Solution:
Either a task or function will work. Note that a return type for the function is optional. It
defaults to a single bit wire.
function print_func(input [7:0] data_in, input [7:0] address);
begin
$display("data_in = %h, address = %h", data_in, address);
end
endfunction
task print_task(input [7:0] data_in, input [7:0] address);

begin
end
endtask
6. Repeat problem 5 but wait for 10 time steps in the procedure before printing out the
values. 15pts Take off 10 points of they use a function and 5 points of the delay is not
correct.
Solution:
Only a task will work because the procedure consumes time.
task print_task(input [7:0] data_in, input [7:0] address);

begin
#10;
end
endtask

7. Create a controller in verilog for the Cypress SRAM we went over in class. The controller
will act as a slave and the master will be an ARM processor as in Figure 1. The controller
will support single and bursting writes and reads as well as write followed by read or
read followed by write. Your controller must be synthesizable. Assume an active high
reset is provided. 90pts
AHB-Lite Bus SRAM Bus

ARM Processor SRAM Controller Cypress SRAM
Figure 1: SRAM Control Design Environment
The AHB-Lite bus is in Table 1. Directions are from the ARM Processors perspective
Signal Width Direction Description

HCLK 1 output Clock
HADDR 21 output Address
HWRITE 1 output Write flag. 1=write, 0=read
HTRANS 2 output The transaction type. 2b00 = IDLE, 2b10 =
NONSEQ
HWDATA 8 output Data to write
HRDATA 8 input Data that was read
Table 1: The AHB-Lite Bus
Timing diagrams of a single write and single read for the AHB-Lite bus are in Figures 2 and 3
respectively.

Address Data
phase Address Data
phase
phase phase
HCLK
HCLK
HADDR A
HADDR A
Data
HTRANS NONSEQ valid
HTRANS NONSEQ
HWRITE HWRITE
HWDATA Data(A) HRDATA Data(A)
Figure 2: AHB-Lite Write Transaction Figure 3: AHB-Lite Read Transaction
The Cypress SRAM I/O is in Table 2. Directions are from the Cypress SRAMs perspective
Signal Width Direction Description

A 21 input Address
CE_b 1 input Chip enable, active low
WE_b 1 input Write enable, active low
OE_b 1 input Output enable, active low
DQ 8 inout Bi-directional data for read or write
Table 2: Cypress SRAM I/O
Timing diagrams of a write and read for the Cypress SRAM are in Figure 4 and Figure 5
respectively.
A Address A Address
WE_b WE_b
CE_b CE_b
OE_b OE_b
DQ Data DQ Data
Figure 4: Cypress SRAM Write Transaction Figure 5: Cypress SRAM Read Transaction
Solution:

module sram_control(
// AHB Bus I/O

input wire HCLK,
input wire [20:0] HADDR,
input wire HWRITE,
input wire [7:0] HWDATA,
input wire [1:0] HTRANS,
output reg [7:0] HRDATA,
// SRAM I/O
inout wire [7:0] DQ,
output reg CE_b,
output reg WE_b,
output reg OE_b,
output reg [20:0] A,
input wire reset

);
// Delay the address by 1 clock cycle

reg [20:0] HADDR_q;
// Reg to assign data out values to

reg [7:0] DQ_reg;
parameter IDLE = 2'b00,

WRITE = 2'b01,
READ = 2'b10;
parameter HTRANS_IDLE = 2'b00;

parameter HTRANS_NONSEQ = 2'b10;
reg [1:0] current_state, next_state;
assign DQ = DQ_reg;
always @* begin
// Defaults
DQ_reg = 8'hZ;
CE_b = 1'b1;
WE_b = 1'b1;
OE_b = 1'b1;
A = 21'b0;
case (current_state)
IDLE: begin
if (HTRANS == HTRANS_NONSEQ) begin
if (HWRITE)
next_state = WRITE;
else
next_state = READ;
end
else
next_state = IDLE;
end
// Do the write on the SRAM
WRITE: begin
A = HADDR_q;
CE_b = 1'b0;
WE_b = 1'b0;
DQ_reg = HWDATA;
if (HWRITE)
next_state = WRITE;
else
next_state = READ;
end
else
next_state = IDLE;
end
// Do the read on the SRAM
READ: begin
A = HADDR_q;
CE_b = 1'b0;
OE_b = 1'b0;
HRDATA = DQ;
if (HWRITE)
next_state = WRITE;
else
next_state = READ;
end
else
next_state = IDLE;
end
default: next_state = IDLE;
endcase
end // always
// Current_state = next state on the active edge of the clock

always @(posedge HCLK or posedge reset) begin
if (reset)
current_state <= IDLE;
else
current_state <= next_state;
end
// Delay the address by 1 clock cycle

always @(posedge HCLK or posedge reset) begin
if (reset)
HADDR_q <= 21'b0;
else
HADDR_q <= HADDR;
end
endmodule

8. Answer the following questions:

a) When should the blocking assignment operator (=) should be used? 10pts
When creating combinatorial logic.
b) When should the non-blocking assignment operator (<=) be used? 10pts

When creating sequential (i.e. flip flops, registers, etc) logic.
c) Complete the verilog code to implement the following boolean equation. 20pts
f ab ab
always @(a or b) begin
if (a)
f = !b;
else
f=b;
end

d) Complete the verilog code to implement a registered version of the same boolean
equation. 20pts
always @(posedge clk or negedge reset)) begin

if (!reset)
f<= 0;
else if (a)
f <= !b;
else
f <= b;
end
9. Without using primitives, write the verilog code, complete the timing diagram below
and draw the resulting circuit using the OSU 0.5um library for a positive edge triggered
flip-flop with active low asynchronous reset and active low synchronous set. Recall that
the reset and set inputs for the DFFSR flip-flop in the OSU 0.5um library are active low.
50pts
Solution:
The Verilog code is:

20 pts for the code
module dff(
input wire clk, reset, set, data_in,
output reg data_out
);
always @(posedge clk or negedge reset) begin

if (!reset)
data_out <= 1'b0;
else if (!set)
data_out <= 1'b1;
else
data_out <= data_in;
end 20pts for the timing diagram
endmodule

Timing diagram:
clk
reset
set
data_in
data_out
10pts for the circuit

Circuit:
OR2X1
data_in
set INVX1 D SQ data_out
DFFSR
reset R
clk
10. The following design will create 2 multipliers. Redesign it to use 1 multiplier. 20pts
module resource_sharing (input wire multab,
input wire [31:0] a, b, c,
output wire [??:0] out);
wire [??:0] out_multab = a*b;
wire [??:0] out_multac = a*c;
assign out = multab ? out_multab : out_multac;
endmodule
Solution:
module resource_sharing (input wire multab,
input wire [31:0] a, b, c,
output wire [63:0] out);

assign out = multab ? a*b : a*c;
endmodule
11. What is the bit-width of the output out in problem 10? Why? 10pts
The bit-width of the output is 64-bits because the output bit-width for a multiply
requires the addition of the inputs bit-width, in this case 32-bits each.
12. Answer the following question about the PROM circuit in the figure below. 15pts each
Programmable
OR-Plane (2n x m)
Fusible Link
in[0]
.
in[1]
Address
.
Decoder
n to 2n
.
in[n-1]
En_bar
out[0]
out[1]
out[m-1]
Figure 6
a) Purpose of the decoder
Every minterm of the inputs is created by the decoder. When an output column of the decoder
is asserted, indicating this minterm has been selected by the inputs, the gate of any remaining n-
type transistors is asserted.
b) Action when a row is asserted and the fuse on the BJTs emitter is intact.
A row being asserted causes any BJT with its gate tied to the row to turn on through the pullup
resister. This causes the column that the source or emitter of the transistor is tied to be logic-1

if the fuse is intact. This will cause the output of the column to be logic-0 due to the inverter on
the column output.
c) Action when a row is asserted and the fuse on the BJTs emitter is not intact.
A fuse not being intact will cause column to be pulsed to logic 0 through the pulldown resistor.
The output of the column will be logic-1 due to the inverter on the column output. Since no
other row is asserted the state of the fuses (intact or not intact) on other rows is irrelevant.
d) How a PROM can be used as a memory

A PROM can be used as a memory by connecting the address lines to the select inputs of the
decoder and leaving the fuse intact on any BJT where the output should be a 0 if the row is
selected through the address and blowing the fuse on any BJT where the output should be a 1 if
the row is selected through the address
e) How a PROM can be used to implement a combinatorial logic equation.
A ROM can be used to create combinatorial logic by connecting the variables of the equation to
the select inputs of the decoder and leaving the fuse intact on any BJT where the output should
be a 0 if the row is selected through the address and blowing the fuse on any BJT where the
output should be a 1 if the row is selected through the address.
13. For the circuit in the figure below and the noted fault answer the following questions.
a s-a-1
b
c w1
d w2 x
e
a. Determine the test vector (i.e. the input values) to sensitize the noted fault. Why
does this test vector sensitize the noted fault? 20pts 10pts for the vector, 10pts for why
Solution: The test vector a=0, or b=0, or c=0 will cause w1 to equal logic-0. This
test vector sensitizes the noted fault because the fault location is driven to the
opposite of the fault tested, in this case a logic-0.
b. Determine the test vector (i.e. the input values) to propagate the noted fault to
an output. Why does this test vector propagate the noted fault to an output?
20pts 10pts for the vector, 10pts for why

Solution: The test vector d=1 and e=1, or d=0 and e=0 will cause w2 to equal
logic-0. This test vector propagates the noted fault to an output because if the
fault exists the output will be logic-1. If the fault does not exist the output will be
a logic-0.
14. Explain using words, not an equation, a flip-flops setup time constraint. 15pts
The amount of time before an active clock edge that the input data must remain stable.
0pts for an equation
15. Explain using words, not an equation, a flip-flops hold time constraint. 15pts
The amount of time after an active clock edge that the input data must remain stable.
0pts for an equation
16. What are the valid start points for a timing arc? 10pts
Primary inputs and the clock input of a flip flop.
17. What are the valid stop points for a timing arc? 10pts
Primary outputs and the D input of a flip flop.

18. For the following circuit draw all possible timing arcs. 20pts
tclk_q tcomb tclk_q
t1_comb tcomb_2
tA
A
tA_1 D Q comb D Q t2_B
B
tB
1 2
1 2 4
clk
3 C
tcomb_C tC
5pts for each correct arc.

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ECE 4242/5242 Department of Electrical and Computer Engineering

Advanced Digital Design Methodology University of Colorado at Colorado Springs

Sample Final Solutions Total of 600 points

2 solutions both by the Absorption theorem

Greg Tumbush Page 1 of 17 Sample Fall Solutions Version 1.0

Greg Tumbush Page 2 of 17 Sample Final Solutions Version 1.0

output reg sync_out

Greg Tumbush Page 3 of 17 Sample Final Solutions Version 1.0

4. Suppose the following circuit has been designed:

Greg Tumbush Page 4 of 17 Sample Final Solutions Version 1.0

task print_task(input [7:0] data_in, input [7:0] address);

Only a task will work because the procedure consumes time.

task print_task(input [7:0] data_in, input [7:0] address);

Greg Tumbush Page 5 of 17 Sample Final Solutions Version 1.0

AHB-Lite Bus SRAM Bus

Figure 1: SRAM Control Design Environment

Signal Width Direction Description

Greg Tumbush Page 6 of 17 Sample Final Solutions Version 1.0

HWDATA Data(A) HRDATA Data(A)

Figure 2: AHB-Lite Write Transaction Figure 3: AHB-Lite Read Transaction

Signal Width Direction Description

Greg Tumbush Page 7 of 17 Sample Final Solutions Version 1.0

// AHB Bus I/O

output reg [7:0] HRDATA,

input wire reset

// Delay the address by 1 clock cycle

// Reg to assign data out values to

parameter IDLE = 2'b00,

parameter HTRANS_IDLE = 2'b00;

reg [1:0] current_state, next_state;

// Current_state = next state on the active edge of the clock

// Delay the address by 1 clock cycle

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8. Answer the following questions:

b) When should the non-blocking assignment operator (<=) be used? 10pts

Greg Tumbush Page 11 of 17 Sample Final Solutions Version 1.0

always @(posedge clk or negedge reset)) begin

The Verilog code is:

always @(posedge clk or negedge reset) begin

Greg Tumbush Page 12 of 17 Sample Final Solutions Version 1.0

10pts for the circuit

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assign out = multab ? a*b : a*c;

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d) How a PROM can be used as a memory

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Greg Tumbush Page 16 of 17 Sample Final Solutions Version 1.0

Greg Tumbush Page 17 of 17 Sample Final Solutions Version 1.0

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assign out = multab ? ab : ac;