Professional Documents
Culture Documents
The International
Microprocessor Prize Winner
When Laurent Lamesch casually men-
w a r e
har C
le
By Laurent Lamesch (Luxembourg)
o n cd
sof d &
twa
IC tester '97 re
ft
-'9
-r 8
o m so
B6
B7
PHI
/RD /RD
/IORQ
SOE SOE
/PIO1
17 17
BSTB BSTB
21 21
BRDY BRDY
GND GND
22 27 R32 180 ZIF16 22 27
VCC IEO B0 IEO B0 VCC9
24 28 R31 180 ZIF15 24 28
IEI B1 IEI B1 VCC10
23 29 R30 180 ZIF14 23 29
INT IC4 B2 INT IC2 B2 VCC12
30 R29 180 ZIF13 GND 30
20
GND B3 B3 GND24
25 31 R28 180 ZIF12 25 31
CLK B4 CLK B4
32 R27 180 ZIF11 32
B5 B5
XTAL 1 19 A17 35 33 R26 180 ZIF10 35 33 J5
20
1 19 RD B6 RD B6 R80
SD 2 18 A16 36 34 R25 180 ZIF9 36 34
2 18 IORQ B7 IORQ B7 1
A13 3 17 LCDE 37 37
3 17 M1 M1 390
A14 4 IC5 16 /PIO0 4 4
4 16 CE CE
/WR 5 15 /IORQ
5 15
/PSEN 6 14 /EPROE A11 5 16 A11 5 16
6 14 C/DSE ASTBY C/DSE ASTBY
/RD 7 GAL16V8 13 PHI A14 6 18 A14 6 18
7 13 B/ASE ARDY B/ASE ARDY
B7 8 12 /PIO1 GND GND
8 12
B6 9 11 D0 19 15 R40 180 ZIF24 D0 19 15 R48 180 ZIF8
9 11 D0 Z80BPIO A0 D0 Z80BPIO A0
10
A[0..17]
D[0..7]
VCC
ZIF[1..24]
ZIF[1..24]
11
D5 VCC 27C020 22 Z1 2 Z20 R17 10k ZIF20
12 E
D6 24 21 67 Z16 1 Z21 R16 10k ZIF21
13 G P3.0 RxD P5.0
D7 GND 22 66 Z15 Z22 R15 10k ZIF22
14 P3.1 TxD P5.1 VCC
R79 SD 23 65 Z14 8x4.7k Z23 R14 10k ZIF23
P3.2 INT0 P5.2
10k J1 VCC /EPROE SCLK 24 64 Z13 Z24 R13 10k ZIF24
LTN211 P3.3 INT1 P5.3
SSTR 25 63 Z12
1 P3.4 T0 P5.4
SOE /SOE 26 62 Z11
2 P3.5 T1 P5.5
T2 /WR 27 61 Z10
3 P3.6 WR P5.6
/RD 28 60 Z9
R97 P3.7 ED P5.7
VCC J4 SD
VCC SD
2.2k 11 SCLK
VAREF 1 SCLK
12 20 SSTR
VAGND P6.0 GND 2 SSTR
GND 4 19 SOE
BC547C /PSEN 49
PE P6.1
18
3 SOE
PSEN P6.2 4
GND 51 17
EA P6.3 5
ALE 50 16
ALE P6.4 6
VCC 40 15
XTAL1 P6.5 7
XTAL 39 14
XTAL2 P6.6 8
VCC
VCC
VSS
10 13
RESET P6.7
XTAL1
KeyboardConnector
16
8
68
AN0
2 1 10k
+
VCC
V+ C1+
+ C17 + 12MHz
10u
10u
+
J6 14 11
T1OUT T1IN
7 10
1 T2OUT T2IN
13 12
2 R1IN R1OUT
GND
8 9
R2IN R2OUT
15
GND
Figure 1. Circuit diagram of the digital control circuit and the RS232 interface.
All input pins of the device under test by means of the outputs on the Z80PIOs 1, 4 and 5 of the 80C535 are used to
(DUT) inserted in the Textool zero-inser- and current limiting resistors. The same detect which DUT pins represent a high
tion force socket, ZIF1, may be pulled PIOs also enable the logic states of the impedance. Furthermore, the supply
to the logic high (H) or logic low (L) level DUT outputs to be checked, while ports voltage pins of the DUT may be con-
1
2
3
GND GND GND GND GND GND GND GND 1k 1k
BC639-16 BC640-16
R75 ZIF24
10k
J3 + +
C2 C14
CON3 10uF 10uF GND GND
J2 VCC ZIF22 R56
1
2
3
D4
+9..15V 1 10k
GND GND
GND 2 R70 R49 T5
D2 G22 T15 V22
1N4001 C10
+
1k 1k
BC639-16 BC640-16
RN5-8 ZIF22
470uF35V 1N4001 Pin16 Pin4 Pin4 Pin20 Pin32,31 Pin20 Pin16
10k
GND GND IC1 IC2 IC4 IC5 IC7 IC8 IC9
GND GND
Pin8 Pin26 Pin26 Pin10 Pin16 Pin10 Pin8 R58
GND ZIF21
10k
GND 10k
1nF R89 R83 GND GND
39k 1k ZIF17 R60
IC6D 10k
D3 13
14 G17 R66 T19 V17 R53 T9
GND
12 R82
1k 1k
1k V9
1N4148 VCC9 BC639-16 BC640-16
V10 RN5-4 ZIF17
LM324 VCC10
V12
VCC12 10k
R84 G24
GND24
6.8k GND GND
ZIF10 R62
10k
C1
C23 R65 T20 R55 T10
GND 1 4 V17 G10 V16
100nF SD
2
STR IC9 Q1
5 V19
SCLK D Q2 1k 1k
1nF 3 6 V21 BC640-16
SSTR CLK Q3 RN5-3 BC639-16
GND 15 7 V20 ZIF16
SOE OE Q4
11
IC6A 14 10k
R91 Q5
D1 2 13 V16
1 Q6
12 V22 GND GND
100k Q7 R78
3 11 V24 ZIF15
Q8
1N4148 10k
LM324 74HC4094 9
4
GND GND
ZIF12 R77
1 4 G22 10k
2
STR IC1 Q1
5 G21
IC6B 6 3
D Q2
6 G20 G12 R64 T22 V10 R73 T12
CLK Q3
7 15 7 G7
OE Q4 1k 1k
5 14 G10 BC640-16
Q5 RN5-2 BC639-16
13 G17 ZIF10
LM324 Q6
12 G12
Q7 10k
11 G15
Q8
GND GND
74HC4094 9 R76
QS
10 10k
QS
R72 T13
V12
1k
BC640-16
ZIF12
Figure 2. Circuit diagram showing the DUT interface and the power supplies. 982020 - 12
nected to GND or a current-limited volt- EPROM is used, connect J1-2 to J1-3. Pressing the escape key takes you to
age source via switching transistors. A 9-way sub-D socket is connected the main menu. There, the following
This voltage source (built around IC6) to J6. This enables you to connect the functions may be selected:
supplies 5.2 V, and its output current is IC tester to the RS232 serial port on your 1. Test IC: the user picks an IC from
limited to about 0.2 A. The actual out- PC. Ground for the serial interface is an IC library, and the DUT is
put current is converted into a propor- taken from J2. The pin connections of checked for correct operation. The
tional voltage for measurement by the the sub-D socket are as follows: test may be repeated. If indicated
controller. by the test vectors, the current
Depending on the size of the test 9-way sub-D J6 J2 consumption of the IC under test is
vector files, the control program of the 2 1 measured and displayed.
3 2
IC tester is contained in a 27C512, 5 2 2. Identify: this allows you to identify
27C010 or 27C020 EPROM. If multiple the type number of an unknown
banks are present inside the EPROM, IC. If the GND and Vcc pins are
then the selection between the 64- Adjustment unknown, only those test vectors
kByte chunks is accomplished by out- are used that have the GND and
puts B6 and B7 of IC2. The 80C535 also The only adjustment in the circuit is the Vcc pins at the same positions. The
controls an LC display and a keyboard DUT supply output voltage. This is set to GND/Vcc pin entry is optional.
with 6 keys. A GAL, IC5, looks after the 5.2 V 0.05 V using preset R82. Next, you can select the libraries
address decoding, and also generates that have to be scanned.
the PHI signal for the Z80PIOs. Operation 3. Retest IC: once an IC has been
The reason for using the Z80PIO to tested or identified, it may be
control and monitor the DUT inputs and The tester is operated using six keys tested again without having to pick
outputs is that this chip is the only labelled Enter, Escape, dn (scroll down), it from the libraries.
widely available 16-bit parallel port IC up, dn2 (fast scroll down), and up2 (fast 4. Trace: all test vectors and the
of which all port line directions are indi- scroll up). The up and dn keys have an response of the DUT to these vec-
vidually controllable, while the output auto-repeat function which causes the tors appear in succession on the
drivers for all port lines consist of push- repeat rate to be automatically LC display.
pull circuits. increased as the key is held depressed. 5. Options: here, you can define
Jumper J1 selects between a 28-pin LED D5 lights to indicate that the IC global options.
and a 32-pin EPROM in position IC7. under test is being powered, and 6. Info: information on version and
When a 28-pin EPROM is used, J1-1 is should not be removed from the ZIF copyright.
connected to J1-2. When a 32-pin socket. 7. Self Check: the IC tester hardware
may be checked using this func- LIST.OUT: List file containing information D5 J7
tion and a voltmeter. on the source file, the binary file, a Led red 3mm
1
1
2
3
4
5
6
7
8
8. Remote Mode: connect a PC to copy of the source file with line num-
the RS232 interface and debug bers, plus, for each line, the bytes that J8
1
SW3
2
test vectors using the DOS program were generated from this line. 3
4
'DN2'
SW2
TVCHK.EXE. TMP.OUT: temporary file, used by 5
6
7 'DN'
ICTVC.EXE. 8
SW1
The up/dn keys are used to scroll one If an error occurs during the compila- 'ESC'
SW5
item up or down. The up2/dn2 keys do tion phase, the relevant error reports 'UP'
the same, but then five items at a time. are written to ERR.OUT. Error reports are SW6
The ent(er) key is used to confirm a not displayed on the PC monitor. 'UP2'
SW4
selection. Esc, finally, jumps to the main TVCHK is a shell program which calls 'ENT'
le
comprises a manual in Word format and some
o n cd
examples. sof d &
twa
ft '97 re
-'9
By Ben de Waal (USA) -r 8
o m so
le
comprises a manual in Word format and some
o n cd
examples. sof d &
twa
ft '97 re
-'9
By Ben de Waal (USA) -r 8
o m so
le
o n cd
by U. Reiser (Germany) sof d &
twa
'97 re
Cable Tester
ft
-'9
-r 8
o m so
IC4
LM2940CT
* T1
provides 12 outputs which supply differ- C3 R2
rot
10k red
ent pulse codes. The receiver detects 100n
14 4
rouge
MCLR rood
the code and indicates it on a 7-seg- RA4
3 BC547B
6 12
2 3 13 6 14 15 6...9V
Transmitter and receiver M
RB7
OSC2 OSC1
RB0
M
IC2 15 X1 16 5
IC3
Both the transmitter and the receiver CD4050
* CD4050
*
are based on a RISC microcontroller C1
4MHz
C2
le
o n cd
by U. Reiser (Germany) sof d &
twa
'97 re
Cable Tester
ft
-'9
-r 8
o m so
IC4
LM2940CT
* T1
provides 12 outputs which supply differ- C3 R2
rot
10k red
ent pulse codes. The receiver detects 100n
14 4
rouge
MCLR rood
the code and indicates it on a 7-seg- RA4
3 BC547B
6 12
2 3 13 6 14 15 6...9V
Transmitter and receiver M
RB7
OSC2 OSC1
RB0
M
IC2 15 X1 16 5
IC3
Both the transmitter and the receiver CD4050
* CD4050
*
are based on a RISC microcontroller C1
4MHz
C2
100
* siehe Text
1k
D3
* voir texte D5 far end of the cable, a run-in start bit is
T2
BC547B rot
5V transmitted (1 ms low/1 ms high), as well
red
rouge
as a stop bit, which is a 4-ms long
BC547B rood
pause (high). The total length of a pulse
C1 R5 R6 b
a sequence is 29 ms.
3k3
3k3
LD2
100n 14 4
1
3
CA
8
CA
c The PIC outputs are connected to
MCLR g
RA0
17 2
f
drivers (type 4049 using the TRANSM49
R2 RA1
18 4
e
S1 program, or type 4050 if you use the
1 5
RA2 d
TRANSM50 version). These buffers
68k
2 R7 7
RA3 820 c 5V
R8
820
9
b ensure that sufficient drive current is
IC1 10 a
dp available for relatively long cables. By
PIC16C84-4 6 HD1105 * b way of constant-current source T1, out-
a
R1
10k
3
RA4 RB0
6 LD2 3 8 c
put RA4 (RTTC) causes the power on
RB1
7 R9
820
1
g
CA CA LED, D4, to flash at a rate of 0.5 s (i.e.,
8 R10 2
RB2
9 R11
820
4
f during the high pause of the test rou-
RB3 820 e
RB4
10 R12
820
5
d
tine). The zener diode makes it impossi-
D1 11 R13 7
RB5
12 R14
820
9
c ble for the LED to light when the battery
RB6 820 b
RB7
13 R15
820
10 a 6...9V voltage drops below the zener voltage.
6V1 dp
0W5 OSC2 OSC1 6
In this way, the LED also acts as a use-
15 X1 16 5
HD1105
* ful low-battery indicator. The transmit-
C4 C5
ter operates off a regulated 5-V supply,
4MHz with only the on indicator being pow-
15p 15p
ered directly by the battery.
982022 - 12
In the receiver (Figure 2), the trans-
mitter signal is evaluated by a
Figure 2. Circuit diagram of the receiver. PIC16C84. The signal
picked up by the test
probe is applied to
Schmitt-trigger input RA4
via a current-limiting
resistor, R1. R2 pulls the
non-used input high,
while D1 eliminates input
voltage surges. The PIC
is constantly busy evalu-
ating the received pulse
trains. If a particular
sequence is recognised
twice in a row, the rele-
vant wire number
appears on the two-digit
LED display. If the test
Figure 3. PCB copper track layouts and component overlays. probe remains logic
high longer than 3 s, the
display is cleared and
the power on LED
flashes (current saving
mode).
Pulses (1 ms low, 1 ms
high) are recognised by
means of three level
measurements. In
standby mode (input
high) the software exe-
cutes a delay loop. If a
low level is detected, the
signal level is checked
again during the pulse
time (after 0.776 ms), to
make sure the first pulse was not Figure 3. The only point to note in the probe to ground, whereupon the buzzer
caused by interference. After a second construction of the transmitter is that the should sound.
period of 0.776 ms, the software assembly code file matches the buffer The circuits are fitted in ABS (strength-
checks that a logic high level is pre- IC you want to use (4049 or 4050). The ened plastic) cases (1016026 mm)
sent. If so, the pulse is considered valid. receiver board allows you to use either having a battery compartment. In the
Next, it is registered in a counter, and common-cathode or common-anode transmitter case, drill one 6-mm hole for
then, after a high period of at least 7-segment displays. In the first case, the miniature toggle switch, fourteen 1-
2 ms, compared with the result of the you fit wire jumpers a-c, else, a-b. Here, mm holes for the outputs plus ground,
previous count. If the result is a match, too, two different programs are avail- and one 3-mm hole for the LED. The test
the wire number is sent to the LED dis- able (receiano.asm and receicat.asm), wires are made from short lengths of
play. If not, the previous result is over- and your choice must match that of light-duty flexible wire and miniature
written by the current one. the displays fitted on the board. test prods or crocodile clips. Inside the
Apart from the pulse interrogation Having finished the soldering work, transmitter case, each wire should have
and the high-level monitoring, the low you may connect the circuits to a its own strain relief in the form of a knot.
duration at the IN input is also under benchtop supply and check that the In the receiver case you should drill
constant examination. If the input supply voltage is 5 V behind the low- holes for the switch and the LED. Also, a
remains low longer than 48 ms, the dis- drop regulators. You may also check 20 by 13 mm rectangular clearance is
play is cleared, D5 is switched off, and the operation of the Low-Battery func- required for the 7-segment displays. Two
RA0 supplies a 2.5-kHz signal to T1. The tion by turning down the supply volt- additional 1-mm holes are required for
transistor, in turn, drives a piezo sounder. age. If the on LED starts to flash after connecting wires to the test probe and
This is the previously mentioned conti- you switch on the transmitter, you may the ground connector. As with he trans-
nuity tester function of the circuit. safely assume that this circuit is func- mitter, these wires should have knots
Meanwhile, the software examines the tional. The different pulse trains sup- acting as strain reliefs at the inside of
input every 0.4 ms. If a high level is plied by the transmitter outputs are eas- the case. (982022-1)
detected, the routine is left. ily observed if you have an oscillo-
The transmitter and the receiver are scope.
each powered by a 9-V PP3 battery. At power-on, the receiver first performs
Both circuits incorporate low-drop volt- a test routine on the displays. If every-
age regulators which enable the batter- thing works as it should, the following dis-
ies to be used until they are almost flat. play segments are switched on one after
another, at 0.6 s intervals: 0b, 0c, 0a, 0d,
Construction 0g, 0e, 0f, 1b, 1c. The piezo buzzer
sounds when the last segment lights. The
The two copper track layouts and com- on LED also lights all the time. As a fur-
ponent mounting plans are shown in ther test, you should connect the test
w a r e
har C
le
Display Refresh
o n cd
sof d &
twa
'97 re
ft
-'9
8
Meter
-r
o m so
Figure 1. The circuit diagram of the display refresh meter contains just a few ICs.
The circuit is built around a member of The package consists of an assembler programmed by way of an SPI bus (ser-
the new AVR RISC processor family from (WAVRASM v. 1.11), a debugger (AVR ial programmable interface). The
Atmel. The development software used Studio v. 1.01 for Windows95/NT) and development board and the associ-
for the project may be found on the the AVR development board software ated software may be obtained from
Atmels Internet site, www.atmel.com. (v. 1.15). The microcontroller may be Atmels sales offices.
PLD Gyroscope
a ila
Version II av P- b
w a r e
har C
le
o n cd
sof d &
Technical characteristics twa
- True closed loop for rotation control '97 re
t
-'9
f
- Auto-calibrate at power-on -r 8
- Remote control for gain (gyroscopic sensitivity) o m so
- Clutch disengage mode with direct retransmission and no restrictions to rotation control
- Watchdog with reset and automatic return to neutral when radio signal fails
- Axial-vibration resistant
- Low power consumption
- High reliability without risk of wear and tear
- Aluminium case protects against dust and water ingress, also reduces electrical noise
- Low cost and weight
model
receiver +
target gain error Ton Ton
value
servo mechanism
(delta)
integrating
rotational
amplifier speed
measurement
(delta) measurement
sensor
conversion
coefficient
measurement
(0) 982024 - 11 ets, which either serve to receive the
servo-control connector, or provide the
Figure 1. Basic structure of the regulation loop applied in the gyroscope.
link with the voltage doubler module.
Potentiometer P1 enables deviations in
The operation of the present gyroscope 0.4 ms) whose function is to control the sensor output voltage to be com-
is based on a regulation loop as shown the amount of rotation of the radio- pensated (1 V in the stand-by state).
in Figure 1. One channel of the radio controlled model. To adjust the pot, apply power to the
control receiver supplies the target gyroscope and turn the wiper until a
value of the rotation. The other channel The schematics voltage of about 2.5 V is measured at
supplies the gain control information. the opamp output (pin 6).
The target and gain data consist of Figure 2 shows the schematic diagram The schematic shown in Figure 3 is
pulses with a variable length (1.5 of the PLD Gyroscope. Apart from the that of a voltage doubler which may
0.4 ms). The loop compares the vari- components already mentioned (PIC be required in case the present circuit
ation of the target value with the varia- U2 and Gyrostar U4), theres not a lot is used in or on a model which is pow-
tion of the measurement result supplied that goes into this design: one voltage ered by a 4.8-V battery pack. The volt-
by the Gyrostar rotation sensor. regulator, U1, and one opamp, U3! The age doubler is not required if your R/C
Depending on the difference between voltage regulator is a low-drop type model uses a battery voltage of 6 volts
these two values (error signal), a pulse from National Semiconductor. The cir- or more. Basically, the circuit contains
is produced with a length T on (1.5 cuit comprises a number of 3-pin sock- just a 555 (U1) and three pairs of sock-
1k2 3 G 1
OUT IN
R05V N
D
C6 2 C4
Construction P1
R1
3
7
6
U3 100u
CR15
1u
CP2
R2
8DIP
R4
C5 3 4
GYROSTAR
10k
R05V
100k
R05V
15
OSC1 OSC2/CLKOUT
100
JMP2X1
SIGN
4MHz
1
2 2
your model is a car or a boat, and to 3
HE14/3M
OUTPUT
3
HE14/3M
planes.
2) Install the gyroscope in the rotation
JP4
axis of the model, with U2 and U4 JP3
1
2
1
2
GAIN
HE14/3M
3
HE14/3M
JMP3x1 JMP3x1
axis. GAIN_REC
VCC
GAIN_GYR
Vdd
cables! 1k
R05
4
10k
Q1
BC640
TO92
C4
1u
C5
1u
JP1
2 CP2
1 CP2
5) Set the rotation and gain controls to 2
3
C6
100uF
CR15
C1
1u
CP2
R2
10k
6
TR
TH CV
5
R05 1
2
3
982024 - 13
1 SPL
+ 15 dB
+ 10 dB
+ 5 dB
0 dB
+ 5 dB
10 dB
15 dB
9V
amplifier, a full-wave rectifier, and D1
2 an LED display. The microphone is
C7
3
D3
10
L10
9 11
R1 MODE L9 D4
C2 R7 IC2 12
L8
22k
5
20k0 SIG 13
6 L7 D5
100 10V R6 RHI 14
P1 7 L6
10k0 REFOUT 15
L5 D6
12k
1k
100k
D10
C3 9V
C4 C8 D11
100 10V
5
SIG 13
6 L7 D15
BT1 13 RHI 14
7 L6
14 R12 REFOUT 15
12k
C9 4 C6 IC1d L5 D16
9V 12 LM3915 16
IC1 L4
220 100n R15 8 17
11 C5 REFADJ L3 D17
1M
25V 18
820
R13 L2
4 1
RLO L1 D18
220n
P2
2
D19
1k
D20
970085 - 12
D19
D18
D17
D16
D15
D14
D13
D12
D9
D8
D7
D6
D5
D4
D3
D2
D10 D20 D1 D11
H3
P1
H1
C3
R4
C2 IC2
R14
R15
C7
D21
R1
R2
R5
C5
R11
IC1
R3
IC3
R13
R9
C8
MIC1
C1
C4 R12
C6
T
R10
R6
P2
D22
R8
H2
H4
R7 C9 + 0
Figure 3. Printed-cir-
Parts list (IC1b and IC1c), and cuit board for the very well. It is therefore
the LED display (IC2, sound-pressure meter. out of the question to
Resistors: IC3, and D1D20). Special care is needed use microphones of
R1 = 22 k Op amp IC1d is used when mounting the unknown origin with
R2 = 220 for creating a virtual LED display. vague or uncertain
R3, R14, R15 = 1 M
earth at half the supply properties. On the
R4 = 1 k
R5, R6, R8 = 10.0 k, 1% (but see voltage. other hand, an expen-
text) The microphone in this application sive standard (test) microphone is a
R7 = 20.0 k, 1% (but see text) must meet certain requirements, of superfluous luxury. A good, linear
R9, R10 = 100 k course, even though it is used in a low- electret microphone is a very good
R11, R12 = 12 k budget version of a sound level meter. compromise between these extremes.
R13 = 820 It must, for instance, be fairly linear, The prototype instrument uses a type
P1 = 47 k (50 k) preset otherwise the circuit cannot perform that is linear within 2 dB over the
P2 = 1 k preset
Capacitors:
C1, C6, C7, C8 = 0.1 F
C2, C3 = 100 F, 10 V, radial 4
C4 = 10 F, 63 V, radial
C5 = 0.22 F
C9 = 220 F, 25 V, radial
Semiconductors:
D1D20 = LED, 3 mm, high effi-
ciency
D21, D22 = BAT85
Integrated circuits:
IC1 = TL074CN
IC2, IC3 = LM3915N
Miscellaneous:
MIC1 = electret microphone with
rubber surround (e.g., MCE2000
from Monacor )
BT1 = 9 V battery with terminal clips
1 off single-pole on/off switch
Case: as desired - see text
PCB Order no 970085-1 (see Read-
ers Services towards the end of
this issue)
Monacor
Inter-Mercador GmbH & Co, KG
Postfach 448 747
D-28286 Bremen
Germany
Telephone +49 421 78650
Fax +49 421 488415/488416
tified signal is differentiated by net- great care is required during soldering. Usable test signals to
work R10-C4 (which constitutes a large Potentiometer P1 has intentionally obtain a frequency characteristic as
time constant) before it is applied to been connected the wrong way described earlier may be obtained
the LED display. around, that is, it has to be turned from the following test CDs: The Test
The display is driven by the well- clockwise to reduce the amplification. (Stax, AXCD 92001); Compact Test
known Type LM3915 drive (IC2). This Note that although E96 type resis- (Pierre Verany, PV 784031); Hi-fi Check
IC contains a voltage reference source, tors are specified for R5R8, E24 types (Stereoplay); and CD-2Check (Monacor
a precise potential divider, and ten may also be used if unavoidable. Their 30.0180).
comparators, each of which can drive values should then be 11 k instead of When the frequency response is
an LED directly. The level of the input 10.0 k or 22 k instead of 20.0 k as being measured, it is advisable to place
voltage to the driver is displayed by the case may be. the loudspeaker well away ( 1 metre)
the LED array in ten steps of 3 dB The prototype is housed in a from reflecting walls or other objects.
each. translucent case, which has the advan- Set the volume of the audio system to
Of course, 3 dB-steps are rather tage of not needing a cutout for the a level where the test signals are well
coarse and the resolution has, there- display. But, of course, any suitable or above the ambient noise level at all
fore, been enhanced by the addition of available case may be used, as long as times. When a suitable level has been
a second driver, IC3, whose reference the battery and finished board can be found, adjust P1 on the sound-pres-
has been shifted by 1.5 dB. This is fitted comfortably inside. sure meter to obtain a 0 reading on the
done by making the potential at the Do not omit the rubber surround LED display.
REFADJ(ust) pin (8) 1.1885 higher supplied with the microphone when Bear in mind that at frequencies
than that at the corresponding pin of fitting this on to the case. This sur- below about 200 Hz, effects of the
IC2. This makes D11 the top of the round damps spurious vibrations and room or hall are so strong that the
decibel scale, followed by D1, D12, D2, makes the microphone less susceptible measured levels say hardly anything
D13, and so on. In other words, the to reflections in or of the case. about the performance of the loud-
LEDs driven by IC2 and IC3 are inter- The display must, of course, be speaker being tested. This may be
laced. This method has a slight draw- given a suitable scale of 15 dB. The checked by holding the microphone
back in that during measurements two scale should have a 0 at its centre and right in front of the loudspeaker. It will
LEDs light simultaneously: the correct this may be placed halfway between be found that a number of peaks and
test result lies somewhere between D5 and D16 as shown in Figure 5. The troughs measured earlier (at the nor-
them. However, it was found that the other markings at 1.5 dB steps are mal test distance of 1 metre) disappear.
operator quickly gets used to this. placed accordingly. An impression of the acoustic per-
formance of the room or hall may be
P O W E R S U P P LY SHIFTING THE obtained by repeating the response
Since the meter is intended for use as REFERENCE OF IC3 measurement at a distance of
a portable instrument, the power sup- 34 metres from the loudspeaker. At
ply must be battery-operated. The Preset P1 is set according to the test CD that distance, there is no question any
current drain is not greater than used, and this will be discussed in the longer of a flat response!
19 mA, so that a 9-V battery will give next section. [970085]
about 100 hours service under normal Preset P2 sets the 1.5 dB shift of the
s
Digital signal processing (DSP) is largely con- Box 1. Feamatyubre eexecuted
s
xample
cerned with the application of Fourier and l All e
directly analysis
e fi les for ny
z-transform techniques to a wide variety of us w a v for ma
l Vario of programs
ty
scientific and engineering problems. Since it l Varie M
appli a c tions CD-RO
d e s on the
involves a transformation of sampled data into l All s
ource c
o
O-PAS
CAL
ri-
the discrete frequency domain, the methods n in TURB x expe
w r it te
fo r c o ple
m
s
ch file
find use in both signal analysis and signal pro- l Bat ansfer
ments f c o m plex tr
o
cessing. Although DSP is very much a tech- l Sim
ulation
e not
nique of the late 20th century, it is based on system
s
o f h ardwar
n
structio
Nyquists sampling theorem, which dates back l Con y
ar
necess
to 1928. Although DSP techniques are highly
This six-part course will
mathematical, this new six-part course will be endeavour to make the most essential
basics of digital signal processing acces-
based on worked-out examples and experi- sible to the reader by examples and
ments. For these, only a PC with soundcard experiments. All the reader needs is a
middle-of-the-road PC equipped with
and CD-ROM drive are necessary. sound-card and CD-ROM drive.
By M. Ohsmann
SEVERAL LEVELS
The simplest of these is simply to carry
Box 2. Parameters of wave files
out the experiments without fully Sampling rate 44 100, 22 050, or 11 025
understanding the fundamentals Bits per sample 16
underlying them.
Format uncompressed
The next one is to carry out new
experiments at the hand of the pro- Channels mono(phonic)
gram supplied The course includes
helpful suggestions for these.
A further level is for readers to
study the mode of operation of the
Box 3. Planned course content
program at the hand of the source 3 Wave files, 3 sampled signals,
texts and the explanations given. Fol- 3 sampling theorem, 3 aliasing,
lowing this, they can write their own 3 downsampling, 3 recursive low-pass and band-pass filters,
program(s) for signal processing and 3 signal generators, 3 filter analysis with sweep frequency,
design their own experiments. 3 spectrum analyser, 3 discrete Fourier analysis,
Finally, they may try to transfer the 3 fast Fourier analysis (FFT), 3 echo generation,
course material to a specific signal 3 step response and frequency response of filters,
processor. It should be noted, however, 3 filter design, 3 finite impulse response (FIR) filters,
that this requires much experience of 3 noise signals, 3 filter analysis with noise signals,
programming since there are a number 3 periodic signals, 3 Fourier synthesis,
of obstacles in the way, such as scaling, 3 frequency modulation, 3 amplitude modulation and demodulation,
differential arithmetic, initialization of 3 phase modulation, 3 quadrature process,
hardware components not covered in 3 wireless facsimile, 3 RDS (radio data services) modulation.
the course (since they do not really per-
tain to signal processing). Those wish-
ing to go into this direction should read inputting of a series of programs in a instance, possible to reconstruct the
relevant publications which will be prescribed order. For example, signals complete response of an SSB trans-
mentioned at the end of the course. are generated, modified (with the aid mitter with the aid of file SSB RECEIVERS.
The contents of the course are of filters), and then displayed. It is, for Since a single experiment frequently
given in Box 3. As mentioned in the
summary, DSP is highly mathematical,
but the course will avoid as much
mathematics as possible.
Box 4. Programs on the CD-ROM
Signal generators
SOF TWARE SIN0 sine wave generator
The signal processing programs pre- SIN1 sine wave generator
sented and used in the course are con- PULSE1 pulse generator
tained as .EXE files on a CD-ROM STEP1 step-wave generator
which will be available through the NOISE1 white-noise generator
Readers services from February 1998 FMSWEEP1 sweep generator
onwards. These programs will enable MUSICG1 sound-program generator
readers not only to carry out the set
exercises, but also to analyse and pro- Filters
duce their own data. SINFIL1 simple band-pass filter
The contents of the CD-ROM are BANDP1 simple band-pass filter
shown in Box 4. BUTTER1 digital Butterworth filter
LP1 simple low-pass filter
Installation ECHO1 echo generator
The software installation instructions FIRFIL1 general-purpose finite impulse response (FIR) filter
are contained in file INSTALL.DOC on the SPECFIL1FIR filter synthesis
CD-ROM mentioned earlier. Basically,
the programs are copied in a specific Modulation, demodulation, mathematics
directory and added, when required, DWNSMPL1 downsampling
to the long WAV files for the relevant SUM1 weighted sum of two signals
part of the course. The CD-ROM also MUL1 product of signals (mixing function, etc)
contains some helpful suggestions AMGEN1 amplitude modulation, synchronous demodulation,
how best to get acquainted with the mixing
software. FMGEN1 frequency modulator
SCHMITT1 Schmitt trigger function
Source codes SHORT1 signal window spacing
Most programs are written in TURBO- RTTYRX1 decoding of serial facsimile data
PASCAL 5.0 and their source code is
included on the CD-ROM to enable Analysers
readers to extend and modify them. INFO1 general information, average value, signal energy
The method of operation of a program SCOPE1 multi-channel oscilloscope
is frequently explained in the course SPEC1 multi-channel spectrum analyser
on the basis of the source code to clar-
ify a particular concept. Miscellaneous
SHELP help function for the PASCAL/EXE program
Experimentation files SPP preprocessor for experimentation files
Many experiments require the
Figure 1. Generated
waveforms are dis-
played as on an oscil- readers themselves to be processed. All enable them to resolve many mea-
loscope. such signals are processed in wave surement problems with the course
files. In the present course, wave files programs. Such files will extend the
(ending in .WAV under DOS or Win- operating range of their PC apprecia-
needs a number of files, there is a sim- dows) form the central means of bly. It is, of course, important to
ple facility of accessing them all at once exchanging data between files. Various arrange the recording parameters so
by means of a preprocessor. parameters of the data are stored in that the programs can execute the files.
the header of the wave files. In the
Preprocessor SPP present course, the parameters shown FIRST EXPERIMENT
The preprocessor program SPP in Box 2 are used. The CD-ROM contains a program
enables the complete sequence of Sound reproduction SIN1.EXE for generating a wave file that
operations in an experiment to be con- Readers who wish to listen to experi- contains a sinusoidal signal. Start with
tained in a single file. Basically, this ments conducted in the course, rather SIN1 <return>. The default setting
program does nothing but combine a than look at a curve on the monitor, ensures that a 2-second long sine wave
number of files necessary for an exper- are offered the opportunity of doing of 1000 Hz is generated. The ampli-
iment by means of a number of so. For this, a suitable program, many tude is 10 000. This signal is loaded
instructions. of which are available on sound-cards into file SIN1.WAV, whereupon the file
For example, to carry out the exper- or as freeware or shareware on the can be played back. This gives readers
iment described in file TEST3.SPP, all Internet, is needed. Preferably, such a the opportunity of generating a sinu-
that is needed to be input is DO TEST3. program should run under DOS. soidal signal for test purposes.
SPP <return>. Try this out when the When it is enabled, a request has to be The parameters of the program
CD-ROM has become available. The made: please play back the file allow other sinusoidal signals to be
result is shown in Figure 1. Other sim- SPEECH1.WAV copied from the generated as well. For instance, if a
ulation programs are started in a sim- CD-ROM. Thereupon, a text with 500 Hz signal with an amplitude of
ilar manner. music should be heard. 5 000 and a sampling value of 100 000
Recording at a sampling rate of 11 025 is to be
SHELP function Readers who wish to record their own generated, readers should access the
The most important parameters of signals, for instance, from a receiver or program with SIN1 \scale=5000 \f0=500
many programs may be listed as a from an electronic circuit, have to \n=100000 \fs=11025 \out=sin2.wav
help by inputting SHELP program name enable a program to make this possi- <return>. The data are loaded into
<return>. ble with the sound-card. This program file SIN2.WAV.
is normally available on the sound- Readers should try to generate a
SOURCE MATERIAL card or as shareware on the Internet. variety of signals and listen to them.
If readers wish to conduct various The recording of wave files is not Operation of the program will be
experiments in signal processing, they really necessary for the present course, explained later.
need signals that can be processed. since all requisite files are provided on
The CD-ROM contains a number of the CD-ROM. SOME THEORY
audio signals that enable all experi- Nevertheless, readers are advised Digital signal processing is based on
ments to be carried out. It is, however, to become acquainted with how to Shannons theorem (1949) that tells us
also possible for signals recorded by prepare a wave file, since this will how often we have to monitor a time-
Figure 2. Sampling of
an analogue signal.
2
x x(t)
t1 t2 t3 tn t
x
x1
x2 xn
x3
t
980015 - 12
registers, ALU and status registers. register R30 duplicates as the Z regis-
sive, and thats where Atmel comes in Below these elements you find the ter for indirect addressing). Atmel also
with its AVR controllers which may be logic for programming the Flash refers to these registers using the term
programmed more than a thousand memory. special functions just like the timers
times using only four lines (SCL, and the I/O registers. The term Special
MOSI, MISO and RESET), and some Function Registers as we know it from
PC software to download the object MEMORY MODEL the MCS51 would have been more
code via the RS232 port. If suitable A short discussion of the memory appropriate. Access to registers R0
hardware is used (as, for example, in model used by AVR controllers may be through R31 is possible using register
the Electronic Handyman), then it is useful before tackling the various spe- instructions as well as via the LDS or
even possible to leave the controller in cial functions and the interfaces with SDS instructions. Note, however, that
its application circuit! the real world. AVR controllers use the access by way of the latter two instruc-
Harvard memory architecture, in tions requires three instruction cycles
which program memory and data and two words in the program mem-
THE PROCESSOR CORE memory are separated. Depending on ory. The same goes for the I/O regis-
Remarkably, the processor core of the external configurations, AVR con- ters: here, access is possible through
AVR series of microcontrollers has no trollers are capable of addressing up to the IN and OUT instructions (1 cycle;
accumulator register for arithmetic 8 Mbytes of program memory and an 1 word each), or (again) via the LDS
functions. Instead, register-to-register equal amount of data memory. The and STS instructions. However,
arithmetic is applied. As long as enough SRAM data memory has a width of because the AT90S1200 has no internal
registers are available, that reduces the eight bits, the program memory, data memory besides the register file
number of instructions for, say, an 16 bits. The first 32 bytes of the data and the I/O registers, the STS and LDS
addition from three to one (load accu- memory cover the Register File (reg- instructions are not available on this
mulator, add, store accumulator isters R0 through R31; controller. In fact, the
results). Otherwise, the processor core Figure 2. Architecture
is MCS-51 compliant, and capable of of the AT90S1200.
executing all the usual instructions.
The AT90S1200 instruction set may be 2
found on this months Datasheets. The
status flags required for the arithmetic
functions are listed in Table 1.
Pipeline technology allows the
processor core to execute an instruc-
tion cycle in one clock period. For the
one-cycle instructions, that results in a
throughput of one million instructions
per megahertz of clock frequency
(1 MIPS/MHz). Unfortunately, setting
and clearing a port pin requires two
clock cycles. Thanks to the static struc-
ture of the processor, the clock fre-
quency may be made as low as you
want, enabling you to achieve an
(almost) directly proportional reduc-
tion in current consumption.
Further features of the AVR series
include a Flashable program memory,
an on-chip EEPROM (size depends on
controller type) and on-chip RAM in
the more extensive models. As with all
controllers, there are also different I/O
modules. The block diagram of the
AT90S1200 (which is also used in the
Electronic Handyman) is shown in
Figure 2. The CPU core comprises a
program counter, stackpointer, instruc-
tion register/decoder, general-purpose
64 kbit/s 64 kbit/s
Internet
service
Provider
User
4 kHz 4 kHz
bauds to the modern V.42 and the ulation, a number of which are vari- Figure 1. The old telephone
developing V.fast running at 33.6/56 ants of the basic methods. Although channel, from modem user to
kbit/s. the analogue and digital basebands are service provider. This network,
A modem has to dissimilar, the modulation techniques, which has a bandwidth of 4 kHz,
(1) modulate an outgoing baseband in general, are not. provides 33.6 kbit/s modems the
signal on to a carrier for transmis- The techniques employed range maximum capacity.
sion through a telephone line or via from two-tone frequency-shift keying
radio link; (FSK), through variants of phase shift
(2) demodulate an incoming modu- keying (PSK), differential PSK (DPSK) quency are amplitude modulated
lated signal from the telephone line to multilevel quadrature amplitude and added to produce a third carrier
or radio link to recover the input modulation (QAM). signal containing both modulations.
baseband information. In FSK, the carrier is switched In the digital variant, which is based
between two frequencies. One of these on PSK and the amplitude variant, a
In this article, only the telephone line is assigned the logic value 0 and the phase shift as well as an amplitude
as transmission medium will be con- other, the binary 1. This technique is shift are possible. Moreover, in this
sidered, but the principles apply also fairly simple, but requires a large band- method, two carrier frequencies are
to other links. width, resulting in low data density. used, each of which carries half of the
Today, the consumer has a choice Phase shift keying, sometimes data transmission.
between an analogue and a digital called phase reversal keying (PRK) is a
telephone line. Transmission rates single-frequency method where the BANDWIDTH
attainable via an analogue line are data bit stream causes a change of car- The restrictions imposed by the ana-
33600 bit/s from the user to the tele- rier phase. The phase shift is defined logue telephone line are difficult to
phone exchange (upstream) and 56000 and can therefore vary only within overcome. They relate mainly to the
bit/s from the telephone exchange to certain fixed values. A binary 0 results bandwidth of the channel, and the
the user (downstream). Note that the in no phase change, while a logic 1 noise added to any signal passing
baud rate is equal to the bit rate only causes a 180 phase shift. Intermediate through it.
when each signal event (or pulse) rep- values are obtained by combinations The usable bandwidth of an ana-
resents one bit condition, as in a binary of bits, such as (in 4-PSK) 00, 01, 10, 11. logue telephone line extends roughly
system. Quadrature amplitude modula- from 200 Hz to 4 kHz. This is an arti-
tion may be analogue or digital. In ficial restriction, imposed to allow the
MODULATION the analogue variant, two quadrature network to carry many telephone calls
There are a great many types of mod- versions of the same carrier fre- at once, It is, however, universal and
56 kbit/s Modem
Exchange Exchange Terminal
Switch Switch Adaptor
970061 - 13
Figure 4. Waveform
0 due to two pulses as
seen by the receiver
when Lucents/Rock-
wells K56flex standard
-0.5 is used. Note that they
have a value only at
their own sampling
point and at sampling
point 8. At all other
-1 sampling points their
-4 -2 0 2 4 6 8 10 value is zero.
Time (samples) 970061 - 14
Amplitude (arbitrary)
not easy and takes up a sizeable chunk
of the available processor capacity. In
both systems, use is therefore made of
controlled ISI, in which a data pulse 0.5
cannot interfere with an adjacent
pulse. Thus, controlled ISI is interfer-
ence that occurs only with one other
pulse. The coding is arranged so that
0
prior calculation can determine which
pulse will be affected by the interfer-
ence. The system is thus aware of this
and can take measures to cope with it.
This technique ensures that the band- -0.5
width of the channel is used to its
greatest extent. The price of it is a more
complex receiver. However, this can
easily be resolved nowadays by the -1
use of inexpensive dig- -4 -2 0 2 4 6 8 10 12
ital signal processors Figure 5. A full set of Time (samples) 970061 - 15
(DSPs). seven pulses as seen
Although both sys- by the receiver when
tems use controlled ISI, Lucents/Rockwells be considered to have a (digitized), some accuracy is lost owing
they use a different standard is used. It is non-defined value. to the conversion from a continuous
technique of coding, evident that the level As it is known that single level to, say, 256 possible levels.
which makes them at the eighth sampling the sampling rate is This conversion error is considered to
utterly incompatible. point is not defined. 8 kHz and that eight be a form of noise since it has a simi-
bits can be coded per lar effect on the signal quality. During
The K56flex pulse, it can be calcu- the transmission from provider to user
standard lated that the digital bandwidth is only one analogue-to-digital converter
In the K56flex standard, the bits are 64 kbit/s. Of this, only 7/8, that is, (ADC) is in use and the quality of this
transmitted in packets of eight. Of 56 kbit/s, is used. must therefore be of a high standard.
these, seven are transmitted in such a The three manufacturers have tack-
way that the interference occurs in the The X2 standard led this aspect in an identical manner.
time reserved for the eighth bit. There- In the X2 standard2), all available As long as the output signal of the
fore, the transmitting of the eighth bit capacity is used, and there is there- ADC is identical to the requisite value,
makes no sense since it would be cor- fore no pause in the data stream. This the quantization noise is minimal.
rupted and so cause interference itself. results in data pulses corrupting adja- How quantization noise arises is
This means that only 7/8 of the maxi- cent pulses. The data is extracted shown in Figure 6 (upper sketch); the
mum capacity is available. from this corrupted data stream by lower sketch shows that when the ref-
The shape of a received wave the use of a Viterbi equalizer. This erence point is chosen well, virtually
when the K56flex standard is used is equalizer analyses the quality of the no quantization noise ensues.
shown in Figure 4 (for claritys sake, telephone line before data are trans- Since the ADC and the digital-to-
only two pulses have been transmitted mitted. To do this, one of the two analogue converter (DAC) are both
here). In this example, the amplitude modems sends a test signal that is 8-bit units, choosing the correct refer-
of both pulses is normalized; the cod- analysed by the other. Any distortion, ence point is not difficult. A sample is
ing usually takes account of the signal echo, and noise can be determined taken when the input level of the data
amplitude (at a resolution of eight from this analysis. Then, the roles are pulse is equal to one of the steps of the
bits). Note that for y1(t) the signal has reversed and a signal transmitted in converter. This ensures that the sam-
a value at sampling times 1 and 8, the opposite direction, whereupon a pling error, and thus the quantization
whereas for y2(t) this is at sampling second analysis is carried out. The noise, is a minimum. If the measured
times 2 and 8. results of the analyses are processed line characteristics are also taken into
The two waves represent the first by a Viterbi algorithm3) and used to account, selecting the reference point
two bits from a group of eight. So, the program the equalizer. In this way, is straightforward.
pulses do not interfere with one the distortion can be anticipated and Once the quantization noise has
another, but would do so with the taken account of in the receiver. been minimized, attention must be
eighth bit (which has not been trans- This technique in which the hard- paid to other sources of noise. Since
mitted). ware anticipates the quality of the tele- these normally do not reside in the
The transmission of a group of phone line is not new and is also used modem, it is not easy to take appro-
seven pulses results in the diagram in modern modems. priate measures to nullify or at least
shown in Figure 5. Here again, only minimize them. The use of a compan-
one pulse can have a value at a given QUANTIZATION NOISE der usually enables the effect of such
sampling time. The eighth pulse may When an analogue signal is quantized sources to be reduced drastically.
2) X2 is also a CCITT Recommendation covering international 3) Information about the Viterbi algorithm may be found at web site
user facilities in public data networks. http://docs.dcs.napier.ac.uk/docs/get/ryan93a/document.html
WHAT OF THE
FUTURE?
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achiev-
The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers
are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in
executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1
MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
DATASHEET
V CC : 2.7 - 6.0V
Brief Description
AT90S1200
AT90S1200
20-Pin Device
Manufacturer:
AT90S1200
Features
#
1/98
AT90S1200 ROR Rd Rotate Right Through Carry Rd(7) C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0) None 1
BSET s Flag Set SREG(s) 1 SREG(s) 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
Elektor Electronics 1/98 39
Mnemonic Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1
SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1
AT90S1200
AT90S1200
if (SREG(s) = 0) then PC PC + k + 1
Rd(b) T
SEC Set Carry C1 C 1
CLC Clear Carry C0 C 1
SEN Set Negative Flag N1 N 1
CLN Clear Negative Flag N0 N 1
SEZ Set Zero Flag Z1 Z 1
CLZ Clear Zero Flag Z0 Z 1
SEI -Global Interrupt Enable I1 I 1
CLI Global Interrupt Disable I0 I 1
Instruction Set Summary 4
5V' C5 5V
1 R2 100p
MIC2 P1b D1 D5
2k2
K2 47k C9
C2 R5 BAT85 BAT85
6 100p
470 R9 R10
7
10 IC1b 10k 10k
40V 5
R6 C7 R8
9
100 10k C11 R11
8
22 IC1c 100
10
2V5 22
R7 R12
D2 D6
LINE K3
220k
100k
BAT85 2V5 BAT85
5V' C4 5V
K4 LINE
R1 100p
MIC1 P1a D3 D7
2k2
K1 47k C10
C1 R4
2
BAT85 BAT85
100p
470 R16 R17
1
10 IC1a 10k 10k
40V 3
R13 C8 R15
13
100 10k C12 R18
14
22 IC1d 100
12
2V5 22
R14 R19
D4 D8
220k
100k
BAT85 2V5 BAT85
5V
IC2 5V 5V'
5V R20
> 9V D11 7805 R3
2k7
100
R22
1N4001 IC1 = OP484 2V5
6k8
D9 4 C6
C17 C16 C15 C3 R21
IC1 C13 C14
2k7
D10 100n
11
100n 100 47 100
25V 63V 5V6 10V 100n 100
1W3 10V
POWER
980007 - 11
Parts list
2
K4
Resistors:
R1, R2 = 2.2 k
H1
H3
R14
R13
R6
R7
R3, R6, R11, R13, R18 = 100 K3 OUT
K2 K1
R4, R5 = 470 R2 R1 D1
R7, R14 = 220 k C3 C1 D2
R18
R19
R11
R12
+
R8, R9, R10, R15, R16, R17 = 10 k D3
R3
R12, R19 = 100 k D4
980007-1
C10
D11
C2 C8 C7
R20, R21 = 2.7 k
R16 R15
R22 = 6.8 k R17 C12 C16
R5
R4
0
P1 = 47 k stereo, logarithmic
D7 D10
potentiometer for board mounting D8
IC1
P1
C4 C11
D6
Capacitors: D5 R22
C5 R8
C1, C2 = 10 F, 40 V, bipolar, radial
R10 C17
C3, C14 = 100 F. 10 V, radial R9 C9 C13 IC2
D9
C4, C5, C9, C10 = 100 pF 1-700089 C6
H4
H2 H5
Integrated circuits:
IC1 = OP484FP (Analog Devices)
(see text)
IC2 = 7805
Miscellaneous:
K1K4 = stereo jack socket, 3.5 mm,
for board mounting
PCB Order no. 980007-1 (see Read-
ers Services section towards the
end of this issue)
OPTIONAL
MODIFICATIONS
crashproof operation;
received from
or its
Electronics or
Elektor Electronics
unauthorized disclosure
or their
on information
experience by
is based
(DS5000T)
this note
not imply
The
in
2 MEMORY
ORGANIZATION
Figure 2 illustrates the address spaces
that are accessed by the DS5000(T). As
shown in the figure, separate address
spaces exist for program and data
memory. Since the basic addressing
capability of the machine is 16 bits, a
maximum of 64 kbytes of program
memory and 64 kbytes of data mem-
ory can be accessed by the DS5000(T)
CPU. The 8 kbyte or 32 kbyte RAM
area inside the DS5000(T) can be used
to contain both program and data
memory.
The real-time clock (RTC) in the
DS5000(T) is reached in the memory
map by setting an SFR (Special Func-
tion Register) bit. The MCON.2 (mem-
ory control) bit (ECE2) is used to select
Figure 2. The logical an alternate data memory map. When
address spaces are ECE2=1, all MOVxs (Move instruc-
largely identical with tions) will be routed to this alternate
those of an 8051 memory map. The real-time clock is a
The DS5000(T) soft processor, except for device consists of three serial device that resides in this area.
microcontroller is an the non-volatile sec- main sections: the If the ECE2 bit is set on a DS5000
8-bit module that is tions. processor, DS5000FP, without a timekeeper, the MOVs will
compatible with the and 8 kbyte or 32 kbyte simply go to a non-existent memory.
8051 family of micro- static random-access Software execution would not be
processors and which offers soft- memory (SRAM), and an (optional, effected otherwise.
ness in all aspects of its application. except T-version) real-time clock. These
The softness is accomplished sections are interlinked by a byte-wide PROGRAM LOADING
through the comprehensive use of address bus, a byte-wide data bus, two The Program Load Modes allow ini-
non-volatile technology to preserve selection lines, CE1 and CE2, and a tialization of the NVRAM (non-volatile
all information in the absence of the read/write line, R/W. RAM) program/data memory. This ini-
supply voltage, VCC. Communication with the outside tialization may be performed in one of
Dependent on which version, the world is via four standard interfaces, two ways.
internal program-cum-data memory that is, 8-bit ports P0P3, an RST (reset)
comprises an 8 kbyte or 32 kbyte non- line, an ALE (Address Latch Enable) 1. Serial Program Loading which is
volatile, static CMOS-SRAM (comple- line, a PSEN (Program Store Enable) capable of performing Bootstrap
mentary metal-oxide silicon static ran- line and an EA (External Access) line. Loading of the DS5000(T). This fea-
dom-access memory). The internal The similarity to the 8051 family ture allows the loading of the appli-
data registers and key configuration devices is evident. cation program to be delayed until
registers are also non-volatile. the DS5000(T) is installed in the end
An optional real-time clock (stan- INSTRUCTION SET system. Dallas Semiconductor
dard in the T-version of the controller) The DS5000(T) executes an instruction strongly recommends the use of
enables constant time monitoring to be set which is object code compatible serial program loading because of
implemented. This clock, controlled by with the industry standard 8051 micro- its versatility and ease of use.
an external crystal, keeps time to a controller. As a result, software devel-
hundredth of a second. opment packages which have been 2. Parallel Program Loading which
written for the 8051 are compatible performs the initial loading from
FUNCTIONAL DIAGRAM with the DS5000(T), including cross- parallel address/data information
The internal arrangement of the assemblers, high-level language com- presented on the I/O port pins. This
DS5000 is shown in Figure 1. The pilers, and debugging tools. mode is timing-set compatible with
the 8751H microcontroller pro-
gramming mode.
Table 1 Crystal frequency and available speeds
The DS5000(T) is placed in its Pro-
Crystal Speed (bps) gram Load configuration by simulta-
frequency (MHz) neously applying a logic 1 to the RST
300 1200 2400 9600 19200 57600
pin and forcing the PSEN line to a
14,7460 S S S S logic 0 level. Immediately following
11,0592 S S S S S S this action, the DS5000(T) will look for
a parallel Program Load pulse, or a
9,21600 S S S S serial ASCII carriage return (0DH)
7,37280 S S S S character received at 9600, 2400, 1200
or 300 bps over the serial port.
5,5296 S S S S The hardware configurations used
1,8432 S S S S to select these modes of operation are
illustrated in Figure 3.
S = supported
SERIAL BOOTSTRAP
LOADER
The Serial Program Load Mode is the 3
easiest, fastest, most reliable, and most
complete, method of initially loading
application software into the
DS5000(T) non-volatile RAM. Com-
munication can be performed over a
standard asynchronous serial commu-
nications port. A typical application
would use a simple RS232 serial inter-
face to program the DS5000(T) as a
final production procedure.
The hardware configuration which
is required for the Serial Program Load
mode is illustrated in Figure 3. Port
pins 2.7 and 2.6 must be either open or
pulled high to avoid placing the Figure 3. The controller may be pro-
DS5000(T) in a parallel load cycle. grammed in two different ways. Parallel
Although an 11.0592 MHz crystal is loading is common, but serial loading
shown in Figure 3, a variety of crystal enables the DS5000(T) to be loaded
frequencies and loader baud rates are with software during an application.
supported, shown in Table 1.
The serial loader is designed to
operate across a three-wire interface
from a standard UART (Universal ister of memory location within the DS5000(T) is initialized so that an exist-
Asynchronous Receiver/Transmitter). DS5000(T). The Verify Cycle is used to ing 4 kbyte program can be pro-
The receive, transmit, and ground, read this byte back for comparison grammed into a DS5000(T) with little
wires are all that are necessary to with the originally loaded value to ver- or no modification. This initialization
establish communication with the ify proper loading. The Security Set automatically sets the Range Address
DS5000(T). Cycle may be used to enable the Soft- for 8 kbytes and maps the lowest
The Serial Bootstrap Loader imple- ware Security feature of the DS5000(T). 4 kbyte bank of Embedded RAM as
ments an easy-to-use command line One may also enter bytes for the program memory. The next 4 kbytes of
interface which allows an application MCON register or for the five encryp- Embedded RAM are map-ped as Data
program in an Intel hex representa- tion registers using the program Memory.
tion to be loaded into, and read back MCON cycle. When this cycle is used, In order to program more than
from, the device. Intel hex is the typ- the absolute register address must be 4 kbytes of program code, the Pro-
ical format which existing 8051 cross- presented at Ports 1 and 2 as in the gram/Verify Expanded cycles can be
assemblers output. The serial loader normal program cycle (Port 2 should used. Up to 32 kbytes of program code
responds to single character com- be 00H). The MCON contents can like- can be entered and verified. Note that
mands which are summarized in wise be verified with the Verify the expanded 32 kbyte Program/Verify
table 2. MCON cycle. cycles take much longer than the nor-
When the DS5000(T) first detects a mal 4 kbyte Program/Verify cycles.
PARALLEL PROGRAM Parallel Program Strobe pulse or Secu- A typical parallel loading session
LOAD CYCLE rity Set Strobe pulse while in the Pro- would follow this procedure. First, set
The Parallel Program Load Cycle is gram Load Mode following a Power the contents of the MCON register
used to load a byte of data into a reg- On Reset, the internal hardware of the with the correct range and partition
only if expanded programming cycles
are used. Next, the encryption regis-
ters can be loaded to enable encryp-
Table 2. tion of the program/data memory (not
required). Then, program the
Command Function DS5000(T) with either normal or
C Return CRC-16 checksum of embedded RAM expanded program cycles and check
the memory contents with Verify
D Dump Intel hex file cycles. The last operation would be to
F Fill embedded RAM block with constant turn on the security lock feature by
either a Security Set cycle or by explic-
K Load 40-bit encryption key itly writing to the MCON register and
L Load Intel hex file setting MCON.1 to a 1.
[980014]
R Read MCON register
T Trace (echo) incoming Intel hex data
U Clear security lock
V Verify embedded RAM with incoming Intel hex
W Write MCON register
Z Set security lock
P Put a value to a port
G Get a value from a port
. B ox able to respond to individual wishes and requests for modifications to, or addi-
tional information about, Elektor Electronics projects.
P.O 14
14 K1
R2
10k
1
6
2
C3
7
470 R3
3
10k
8
16V R1
4
10k
9
5
SUBD-O9F D1
14
1N4148
4 6
MCLR RB0
16 7
IC1 OSC1 RB1
15 IC2 8
78L05 OSC2 RB2
17 9
RA0 RB3
18 10
RA1 PIC16 RB4
1 C84 11
RA2 RB5
Mini PIC Programmer The additional component is a 2
3
RA3 RB6
12
13
Dear Editor, in the June 1997 470-F, 16V electrolytic capac- C1 C2
D4
RA4 RB7
D2 D3
programmer for the PIC16C84. between resistor R3 (positive 100n 14V 5V6 5V6
SWITCHBOARD
Switchboard allows PRIVATE READERS of Elektor Electronics one SWAP Tektronix/Telequipment D65 FOR SALE Kits for 1.2 GHz
FREE advertisement of up to 106 characters, including spaces, com- dual-beam scope in g.w.o. for Bb Multifunction Frequency Meter (EE
mas, numerals, etc., per month. The advertisement MUST relate to clarinet, must also be in g.w.o. Dec 1992). Unmatched project. Kit
electronics, and it MUST INCLUDE a private telephone number or Phone Graham on (01142) 483587. includes EPROM, PCB, LCD, front
name and address; post office boxes are NOT acceptable.
panel, drilled case, all parts and
Elektor Electronics (Publishing) can not accept responsibility for any
correspondence or transaction as a result of a free advertisement or WANTED National cathode-ray description. Few available, ultra-low
of any inaccuracy in the text of such an advertisement. oscilloscope model VP-513A manu- price 75 each. Anita, Sibberkerkstr
Advertisements will be placed in the order in which they are als or diagram. Willing to pay. John 100, NL-6301-AW Valkenburg,
received. Elektor Electronics (Publishing) reserve the right to refuse S. Syros, 26 Kyprou Str., Athens Netherlands. Email techtext@worl-
advertisements without giving reasons or without returning them. 141-22, Greece. donline.nl.
SWITCHBOARD
Switchboard allows PRIVATE READERS of Elektor Electronics one SWAP Tektronix/Telequipment D65 FOR SALE Kits for 1.2 GHz
FREE advertisement of up to 106 characters, including spaces, com- dual-beam scope in g.w.o. for Bb Multifunction Frequency Meter (EE
mas, numerals, etc., per month. The advertisement MUST relate to clarinet, must also be in g.w.o. Dec 1992). Unmatched project. Kit
electronics, and it MUST INCLUDE a private telephone number or Phone Graham on (01142) 483587. includes EPROM, PCB, LCD, front
name and address; post office boxes are NOT acceptable.
panel, drilled case, all parts and
Elektor Electronics (Publishing) can not accept responsibility for any
correspondence or transaction as a result of a free advertisement or WANTED National cathode-ray description. Few available, ultra-low
of any inaccuracy in the text of such an advertisement. oscilloscope model VP-513A manu- price 75 each. Anita, Sibberkerkstr
Advertisements will be placed in the order in which they are als or diagram. Willing to pay. John 100, NL-6301-AW Valkenburg,
received. Elektor Electronics (Publishing) reserve the right to refuse S. Syros, 26 Kyprou Str., Athens Netherlands. Email techtext@worl-
advertisements without giving reasons or without returning them. 141-22, Greece. donline.nl.
C3
TR1
source, the power cut should not last C2
for more than a couple of hours C5
RE1
COMPONENTS LIST
Resistors:
3
R1 = 100 (see text)
Capacitors:
C1-C4 = 100nF
C5 = 2200F 25V
Semiconductors:
B1,B2 = B80C1000
D1 = 1N4001
Miscellaneous:
K1 = PCB terminal block, 2-way,
pitch 7.5mm
TR1 = 12V 3VA3 transformer, e.g.,
Monacor 3112, or 2x12V 3VA3, e.g.
Monacor 3212
Bt1 = external rechargeable battery
pack, NiCd, 12V
Re1 = 12V relay E-card (Siemens)
V23127-B2-A101
Printed circuit board not available
ready-made
the same voltage, i.e., about 17.4 V capacity, the lower the Figure 3. Finished The finished circuit
(under no-load conditions). value of R1, and the board, just before it is board should be fitted
The voltage across C5 is also used longer the power cut mounted into its plas- in an all-plastic case
to charge the battery pack by way of a the UPS is capable of tic case. with due attention paid
series resistor, R1. More about this fur- covering. to electrical safety, in
ther on. particular, the connec-
When the mains voltage disap- tion between the board and the mains.
pears, the relay will almost instantly CONSTRUCTION Be sure to use properly rated cable and
lose its coil voltage because D1 blocks The PCB design for the UPS is shown a rubber grommet plus strain relief. If
the higher voltage which still exists at in Figure 2. Regrettably, this board is you feel uneasy about mains cable
its cathode side. Consequently, the not available ready-made through our connections, ask a more experienced
relay contact falls back, and connects Readers Services, so you have to pro- friend for assistance.
the + terminal of the battery to the duce it yourself, or have it produced.
+ input of the base unit. D1 also pre- All parts are mounted on to the board
vents the battery from taking over the as indicated by the component over- FINAL HINTS
relay coil supply. The ground line, as lay. Be sure to fit the bridge rectifiers Make sure you know the polarity of
you will recall, is not switched because in accordance with the ~, and + the low-voltage d.c. input socket on
it is shared between the battery and symbols that you may see printed on the base unit, because you may have
the mains supply/charger. The charge top of the devices check against the to make a new cable to connect the
built up in C5 helps to ensure that the PCB overlay! To assist in their cooling, UPS. Also measure the no-load output
base unit is never actually without these rectifiers must be mounted at voltage of the mains adapter. In most
power, even if there is a short mains some distance above the board sur- cases, the base unit will have an inter-
interruption. face. The same applies to resistor R1, nal 8-volt voltage regulator, which will
which may run a bit hot to the touch. happily accept any unregulated input
Read the inset on the transformer voltage between 12 and 18 volts.
R1 AND and the bridge rectifiers if you want to Once you have the UPS up and
THE BAT TERY PACK use a transformer with a single sec- running, your cordless telephone
This circuit is designed to charge a ondary winding. always works. (970093-1)
pack of 10 NiCd cells, not a (sealed)
lead-acid or gel battery. In most cases,
NiCd cells withstand (nearly) continu-
Two secondaries, two bridges
ous charging fairly well provided the Some of you may wonder why the two The solution with two bridge rectifiers
charging current is smaller than about secondary windings of the mains as adopted here prevents unneces-
1/40th part of the nominal capacity. This transformer are connected to separate sary self-heating of the transformer.
capacity you will typically find printed bridge rectifiers rather than in parallel. Because of the blocking action of the
on the battery, and is usually The reason is that many of the cur- diodes in the bridge rectifiers, the
expressed in mAh (milli-ampre-hour). rently available low-power PCB-mount highest rectified voltage automatically
So, for 800-mAh batteries, you would transformers have two secondary appears at the output, and it is not
choose a charging current of 800/40 or windings which supply slightly differ- possible for one winding to load the
about 20 mA. This is not critical, ent voltages. As opposed to modern
other.
though, and in fact any value between toroid transformers, these windings
are not matched using bifilar winding No problem if you happen to have a
15 mA and 30 mA will be just fine. In transformer available with a single 12-
practice, you have to establish the techniques. The resulting difference
between the exact secondary voltages V secondary, which (1) fits on the
charging current, and adapt the value board and (2) is capable of supplying
of R1 until the desired current is may cause appreciable losses (dissi-
pation) if the windings are connected the necessary current: in that case,
achieved. The charging current is read-
in parallel, because the winding sup- omit B1, C1 and C2, and fit a wire link,
ily calculated by measuring the voltage
plying the higher voltage will attempt X, as indicated by the dashed line on
drop across R1 and dividing it by the
to compensate the difference. the component overlay.
value of R1. The higher the battery
Elektuur 1/98
58
Visit our Web site at http://ourworld.compuserve.com/homepages/elektor_uk
R2
3V
1 1M
470k
4
G1
1n 11
C3
3V
15 3
3D + D5 D7 D6
1 2
JP1
IC2 = 74HC14 10 6
9 7
IC2a 12
BT1 1 2CT=0/2CT=15
1 13 D1 D4
16 14 2 1,2,4CT=0
3V IC1 IC2 IC2b 1,2,4CT=15
3
8 7 1 74HC191
4
13 IC2f 6 5
1 1
12
IC2c 980021 - 11
the finger and the two tracks, and the IC1 = 74HC191
battery and the +ve and ve battery IC2 = 74HC14
IC2
C1
Elektuur 1/98 59
Smartcard
reader/writer
In last months instal- part 2
ment we discussed
the hardware, which
consists of two sec-
tions: the card reader
module and the com-
puter interface. In this
second and final
instalment we will
concentrate on the
software utilities
which are part and
parcel of the project.
ply make a note of the ones that seem SOME HELPFUL UTILITIES
to be accepted. Figure 5. Structure of Although the four software utilities
The bytes A1 and A2 which follow the header which is already mentioned allow you to tackle
the INS code constitute what is present in all instruc- all topical operations to the most fre-
tions complying with
referred to as the command reference. quently used Smartcards, a couple of
the T=0 format.
This may be the physical address of a small programs have been added to
memory address range to be read or the toolkit for special applications and
written, or the number of a code, a instruction is badly formulated: for advanced users.
key, etc. example, 6BH for incorrect reference RDINV (Read INVerted) and
The fifth byte, L, specifies the (you may be attempting to read an RDIR (Read DIRect) enable you to
length of the data block associated address which does not exist), or 67H read, on inverted-ISO cards and
with the instruction: data which are for incorrect length (you may be pre- straight-ISO cards respectively, a spec-
due for transmission to the Smartcard senting a code which is either too long ified number of bytes (up to 250), start-
if the instruction is inbound, or data or too short). ing from a specified address (which
awaited by the Smartcard if the The value 6FH is reserved to signal has to be in an area which can be read
instruction is outbound. the occurrence of an incident whose freely).
A length of 00H is commonly asso- cause and nature are undetermined. In addition to their hexadecimal
ciated with instructions which are nei- The meanings of reports starting display function, these programs also
ther inbound nor outbound: card with a 9, as well as those of SW2 save the results of the read operation
invalidation, rehabilitation, sleep, code bytes, is not subject to regulations, and in a file called CARD.CAR, the con-
verification, etc. will typically depend on the applica- tents of which may provide a useful
Once it has recognised the header tion. starting point for all kinds of informed
of a valid instruction, the Smartcard Meanwhile, general consensus has processing, without having to re-read
replies by transmitting a procedure byte. established the following meanings: the card all the time.
This immediately precedes the block The utilities INVCLASS and
of data returned by the card if the 9010H: incorrect code applied (first attempt); DIRCLASS enable you to run a sys-
instruction is outbound. Alternatively, 9020H: incorrect code applied tematic ISO-class exploration on a
if the instruction is inbound, it is a (second attempt); totally unknown Smartcard by trying
request to send aimed at the card 9040H: incorrect code applied (third attempt); out all possible combinations within a
reader. 9080H: incorrect code applied (card blocked); totally harmless reading sequence.
In the latter case, it is self-evident 9001H: failure to write to EPROM; Finally, we should temper your
that the card reader has to transmit 9202H: failure to write to EEPROM; hopes of using this little tool to dis-
exactly the number of bytes declared in 9802H: invalid secret code; cover a confidential code on the
the L byte. 9804H: bad code applied; Smartcard, as any properly protected
Most of the time, the procedure 9806H: code cancelled; card will permanently block itself after
byte will be identical to the opcode 9810H: security condition not satisfied; three unsuccessful attempts.
(INS). It may, however, assume a value 9820H: inactive secret code. (970068-2)
of INS+1 to indicate that the Smart-