Revision Problems ECE3073/TRC3300 Weeks 7-12

Lindsay Kleeman

Caveat: The problems here do not represent all topics from the lectures that are
examinable. Some problems are based on end of chapter exercises from the text Wolf
and these are labelled with the chapter. Students should refer to the text by Wolf, other
references, the web pages, lecture notes and lab exercises to fully revise the material
ready for the final exam. Previous exam questions can also be attempted to test your
understanding but should not act as a guide to what you need to know.

C1. Do the exercises on slide 28 of the Compilation.pdf notes.

C2. The following C code

int a[5]={0,2,4,6,8}, b[5] = {1,2,3,4,5};

int i=0;
while (i < 10){
a[i/2] += b[i/2];
i += 2;
}
is compiled into NIOS-II assembler code as follows:
0x000407bc <main+116>: movhi r2,5
0x000407c0 <main+120>: addi r2,r2,-17712
0x000407c4 <main+124>: addi r4,fp,-40
0x000407c8 <main+128>: mov r5,r2
0x000407cc <main+132>: movi r6,20
0x000407d0 <main+136>: call 0x409c8 <memcpy>
0x000407d4 <main+140>: movhi r2,5
0x000407d8 <main+144>: addi r2,r2,-17692
0x000407dc <main+148>: addi r4,fp,-20
0x000407e0 <main+152>: mov r5,r2
0x000407e4 <main+156>: movi r6,20
0x000407e8 <main+160>: call 0x409c8 <memcpy>
0x000407ec <main+164>: stw zero,-60(fp)
0x000407f0 <main+168>: ldw r2,-60(fp)
0x000407f4 <main+172>: cmpgei r2,r2,10
0x000407f8 <main+176>: bne r2,zero,0x40874 <main+300>
0x000407fc <main+180>: ldw r3,-60(fp)
0x00040800 <main+184>: srai r2,r3,31
0x00040804 <main+188>: srli r2,r2,31
0x00040808 <main+192>: add r2,r3,r2
0x0004080c <main+196>: srai r3,r2,1
0x00040810 <main+200>: muli r2,r3,4
0x00040814 <main+204>: addi r4,fp,-60
0x00040818 <main+208>: add r2,r2,r4
0x0004081c <main+212>: addi r5,r2,20
0x00040820 <main+216>: muli r2,r3,4
0x00040824 <main+220>: addi r3,fp,-60
0x00040828 <main+224>: add r2,r2,r3
0x0004082c <main+228>: addi r4,r2,20
0x00040830 <main+232>: ldw r3,-60(fp)
0x00040834 <main+236>: srai r2,r3,31
0x00040838 <main+240>: srli r2,r2,31
0x0004083c <main+244>: add r2,r3,r2
0x00040840 <main+248>: srai r2,r2,1
0x00040844 <main+252>: muli r2,r2,4
0x00040848 <main+256>: addi r3,fp,-60
0x0004084c <main+260>: add r2,r2,r3
0x00040850 <main+264>: addi r2,r2,40
0x00040854 <main+268>: ldw r3,0(r4)
0x00040858 <main+272>: ldw r2,0(r2)
0x0004085c <main+276>: add r2,r3,r2
0x00040860 <main+280>: stw r2,0(r5)
0x00040864 <main+284>: ldw r2,-60(fp)
0x00040868 <main+288>: addi r2,r2,2
0x0004086c <main+292>: stw r2,-60(fp)
0x00040870 <main+296>: br 0x407f0 <main+168>

a) What are the addresses of the two arrays and how are they stored during the
execution of the program? You may need to revise the document
tut_nios2_introduction.pdf on the webpage under week7 lectures.
b) How is the variable i stored? Can a register be used instead?
c) How and where is the while condition implemented?
d) Can you optimise the code by replacing some lines of assembly code with fewer
lines?

Q5.1

Write C code for a state machine that implements a four-cycle handshake. Assume that
you are writing the code for a master requesting data from a slave. The master issues a
request by asserting a 1 on the line REQ and waits for the slave to assert a 1 on the ACK
line. Once the ACK is received then data is read from DATA[7:0] lines and the REQ line
is dropped. The slave can then drop the ACK line.

Write the software from the master perspective and also as a separate design from the
slave perspective. Assume that the master hardware is configured so that the ACK line
generates an interrupt on rising and falling edges and the slave hardware generates an
interrupt on both edges of the REQ line. Assume that you have the real time kernel
uC/OS-II available.
- explanation: Each iteration should contain two statements in part a and three
in part b. You will need to also change the i++ in the for loop.
c. if (c<5 && b > 7) proc1();
else if (a < 5) proc2():
else if (b > 7) proc3();
else proc4();
ADC/DAC questions

AD1. Suppose an analogue signal has a bandwidth of 100 kHz and a signal to
noise ratio of 60 dB and signal range of 0 to 10 mV. Design an ADC interface to
a microcontroller by specifying the pre-amplification gains, filtering, number of
bits and minimum sample rate required. Assume that the ADC reference voltage
is 5 V.

AD2.
a) What is the maximum sample rate of an Integrating ADC (p15 of
ADC_DAC.pdf) given the Vref, R and C of the integrator? Assume that the
maximum input voltage is Vref.
b) For a desired 10 bits in the conversion of an Integrating ADC what is the
required frequency of the clock in the circuit given that the ADC operates at
the maximum sample rate as determined in part a?

AD3
e) For the same conversion rates, what is the ratio of the clock frequencies of an
Integrating ADC versus a Successive Approximation converter?
f) Describe the algorithm that the controller of a Successive Approximation
converter would use. Write this in Verilog using a single always block.

AD4
a) What is the Thevenin equivalent output resistance an R2R ladder circuit (p22
of ADC_DAC.pdf)? Does this depend on the number of 1s in the binary
number to be converted?
b) What is the Thevenin equivalent voltage of the R2R ladder as a function of the
binary number to be converted?

AD5 Explain why a 12 bit pipelined ADC constructed out of four 3 bit flash
converters is preferred to just a single 12 bit flash converter?