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Abstract: We evaluated the use of a true single phase clocking (TSPC) circuit as a high-frequency divider-by-3
circuit. This divider consists of two TSPC D-flip-flops (D-FFs) with NOR gate logic circuitry. To achieve high-
speed operations as well as downsize the curcuit, the NOR functions are implemented into the TSPC D-FF. We
designed the divider using a 0.18-m RF CMOS process; the circuit is 100 200 m2 . In the measurements, we
confirmed the frequency divided by 3 at less than 3.14 GHz clock with 2.34 W.
KeyWords: SCL, TSPC, High frequency divider, Divider-by-3 circuit, High speed operation.
1 Introduction VDD
Q1[t]=0 Q2[t]=0
D Q1 2AND D Q2
Q1[t+1]=1 Q2[t+1]=0
TSPC TSPC
Q1B Q2B
Q1[t+2]=1 Q2[t+2]=1
:clk :clk
Q1[t+3]=0 Q2[t+3]=0
:clk
(a) TSPC-divider-by-3 circuitry
VDD
Q1 Q2
Q2
Q2
Output buffer
4.3
6 mA
5 Conclusion
4.2 We designed a high-frequency-TSPC divider-by-3 cir-
5 mA
4.1 cuit. This divider, which has two TSPC D-FFs, con-
Frequency (GHz)
References:
[1] Sayfe Kiaei, San-Hwa Chee and Dave All-
stot, CMOS Source-Coupled Logic for Mixed-
= 2.3 V was given, operation frequency increased upto Mode VLSI, 1990 IEEE International Sympo-
4 GHz with 4.16 mW. sium on Circuits and Systems, vol. 2, pg. 1608-
1611, IEEE, 1990.
Since the measurement setup was a 50 - termi- [2] Behzad Razavi, Kwing F. Lee, and Ran H. Yan,
nation, the output amplitude was small. This result Design of High-Speed, Low-Power Frequency
was same as that in simulation one. However, during Dividers and Phase-Locked Loops in Deep Sub-
the measurement, when an input signal of more than micron CMOS IEEE Journal of Solid-State Cir-
3.14 GHz was given to the circuit, it worked as a di- cuits, VOL. 30, NO. 2, pp. 101-109, 1995
vider by 4. The main reason for this unusual operation [3] Y. Ji-ren, I. Karsson, and C. Svenson A
is the parasitic capacitance of the feedback line. If a True Single-Phase-Clock Dynamic CMOS Cir-
signal delay occurs, the updating of the next stage also cuit Tectilque, IEEE Journal of Solid-State Cir-
falls behind. cuits, VOL. SC-22,NO. 5, pp. 899-901, 1987.
Probe
Signal station
Oscilloscope
generator
50 50
DUT
0
2.0 2.1 2.2
Time (nsec)
Figure 7: Measurement setup.
(a) Open
0.5
1.8
AC voltage (V)
Voltage (V)
VDD VDD
4.2
4
2.08 mA
3.8
100 m 1.86 mA
3.6
1.68 mA
120 m