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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

1. (a) 45 mW

(b) 2 nJ

(c) 100 ps

(d) 39.212 fs

(e) 3

(f) 18 km

(g) 2.5 Tb

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

2. (a) 1.23 ps

(b) 1 m

(c) 1.4 K

(d) 32 nm

(g) 130 ml

(h) 100 m

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

3. (a) 1.212 V

(b) 100 mA

(c) 1 zs

(d) 33.9997 zs

(e) 13.1 fs

(f) 10 Ms

(g) 10 s

(h) 1 s

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

4. (a) 1021 m

(b) 1018 m

(c) 1015 m

(d) 1012 m

(e) 109 m

(f) 106 m

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

5. (a) 373.15 K

(b) 255.37 K

(c) 0 K

(d) 149.1 kW

(e) 914.4 mm

(f) 1.609 km

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

6. (a) 373.15 K

(b) 273.15 K

(c) 4.2 K

(d) 112 kW

(e) 528 kJ

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

Solving, N = 11.9

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

Thus, the daily cost is (0.033)(2.5)(9) + (0.057)(2.5)(24 9) = $2.88

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

14. 2

11.25 109 m2

(800 W/m )(0.1)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

dq/dt = (5/2) e-t/2 C/s = 2.5e-t/2 A

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

6.242 10 electrons 100 cm

31 2

35 2

(b)

= 7.94810 electrons/m

1m

2

1 cm

2

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(a) q(0) = 9 C

(b) q(1) = 1 C

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

i = dq/dt = 20t 22 = 0

Solving, t = 1.1 s

(b)

200 100

q

i

100 50

0 0

-100 -50

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

t (s)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

or when t = 0.01n.

Therefore, the current drops to zero 201 times (t = 0, t = 0.01, t = 2)

in the interval.

1

1 1 114

(b) q idt 114 sin100 t cos100 t 0 C net

0 0 100 0

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

1 T 1 8

21. (a) Define iavg =

T 0

i(t )dt tdt 2.25 A

8 0

t t

(b) q(t ) i(t )dt t dt =

0 0

0, 6 t < 8

2

500(t 8) mC, 8 t < 14

18

16

14

12

10

q (C)

0

0 2 4 6 8 10 12 14

t(s)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

22. (a) iavg = 750 mA

4

(b) iavg = 1A

3

3t q(0) 3t 1 C, 0 t 1 s

t q(1) t 4 C, 1 t 2 s

(c) q(t ) i (t )dt

t q(2) t 2 C, 2t 3 s

q(3) 5 C, 3 t 4 s

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

A to D = 8 pJ so C to D = 3 pJ

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

vy = vx = +6.241015 V

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

25. (a) Voltage is defined as the potential difference between two points, hence two wires are

needed (one to each point).

(b) The reading will be the negative of the value displayed previously.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(a) (+1)(1) = 1 W

(b) (-1)(1) = 1 W

(e) A negative value for absorbed power indicates the element is actually supplying

power to whatever it is connected to.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(b) Open circuit corresponds to zero current, hence voc = 500 mV.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

Psupplied =

(2)(2) = 4 W;

(8)(2) = 16 W;

(10(-4) = -40 W;

(10)(5) = 50 W;

(10)(-3) = -30 W

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

32. The remaining power is leaving the laser as heat, due to losses in the system.

Conservation of energy requires that the total output energy, regardless of form(s), equal

the total input energy.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

33. (a) VR = 10 V, Vx = 2 V

Pabs =

(2)(-10) = 20 W;

(10)(10) = 100 W;

(8)(-10) = 80 W

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

34. (a) VR = 10 0 V, Vx = 92 V

PVR(supplied) = (100)(-5Vx) = -100(5)(92) = -46.00 kW

P5Vx(supplied) = (8)(5Vx) = (8)(5)(92) = 3.68 W

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

36. First, it cannot dissipate more than 100 W and hence imax = 100/12 = 8.33 A

10 A is too large; 1 A is just on the board and likely to blow at minimum power

operation, so 4 A is the optimum choice among the values available.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

37. (-2ix)(-ix) = 1

Solving, ix = 707 mA

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

7

(e) = 1.5 mA

4.7 103

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(2420)(0.001) = 2.42 V

(2420)( 410-3sin 44t) = 9.68 sin44t V

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(a) I (mA)

5

V (V)

-10 10

-5

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

41. We expect the voltage to be 33 times larger than the current, or 92.4 cos t V.

100

80

60

40

20

v(t) (V)

-20

-40

-60

-80

-100

0 1 2 3 4 5 6 7

t (s)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(b) R =

(c) R = 0

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

43. (a)

(b) 10 ns

(c) 5 s

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(a) i = 210-3/100 = 20 A

(b) i = 1/100 = 10 mA

(e) i = 0

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

ihi = 9/990 = 9.09 mA

Phi = 92/990 = 81.82 mW

9/900 = 10 mA;

92/1100 = 73.6 mW;

92/900 = 90.0 mW

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

1.5

0.5

Voltage (V)

-0.5

-1

-1.5

-2

-10 -8 -6 -4 -2 0 2 4 6 8

Current (mA) -4

x 10

(b) A best fit (using MATLAB fitting tool in plot window) yields a slope of 2.3 k.

However, this is only approximate as the best fit does not intersect zero current at

zero voltage.

1.5

data 1

y = 2.3e+003*x - 0.045

1 linear

0.5

Voltage (V)

-0.5

-1

-1.5

-2

-10 -8 -6 -4 -2 0 2 4 6 8

Current (mA) -4

x 10

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

PVs(supplied) = VsI

PR1(absorbed) = I2R1

PR2(absorbed) = (VR2)2/R2

We substitute Eq. [2] into Eq. [1] and solve for (VR2)2:

R22 R2

(VR2)2 = Vs2 hence VR2 = Vs . QED.

R1 R2 R1 R2

2

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

0.04

0.035

0.03

0.025

Power (W)

0.02

0.015

0.01

0.005

0

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Vresistor (V)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

50. <DESIGN>

L L

R 10 .

A A(qN D n )

Using the wafer thickness as one dimension of our cross sectional area A, A = 300x m2

and y is the other direction on the surface of the wafer, so L = y.

into a rectangle measuring 62.5 m wide by 6000 m long. Contact along narrow sides

of the 6000 m long strip.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

51. = (qNDn)-1. Estimating n from the graph, keeping in mind half-way on a log scale

corresponds to 3, not 5,

2

10

1

10

resistivity (ohm-cm)

0

10

-1

10

-2

10

-3

10

14 15 16 17 18 19

10 10 10 10 10 10

ND (/cm3)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

We note 28 AWG wire has a resistance of 65.3 ohms per 1000 ft length (at 20 oC).

There, 1531 ft is approximately 100 ohms and 7657 ft is approximately 500 ohms.

These are huge lengths, which reincorces the fact that copper wire is a very good

conductor.

*The next connection slides along the (uninsulated) coil. When connection is

approximately 20% of the length as measured from the left, R = 100 ohms. When it is at

the far (right) end, R = 500 ohms.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

R = (500 ft)(2.52 ohms/1000 ft) = 1.26 ohms

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

54. (a) 28 AWG = 65.3 ohms per 1000 ft therefore length = 1000(50)/65.3 = 766 ft

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

Choose 28 AWG wire. Require (10)(100)/(65.3) = 153 feet (rounding error within 1% of

target value). Wrap around 1 cm diameter 47 cm long wooden rod.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

The resistivity is therefore 8.4805/1.7654 = 4.804 times larger

(a) With constant voltage, the current will be (100/4.804) = 20.8% of expected value

(b) No additional power wil be wasted since the error leads to lower current: P = V/R

where V = unchanged and R is larger (0%)

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

P = i2R so

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

(a) IC = IB = 10 mA

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

59. Take the maximum efficiency of a tungsten lightbulb as 10%. Then only ~10 W (or 10

J/s) of optical (visible) power is expected. The remainder is emitted as heat and invisible

light.

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Engineering Circuit Analysis 8th Edition Chapter Two Exercise Solutions

60. Assuming the batteries are built the same way, each has the same energy density in terms

of energy storage.

Consequently, for the same voltage, we would anticipate the larger battery can supply the

same current for longer, or a larger maximum current, before discharging completely.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

1. (a) 5 nodes

(b) 7 elements

(c) 7 branches

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

2. (a) 4 nodes;

(b) 7 elements;

(c) 6 branches (we omit the 2 resistor as it is not associated with two distinct nodes)

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

3. (a) 4 nodes

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

4. (a) 6 elements;

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

5. (a) 4 nodes

(b) 5 elements

(c) 5 branches

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

6. The parallel-connected option would allow most of the sign to still light, even if one or

more bulbs burn out. For that reason, it would be more useful to the owner.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

7. iA + iB = iC + iD + iE

(a) iB = iC + iD + iE iA = 3 2 + 0 1 = 0 A

(b) iE = iA + iB iC iD = -1 -1 + 1 + 1 = 0 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

8. (a) By KCL, I = 7 6 = 1 A

(b) There is a typographical error in the 1st printing. The source should be labelled 9 A.

Then,

By KCL, 9 = 3 + I + 3 so I = 3 A.

(c) No net current can flow through the this resistor or KCL would be violated.

Hence, I = 0.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

9. We note that KCL requires that if 7 A flows out of the + terminal of the 2 V source, it

flows left to right through R1. Equating the currents into the top node of R2 with the

currents flowing out of the same node, we may write

7A

7 + 3 = i2 + 1

or

i2 = 10 1 = 9 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

10. By KCL, 1 = i2 3 + 7

Hence, i2 = 3 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

11. We can determine RA from Ohms law if either the voltage across, or the current through

the element is known. The problem statement allows us to add labels to the circuit

diagram:

7.6 A

Iwire

IRA

= 1.5 A

Iwire = 1.5 (-1.6) = 3.1 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

And, IC = IB = 15.0 mA

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

13. I3 = 5Vx

Vx = (210-3)(4.7103) = 9 V

Therefore I3 = 47 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

14. With finite values of R1 some value of current I will flow out of the source and through

the left-most resistor. If we allow some small fraction of that current kI (k < 1) to flow

through the resistor connected by a single node, to wher does the current continue? With

nowhere for the current to go, KCL is violated. Thus at best we must imagine an equal

current flowing the opposite direction, yielding a net zero current. Consequently, Vx

must be zero.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Hence, v1 = v2 v3 = 0 + 17 = 17 V

(d) v1 = v2 v3 = -2 2 = 4 V

(e) v2 = v1 + v3 = 7 + 9 = 16 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

17. By KVL, +9 + 4 + vx = 0

Therefore vx = 13 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

(b) 10 + 2i 1.5 + 2i + 2i + 2 1 + 2i = 0

Hence, 8i = 8 so i = 1 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Or -19 + 12 + 1.5 v2 1.5 + 3 = 0

Solving, v2 = 4 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

20. We note that vx does not appear across a simple element, and there is more than one loop

that may be considered for KVL.

+4 23 + 12 + v3 + vx = 0

Or

+4 23 +12 1.5 + vx = 0

Solving, vx = 8.5 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

21. We apply KCL/KVL and Ohms law alternately, beginning with the far left. Knowing

that 500 mA flows through the 7.3 resistor, we calculate 3.65 V as labelled below.

Then application of KVL yields 2.3 7.3 = 1.35 V across the 1 resistor.

This tells us that -1.35/1 = -1.35 A flows downward through the 1 resistor. KCL now

tells us that 0.5 (1.35) = 1.85 flows through the top 2 resistor. Ohms law dictates a

voltage of 3.7 V across this resistor in this case.

the right-most 2 resistor, as labelled below. Since this voltage also appears across the

current source, we know that

Vx = 5.05 V

+ 3.7 V

1.85 A

+ 3.65 V +

+

-5.05 V

-1.35 V

-1.35 A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Define a clockwise current I. Then v1 = IR1 and v2 = IR2.

-vs + IR1 + IR2 = 0

Thus, vs = (R1 + R2)I and I = v1/R1

so vs = (R1 + R2)v1/R1 or v1 = vsR1/(R1 + R2). QED

(PROOF)

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

i3 = 5v1 = 10 A

i1 = i2 + i3 = 10.33 A

i5 = (5/3)/5 = 333 mA

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

24. Define the current I flowing out of the + reference terminal of the 5 V source. This

current also flows through the 100 and 470 resistors since no current can flow into

the input terminals of the op amp.

5 + 100I = 0 [2]

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Absorbed power:

Source vs1: +(8)(+4.2) = 33.60 W

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

4.5 + 2I 40I + 5I = 0

ABSORBED POWER

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

ABSORBED POWER

500 : 500(I2) = 413.2 W

1 k: (1000)(I2) = 826.5 W

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Hence, ix = 10/92 = 108.7 mA

12 V (12)(-0.1087) = -1.304

27

33

13

19

2V (2)(0.1087) = 0.2174

and v1 = 33ix. Solving together, ix = 10/211 = 47.39 mA

Element Pabsorbed (W)

12 V -0.5687

27

33

Dep source

19

2V 0.09478

Solving, ix = 10/83 = 120.5 mA

12 V -1.446

27

33

Dep source

19

2V 0.2410

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

-3 + 100ID + VD = 0

Substituting in the equation which related the diode current and voltage,

VD

-3 + (100)(2910-12) e 2710 1

3

Solving either by trial and error or using a scientific calculators equation solver,

VD = 560 mV

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Solving, v = 5.333 V

(b)

3A (-5.333)(-3) = 16.00 W

7A (-5.333)(7) = -37.33 W

4 (4)(-1.333)2 = 7.108 W

2 (2)(-2.667)2 = 14.23 W

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

31. Consider the currents flowing INTO the top node. KCL requires

-2 i1 3 i2 = 0

Or i1 + i2 = -5 [1]

v/10 + v/6 = 5

Solving, v = 18.75 V

and the power supplied by the 3 A source is (3)( 18.75) = 56.25 W

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

1 + 2 = v/5 + 5 + v/5

Solving, v = 5 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

33. Summing the currents flowing into the top node, KCL yields

v v + 2 v/3 = 0

= (3)( v/3)(v) = 36/49 W (-735 mW)

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

34. Define the center node as +v; the other node is then the reference terminal.

v v v

KCL yields 3 103 5 103

1000 4700 2800

Solving, v = 1.274 V

(a) R Pabsorbed

1 k 1.623 mW

4.7 k 345.3 W

2.8 k 579.7 W

3 mA (v)(310-3) = 3.833 mW

-3

5 mA (v)( 510 ) = +6.370 mW

P supplied 2.548 mW

Thus, P supplied Pabsorbed .

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

(a) veq = 0 3 3 = 6 V;

(b) veq = 1 + 1 1 = 1 V;

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

(a) ieq = 0 + 3 + 3 = 6A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

37. The voltage sources are in series, hence they may be replaced with veq = 2 + 2 12 + 6

= 6 V. The result is the circuit shown below:

1 k

6 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

38. We may first reduce the series connected voltage sources, or simply write a KVL

equation around the loop as it is shown:

+2 + 4 + 7i + v1 + 7i + 1 = 0

Setting i = 0, v1 = 7 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

39. The current sources are combined using KCL to obtain ieq = 7 5 8 = 6 A.

The resulting circuit is shown below.

6 A 2 3

v v

(a) KCL stipulates that 6 v.

2 3

Solving, v = 36/5 V

Source Psupplied (W)

7 A source (7)(-36/5) = 50.4 W

5 A source (-5)(-36/5) = 36 W

8 A source (-8)(-36/5) = 57.6 W

43.2 W so confirmed.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

(b) Yes. Current sources in series must carry the same current. Voltage sources in

parallel must have precisely the same voltage.

(c)

1 4V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

1/Req = 1 + 1/4 + 1/3 = 19/12 -1

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

44. The 2 sources may be replaced with a 2 V source located such that i flows out of the +

reference terminal.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

And Req = 5 || 5 = 2.5

(a)

4A 2.5

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

46. Looking at the far right of the circuit, we note the following resistor combination is

possible: 3 || 9 + 3 + 5 + 3 ||6 = 2.25 + 8 + 2 = 12.25

Since this voltage appears across the current source and each of the three resistance (3 ,

5 , 12.25 ), Ohms law again applies: i3 = vx/3 = 542 mA

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

After this, we have three resistors in parallel but should not involve the 15 resistor as it

controls the dependent source. Thus, Req-1 = 1/3 + 1/12 and Req = 2.4 .

The simplified circuit is shown below.

Summing the currents flowing into the top node,

vx vx

2 4i 0 [1]

2.4 15

v v 4

2 x x vx 0

2.4 15 15

Solving, vx = 2.667 V

2.4

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

The independent sources may be combined into a single 4 + 3 9 = -2 A source (arrow

pointing up). We leave the 6 resistors; at least one has to remain as it controls the

dependent source. A voltage v is defined across the simplified circuit, with the + terminal

at the top node.

-2 2i = v/8.5 + v/6 + v/6 [1]

where i = v/6. Thus, Eq. [1] becomes -2 2v/6 = v/8.5 + 2v/6 or v = -19 V.

We have lost the 15 resistor temporarily, however. Fortunately, the voltage we just

found appears across the original resistor combination we replaced. Hence, a current -

19/8.5 = -2.235 A flows downward through the combination.

v 6(-2.235) = -5.59 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

= (33/7) || [33/8 + 33/9 + 1.571] = 3.1355

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

(b) v1 = v v2 = 2 1 = 1 V

(c) v = v1 + v2 = 3 + 6 = 9 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

52. (a) i1 = i i2 = 8 1 = 7A

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

R1 = v/i1 = 1

R2 = v/i2 = 833.3 m

R3 = v/i3 = 125 m

R4 = v/i4 = 322.6 m

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

2

vx 3 900 mV

2 3 1.667

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

V3 = (9)(3)/(1 + 3 + 5 + 7 + 9) = 1.08 V

V7 = (9)(7)/(1 + 3 + 5 + 7 + 9) = 2.52 V

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

We note the resistor combination (4 + 4) || 4 + 5 = 8 || 4 + 5 = 7.667 .

This appears in parallel with the 1 and 2 resistors, and experiences current i2.

Define the voltage v across the 25 A source with the + reference on top. Then,

v v v

25

1 2 7.667

i2= i1 v/2 = 2.005 A

branches, so we may write

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

2 k || 4 k = 8/6 k

3 k || 7 k = 21/10 k

6.433 k. That parallel combination is equivalent to 2.466 k.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

58. We could use voltage division for determining those voltages if i 1 = 0. Since it is nonzero

(presumably circuit analysis will verify whether this is the case), we do not have equal

currents through the two resistors, hence voltage division is not valid.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

60. We can apply voltage division to obtain v by first combining the 15 k and 3 k

resistors: 15 k || 3 k = 2.5 k.

Then by voltage division,

2.5

v 6 106 cos 2300t V 4.28cos 2300t V

1 2.5

= -3300(32210-3)(4.2810-6)cos 2300t

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

40 + 50 || (20 + 4) = 56.22

Further, the 10 || 10 can be replaced with a 5 resistor without losing the desired

voltage. Hence, v appears across 5 || 56.22 = 4.592

(b) The 4 resistor has been lost but we can return to the original circuit and note the

voltage determined in the previous part. By voltage division, the voltage across the 50

resistor is v(50 || 24)/(40 + 50 || 24) = 108.5 mV.

v4 = v50(4)/(20 + 4) = 18.08 mV

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

This is in parallel with 10 , yielding 8.49 in series with 20 .

Thus, I = 2/28.49 = 70.2 mA flows through the left-most 2 resistor.

This is split between the 10 and 56.22 combination.

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Engineering Circuit Analysis 8th Edition Chapter Three Exercise Solutions

Note the combination Req = 2/3 + 2 + 5 = 7.667 .

By inspection, I2left = 2 A;

I2middle = 0.7895(1)/3 = 263 mA

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

4 2 v1 9

1. (a)

1 5 v2 4

1 0 2 v1 8

(b) 2 1 5 v2 7

4 5 8 v3 6

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

2 1

2. (2)(3) (1)(4) 6 4 = 10

4 3

0 2 11

6 4 1 0 6[2(5) (11)(1) 3[(2)(1) (11)(4)] = 252

3 1 5

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

4 2

(4)(5) (2)(1) 18

1 5

9 2

4 5 45 8

v1 2.056

4 2 18

1 5

4 9

1 4 16 9

v2 0.3889

4 2 18

1 5

(b)

1 0 2

2 1 5 1[(1)(8) ( 5)(5)] 0 2[(2)(5) (1)(4)] 21

4 5 8

8 0 2

7 1 5

6 5 8 182

v1 8.667

21 21

1 8 2

2 7 5

4 6 8 182

v2 8.667

21 21

1 0 8

2 1 7

4 5 6 7

v3 0.3333

21 21

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

990 = (66 + 15 + 100)v1 15v2 110v3

308 = -14v1 + 36v2 22v3

0 = -140v1 30v2 + 212v3

Solving, v1 = 13.90 V

v2 = 21.42 V

v3 = 12.21 V

(b)

>> e1 = '990 = (66 + 15 + 110)*v1 - 15*v2 - 110*v3';

>> e2 = '308 = -14*v1 + 36*v2 - 22*v3';

>> e3 = '0 = -140*v1 - 30*v2 + 212*v3';

>> a = solve(e1,e2,e3,'v1','v2','v3');

>> a.v1

ans =

1070/77

>> a.v2

ans =

4948/231

>> a.v3

ans =

940/77

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

1596 (114 19 12)v1 19v2 12v3

180 = -v1 + (1 + 6)v2 6v3

1064 = -14v1 133v2 + (38 + 14 + 133)v3

>> e1 = '7 = v1/2 - (v2 - v1)/12 + (v1 - v3)/19';

>> e2 = '15 = (v2 - v1)/12 + (v2 - v3)/2';

>> e3 = '4 = v3/7 + (v3 - v1)/19 + (v3 - v2)/2';

>> a = solve(e1,e2,e3,'v1','v2','v3');

>> a.v1

ans =

16876/563

>> a.v2

ans =

54088/563

>> a.v3

ans =

43400/563

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

6. The corrected code is as follows (note there were no errors in the e2 equation):

>> e2 = '2 = (v2 - v1)/2 + (v2 - v3)/14';

>> e3 = '0 = v3/10 + (v3 - v1)/3 + (v3 - v2)/14';

>> a = solve(e1,e2,e3,'v1','v2','v3');

>> a.v1

ans =

1178/53

>> a.v2

ans =

9360/371

>> a.v3

ans =

6770/371

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

v1 v2 v1 v1 v3

7

4 2 19

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

v1 v1 v2

5 [1]

1 5

v v v

4 2 2 1 [2]

2 5

Hence,

i = (v1 v2)/5 = 1.625 A

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

9. Define nodal voltages v1 and v2 on the top left and top right nodes, respectively; the

bottom node is our reference node. Our nodal equations are then,

v1 v1 v2

3 (2 3)v1 3v2 18

3 2

v v

2 v2 2 1 v1 (2 1)v2 4

2

P1 = (v2)2/1 = 27.79 mW

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

v1 v1 v2

2 10v1 9v2 18

9 1

v v v

15 2 2 1 2v1 3v2 30

2 1

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

11. We note that he two 6 resistors are in parallel and so can be replaced by a 3 resistor.

By inspection, i1 = 0.

v A v A vB

2 (1 3)v A 3vB 6 [1]

3 1

v v v

4 B B A 3v A (1 3)vB 12 [2]

3 1

Solving,

vA = -1.714 V and vB = -4.28 V. Hence, v1 = vA vB = 2.572 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

Define v2 across the 2.5 A source, + reference at the top.

Define v3 acros the 200 resistor, + reference at the top.

v1 v1 v p

10 [1]

20 40

v p v1 v p v2 v p

0 + [2]

40 50 100

v2 v p v2 v3

2 2.5 [3]

50 10

v v v

52 3 2 3 [4]

10 200

Solving, vp = 171.6 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

13. Choose the bottom node as the reference node. Then, moving left to right, designate the

following nodal voltages along the top nodes: v1, v2, and v3, respectively.

v1 v3 v1 v2

8 4 [1]

3 3

v v v v v

4 2 2 1 + 2 3 [2]

5 3 1

v v v v v

5 3 1 3 2 + 3 [3]

3 1 7

v5 = v2 = 8.833 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

14. Assign the following nodal voltages: v1 at top node; v2 between the 1 and 2

resistors; v3 between the 3 and 5 resistors, v4 between the 4 and 6 resistors. The

bottom node is the reference node.

v1 v2 v2 v3 v2 v3

2 + [1]

1 3 4

v v v

3 2 2 1 [2]

2 1

v v v v v

3 3 3 1 + 3 4 [3]

5 3 7

v v v v v

0 4 4 1+ 4 3 [4]

6 4 7

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

15. First, we note that it is possible to separate this circuit into two parts, connected by a

single wire (hence, the two sections cannot affect one another).

v1 v1 v3

2 [1]

2 6

v v v v v

2 2 2 3 + 2 4 [2]

5 2 10

v v v v v v

1 3 1 3 2 + 3 4 [3]

6 2 5

v v v v v

0 4 2 4 3 + 4 [4]

10 5 5

Solving,

v1 = 3.078 V

v2 = -2.349 V

v3 = 0.3109 V

v4 = -0.3454 V

v5 v5 v7

2 + [1]

1 4

v v v v v

2 6 6 8 6 7 [2]

4 4 2

v v v v v v

6 7 5 7 6 + 7 8 [3]

4 2 10

v v v v v

0 8 8 6 + 8 7 [4]

1 4 10

Solving,

v5 = 1.019 V

v6 = 9.217 V

v7 = 13.10 V

v8 = 2.677 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

16. We note that the far-right element should be a 7 resistor, not a dependent current

source.

The bottom node is designated as the reference node. Naming our nodal voltages from

left to right along the top nodes then: vA, vB, and vC, respectively.

v A vC v A vB

0.02v1 + [1]

5 3

v v v v

10 B A B C [2]

3 2

v v v vA

0 C B C [3]

2 5

However, we only have three equations but there are four unknowns (due to the presence

of the dependent source). We note that v1 = vC vB. Substituting this into Eq. [1] and

solving yields:

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

17. Select the bottom node as the reference node. The top node is designated as v1, and the

center node at the top of the dependent source is designated as v2.

v1 v2 v1

1 [1]

5 2

v2 v2 v1

vx [2]

3 5

We have two equations in three unknowns, due to the presence of the dependent source.

However, vx = v2, which can be substituted into Eq. [2]. Solving,

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

18. We first create a supernode from nodes 2 and 3. Then our nodal equations are:

v1 v3 v1 v2

35 + [1]

1 5

v2 v2 v1 v3 v3 v1

58 + [2]

3 5 2 1

We also require a KVL equation that relates the two nodes involved in the supernode:

v2 v3 4 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

19. We name the one remaining node v2. We may then form a supernode from nodes 1 and 2,

resulting in a single KCL equation:

v1 v2

35 +

5 9

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

20. We define v1 at the top left node; v2 at the top right node; v3 the top of the 1 resistor;

and v4 at the top of the 2 resistor. The remaining node is the reference node.

We may now form a supernode from nodes 1 and 3. The nodal equations are:

v3 v1 v2

2 + [1]

1 10

v v v

2 4 + 4 2 [2]

2 4

is v1 v3 = 6. Solving,

v1 = 4.019 V

v2 = 5 V

v3 = 1.909 V

v4 = 4.333 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

21. We first select a reference node then assign nodal voltages as follows:

v1 v2 v3 v4 v5

v6

Ref

There are two supernodes we can consider: the first is formed by combining nodes 2, 3

and 6. The second supernode is formed by combining nodes 4 and 5. However, since we

are asked to only find the power dissipated by the 1 resistor, we do not need to perform

a complete analysis of this circuit.

Since this is the voltage across the resistor of interest, P 1 = (1)2/1 = 1 W

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

22. We begin by selecting the bottom center node as the reference node. Then, since 4 A

flows through the bottom 2 resistor, 4 V appears across that resistor.

Naming the remaining nodes (left to right) v1, v2, v3, v4, v5, and v6, respectively, we see

two supernodes: combine nodes 2 and 3, and then nodes 5 and 6.

v1 v2

46 [1]

14

v v v v

0 2 1+ 3 4 [2]

14 7

v v v 1 v4 v5

0 4 3 + 4 + [3]

7 2 7

v v v

6 6 + 5 4 [4]

3 7

with

v2 v3 4 [5]

v6 v5 3 [6]

Solving,v4 = 0. Thus, the current flowing out of the 1 V source is (1 0)/2 = 500 mA

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

23. We select the central node as the reference node. We name the left-most node v1; the top

node v2, the far-right node v3 and the bottom node v4.

By inspection, v1 = 5 V

We form a supernode from nodes 3 and 4 then proceed to write appropriate KCL

equations:

v2 v2 v3

1 [1]

2 10

v v v v v

5 3 2 + 3 + 4 1 [2]

10 20 12

Solving, v2 = v = 1.731 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

24. A strong choice for the reference node is the bottom node, as this makes one of the

quantities of interest (vx) a nodal voltage. Naming the far left node v1 and the far right

node v3, we are ready to write the nodal equations after making a supernode from nodes 1

and 3:

v1 vx v3

1 8 [1]

8 2

v v v

8 x 1 + x [2]

8 5

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

25. We select the bottom center node as the reference. We next name the top left node v1, the

top middle node v2, the top right node v3, and the bottom left node v4.

v4 v2 v3

2 [1]

4 2

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

26. Our nodal equations may be written directly, noting that two nodal voltages are available

by inspection:

vx 2 vx vx v y

0 + [1]

1 1 4

v y vx v y kv y

1 + [2]

4 3

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

27. If we select the bottom node as our reference, and name the top three nodes (left to right)

vA, vB and vC, we may write the following nodal equations (noting that vB = 4v1):

v A 4v1 v A vC

2 [1]

2 3

v 4v1 vC v A

v1 C + [2]

5 3

And v1 = vA vC

Solving, v1 = 480 mV

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

28. With the selected reference node, v1 = 1 V by inspection. Proceeding with nodal analysis,

v2 v1 v2 v3

3 [1]

1 2

v3 v2 v3 v4

2vx + [2]

2 1

v4 v4 v3 v4 v1

0 [3]

3 1 4

And to account for the additional variable introduced through the dependent source,

vx = v3 v4

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

29. We define two clockwise flowing mesh currents i1 and i2 in the lefthand and righthand

meshes, respectively. Our mesh equations are then

1 5i1 i2 [1]

2 i1 6i2 [2]

Solving,

i1 = 275.9 mA and i2 = 379.3 mA

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

14(i1 i2 ) 3i1 12 0 [2]

Solving,

i1 = 1.130 A and i2 = 515.5 mA

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

15 11 10i1 i2 [1]

21 11 i1 10i2 [2]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

(1)(i2 i1 ) 6i2 9(i2 i3 ) 0 [2]

5(i3 i1 ) 3 9(i3 i2 ) 7i3 0 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

0 i1 16i2 9i3 [2]

3 5i1 9i2 21i3 [3]

Thus,

P1 = (i2 i1)2(1) = 703.9 mW

P6 = (i2)2(6) = 135.4 mW

P9 = (i2 i3)2(9) = 41.62 mA

P7 = (i3)2(7) = 172.5 mW

P5 = (i3 i1)2(5) = 3.463 W

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

34. The 220 resistor carries no current and hence can be ignored in this analysis. Defining

three clockwise mesh currents i1, i2, iy left to right, respectively,

4700(i2 i1 ) (4700 1000 5700)i2 5700iy 0 [2]

5700i2 (5700 4700 1000)iy 0 [3]

(b) Since no current flows through the 220 resistor, it dissipates zero power.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

35. We name the sources as shown and define clockwise mesh currents i1, i2, i3 and i4:

V2

V3

V1

To obtain i1 i3 = 0 [1], i1 i2 = 0 [2], i3 i4 = 0 [3], i2 i4 [4],

we begin with our mesh equations:

0 7i1 2i3 [6]

V2 8i2 5i1 3i4 [7]

V3 10i4 3i2 7i3 [9]

It is therefore not possible to select nonzero values for the voltage sources and meet

the specifications.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

36. Define a clockwise mesh current iy in the mesh containing the 10 A source. Then, define

clockwise mesh currents i1, i2 and ix, respectively, in the remaining meshes, starting on

the left, and proceeding towards the right.

By inspection, iy = 10 A [1]

Then,

3 + (8 + 4)i1 4i2 = 0 [2]

4i1 + (4 + 12 + 8)i2 8i3 = 0 [3]

8i2 + (8 + 20 + 5)ix 20ix = 0 [4]

Solving, ix = 6.639 A

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

Our mesh equations then are:

0 = 5i2 4i1 [2]

0 = 5i3 i1 [3]

Then, i = i3 i2 = 260.8 mA

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

38. In the lefthand mesh, we define a clockwise mesh current and name it i2.

Then, our mesh equations may be written as:

3i2 + (3 + 5)i1 + 1 = 0 [2]

(note that since the dependent source is controlled by one of our mesh

currents/variables/unknowns, these two equations suffice.)

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

39. Define clockwise mesh currents i1, i2, i3 and i4. By inspection i1 = 4 A and i4 = 1 A.

(a) Define vx across the dependent source with the bottom node as the reference node.

Then,

vx + 7i3 2 = 0 [2]

Thus, i2 + 6i3 = 5 [3]

We first add Eqs. [1] and [2], so that our set of equations becomes:

i2 + 6i3 = 5 [3]

(b) Using nodal analysis, we define V1 at the top of the 4 A source, V2 at the top of the

dependent source, and V3 at the top of the 1 A source. The bottom node is our reference

node.

Then,

V1 V1 V2

4

2 1

V V V V

5ix 2 1 2 3

1 5

V V V

1 3 3 2

2 5

and

ix = V2/2

Solving, V1 = 6 V and V2 = 5 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

40. Define a clockwise mesh current i1 for the mesh with the 2 V source; a clockwise mesh

current i2 for the mesh with the 5 V source, and clockwise mesh current i 3 for the

remaining mesh.

2 + (2 + 9 + 3)i1 + 1 = 0

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

41. We define four clockwise mesh currents. In the top left mesh, define i 1. In the top right

mesh, define i2. In the bottom left mesh, define i3 (note that i3 = ix). In the last mesh,

define i4. Then, our mesh equations are:

5i3 i4 9 = 0 [2]

11i2 + 0.2ix = 0 [3]

5i4 4i2 i3 = 0.1va [4]

where va = 7i1.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

42. Our best approach here is to define a supermesh with meshes 1 and 3. Then,

7i1 + (7 + 1 + 3)i2 3i3 = 0 [2]

i3 i1 = 2 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

43. In the one remaining mesh, we define a clockwise mesh current i 2. Then, a supermesh

from meshes 1 and 3 may be formed to simplify our analysis. Hence,

10i1 + 16i2 i3 = 0 [2]

i1 + i3 = 5 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

44. Define (left to right) three clockwise mesh currents i 2, i3 and i4. Then, we may create a

supermesh from meshes 2 and 3. By inspection, i4 = 3 A.

5i2 + (3 + 5 + 10 + 11)i1 11i3 = 0 [2]

i3 i2 = 9 [3]

Solving, i1 = 874.3 mA

i2 = 7.772 A

i3 = 1.228 A

i4 = 3 A

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

i1 + i2 = 1

i1 i3 = 3

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

46. By inspection, the unlabelled mesh must have a clockwise mesh current equal to 3 A.

Define a supermesh comprised of the remaining 3 meshes. Then,

and i1 i3 = 2 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

47. By inspection, i1 = 5 A.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

48. Define clockwise mesh current i2 in the top mesh and a clockwise mesh current i 3 in the

bottom mesh. Next, create a supermesh from meshes 2 and 3. Our mesh/supermesh

equations are:

(1)i3 (1)i1 + 3i2 3i1 8 + 2i3 = 0 [2]

and

i2 i3 = 5i1 [3]

(Since the dependent source is controlled by a mesh current, there is no need for

additional equations.)

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

We form a supermesh from meshes 2 and 3 since they share a (dependent) current source.

5 + i3 + 2(i3 i1) + 4(i2 i1) = 0 [2]

Also,

i2 i3 = 1.8v3 where v3 = i3(1) = i3. Hence, i2 i3 = 1.8i3 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

50. With the top node naturally associated with a clockwise mesh current i a, we name (left to

right) the remaining mesh currents (all defined flowing clockwise) as i 1, i2 and i3,

respectively.

Then,

2ia + 3ia 3i1 + 10ia + 4ia 4(6) + 5i2 5(6) = 0 [2]

Also, i2 ia = 5 [3]

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

51. (a) 4;

We also note that a supermesh is indicated so the actual number of mesh

equations is only 3.

(c) With nodal analysis we obtain i5 by Ohms law and 4 simultaneous equations.

With mesh/supermesh, we solve 4 simultaneous equations and perform a subtraction.

The difference here is not significant.

In the case of v7, we could define the common node to the 3 A source and 7 W

resistor as the refernce and obtain the answer with no further arithmetic steps. Still,

we are faced with 4 simultaneous equations with nodal analysis so mesh analysis is

still preferable in this case.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

52. (a) Without employing the supernode technique, 4 nodal equations would be required.

With supernode, only 3 nodal equations are needed plus a simple KVL equation. (Then

simple division is necessary to obtain i5).

(b) Although there are 5 meshes, one mesh current is available by inspection, so really

only 4 mesh equations are required.

(c) The supernode technique is preferable here regardless; it requires fewer simultaneous

equations.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

53. (a) Nodal analysis requires 2 nodal equations and 2 simple subtractions

Mesh analysis requires 2 mesh equations and 2 simple multiplications

Neglecting the issues associated with fractions and grouping terms, neither

appears to have a distinct advantage.

(b) Nodal analysis: we would form a supernode so 2 nodal equations plus one KVL

equation. v1 is available by inspection, v2 obtained by subtraction.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

54. (a) Mesh analysis: Define two clockwise mesh currents i 1 and i2 in the left and right

meshes, respectively. A supermesh exists here.

and i1 + i2 = 11 [2]

(b) Nodal analysis: Define the top left node as v1, the top right node as vx.

and v1 vx = 22 [2]

Solving, v1 = 22 V and vx = 0

(c) In terms of simultaneous equations, there is no real difference between the two

approaches. Mesh analysis did require multiplication (Ohms law) so

nodal analysis had a very slight edge here.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

55. (a) Nodal analysis: 1 supernode equation, 1 simple KVL equation. v1 is a nodal voltage

so no further arithmetic required.

(b) Mesh analysis: 4 mesh equations but two mesh currents available by inspection so

only two mesh equations actually required. Then, invoking Ohms law is required to

obtain v1.

(c) Nodal analysis is the winner, but it has only a slight advantage (no final arithmetic

step). The choice of reference node will not change this.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

56. (a) Using nodal analysis, we have 4 nodal voltages to obtain although one is available by

inspection. Thus, 3 simultaneous equations are required to obtain v1, from which we may

calculate P40.

(b) Employing mesh analysis, the existence of four meshes implies the need for 4

simultaneous equations. However, 2 mesh currents are available by inspection, hence

only 2 simultaneous equations are needed. Since the dependent source relies on v1, simple

subtraction yields this voltage (0.1 v1 = 6 4 = 2 A).

Mesh wins.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

57. (a) Nodal analysis: 2 nodal equations, plus 1 equation for each dependent source that

is not controlled by a nodal voltage = 2 + 3 = 5 equations.

(b) Mesh analysis: 3 mesh equations, 1 KCL equation, 1 equation for each dependent

source not controlled by a mesh current = 3 + 1 + 2 = 6 equations.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

Replace the independent current source of Fig. 4.28 with a dependent current source.

v1

i1

(a) Make the controlling quantity 8v1, i.e. depends on a nodal voltage.

(b) Make the controlling quantity 8i1, i.e. depends on a mesh current.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

59. Referring to the circuit of Fig. 4.34, our two nodal equations are

v1 v1 v2

5 [1]

1 5

v v v

4 2 2 1 [2]

2 5

Hence,

i = (v1 v2)/5 = 1.625 A

In PSpice,

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

v v v

2 1 1 2 10v1 9v2 18

9 1

v v v

15 2 2 1 2v1 3v2 30

2 1

Using PSpice,

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

v1 v3 v1 v2

8 4 [1]

3 3

v2 v2 v1 v2 v3

4 + [2]

5 3 1

v3 v1 v3 v2 v3

5 + [3]

3 1 7

v5 = v2 = 8.833 V

Within PSpice,

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

62. Referring to Fig. 4.41, first, we note that it is possible to separate this circuit into two

parts, connected by a single wire (hence, the two sections cannot affect one another).

For the left-hand section, our nodal equations are:

v1 v1 v3

2 [1]

2 6

v v v v v

2 2 2 3 + 2 4 [2]

5 2 10

v v v v v v

1 3 1 3 2 + 3 4 [3]

6 2 5

v v v v v

0 4 2 4 3 + 4 [4]

10 5 5

Solving,

v1 = 3.078 V, v2 = 2.349 V, v3 = 0.3109 V, v4 = -0.3454 V

v v v

2 5 + 5 7 [1]

1 4

v v v v v

2 6 6 8 6 7 [2]

4 4 2

v v v v v v

6 7 5 7 6 + 7 8 [3]

4 2 10

v v v v v

0 8 8 6 + 8 7 [4]

1 4 10

Solving, v5 = 1.019 V, v6 = 9.217 V, v7 = 13.10 V, v8 = 2.677 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

63. Referring to Fig. 4.43, select the bottom node as the reference node. The top node is

designated as v1, and the center node at the top of the dependent source is designated as

v2. Our nodal equations are:

v1 v2 v1

1 [1]

5 2

v v v

vx 2 2 1 [2]

3 5

We have two equations in three unknowns, due to the presence of the dependent source.

However, vx = v2, which can be substituted into Eq. [2]. Solving,

v1 = 1.484 V and v2 = 0.1936 V

By PSpice,

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

.OP

V1 1 0 DC 40

R1 1 2 11

R2 0 2 10

R3 2 3 4

R4 2 4 3

R5 0 3 5

R6 3 4 6

R7 3 9 2

R8 4 9 8

R9 0 9 9

R10 0 4 7

( 9) 3.8487

v 40 v2 v2 v3 v2 v4

0 2

11 10 4 3

v v v v v v v

0 3 2 3 3 4 3 9

4 5 6 2

v v v v v v v

0 4 3 4 4 9 4 2

6 7 8 3

v v v v v

0 9 4 9 3 9

8 2 9

Solving,

v1 = 40 V (by inspection); v2 = 8.344 V; v3 = 4.367 V; v4 = 5.200 V; v9 = 3.849 V

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

4.5 V across terminal C and the reference terminal;

5 V across terminal B and the reference terminal.

Although this leads to I = 1 A, which is greater than 1 mA, it is almost 1000 times the

required value. Hence, scale the resistors by 1000 to construct a circuit from 3 k, 1 k,

500 , and 4.5 k. Then I = 1 mA.

1 k = 1 k; 4.5 k = 2 k + 2 k.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

66. (a) The bulbs must be connected in parallel, or they would all be unlit.

(b) Parallel-connected means each bulb runs on 12 V dc. A power rating of 10 mW then

indicates each bulb has resistance (12)2/(1010-3) = 14.4 k

Given the high resistance of each bulb, the resistance of the wire connecting them is

negligible.

SPICE OUTPUT: (edited slightly for clarity)

.OP

V1 1 0 DC 12

R1 1 0 327.3

**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C

**********************************************************************

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

( 1) 12.0000

VOLTAGE SOURCE CURRENTS

NAME CURRENT

V1 -3.666E-02

JOB CONCLUDED

1

Req 327.3 . This would draw (12)2/327.3 = 440 mW.

1

(44) 14400

(A more straightforward, but less interesting, route would be to multiply the per-bulb

power consumption by the total number of bulbs).

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

We select nodal analysis, with the bottom node as the reference terminal. We then assign

nodal voltages v1, v2, v3 and v4 respectively to the top nodes, beginning at the left and

proceeding to the right.

Arbitrarily select v2 = 1.4 V, v3 = 1 V.

So, element B must be a 1.4 V voltage source, and element C must be a 1 V voltage

source. Choose A = 1 A current source, D = 1 A current source; F = 500 mV voltage

source, E = 500 mV voltage source.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

68. (a) If the voltage source lies between any node and the reference node, that nodal voltage

is readily apparent simply by inspection.

(b) If the current source lies on the periphery of a mesh, i.e. is not shared by two meshes,

then that mesh current is readily apparent simply by inspection.

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

69. (a) Although mesh analysis yields i2 directly, it requires three mesh equations to be

solved. Therefore, nodal analysis has a slight edge here since the supernode technique

can be invoked.

We choose the node at the + terminal of the 30 V source as our reference. We assign

nodal voltage vA to the top of the 80 V source, and vC to the - terminal of that source.

vB, the nodal voltage at the remaining node (the - terminal of the 30 V source), is seen

by inspection to be -30 V (vB = -30 [1]). Our nodal equations are then

v v v v

0 A B C C [2]

10 30 40

and vA vC = 80 [3]

Solving,

vA = 10.53 V, vB = -30 V, and vC = 69.47 V.

Hence

i2 = vC/30 = 2.316 A

(b)

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Engineering Circuit Analysis 8th Edition Chapter Four Exercise Solutions

Nodal analysis:

Assign v1 to the top node of the diamond; the bottom node is our reference node. Then v2

is assigned to the lefthand node of the diamond; v3 is assigned to the remaining node.

We can form a supernode from nodes 1,2, and 3, so

v1 80 v2 v3

0 [1] and

10 30 40

v3 v1 30 [2] and

v2 v3 2.5 [3]

Solving, v3 = 68.95 V

Mesh analysis:

80 (10 20 30)i1 20i2 30i3 0 [4]

20i2 20i1 30 2.5 0 [5]

(30 40)i3 30i1 2.5 0 [6]

Solving, i3 = 1.724 A

Hence, v3 = 40i3 = 68.95 V

There does not appear to be a clear winner here. Both methods required writing and

solving three simultaneous equations, practically speaking. Mesh analysis then required

multiplication to obtain the voltage desired, but is that really hard enough to give nodal

analysis the win? Lets call it a draw.

(b)

(c) In this case, perhaps mesh analysis will look slightly more attractive, but via nodal

analysis Ohms law yields i2 easily enough.

Perhaps all this change does it make it more of a draw.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

1. (a) flinear = 1 + x

(b)

x flinear ex %error

10-6 1.000001 1.000001000 -

10-4 1.001 1.00100005 -

10-2 1.01 1.010050167 0.005%

0.1 1.1 1.105170918 0.5%

1 2 2.718281828 26%

(c) Somewhat subjectively, we note that the relative error is less than 0.5% for x < 0.1 so

use this as our estimate of what constitutes reasonable.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

8t 4sin 2t

(a) Define %error 100

4sin 2t

t 8t 4sin2t %error

10-6 810-6 8.00010-6 0% (to 4 digits)

10-4 810-4 8.00010-4 0% (to 4 digits)

10-2 810-2 0.07999 0.01%

10-1 810-1 0.7947 0.7%

1.0 8.0 3.637 55%

(b) This linear approximation holds well (< 1% relative error) even up to t = 0.1. Above

that value and the errors are appreciable.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

3 18 8 16

3. i8 6 A only 6 A. i8 2 V only 2 A

3 8 11 3 8 11

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

4. (a) We replace the voltage source with a short circuit and designate the downward current

through the 4 resistor as i'.

Next, we replace the current source in the original circuit with an open circuit and

designate the downward current through the 4 resistor as i".

Then, i" = 1/13 = 0.07692 A

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

14

5. (a) Replacing the 5 A source with an open circuit, ix 3 A only 3 1.75 A .

14 10

5

Replacing the 3 A source with an open circuit, ix 5 A only 5 1.316 A .

19

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

resistor. Thus, v1 7 A = (7)(1||12) = (7)(0.9231) = 6.462 V

by current division,

7

v1 4 A (1) 4 2.154 V

7 7

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

7

7. (a) v2 7 A (5) 7 12.89 V

19

14

v2 2 A (5) 2 7.368 V

19

(b) We see from the simulation output that the 7 A source alone contributes 12.89 V. The

output with both sources on is 5.526 V, which agrees within rounding error to our hand

calculations (5.522 V).

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

8. (a) 4 V 8 V; 10 V 20 V

(b) 4 V 4 V; 10 V 10 V

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

3 || 2 1|| 3

9. vx 12 (15) 2.454 V

(3 || 2) 1 (1|| 3) 2

3 || 2 1|| 3

vx 6 (10) 0.5454 V

(3 || 2) 1 (1|| 3) 2

3 || 2 1|| 3

vx 6 (5) 1.909 V

(3 || 2) 1 (1|| 3) 2

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

10. (a) With the right-hand voltage source short-circuited and the current source open-

circuited, we have 2 || 5 = 10/7

1

By voltage division, vx lefthand 4 V (4) 0.7368 V

3 1 10 / 7

With the other voltage source short-circuited and the current source open-circuited, we

have (3 + 1) ||5 = 2.222 .

2.222 1

v5 4 2.105 V . Then, vx 2.105 0.5263 V

2.222 2 righthand4 V

4

3

vx 2 A (1) 2 1.105 V

3 1 10 / 7

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

11. We select the bottom node as the reference, then identify v1 with the lefthand terminal of

the dependent source and v2 with the righthand terminal.

v1 1 v1 v

2 0 and

5000 7000 2000

0.2

1 v1 v2 0

7000

Solving, v1 = 0.237 V

v1 v v

1 2 2 and

5000 7000 2000

0.2

1 v1 v2 0

7000

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

12. We note that the proper label for the voltage source is 4 V.

With the current source open-circuited, we name the top of the 2 resistor v1, identify

the current through it as i1, and the voltage across the 3 resistor as v.Applying nodal

analysis yields

v1 4 v1 v1 v

0 [1] and

7 2 1

v v v1 v1

0.4i1 [2] where i1 .

3 1 2

We next short circuit the voltage source, name the node at the top of the 2 resistor v2,

the current through it i1, and the voltage across the 3 resistor v. Then,

v2 v2 v2 v

6 [1] and

7 2 1

v v v2 v2

6 0.4i1 [2] where i1

3 1 2

Thus, v = v + v = 3.375 V

(b) i1 = i1 + i1 = 625 mA

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

13.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

R 3

14. vL 3 ; iL

R 5000 5000 R

2.5

2

vL (V)

1.5

0.5

0

0 1 2 3 4 5 6

iL (A) -4

x 10

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

15. We cannot involve the 5 resistor in any transforms as we are interested in its current.

parallel with 11 .

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

16. For the circuit depicted in Fig. 5.22a, i7 = (5 3)/7 = 285.7 mA.

Thus, the power dissipiated by this resistor is unchanged since it is proportional to (i 7)2.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

17. (a) The transform available to us is clearer if we first redraw the circuit:

We can replace the current source / resistor parallel combination with a 10 V voltage

source (-

analyzed with mesh analysis:

Solving, i = 577.5 nA

(b)

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

Combine the 27 A and 750 k to obtain 20.25 V in series with 750 k in series with

3.5 M.

Convert this series combination to a 4.25 M resistor in parallel with a 4.765 A source,

arrow up.

Convert the 15 V/ 1.2 M series combination into a 12.5 A source (arrow down) in

parallel with 1.2 M. This appears in parallel with the current source from above as well

as the 7 M and 6 M.

4.765 A yield a -7.735 A source (arrow up) in parallel with 825.4 k in parallel with 6

M.

Convert the current source and 825.4 k resistor into a -6.284 V source in series with

825.4 k and 6 M.

6.384

Then, P6 M

6 10 5.249 W

6

6 10 825.4 103

6

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

19. (a) We combine the 1 and 3 resistors to obtain 0.75 . The 2 A and 5 A current

sources can be combined to yield a 3 A source.

These two elements can be source-transformed to a (9/4) V voltage source (+ sign up)

in series with a 0.75 resistor in series with the 7 V source and the far-left 3 resistor.

(b) In the original circuit, we define the top node of the current sources as v1 and the

bottom node is our reference node.

Solving, v1 = 2/5 V and so the clockwise current flowing through the 7 V source is

Analyzing our transformed circuit, the clockwise current flowing through the 7 V source

is (-7 9/4)/3.75 = -37/15 A.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

20. (a) We start at the left, switching between voltage and current sources as we

progressively combine resistors.

477 || 22 = 14.99

parallel with 24.99 and 7 . 24.99 || 7 = 5.468

with next 7 to obtain 12.468 . Back to current source: 0.8306/12.468 = 0.06662 A in

parallel with 12.468 and 9 .

12.468 ||9 = 5.227 . Back to voltage source: (0.06662)(5.22) = 0.3482 V in series with

5.227 . Combine with 2 to yield 7.227 .

(c) We note good agreement with our answer in part (b) but some rounding errors creep

in due to the multiple source transformations.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

21. We combine the 3 V source and 3 resistor to obtain 1 A in parallel with 3 in parallel

with 7 . Note that 3 || 7 = 21/10 . We transform the 9 A current source into an 81 V

source, + reference on the bottom, in series with 9 .

We combine the two 10 resistors in parallel (5 ) and the dependent current source to

obtain a dependent voltage source, + reference on the right, controlled by 25 Vx. This

source is in series with 14 . Transforming the current source back to a voltage source

21

allows us to combine the 81 V source with (1)(21/10) V to obtain 81 V. We are left

10

21 21

with an independent voltage source 81 V in series with 14 in series with the

10 10

dependent voltage source, in series with the 4 resistor:

21 21

81 14 i 25Vx 4i 0

10 10

where

Vx 4i

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

22. (a) Because the controlling current flows through the dependent source as well as the 7

, we cannot transform the dependent voltage source into a dependent current source;

doing so technically loses I1.

Thus, the only simplification is to replace the voltage source and 11 resistor with a

(9/11) A current source (arrow up) in parallel with an 11 resistor.

(c)

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

23. The 2 resistor and the bottom 6 resistor can be neglected as no current flows through

either. Hence, V1 = V0.

reference at the bottom) in series with a 6 resistor.

+72V1 0.7 + 13 i = 0

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

24. The independent source may be replaced by a (2/6) A current source, arrow pointing up,

in parallel with 6 . The dependent voltage source may be replaced by a dependent

current source (arrow pointing up) controlled by v3. This is in turn in parallel with 2 .

Choose the bottom node as the reference noded. Name the top left node va and the top

right node vb. Then,

2 v v v

4v3 a a b

6 6 3

and

vb va vb

v3

3 2

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

So:

RL VL

1 1.688 V

3.5 3.313 V

6.257 3.995 V

9.8 4.410 V

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

VL = Vth(RL)/(Rth + RL)

RL () VL (V)

1 1.688

3.5 3.316

6.257 4.000

9.8 4.410

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

27. (a) We remove RL and replace it with a short. The downward current through the short is

then

Returning to the original network, open circuit the current source, remove R L. Looking

into the open terminals we find RN = 2 || (2.5 + 0.8) = 1.245

(c)

RL () iL(mA)

0 242.4

1 134.4

4.923 48.93

8.107 32.27

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

v1 4.2 v v v

0 1 1 oc [1]

1800 2500 744

voc v v

0 oc 1 [2]

2500 744

4.2 7441

isc 1 1 1

= 1.364 mA

1800 1800 2500 744

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

v1 4.2 v v v

0 1 1 oc [1]

1800 2500 744

voc v v

0 oc 1 [2]

2500 744

4.2 7441

isc 1 1 1

= 1.364 mA

1800 1800 2500 744

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

30. (a) Define three clockwise mesh currents i1, i2 and i3, respectively in the three meshes,

beginning on the left. Short the opn terminals together. Then, create a supermesh:

i3 i2 0.3 [3]

Short the voltage source, open circuit the current source, and look into the open

terminals:

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

31. Select the top of the R4 resistor as the reference node. v1 is at the top of R5, v2 is at the +

of voc and v3 is at the - of voc. The bottom node is the negative reference of voc.

v v v v v

Then i1 1 1 3 1 2 [1]

R2 R5 R3

v2 v1 v2

0 [2]

R3 R1

v3 v1 v3

0 [3] Solving,

R5 R4

R2 ( R1R5 R3 R4 )i1

vth voc v2 v3

R1R2 R1R4 R2 R3 R1R5 R2 R4 R2 R5 R3 R4 R3 R5

Next, short the open terminals and define four clockwise mesh currents i 1, i2, i3, and i4. i1

is the top mesh, i3 is the bottom left mesh, i4 is the bottom right mesh, and i2 is the

remaining mesh. Then

R2i2 ( R2 R4 R5 )i3 R5i4 0 [1]

Solving, isc = i4 =

R2 R1R5 R3 R4

i1

R1R2 R3 R1R2 R5 R1R3 R4 R1R3 R5 R2 R3 R4 R1R4 R5 R2 R4 R5 R3 R4 R5

R1R2 R1R4 R2 R3 R1R5 R2 R4 R2 R5 R3 R4 R3 R5

2.296

2

(b) Voc = 2.2964 V; Rth = 1.66 M Hence P1M =

1.66 10 6

10 6

106 = 745 nW

(c)

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

32. Define three clockwise mesh currents i1, i2, i3 starting on the left.

Then

2 2i1 6i2 i3 0 [1]

i2 4i3 4 0 [2]

i2 i1 2 [3]

Solving,

i2 = 129 mA. Hence, voc = vx = 5i2 = 645.2 mV

Next, short the voltage sources and open circuit the current source. Then,

Rth = 5 || (2 + 3) = 2.5

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

v 2 v1 v2

2 1 [1]

2 5

v v v 4

0 2 1 v2 2 [2]

5 3

Solving, v1 = 54/31 V and v2 = 34/31 V. Thus, VTH = vX = v1 v2 = 645.2 mV

(c) 363.7 mA

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

34. (a) Define three clockwise mesh currents i1, i2, i3, respectively, starting on the left, in

addition to isc which flows through the shorted leads once RL is removed.

2.5 1000i3 1000i2 0 [2]

RTH

(b) iRL isc 34.63 mA

RL RTH

(c)

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

35. (a) We select the bottom node as the reference node. The top left node is then 2 V by

inspection; the next node is named v1, the next v2, and the far right node is voc.

v 2 v1 v1 v2

0 1 [1]

10 7 20

v v v

0 2 1 2 [2]

20 7

Solving,

v2 voc 185.3 mV

Next, we short the output terminals and compute the short circuit current. Naming the

three clockwise mesh currents i1, i2 and isc, respectively, beginning at the left,

2 17i1 7i2 0 [1]

7i1 34i2 7isc 0 [2]

7i2 37isc 0 [3]

Solving, isc = -5.2295 mA.

Hence

v

RTH oc = 35.43

isc

(b) Connecting a 1 A source to the dead network, we can simplify by inspection, but

performing nodal analysis anyway:

v v v v

0 1 1 1 2 [1]

10 7 20

v v v v v

0 2 1 2 2 test [2]

20 7 30

v v

1 test 2 [3]

30

Solving, vtest = 35.43 V hence RTH = 35.43/1 = 35.43

(c) Connecting a 1 A source, we can write three mesh equations after defining clockwise

mesh currents:

0 17i1 7i2 [1]

0 7i1 34i2 7i 3 [2]

1 7i2 37i3 [3]

Solving,

i3 = 28.23 mA. Thus, RTH = 1/(i3) = 35.42

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

36. (a) We can ignore the 3 resistor to determine voc. Then, i4 = (1)(2)/(2 + 5) = 2/7 A.

Hence, voc = 4i4 = 1.143 V

isc: A source transformation is helpful here, yielding 2 V in series with 2 . Then noting

that 3 || 4 = 1.714 , V3 = 2(1.714)/(3 + 1.714) = 0.7272 V

Hence,

isc = v3/3 = 242.4 mA

(b) Connect the 1 A source as instructed to the dead network, and define vx across the

source. Then vx = (1)(3 + 4 ||3) = 4.714 V.

Hence,

RTH = 4.714

(c) Connect the 1 V source to the dead network as instructed, and define ix flowing out of

the source. Then, ix = [3 + 3 ||4]-1 = 1/4.714 A.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

37. (a) With the terminals open-circuited, we select the bottom node as our reference and

assign nodal voltages v1, v2, and v3 to the top nodes, respectively beginning at the left.

Then,

v v v

222 1 1 2 [1]

6 17

By inspection, v2 = 20 V [2]

v v v v

33 3 2 3 3 [3]

9 4 2

Solving,

voc = v3 = 35.74 V

Next, we short the output terminals and compute isc, the downward flowing current:

KCL requires that isc = 20/9 33 = 30.78 A

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

(d) Note that the magnitude of RTH is the same as that of the voltage across the 1 A

source.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

39. We connect a 1 A source across the open terminals of the dead network, and compute the

voltage vx which develops across the source.

Hence,

RTH = vx/1 = 100.5 m

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

40. We short the terminals of the network and compute the short circuit current. To do this,

define two clockwise mesh currents (the 1500 resistor is shorted out).

500ix 2ix 2500i2 0 [1]

i2 ix 0.7 [2]

Solving, i2 = isc = iN = 116.3 mA

Next, we zero out the independent source and connect a 1 A test source across the

terminals a and b. Define vx across the current source with the + reference at the arrow

head of the current source. Then,

v v

1 x 1 [1]

1500 3000

v1 vx 2ix [2]

v1

ix [3]

3000

Solving, vx = 998.8 V, so RTH = vx/1 = 999.8

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

41. We define nodal voltage v1 at the top left node, and nodal voltage v2 at the top right node.

The bottom node is our reference node. By nodal analysis,

v1 v2

0.02v1 [1]

10 10 20 103

3

and v2 v1 = 1 [2]

Solving,

v1 = 2.481 mV = voc = vTH

Next, short the 1 V independent source and connect a 1 A source across the open

terminals. Define vtest across the source with the + reference at the arrow head of the

source.

Then

v1 v1

1 0.02v1 [1]

10 10 20 103

3

v1 vtest 49.63 V

Hence,

RTH = vtest/1 = 49.63

2

2.481103

PRL RL . Plugging in resistor values,

RL 49.63

(a) 5.587 nW

(b) 1.282 nW

(c) 578.5 pW

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

42. Connect a 1 A source across the open terminals with the arrow pointing into terminal a.

Next define vab with the + reference at terminal a and the - reference at terminal b.

Define three clockwise mesh currents i1, i2, and i3, respectively, beginning with the

leftmost mesh.

By inspection, i3 = 1 A [1]

Also by inspection, i1 = 0.11vab [2]

Then,

11i1 32i2 0.5vab 15i2 15i3 0 [3]

and

vab 15(i2 i3 ) [4]

Solving, i2 = -0.1197 A

Hence, vab = 13.20 V and RTH = vab/1 = 13.20

Since there is no independent source in the network, this represents both the Thvenin

and Norton equivalent.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

43. Connect a 1 A source to the open terminals, and select the bottom node as the reference

terminal. Define v1 at the top of the 1 A source. Then

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

44. Disconnect the two elements left of the dashed line. Then apply a 1 A test source to the

open terminals and define vx across the 1 A source such that the + reference is at the

arrow head of the source. By nodal analysis,

vx v v

1 x 2 [1]

2 10 6

r

v2 vx v v

0.02v 2 2 [2] and

r 1000 2000

v vx v2 [3]

Solving,

2 106 43r 2000 vx 2 10 43r 2000

6

vx . Hence, RTH

43r 6.002 106 1 43r 6.002 106

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

v v v v v

0 d in d d out [1]

R1 Ri Rf

vout Avd vout vd

0 [2]

Ro Rf

Solving,

vout

R o AR f Ri

vin

R1R f R1Ri R1Ro R f Ri Ri Ro AR1Ri

We now find RTH by injecting 1 A of current into the dead network and determining the

voltage which develops:

v v v v

0 d d out d [1] and

R1 Rf Ri

vout vd vout Avd

1 [2]

Rf Ro

vout Ro ( Ri R f R1R f R1Ri )

Solving, RTH vout

1 Ri Ro R1Ro Ri R f R1R f R1Ri AR1Ri

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

2

2

12 144 R 144 R 1

46. (a) PR R

Rs R Rs R 1000 1000 1 R

2

1000

0.04

0.035

0.03

0.025

P (W)

0.02

0.015

0.01

0.005

0

0 500 1000 1500 2000 2500 3000

R (ohms)

2

R R R R

2

1 2 2 1

dPR 144 Rs Rs Rs Rs

(b)

R Rs R

4

d

1

s

R

Rs

We see from the graph that maximum power is transferred when R = 1000 = Rs.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

48. (a) A quick source transformation and we have all voltage sources. Then, remove R out

and short the open terminals. Mesh analysis yields

2000i1 2000i2 2 3 0 [2]

Solving,

iN = i2 = 500 A

Next, zero out all sources, remove Rout, and look into the open terminals.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

49. Yes, it would theoretically result in maximum power transfer. Since were charged for

the energy we use (power multiplied by time), this would cost the consumer a fortune. In

reality, we dont want all the power the utility can provide only the amount we need!

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

50. We need only RTH. Setting all sources to zero, removing R L, and looking into the

terminals,

RTH = 5 || 2 || 3 = 967.7 m

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

51. We first perform two source transformations such that a voltage source with value 9R s

appears in series with a 6 V source, Rs and a 3 resistor.

2

9 Rs 6

(a) P9 9 = 81 W

3 Rs 9

(b) If 3 + Rs = 9 , maximum power is delivered.

Hence,

Rs = 6 and P9 = 361 W

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

0.1v2 2i 5 7i 3.3i 0 where v2 3.3i

Hence,

0.1(3.3i) 12.3i 5

Solving,

i = 417.7 mA and so v2 = 1.378 V = vTH

v 0.1v2

1 2 . Solving, v2 = 10 V.

9

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

53. We connect a 1 A source across the open terminals and define vtest across the source such

that its + reference corresponds to the head of the current source arrow. Then, after

defining nodal voltages v1 and v2 at the top left and top right nodes, respectively,

v1 v1

1 and so v1 = 3.077 V

5 8

v2

1 0.2v1 so v2 = -3.846 V

10

ensure maximum power transfer.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

54. We zero out the current source and connect 1 A to terminals a and b. Define clockwise

mesh currents i1, i2, i3 and i4 left to right, respectively.

By inspection i4 = 1 A

Then

100i1 50i2 50i3 0 [1]

50i2 80i3 10(1) 0 [2]

and i2 i1 0.1vab [3]

and vab 10(i3 1) [4]

Select 17.78 then to obtain maximum power transfer.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

55. We note that the equations which describe the two equivalent circuits are already

developed and provided as Eqs. 23-24 and Eqs. 25-26, respectively. Equating terms most

directly results in the equations for R1, R2 and R3.

The next step is to divide those equations to find the following ratios:

R1 RA R1 RB R R

; and 2 B .

R2 RC R3 RC R3 RA

These three equations yield two equations for RA, two for RB and two for RC, which

may be equated (respectively) to obtain:

R3 R

RB 1 RC 0

R2 R2

R2 R

RA 1 RC 0

R3 R3

R2 R

RA 3 RB 0

R1 R1

R1R2 R2 R3 R3 R1 R R R2 R3 R3 R1 R R R2 R3 R3 R1

RA , RB 1 2 , RC 1 2

R2 R3 R1

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

Then,

R1 = (33)(17)/ = 7.901

R2 = (17)(21)/ = 5.028

R3 = (21)(33)/ = 9.761

Then,

R1 = (1.1)(4.7)/7.9 = 654.4

R2 = (4.7)(2.1)/7.9 = 1.249 k

R3 = (21.)(1.1)/7.9 = 292.4

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

=2+3+R=5+R

R1 = 2R/ = 2R/(5 + R)

R2 = 3R/ = 3R/(5 + R)

R3 = (3)(2)/ = 6/(5 + R)

We now have 30 in series with R1, 10 in series with R2. Those branches are in

parallel. The total is in series with R3.

The new network then is equivalent to

2R 3R 6

(30 + R1) || (10 + R2) + R3 = 30 || 10

5 R 5 R 5 R

2

6R

300(5 R ) 110R

= 5 R 6 9

40(5 R) 5R 5 R

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

59. RA = 42 ; RB = 200 ; RC = 68 .

Then R1 = 27.10 , R2 = 43.87 , and R3 = 9.213

Solving, R = 74.86

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

60. Define Rx = R || RB

RA = RB = RC = 3R2/R = 3R

R22 = (0.75R)(3R)/(3R + 0.75R + 3R) = R/3

R33 = (3R)(3R)/(3R + 0.75R + 3R) = 4R/3

RBB = (R2 + 4R2/3 + 4R2/3) = 11R/4

RCC = (R2 + 4R2/3 + 4R2/3)/R = 11R/3

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

Identify the 11, 23 and 31 as R1, R2, R3 and convert to a network with

RA1 = 56.83

RB1 = 42.16

RC1 = 118.82

Identify the 55, 46, and 61 as R1, R2, R3 and convert to a network with

RA2 = 188.93

RB2 = 142.48

RC2 = 158.02

RB1 || RB2 = 32.53

25 || RA2 = 22.08

We are now left with a network identical to that in FIg. 5.46, in parallel with the 63

resistor. Converting the upper network to a Y network and simplifying, we obtain

RTH = 25.68

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

RB = /R3 = 21.5

RC =/R1 = 14.3

Then R11 = 2.116, R22 = 2.461 and R33 = 0.0377. This last resistance appears in

series with 10 .

Ra = /2.461 = 21.29

Rb = /10.31 = 5.082

Rc = /2.116 = 24.76

By inspection,

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

RTh = 6.098 W

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

IN = Voc/RTh = 5.333/8 = 666.7 mA

and the Norton equivalent is 666.7 mA in parallel with 8

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

65. (a) Although this network may be simplified, it is not possible to replace it with a

three-resistor equivalent.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

66. The wording points to the need for a Thvenin (Norton) equivalent. Simplifying using -

conversion, note 1 k || 7 k = 875 ; 10 k || 2.2 k = 1.803 k

R1 = (10)(4)/19 = 2.105 k

R2 = (4)(5)/19 = 1.053 k

R3 = (5)(10)/19 = 2.632 k

2

VTh 1

Then, Pabs =

RTh R R

(a) 175 nW

(b) 1.67 nW

(c) 24.38 pW

(d) 2.02 aW

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

67. (a) Change the 25 V source to 10 V, then the two legs are identical.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

68. As constructed, we may find the power delivered to the 2.57 resistor by first

employing mesh analysis. Define clockwise mesh currents i1 on the left and i2 on the

right, respectively.

-10 + 13.57i2 15i1 = 0

Superposition may not be applied to power in the general case, but we can argue that if

each source provides the same current to the load, each contributes equally to the power

delivered to the load. Noting that 15 || 2.57 = 2.194 ,

2.194

V 15 2.194 4.077

I"25V "

2.57 2

Similarly,

2.194

V 15 2.194 4.077

I"10V "

2.57 2

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

Power to load is three times too large, so the voltage is 3 times too large, so reduce all

1

sources by :

3

0.8 A becomes 461.9 mA

0.1 A becomes 57.74 mA

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

70. We first simplify the circuit and obtain its Thvenin equivalent.

Choose the bottom node as the reference. Designate the top left nodal voltage V 1 and the

top right nodal voltage V2. Then

V1 V1 V2

0.4 0

8.4 1.8

V2 V2 V1

0.1 0

5 1.8

To precisely mimic the behavior of the circuit at the open terminals, the battery should

have an open circuit voltage of 769.7 mV, and an intenral series reistance of 3.355 .

There is no way to specify tolerance without knowing the details of the actual load.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

71. To solve this problem, we need to assume that 45 W is a designation that applies when 120

Vac is applied directly to a particular lamp. This corresponds to a current draw of 375 mA, or a

light bulb resistance of 120/ 0.375 = 320 .

In the original wiring scheme, Lamps 1 & 2 draw (40)2 / 320 = 5 W of power each, and Lamp 3

draws (80)2 / 320 = 20 W of power. Therefore, none of the lamps is running at its maximum

rating of 45 W. We require a circuit which will deliver the same intensity after the lamps are

reconnected in a configuration. Thus, we need a total of 30 W from the new network of

lamps.

There are several ways to accomplish this, but the simplest may be to just use one 120-

Vac source connected to the left port in series with a resistor whose value is chosen to obtain 30

W delivered to the three lamps.

In other words,

2 2

213.3 213.3

120 Rs 213.3 60 Rs 213.3

2 30

320 320

Solving, we find that we require Rs = 106.65 , as confirmed by the PSpice simulation below,

which shows that both wiring configurations lead to one lamp with 80-V across it, and two

lamps with 40 V across each.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

72. (a) Source transformation can be used to simplify either nodal or mesh analysis by

having all sources of one type. Otherwise, repeated source transformations can in

many instances be used to reduce the total number of components, provided none

of the elements involved are of interest.

interest, since that information will be lost.

(d) This is the same as replacing the source with a short circuit, so theoretically

any current value is possible.

(e) This is the same as replacing the sources with an open circuit, so theoretically

any voltage is possible.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

73. (a) Define a nodal voltage V1 at the top of the current source IS, and a nodal voltage

V2 at the top of the load resistor RL. Since the load resistor can safely dissipate 1 W, and we

know that

V22

PRL =

1000

then V2 max

31.62 V . This corresponds to a load resistor (and hence lamp) current of

32.62 mA, so we may treat the lamp as a 10.6- resistor.

Vx = V1 5 Vx or Vx = V1/ 6 [3]

Substituting Eq. [3] into Eqs. [1] and [2], we find that

7 V1 = 1200 IS [1]

-5000 V1 + 6063.6 V2 = 0 [2]

Substituting V2 max

31.62 V into Eq. [2] then yields V1 = 38.35 V, so that

The lamp current does not exceed 36 mA in the range of operation allowed (i.e. a load

power of < 1 W.) The simulation result shows that the load will dissipate slightly more than 1 W

for a source current magnitude of 224 mA, as predicted by hand analysis.

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

Imax = 35 mA

Rmin = 47

Rmax = 117

With only 9 V batteries and standard resistance values available, we begin by neglecting

the series resistance of the battery.

For safety, we design assuming the minimum LED resistance and so must selct

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Engineering Circuit Analysis 8th Edition Chapter Five Exercise Solutions

75. We note that the buzzer draws 15 mA at 6 V, so that it may be modeled as a 400-

resistor. One possible solution of many, then, is:

Note: construct the 18-V source from 12 1.5-V batteries in series, and the two 400-

resistors can be fabricated by soldering 400 1- resistors in series, although theres

probably a much better alternative

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

P100 = (vout)2/100

(a) 0.5 2 0.04

(b) 22 88 77.44

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) vout = 10sin 10 t V

10

2

va (V)

-2

-4

-6

-8

-10

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

t (s)

30

20

10

va (V)

-10

-20

-30

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

t (s)

140

120

100

va (V)

80

60

40

20

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

t (s)

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(c) R1 = 1000 is okay, but R2 = 0 leads to shorting of voltage source. Thus, vout = 0.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

5. <Design> We note a typographical error in the first printing; the desired output is actually

4cos 5t V.

(a) Need gain of 4/9. This is not possible in a noninverting configuration so we choose

an inverting amplifier with Rf/R1 = 4/9. Selecting Rf = 4 k yields R1 = 9 k.

(b) We have a source 9 cos 5t V with its positive terminal grounded and its negative

terminal connected to R1. Then vout = (-4/9)(-9 cos 5t) = 4 cos 5t V.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Rf/R1 = 5/9. For standard 10% resistor values, selecting Rf = 10 leads to R1 = 18 .

Next, connect the negative terminal of a 9 V source to R1, and ground the positive

terminal of the source.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) R2 = 23.12

(b) R2 = 5.241

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) 1 V

(b) 17.0 V

(c) Regardless of component values chosen above, the circuit is electrically equivalent to

the inverting amplifer circuit depicted in Fig. 6.3.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

10. <Design> One posible solution: Define v1, v2, v3 as being with respect to ground (i.e. think

of them as nodal voltages, with ground as the reference).

(a) Implement the following, with all resistors as 1 . Define i as upwards through RL.

i = -vout/RL = v1 + v2 + v3

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) Implement the circuit below, with all resistors equal to 1.5 k.

Thats done by using two of the 1.5 k resistors, three 50 resistors in series, and 4

6 k resistors in parallel.

(b) This is a classic difference amplifier with vout = v2 v1, since all resistor values are

equal.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

12. The two 850 resistors may be combined to 1700 . Peform a source transformation on

the current source so that a 10 V source is in series with 10 k, connected to the non-

inverting input.

No current flows through the 1 M so it is neglected.

Solving, V1 = 27.0 V

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

v v v vout

0

R1 Rf

R3

v v2 since v v

R2 R3

R3 R3

v2 v1 v2 vout

R2 R3 R2 R3

0

R1 Rf

Solving for vout leads to:

Rf R3 Rf

vout 1 v2 v1

R1 R2 R3 R1

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

14. (a) No current can flow into either input pin of an ideal op amp.

(b) There can be no voltage difference between the input pins of an ideal op amp.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Rf 500

Ry I s 1

3

vout 1 4.7 10 2 10 14 V

3

Rx 1000

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Rf

vout 1 Ry I s

Rx

Rf

2 1

500 10 10

3

250

Solving,

Rf = 350

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

3

vout 103 v 1000 3v

1

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

18. The first stage is an invertign amplifer which puts (2)(-5/10) = -1 V across the 10

resistor.

The second stage is also an inverting amplifer which multiples the voltage across the 10

resistor by -2000/Rx.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

19. Left stage is an inverting amplifer with gain -5/10 hence (-5/10)(2) = -1 V appears across

the 10 resistor.

The right hand stage is also an inverting amplifer, now with gain -2000/Rx (Rx in

ohms).

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

20. The left-hand stage provides (1 + 15/10)vin = 2.5vin to the second stage.

(a)

15

10

5

vout (V)

-5

-10

-15

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

vin (V)

(b)

-0.5

-1

-1.5

vout (V)

-2

-2.5

-3

-3.5

-4

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

R4 (ohms)

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(vleft = output of left-hand stage).

Hence, vout =

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Thus,

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

23. The last stage is merely a buffer and has no effect on the output.

The remainder is a summing amplifier with (defining R f = 200 k),

0 v1 0 v2 0 v3 0 vout

0

R1 R2 R3 Rf

v v v v v v

Solving, vout R f 1 2 3 200 103 1 2 3

R1 R2 R3 R1 R2 R3

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Max summed voltage = 15 V

Adjust to obtain 2 V output when all three inputs are 3 V.

We take a summing amplifier with all resistor values set to 1 . This output is fed

into an inverting amplifer with R1 = 15 and feedback resistor Rf = 2

When v1 = v2 = v3 = 5 V, vout = (-2/15)[-(5 + 5 + 5)] = 2 V (Ok)

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) We start with a difference amplifer as shown in Table 6.1 with all resistors set to 1

k, but with v2 designated as the input voltage to the inverting input and v1 to the

noninverting input. The output of this stage is taken to the input of an inverting

amplifer with R1 = 1 k and Rf = 10 k

For v1 = v2, vout = 0; for v1 v2 = 1 the output is 10 V.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Sensor: 10 V = 1 kg therefore 400,000 kg on one sensor yields 4 V

We take a general summing amplifier with all resistors set to 1 k. The output of this

stage is taken as the input voltage to an inverting amplifier with R 1 = 4 k and Rf = 10

k.

(b) The first stage sums the three sensor voltages v1, v2 and v3 to obtain (v1 + v2 + v3)

at the input to the second stage. The second stage multiplies this voltage by -2.5.

If v1 + v2 + v3 = 4 V (400,000 kg total), vout = -2.5(-4) = 10 V.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) Designate the tank sensor output voltages as v1, v2, v3, v4. Each has a maximum

value of 5 V. We desire 3 V when their sum is 20 V, and 1.5 V when their sum is

zero.

(b) The first stage sums the sensor voltages and attenuates the result such that -1.5 V is

obtained at the stage output when each sensor voltage is 5 V. The second stage adds

the necessary dc offset and inverts the sign of the output voltage. Thus, when all input

voltages are equal to zero, vout = (-1)(0 1.5) = 1.5 V.

When all voltages are 5 V, vout = (-1)[-(75)(5 + 5 + 5 + 5)/1000 1.5) = 3 V

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

28. The left-hand stage is an inverting amplifer with output voltage vout = -(R2/R1)vin.

irrelevant as long as it is greater than zero.

The last stage is a voltage follower and so does not affect the output.

Thus, 4 = -(200/50)(-R2/R1)(8)

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

29. The left-hand stage is a general difference amplifer. The right-hand stage is a simple

inverting amplifer which multiplies the output of the differnce amplifer by (1 + R 6/R4).

Analyzing the left-hand stage then:

R3

v v vin

R2 R3

So 0

R4 R1

1 1 R3 1

vout ( R4 R6 ) vin

R4 R1 R2 R3 R1

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

We use a circuit such as the one in Fig. 6.19a, but with two 9 V batteries in series for a

total of 18 V.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Finally,

R f RL

(5.1) 1 4

R1 RL Rx

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) No diode is specified so we opt for the circuit of Fig. 6.20 and employ a 1N750,

which has a Zener voltage of 4.7 V. We base our design on the simulation result of

Fig. 6.19c, which shows a voltage of 4.733 V achieved at a current of 37.1 mA (R ref =

115 and 9 V source). Thus we need 1 + Rf/R1 = 5/4.8. For simplicity we select Rf

= 1 k so that R1 = 15.67 k.

(b) With an infinite load we are accurate to better than 1% of the target value (5 V).

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

33. (a) A 1N750 Zener diode can be used to obtain a reference voltage of 4.7 V but the non-

inverting circuit of Fig. 6.20 cannot achieve a gain of less than unity. So, instead, employ

two cascaded inverting amplifiers, one to invert the sign of the voltage and one to reduce

the voltage from 4.7 V to 2.2 V. The circuit then is

Rf3 = (2.2/4.7)R1 = 468

(b) The evaluation version of PSpice will not allow the full circuit to be simulated, so we

omit the middle stage (used only to invert the sign) and simulate the rest, confirming

better than 1% accuracy with respect to our target value of 2.2 V.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

34. The output voltage of the circuit in Fig. 6.53 should be labelled V 1.

(a) Zener voltage is 4.7 V. For 9 V supply, the current through the 400 resistor is

(9 4.7)/400 = 10.75 mA

From Fig. 6.19b this current is reasonable for th diode to be in breakdwon. Since this

is a non-inverting amplifer, V1 = (1100/890 + 1)(4.7) = 10.5 V

(b) From Fig. 6.18b, 12 V results in breakdown but the current will be (12 4.7)/400 =

18.3 mA, which is still less than the maximum rated diode current; we expect

V1 = 10.5 V also.

precisely 10.50 V was obtained for a 12 V battery voltage. In comparing the voltages

at the input, we see the difference originates from a value closer to the design value

(4.7 V) across the Zener diode.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) We use a circuit such as that shown in Fig. 6.22, with a 9 V battery and 1N750 Zener

diode. We increase the 100 to 115 . Name the 4.9 k resistor R1.

and the current through RL is (4.73RL/R1)/RL = 4.73/R1

(b) Here we simulate the performance for RL = 1 k and RL = 50 k, and note a more

elegant solution is possible using PARAM. For 1 k, we find the circuit performs as

desired, but at the other extreme (50 k), the circuit fails as it enters saturation. The

maximum resistance for 18 V supplies, a typical upper limit for the A741, is then 17.6

k.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

(a) We use a circuit such as the one in Fig. 6.22. A 9 V battery is employed, but with a

1N4733 diode (5.1 V at 76 mA) is used. Rename the 4.9 k resistor R1.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

37. (a) We design a circuit based on that shown in Fig. 6.22 but using the specified diode

instead. With a battery voltage of 24 V, assuming 20 V across the Zener diode and a

diode current of 50% its maximum (12.5 mA), we compute

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

38. Define nodeal voltages v- and v+ at the op amp input terminals. Then

v v2 v vout

0

R1 R2

v v1 v v vout

0

R3 RL R4

With an ideal op amp, v- = v+.

Solving, vout

R1R4 RL R2 R4 RL v1 (R2 R3 R4 R2 R3 RL R2 R4 RL )v2

R1R3 R4 R1R4 RL R2 R3 RL

v R1R4v1 R2 R3v2

And I L

RL R1R3 R4 R1R4 RL R2 R3 RL

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

39. Define two nodal voltages vm and vp at the inverting and non-inverting input terminals,

respectively. For an ideal op amp, vm = vp. Then,

vp v p vout

0 [1]

1000500

v p v1

v p v p vout

0 [2]

1000 100 500

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

0 [1]

250 1400 2 106

vout vd 0.45 vout 2 105 vd

0 [2]

1400 75

Thus, the ideal model is accurate to better than 0.1%.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

41. (a) Employing nodal analysis and defining nodal voltages v- and v+ at the input,

v 2 v vout v v

0 [1]

1500 1500 2 106

v 5 v v v

0 6 [2]

1500 1500 2 10

vout v vout 2 105 vd vout

0 [3] and

1500 75 RL

vd v v [4]

Solving,

1.067 104 RL

vout

3.556 103 RL 2.669

We note that for any appreciable value of RL, the exact model reduces to

(1.067104)/(3.56103) = 3.0006 V

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

42. (a) CMRR is the ratio of differential mode gain to common mode gain. If the same signal

is applied to both input terminals, ideally no output is generated. In reality, any

common component of the input voltages will be amplified slightly.

(b) Slew rate is the rate at which the output voltage can respond to changes in the input

voltage. This real limitation leads to distortion of the waveform above some

frequency.

(c) Saturation refers to the inability of an op amp circuit to generate an ouptutp voltage

larger than the supply voltage(s). If the input is too large, further increases do not lead

to correspondingly larger output.

(d) Feedback refers to routing some portion of the output to the input. Negative fedback

helps stabilize a circuit. Positive feedback can lead to oscillation.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

43. (a) Using the ideal op amp model, we end up with an ideal voltage follower so the output

is vout = 2 V.

(b) Using parameters for a 741 op amp in conjunction with nodal analysis,

0 [1]

4700 2 106 75

2 vd vout 0 [2]

(d) All three agree to at least four decimal places, so the ideal model is adequate in this

instance.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

44. We identify the non-grounded side of the 250 with the nodal voltage vm., and assume

zero output resistance and infinite input resistance.

v 1400

For an ideal op amp, out 1 6.60

0.45 250

0

250 1400

14.85 A

which can be solved to obtain Avd .

5 A 33

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

45. (a) The LF411 has a much higher slew rate (15 V/s) than the A741 (0.5 V/s). Both are

adequate at low frequencies but in the kHz range the LF411 will show better performance.

(b) Both op amps due well in this circuit up to 300 kHz, but the LF411 is performing well

even at 1 MHz, although not perfectly at that frequency.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

We therefore expect an output of (1.1)(2) = 2.2 V

The output voltage cannot exceed the supply voltage, or 9 V in this case.

Thus, (1 + Rf/4700)(2.2) = 9

(b) Summary, using LF411: For Rf = 14.5 k, ideal model predicts 8.17 V, PSpice

yields 8.099 V, so were just barely in saturation with this value of resistance.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

v 0.45 vd 0.45 vout vd

0 d [1]

250 1400 Rin

vout vd 0.45 vout Avd

0 [2]

1400 Ro

Solving,

(d) OPA690 (note assuming Ro = 0): vd = 707 V; input bias current = 3.72 nA

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

A

48. CMRRdb = 20 log dB

ACM

where A = differential mode gain and ACM = common mode gain.

A

Solving, ACM CMRRdB

20

10

A741 2105 90 6.3

LM324 105 85 5.6

LF411 2105 100 2.0

AD549K 106 100 10.

OPA690 2800 65 1.6

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

1 V, no finger (R 10 M)

Desired: vout

1 V, finger present (R < 10 M)

finger present, a voltage greater than 1 V appears at the inverting input, so that the output

voltage is -1 V. With the finger present, the voltage at the inverting input will drop below

50% of the driving voltage (2 V), so that +1 voltage will appear at the output.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

We build a two-stage circuit where a comparator has vin applied to its non-inverting

input, and a 1 V reference to the inverting input. The output of this stage is 0 V when vin

> 1 V and -1.3 V otherwise. This is summed with a -1.2 V reference source, the output of

which is inverted and so is either +2.5 V for vin > 1 V or +1.2 V otherwise.

vin

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

R4 1 R2 R1 R2

vout v v

R3 1 R4 R3 R1

The differential input is v v and hence the differential gain is

R4 1 R2 R1 R2

v v

R 1 R4 R3

Adm out 3

v R1

[1]

v v v v

For common mode components we must average the inputs, and hence the common-

mode gain is

R4 1 R2 R1 R2

v v

R 1 R4 R3

Acm 2 out 2 3

v R1

[2]

v v v v

Adm

CMRR is defined as the absolute value of their ratio: CMRR = .

Acm

R2 v v v v

Eq. [2] above reduces to Acm 2 . Thus, CMRR = .

R1 v v 2 v v

v v

(b) All resistors are different. Then the above reduces to CMRR =

2 v v

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

53. Since the reference voltage v1 is applied to the inverting terminal, we expect the output to

follow the negative supply voltage (0 V, here) until vactive > vref at which point it follows

the positive voltage supply.

18

16

14

12

10

vout (V)

0

-5 -4 -3 -2 -1 0 1 2 3 4 5

vactive (V)

18

16

14

12

10

vout (V)

0

-5 -4 -3 -2 -1 0 1 2 3 4 5

vactive (V)

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

54. We have a comparator circuit with zero reference tied to the inverting input, and matched

12 V supplies. The expected (ideal) output is therefore:

vout (V)

12

vactive (V)

12

Simulating using a A741 results in the following, which exhibits the expected shape

with only a slight reduction in maximum and minimum voltages:

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

This comparator circuit follows the negative supply voltage (0 V) until vin exceeds 1.5 V,

at which point 5 V appears at the output.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

56. <Design>

We note that the short circuit should not appear across the + and terminals of vout as it

appears in the first printing.

(a) We designate the bottom node as the reference node, then name the top node V in, the

node at the + terminal of Vout as VA, and the remaining node VB.

R2 R3

By voltage division, VA Vref and VB Vref . Thus,

R1 R2 R3 RGauge

R2 R3

Vout VA VB Vin .

R1 R2 R3 RGauge

R R

Vout Vin G G 0

2 RG RG

Connect -12 V to pin 4; connect +12 V to pin 7. Ground pin 2.

Employ a bridge circuit such as the one shown in Fig. 6.60(a) with the strain gauge in

place of RGauge and all other resistors precisely 5000 . Connect four 12 V supplies in

series to botain Vin = 48 V. Then Vout = Vin(2.510-6) = 1.210-4 V. A 1 V signal

requires a gain of 1/1.210-4 = 8333.

This value is in excess of our maximum gain of 1000 so connect a resistor having

50.5 103

value 50.55 across pins 1 and 8. This provides a gain of 1000.

1000 1

The voltage Vout is connected across pins 3 and 2 with the + reference at pin 3. We

still require a gain of 8.333 so connect the pin 6 output to the non-inverting terminal

of a non-inverting amplifer powered by 12 V supplies. Then, set R 1 = 1 k and Rf =

7.333 k. This completes the design.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

We thus need a circuit with minimum gain 5/0.25 = 20

Select a non-inverting amplifer circuit. Connect the microphone to the non-inverting

input terminal, select R1 = 1 k and so Rf = 19 k.

(b) Although general speaking may not correspond to peak microphone voltage, we are

not provided sufficient information to address this, and not that he gain may need

adjusting in the final circuit.

Thus, we should connect the feedback resistor Rf in series with a variable 20 k

resistor, initially set to 0 . This will allow us to vary the actual gain between 1 +

Rf/R1 = 1 + 19/1 = 20 and 1 + 39/1 = 40.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

We employ a summing amplifer such as that shown in Table 6.1, but with 5 inputs. We

model each microphone as an ideal voltage source and connect a reistor R 1, R2 etc with

each.

We set R1 = R2 = R3 = R4 = 1 k and Rf = 10 k

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

Deliver 1.5 V to RL

Arbitrarily, select Vs = 1 V.

Assume the resistance scales linearly with light intensity, so

100 103 10 103

R f 2 candela (2) 100 10 70 k

3

0 6

With Rf = 70 k and vout = (1 + Rf/R1)Vs = 1.5, R1 = 2Rf = 140 k

Check:

0 candela leads to Rf = 100 k, so vout = (1 + 100/140)(1) = 1.7 V and it will not

activate.

6 candela leads to Rf = 10 k so vout = (1 + 10/140)(1) = 1.07 V and it will

activate.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

When the wind velocity exceeds 50 km/h, the fountain height must be 2 m.

We assume the valve position tracks the applied voltage linearly (e.g. 2.5 V corresponds

to 50% open). We also assume the flow rate scales linearly with the valve position.

greater than 50 km/h, the comparator stage outputs 0 V. This is summed with 3 V, the

sign of which is inverted by the second stage to yield 3 V, or 2 m height. When the sensor

voltage drops below 2 V, the comparator stage output is 2 V. This is summed with 3 V

and the sign inverted, or 5 V output, corresponding to the valve fully open, which is

presumably 100 l/s flow rate.

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Engineering Circuit Analysis 8th Edition Chapter Six Exercise Solutions

v v v v

0 m 1 m out [1]

R R

R v2

vm v2 [2]

2R 2

Consequently,

0.5v2 v1 0.5v2 vout

0 and vout = v2 v1. Thus, the resistor value is unimportant.

R R

(a) (b)

8 1

0.8

6

0.6

4

0.4

2

0.2

vout (V)

vout (V)

0

0

-2

-0.2

-4 -0.4

-6 -0.6

-8 -0.8

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

t (s)

t (s)

(c)

-1

-1.1

-1.2

-1.3

-1.4

vout (V)

-1.5

-1.6

-1.7

-1.8

-1.9

-2

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

t (s)

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dv

1. Assuming the passive sign convention, i = C .

dt

(a) i = 0 (dc)

(b) i = (220)(9)(16.2)e 9t = 32.08e9t A

(c) i = (220 10 9 )(8 10 3 )(0.01) sin 0.01t = 17.6sin 0.01t pA

(d) i = (220 109 )(9)(0.08) cos 0.08t = 158.4 cos 0.08t nA

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dv

iC = C = 0A for t 0

dt

ic(A)

1.5

5

t (s)

1.5

(b) vc = 4 cos t

dvc

ic = C = (13 1012 ) ( 4 sin t ) = 0.1633sin t nA for t 0s

dt

ic (nA)

0.1633

t(s)

1 3 5

-0.1633

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

For t > 4 s, v = 1 V therefore iC = 0

1

For all other times, v = t + 3

2

(a) C = 1 F, assume passive sign convention.

dv 1

iC = C = (106 ) = 0.5 106 A for 0 t 4 s

dt 2

ic (A)

0.5

4

t (s)

0.5

1

(b) iC = (17.5 1012 ) = 8.75 pA for 0 t 4 s

2

ic (pA)

4

t (s)

8.75

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

4. (a) = 1.35 0

A 1.35 8.854 1012 2.5 106

C = = = 29.88 pF

d 106

(b) = 3.5 0

C = = = 77.47 pF

d 10 6

(c) = 0 ; d = 3.5 m

C = = = 6.324 pF

d 3.5 106

(d) = 0 ; A = 2 A = 5 106 m 2 ; d = 1 m

A 8.854 10 12 5 106

C = = = 44.27 pF

d 1 10 6

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

A

A = (100 10 6 )(750 106 ) = 7.5 108 m 2 . C = .

d

(a) C = 91.64 pF

(b) C = 3.321 nF

(c) C = 3.32 pF

(d) C = 13.28 pF

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

We require a 100nF capacitor constructed from 1m thick gold foil that fits entirely

within the volume of a standard AAA battery with the available dielectric having

permittivity 3.10. A standard AAA battery has approximately a length of 4.45cm

and the circular diameter of 1.05cm.

d= = 9

A = 2.744 10 4 Am

C 100 10

If we select the area of the plates as 4 cm2, the gap spacing between the plates is d =

0.1097m.

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

0 A

We recall that for a parallel-plate (air separated) capacitor, C = d where e is the

relative permittivity of the spacer material, A = the plate area, d = the plate spacing, and

the remaining term is the free-space permittivity. We propose to vary the capacitance

value by sliding one conductor past the other.

We being with a flat piece of glass 1 m by 1 m and 2 mm thick (none of these dimensions

are critical). Coat the center of the glass with a 0.1 mm thick layer of gold (material and

thickness not critical) having dimensions 100 mm by 100 mm. Take a piece of plastic (e

= 3) 0.01 mm thick. Coat the top side with a 0.1 mm thick layer of gold measuring 336

mm by 336 mm. We expect the metal to stiffen the plastic sufficiently so sliding will

work. Place the plastic on the metal-coated glass slide, both metal layers facing upwards.

Make electrical contact off to the side and neglect its contribution to capacitance (assume

negligibly thin wire).

When the top metal layer is completely over the bottom metal layer, (the smaller area is

the A in our equation), we have C = (3)(8.854e-12)(336e-3)(336e-3)/(0.01e-3) = 300 nF

(to three significant figures). We then slide the top metal layer along glass until only one-

third its length overlaps the bottom metal layer. This reduces the effective area of the

capacitor by one-third, and hence the capacitance becomes 100 nF.

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

In the first printing, the capacitance range was stated as 50 nF to 100 nF, but this should

be changed to 50 pF to 100 pF to obtain more realistic areas.

We begin by noting that there is no requirement for linear correlation between knob

position and capacitance, although that might be desirable.

Take two discs of plastic, each approximately 3 mm thick (so that they are stiff) and

radius 85 mm. Coat one side of each disc with gold (thickness unimportant) but over only

half the area (i.e. from 0 to 180 degrees). Mount the discs with the metal layers facing

each other, separated by a 1 mm thick plastic spacer of very small diameter using a thin

nonconducting rod as an axis.

0 A

Then, with C = d where e is the relative permittivity of the spacer material, A = the

plate area, d = the plate spacing, when the two metal halves are aligned over one another

the capacitance is 100 pF. Rotating one disc by 90 degrees reduces the effective (overlap)

area by one-half, and hence the new capacitance is 50 pF.

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

9. C= , W in cm

W

1

(2)(11.8)(8.854 1014 ) 2

W = 19 ( 0.57 V A )

(1.602 10 )(10 )

18

VA W(cm) C

-1 V 4.52510-6 2.309 fF

-5 V 8.52410-6 1.226 fF

-10 V 1.17410-5 890 aF

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

(b) Graph

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

(c) Graph

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dv 1

11. C = 33 mF. i = C so v = idt .

dt C

(a) Graph

150

100

v (V)

50

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

t (s)

v(0.6 s) = 72.72 V

v(1.1 s) = 72.72 + 48.48 = 121.2 V

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1

(a) Wc = Cvc 2 = 0.5 1.4 ( 8 ) = 44.8 J

2

12.

2

1

(b) Wc = Cvc 2 = 0.5 23.5 1012 ( 0.8 ) = 7.52 pJ

2

2

1

(c) Wc = 295 109 + Cvc 2 = 295 109 + 0.5 17 109 (12 ) = 1.519 J

2

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

13. C = 137 pF

12 V, t < 0 1

. Energy = C [ vC ] .

2

vC (t ) = 2t

12e V, t 0 2

(a) t = 0: 9.864 nJ

(d) t = 1 s: 180.7 pJ

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

14. (a) After being connected to DC source for a very long time, the capacitor act as open

circuit.

Therefore, current through the circuit is,

V 1.2

i= = = 19.3548mA

R 40 + 22

P40 = i 2 R = (19.3548 103 ) 2 40 = 14.984mW

vC = 0.193548 22 = 0.4258V

PSpice Verification:

(b) After being connected to DC source for a very long time, the capacitor act as open

circuit.

Therefore, current through the circuit is,

i = 0A

P40 = 0W

vC = 1.2V

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

7

vC = (4.5 10 9 )(13) = 13.65 109 V so vC = 13.65 nV

13 + 10 + 7

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

l

N2A

L=

l

where = 4 10 7 H / m

N = Number of turns d

A = Area of cross-section = r 2 , m 2

l = Length of the wire, m

r = outside radius of the coil(form + wire), m

If we take a plastic form and wound 29 AWG copper wire (diameter = 0.286mm) round

it, we can construct a 30nH inductor. For that if we choose N = 22 turns, r = 60 mm, we

can find the length of the wire.

l= = = 57.87 m

L 30 109

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

17. L = 75 mH.

di

v=L .

dt

Voltage can change instantaneously but current cannot (or voltage becomes infinite).

(a) v (mV)

150

2 2.5

t (s)

-1

-150

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

2

iL = 106 tA for 0 t 5 s

5

iL = 2 A for 5 t s

diL 2

vL = L = 17 10 9 106 = 6.8 fV

dt 5

vL(fV)

0 5

t(s)

-6.8

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

di di

19. v=L = (4.2 10 3 )

dt dt

(a) v = 0

(d) -54.6e-t pV

= 4.2(1 14t )e14t mV

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

(b) iL = 800mA, vL = 0V

(c) iL = 8 A, vL = 0V

diL

(d) iL = 4e t A, vL = L = 8 10 12 4e t = 32e t pV

dt

= 8 1012 ( e t (1 t ) ) = 8e t (1 t ) pV

diL

(e) iL = 3 + te t A, vL = L

dt

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

(a) vL = 0; iL = is = 1 mA

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

diL

23. vL = L .

dt

Between -2 and 1 s, slope = (2 0)/(-2 0) = -1

Between 1 and 3 s, slope = -1/2

For t > 3 s, slope = -2/-3 = 2/3

(b) v(0) = (1)(-1) = -1 V

(c) v(1.5) = (1)(-1/2) = -0.5 V

(d) v(2.5) = (1)(-1/2) = -0.5 V

(e) v(4) = (1)(2/3) = 0.67 V

(f) v(5) = 0.67 V

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

t

1 5

24. (a) iL = 5dt + iL (0) = t = 833.33tA

L0 6 103

t

cos1200 t

t

1 100

(b) iL = 100sin1200 tdt =

L0 6 103 1200 = 22.619 (1 cos1200 t ) A

0

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

t

iL =

1

L 0.1

4.3t dt + iL(0.1) =

4

(

4.3 2

)

t 0.01 + 100 106

(a) -10.65 mA

(b) -10.65 mA

(c) -8.473 mA

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1 2

26. (a) E = LiL = 0 J

2

(b) E = LiL 2 = 0.5 110 9 (103 ) = 5 10 16 J

1 2

2

1

(c) E = LiL 2 = 0.5 1 109 ( 20 ) = 2 107 J

2

2

(d) E = LiL 2 = 0.5 1 109 ( 5sin 6t 103 ) = 1.25sin 2 6t 10 14 J

1 2

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

(a) 808.5 mJ

(b) 1.595 nJ

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

28. (a) After being connected to DC source for a very long time, the inductors act as short

circuits.

10

The total current in the given circuit then, i = 1

= 0.563mA

4.7 1

+ 7 + 16 10

1 3

2

1

4.7 1 1

+ 7 10

3

2

Therefore, current ix = 0.563 10 3 = 141.502 A

7 10 3

(b) After being connected to DC source for a very long time, the capacitor act as open

circuit and inductor act as short circuits.

(5 + 21 ) 103

1 1

5 103

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

29. (a) 5 + V / 27 + V / 30 + (V 1) / 20 = 0

Solving, V = 41.95 V

By voltage division, Vx = (12/27)(41.95) = 18.64 V

(b) 5 + V / 27 + V / 20 + (V 1) / 20 = 0

Solving, V = 36.85 V

By voltage division, Vx = (12/27)(36.85) = 16.38 V

(c) 5 + V / 27 + (V 1) / 20 = 0

V = 58.02 V

By voltage division, Vx = (12/27)(58.02) = 25.79 V

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

30. (a) Taking inductor as the load, the thevenin equivalent resistance is given by,

Req = (101 + 47 1 ) 103 = 8.245k

1

47 103

The thevenin voltage is given by, VT = 4 = 3.298V

( 47 + 10 ) 103

(b) After being connected to DC source for a very long time, the inductor acts as a short

circuit.

4

iL = = 400 A

10 103

P10 k = iL 2 R = ( 0.4 103 ) 104 = 1.6mW

2

P47 k = 0W

1 2 2

WL =

2

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1 1 1

31. Ceq1 = + + = 545.4 mF

1.5 2 1.5

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1 1 7

= + L+ = L

1 1 1 1 3

Lequiv

32.

+ +

2L L 2L L

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

Place five such strands in parallel.

(1/5 + 1/5 + 1/5 + 1/5 + 1/5)-1 = 1.25 H

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

34. Starting from the rightmost end, we have, a series combination of 2F, 12F and 2F, for

1 12

which the equivalent capacitance is, Ceq1 = = F

1 1 1 13

+ +

2 12 2

This is in parallel with the series combination of 8F and 5F. Therefore,

1 12 52

Ceq 2 = + = F

1 1 13 13

+

8 5

Now, this is in series with 4F and 1F which yields the new capacitance as,

1 2

Ceq 3 = = F

1 13 3

+1+

4 52 .

This combination is in parallel with 5F and the final equivalent capacitance is,

1

Ceq 2 = 1

= 3.1315 F

2 1

+ 5 + 7

3

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

5 + (1/12 + 1/1)-1 = 5.923 F

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

36. Towards the rightmost end (b terminal) of the given circuit, 12H is in series with 1H, the

combination is in parallel with 5H. Therefore, the equivalent inductance is given by,

1 65

Leq1 = = H

1 1 18

+

(12 + 1) 5

On the left side (a terminal) 12H is in parallel with 10H, and the combination is in series

with 7H and the whole combination is in parallel with 4H. Therefore, the equivalent

1 548

inductance on this side is given by, Leq 2 = 1

= H

181

1

1 1 + 7 + 4

1

+

12 10

The total equivalent inductance seen from the a b terminal then becomes,

65 548

Leq = Leq1 + Leq 2 = + = 6.638 H

18 181

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

38. (a) For each element as 10 resistor, the equivalent resistance is given as,

1

Req =

1 1

+

( R + R + R ) 1

( ) ( )

1 1

+ 1 + + 1 + 1 + 1

R R R R R R

= 1.1379 R = 11.379

(b) For each element as 10H inductor, the equivalent inductance is given as,

1

Leq =

1 1

+

(

( L + L + L ) 1 1

) ( )

1 1

L +L + L + L 1 + L 1 + L 1

= 1.1379 L = 11.379 H

(c) For each element as 10F capacitor, the equivalent capacitance is given as,

1 1

Ceq = 1 +

(

( C + C + C ) ( C + C ) 1 + C 1 + ( C + C + C ) 1

1 1

)

= 0.8787C = 8.7878 F

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

41.

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1 1

= 1+ + = 3H

1 1 1

Lequiv

42. (a) 1 1

+ + +

2 2 3 3 3

1 1 1 1

Lequiv = 1+ + = 1+ +

1 1 1 1 1

+ + + 1 1

2 3

2 2 3 3 3 2 3

For the general network of this type having N stages, we can write,

1 1 1

Lequiv = 1 + + + .... +

1 1 1 1 1 1 1

+ + + + ... +

2 2 3 3 3 N N

1 1 1

= 1+ + + .... + = N

1 1 1

2 3 N

2 3 N

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1

43. Far right: (2 pF ) 1 + (2 pF ) 1 = 1 pF

Which is in parlle with 2 pF, for a combined value of 3 pF.

1 6

Since (3 pF ) 1 + (2 pF ) 1 = pF and this is in parallel with 2 pF,

5

we obtain a total of 16/5 pF.

This equivalent value is in sries with 2 pF, hence the final value is 1.23 pF.

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

44. For the rightmost end, 1nH is in series with 1nH, the combination is in parallel with 1nH.

1 2

Leq1 = = nH

1

+1 3

2

This combination is in series with 1nH and the new combination is in parallel with 1nH.

1 5

Leq 2 = = nH

1

+1 8

2

+ 1

3

Now, this combination is in series with 1nH. Hence the net equivalent inductance is given

by,

5

Leq = + 1 = 1.625nH

8

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

d ( v1 v3 ) dv1 v1 v2

45. (a) 0 = C1 + C2 +

dt dt R

dv1 v1 v2 dv

or ( C1 + C2 ) + = C1 3 [1]

dt R R dt

v2 v2 v1 1

t

Next, is = + + ( v2 v5 ) dt iL (0 ) or

R R L t0

t t

v v 1 1

1 + 2 2 + v2 dt = iL (0 ) is + vs dt [2]

R R L t0 L t0

(b)

t t

1 1

vs + ( i1 iL ) dt + ( i i ) dt = 0

1 2

C1 t0 C2 t0

t

1

C2 (i

t0

2 i1 ) dt + R ( i2 iL ) + R ( i2 is ) = 0

t

diL 1

L + R ( i2 iL ) + ( iL i1 ) dt = 0

dt C1 t0

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

46. (a)

vC vS dv vC vL

5 10 6 C

=0

20 dt 10

vC vL 1 t

v dt ' 2 = 0

10 8 10 3 0 L

(b)

t

1

v S = 20i 20 +

5 106 0

(i 20

i L )dt '+ 12

t

1 diL

(i

5 10 6 0 20

i L )dt '+ 12 = 10i L + 8 10 3

dt

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

t t

1 1

(a) is = vdt + i1 (0) + vdt + iL (0)

60 40

dis 1 1

= v + v v (t ) = 5e 200 t V

dt 6 4

t

1

(b) i1 (t ) =

60 vdt + i1 (0) = 4.17e 200t + 20 mA

t

1

(c) i2 (t ) = vdt + i2 (0) = 6.25e200t + 40 mA

40

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

d 1

48. (a) i (t ) = C eq v S = (1 + 4 1 ) 10 6 ( 80) 100e 80t = 6.4e 80t mA

dt

t

1

C 0

(b) v1 (t ) = v1 (0) + i (t )dt '

t

1

= 20 + 6 (6.4 103 ) e80t dt ' = 80e 80t 60V

10 0

t

1

C 0

(c) v2 (t ) = v2 (0) + i (t )dt '

t

1

= 80 + (6.4 103 ) e 80t dt ' = 20e 80t + 60V

4 106 0

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

49. It is assumed that all the sources in the given circuit have been connected for a very long

time. We can replace the capacitor with an open circuit and the inductor with a short

circuit and apply principle of superposition.

By superposition, we get,

vC = 0.6 + 9 + 0 + 0 = 9.6V

vL = 0 = 0V

Pspice verification:

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

50. Let us assign the node voltages as V1, V2, V3 and V4 with the bottom node as the

reference.

Supernode:

v1 v2

t

1

(v v4 )dt ' =

3 20 t

1,4 Supernode: 20 10 e +

50 103

3

0

50

and 0.8v1 + 0.2v2 v4 = 0

v1 v2 6 dv2 v2 40e20t

Node 2: = 10 +

50 dt 100

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dvC f

iC f = C f

dt

dvs 0 vout

Cf =

dt R1

dvs

Thus, vout = R1C f

dt

dvs vd Avd

Cf =

dt R1

vout

vout

dvs

Cf = A

dt R1

dvs vout

R1C f = v out

dt A

A dvs

Solving, vout = R1C f

1 A dt

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

R1 = 100k , C f = 500 F , vs = 20 sin 540t mV

t

1

vout (t ) =

R1C f v dt ' v

0

s cf (0)

10 3

t

= 20sin 540tdt ' = 0.7407 cos 540t + C V

(b) A = 5000, Ri = 1M , and Ro = 3;

R1 = 100k , C f = 500 F , vs = 20 sin 540t mV

v d + vs vd d

+ + C ( vd + vout ) = 0...............(1)

R1 Ri dt

d v Avd

C ( vd + vout ) + out = 0................(2)

dt Ro

On solving these two equations, we get,

vd = 2 104 vout 6 10 9 vsV

vout = 6.4787 108 cos 540tdt ' 4 10 4 sin 540tdt '

C being a constant value

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

t

1

L 0

53. iL = vs dt + iL (0 ) . Assuming an ideal op amp,

0 vout

t

1

L 0

vs dt + iL (0 ) =

Rf

t

Rf

v dt + R i (0

Thus, vout = s f L )

L 0

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dvC f 0 vout

iC f = C f ; iR f = ; vC f = 0 vout

dt Rf

dvC f 0 vout

iC f = C f ; iR f = ; vC f = 0 vout

dt Rf

dvout vout v

Cf + = s

dt Rf R1

dvout v v

+ out = s

dt Rf C f R1C f

t

1

vout =

R1C f v dt v

0

s Cf (0)

In case of practical integrator circuit, when Rf is very large, the solution of the equation

obtained in (a) is equation 17 itself. In case of ideal integrator under DC conditions, the

capacitor acts as an open circuit and therefore op-amp gain is very high. As we know that

op-amp has input offset voltage, the input offset voltage gets amplified and appears as an

error voltage at the output. Due to such error voltage the op-amp can get easily saturated.

So in order to reduce the effect of such error voltage, usually a very large resistor is

added in parallel with the feedback capacitor in case of practical integrator circuit.

Thereby the DC gain is limited to Rf/R1 .

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

We want, 1V = 1C/s

dvs

vout = RC

dt

103V

vout = 1 = RC

s

RC = 1000

If we arbitarily select R = 1M , C = 1000 F

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

60. (a, b)

(c)

t

1

is (v 1 v2 )dt i1 (0 ) = 0

3 0

t t t

1 1 1

3 0

(v 1 v2 )dt + i1 (0 ) v2 dt i1 (0 ) v2 dt i2 (0 ) = 0

6 0 4 0

v1 = vs

d ( v1 v2 ) dv

6 4 2 =0

dt dt

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

61. (a,b)

(c)

d

Original circuit, mesh: 2 + 10i1 + 4 (i1 i2 ) = 0

dt

d

7i2 + 4 (i2 i1 ) = 0

dt

Nodal: v1 = - 2 V

v v v 1

t

0 = 2 1 + 2 + v 2 dt + i1 (0 ) i2 (0 )

10 7 4 0

New, mesh: i1 = -2 A

t

1 1 1 1

0 = + i2 i1 + i2 dt + v2 (0 )

7 10 10 4 0

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

62. (a, b)

vs 100(i1 i2 ) = 0

d ( i2 i3 )

100(i1 i2 ) 10 =0

dt

d ( i2 i3 ) 1

t

10 106 0

10 i3 dt vC (0 ) = 0

dt

i1 = is

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

63. (a)-(b)

di1

2i1 + + 16(i1 i2 ) 100 = 0

dt

di1

2 + 20(i2 i3 ) 16(i1 i2 ) = 0

dt

di

80i3 + 3 3 20(i2 i3 ) = 0

dt

v1 = 100V

v1 v2

t

( v2 v3 ) dt i1 (0 ) = 0

2 0

t t

v 1

( v2 v3 ) dt +i1 (0 ) 163 2 ( v3 v4 ) dt i2 (0 ) = 0

0 0

v4 ( v4 v5 )

t

1

( )

2 0

v3 v4 dt + i2 (0 ) =0

20 80

( v4 v5 ) 1 t v dt i (0 ) = 0

3 0

5 3

80

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

i1 = 100 A

i1 i2

t

( i2 i3 ) dt v1 (0 ) = 0

2 0

t t

i3 1

( i2 i3 ) dt +v1 (0 ) ( i3 i4 ) dt v2 (0 ) = 0

0

16 2 0

1

t

i (i i )

( i3 i4 ) dt + v2 (0 ) 4 4 5 = 0

2 0 20 80

( i4 i5 ) 1 t i dt v (0 ) = 0

3 0

5 3

80

dv1

2v1 + + 16(v1 v2 ) 100 = 0

dt

dv2

2 + 20(v2 v3 ) 16(v1 v2 ) = 0

dt

dv

80v3 + 3 3 20(v2 v3 ) = 0

dt

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

64. (a)

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

66. (a) For DC conditions, the capacitor acts as an open circuit. Therefore, the total current I

7

I= = 55.56 A

( 80 + 46 ) 103

in the circuit is: P80 k = I 2 R = ( 55.56 106 ) 80 103 = 246.95W

2

2

1

(c) Energy stored in the capacitor: wc = Cvc 2 = 0.5 10 106 2.556 2 = 32.665 J

2

(d) Pspice Verification

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1

67. (a) By current division, iL = 6 10 3 440 = 11.52 mA .

1 1 1

+ +

810 120 440

Thus, vx = (440(iL) = -5.069 V

1 2 1

(b) wL = Li = 132.7 J . wC = Ci 2 = 12.85 J

2 2

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1 2 1 2

68. (a) WL =

2 2

(b)

t

t

L

1.3043107

iL (t ) = e R

=e mA

iL (0ms ) = 1mA

130109

7

iL (130ns ) = e1.304310 mA = 0.369mA

260109

1.3043107

iL (260ns ) = e mA = 0.1362mA

9

50010

1.3043107

iL (500ns ) = e mA = 0.0216mA

At, t = 130ns,

WL = LiL 2 = 6 10 3 ( 0.369 10 3 ) = 0.408nJ = 13.6% of the initial energy stored .

1 1 2

2 2

At, t = 500ns,

WL = LiL 2 = 6 10 3 ( 0.0216 103 ) = 1.399 pJ = 0.046% of the initial energy stored .

1 1 2

2 2

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

1

69. (a) w = ( )(10 10 6 )(81) = 405 J

2

(b) no - the resistor will slowly dissipate the energy stored in the capacitor

RC = 0.460 s = 460 ms

Hence w = 54.81 mJ or 13.5% of initial amount stored.

vc(2.3 s) = 0.0606 V

Hence w = 18.39 nJ = 0.0045% of initial amount stored.

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

70. (a) When we analyze the given circuit with the DC conditions for a long time, the circuit

can be redrawn as below.

1 1

Energy stored in the 1F capacitor is: Wc = CvC 2 = 10 6 4 2 = 8 J

2 2

Current, iL= 0 A. Energy stored in the 2mH inductor is: WL = 0J

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dvs

71. vout = R f C1 = 103 100 103 2 103 cos(2 103 t )

dt

= 1.25664 105 cos(2 103 t )V

If we plot, vout as a function of time over 0t 5ms, our graph looks as below.

V(V)

t(s)

But, since the output for the op-amp is 15V, we can say that in this case, all the voltage

above 15 V will be clipped. This can be easily seen in the output in the Pspice.

(b) Pspice-verification

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

L dvs

72. (a) vout = = 8 10 11 150.796 cos(120 t )

R1 dt

= 1.2063 105 cos(120 t )V

If we plot, vout as a function of time over 0t 100ms, our graph looks as below.

V(V)

t(s)

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

100 103

t t

Rf

73. a) vout =

L 0

vs dt = 3

100 10 0

5sin(4 103 t )dt '

V(V)

t(s)

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

dvout v v

74. (a) + out = s

dt Rf C f R1C f

V(mV)

t(ms)

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Engineering Circuit Analysis 8th Edition Chapter Seven Exercise Solutions

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Chapter 8

Ebrahim Forati

09/09/2012

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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a) i(t ) 3e10

12

t

1) mA

i (0) 3 mA

i (1 ps ) 1.1 mA

b) i (2 ps ) 0.4 mA

i (5 ps ) 0.02 mA

c) W (1 ps) 6 1016 Joul

W (5 ps) 2 1019 Joul

2) ) L=5 H

W (0) 2.5 Joul

W (50ms ) 338.6 103 Joul

b)

W (100ms ) 45.8 103 Joul

W (150ms ) 6.2 103 Joul

3) L=R=1, I(0)=1

a) ( ) V

( ) V

( )

( ) V

( )

( ) V

( )

b)

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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( ) Watt

( )

( )

C)

0.00454 percent

4) R/L=1000

5) a) 14S+5=0

b) -9S-18=0

c) S+18+R/B=0

d) S^2+8S+2=0

6) a)

b)2

c)

d)

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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7) a) ( )

b) ( )

c) ( )

d) ( )

( )

8) a) ( ) ( )

b) ( ) ( )

c) ( ) ( )

d) ( ) ( )

9) a) ( ) ( )

( ) ( )

b) ( ) ( )

( ) ( )

( ) ( )

10) a) ( ) ( )

b) i(0)=i(1.3 ns)=

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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11) a)

b)

c) 1/sec

12)

b)

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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c)

13)

a)

b)

c)

d) Transmits to the other side of the cell.

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14) a) 1/8 sec

b) 5/41 sec

c) 1/10 sec

d) 4/150 sec

15)

i0 1 A

R 1 L5 H

16)

c)

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17)

a) v(t)=9*exp(-t/0.022)

b)

T (ms) 11 ms 33 ms

W (J) 0.32778058208 0.04436027791

c)

v(t)=9*exp(-t/2200)

T (ms) 11 ms 33 ms

W (J) 0.89099109004 0.890973270

18)

a)0.01 s

b)0.1s

c)1s

d) simulation

19)

20)

a)9*10^-7 s

b)

V(t) -volt 1.47152 0.541341 0.02695

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21)

a) 1.05 s

b)i1(t)=0.380952 * exp(-t/1.05)

c)0.671905 w

22)

a) tau = 169.15*10^-3 s

c) w =2.92483 * 10 ^ -8 j

23)

a)

T 0 984 1236

v(t) volt 20 7.35759 5.7301

b)

w =1.95857 j

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24)

a) 3*10^-3 (s)

b)20 volt

c)20* exp(-t/15*10^4)

d)2.70671 volt

25)

a) ( )

b) i(( )=0

c)

26)

a) v(t)=(R4*R3/(R4+R3)iL(0)*exp(-1.97143*10^6))

b) 0.000191917 volt

27)

0.2105 0.1263 0.1263 0.1263 0 10.637 *exp(-t/0.011875)

28)

T 0+ 0- 1 mu s 10 mu s

iL 3.6/5 3.6/5 0.6514829 0.26487319

vL 0.00001296 0 0.00001296*0.9048 = 0.00001296*0.3678=

0.0000117262 0.00000476668

vR 1.44 1.442*10^3 2*10^3*0.6514829=1302.9658 2*10^3*0.26487319=529.74638

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29)

I1(t) = -3 A t>0

I1(t) = 2 A t<0

30)

a) T = Ln(0.5) *(L/R)=0.00770163533 s

31)

I1=36/5*10^-3*exp(-4/5*10^3*t) -36/5*exp(-4/5*10^3*t)

IL= 9/5*10^-3*exp(-4/5*10^3*t)

I2=-i1-iL

I2=-(36/5*10^-3*exp(-4/5*10^3*t) -36/5*exp(-4/5*10^3*t)+ 9/5*10^-3*exp(-4/5*10^3*t))

T 1ms 3ms

I1(A) -3.2319 -0.6525

I2(A) 3.2311 0.6524

32)

vx=(0.75)*(1+exp(-100*t))

t=0.005s

vx=1.2049 v

33)

34)

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35)

a) R1=40 ohms

Ro= 60 ohms

36)

Vc(0-) = Vc(0+) = 2.5 v

C=21/22 F

37)

a) ( )

( )

b) ( )

( )

c ) ( )

( )

d) ) ( )

( )

38)

a)Vc(0-) = 80/23 v

b) Vc(0+) = 80/23 v

c) RC= -11.5/24 ms

d) Vc = 80/23 * exp(15/16 t)

39)

a) v1(0-) = 100

v2(0-) = 0

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vR(0-)=0

b) v1(0+) = 100

v2(0+) = 0

vR(0+)=100

c)

0.08 s

d)

( ) ( )

e)

( ) ( )

f)

( )

( )

g)

( )

( )

( )

( )

( )

40)

iL(0+)=iL(0-)=1.5 mA

iL(t)=1.5*10^-3*exp(-21/24*10^3*t)

a) t=0, P=54 nJ

b) t=1 ms, iL= 6.2529e-004, p= 9.3837e-009 J

c) t=5 ms, iL=1.8882e-005, p= 8.5567e-012 J

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41)

T -2 0 2

F(t) 0 3 3

G(t) 8 8 0

H(t) 0 0 0

Z(t) 11 11 4

42)

T -1 0 3

F(t) -1 0 0

G(t) 10 10 8

H(t) 2 2 1

Z(t) 2 2 3

43)

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44)

F(t)=u(t-1)-u(t-2)+u(1-t)

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45)

v(t)=3[u(t-2)-u(t-3)]-2[u(t-3)-(t-5)]-4[u(t-1)-u(t-2)]-2[u(1-t)]

46)

a) i=0

b) i=0

c) i=0

d) i=0;

e) ( )

47)

a) ( ) ( ) ( )

( )

b) ( )

C) Spice simulation

48)

a)

( ) ( ) ( )

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b) ( )

( )

( )

49) a)

( ) ( ) ( )

b)

50)

a)

( ) ( ) ( )

b)

( ) ( )

c)

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51)

a) ( ) ( ) ( )

b) ( ) ( )

c) t=58.6 msec

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52) a) ( ) ( ) ( )

b)

53)

( ) ( )

54) ( )

55)

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In R=1 case, the inductor stores more energy at t=1 sec. Because, the current peak is bigger.

56) a)

( ) ( ) ( )

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b)

57)

( ) ( )

58)

a) ( )

b) Spice verification

59)

a) ( )

b) Spice verification

60)

a)

( ) ( ) ( )

( )

b)

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61)

a)p = 0.4036 w

b)p = 17.9072 w

62)

Vc(t)=0.09*25(1-exp(-t/25*10^6))

T 0+ 25 150

Vc(t) 0 1.4223 2.25

63)

Vc(t)=5-5*exp(-t/25*10^6)

T=25 mu s -------- p=2w

b)

65)

V(t)= 9/16*10^3*(exp(-t/16*10^3)-exp(-t/8*10^3))

66)

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67)

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68) this is not a pulse! (pulse width is the same as the period)

69) this is not a pulse! (pulse width is the same as the period)

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70) a) ( )

b) ( )

c) ( )

d) ( )

e) ( )

71) a) ( )

b) ( )

c) ( )

d) ( )

e) ( )

f) ( )

72)

a)

b) ( )

c)

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d)

( )

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73)

0.14 %

No, it doesnt. Because, the time constant remains almost the same.

74)

a) ( )

b) ( )

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Engineering Circuit Analysis 8th Edition Chapter Nine Exercise Solutions

(a) For Source-free parallel RLC circuit:

1

0

LC

1

2 RC

For overdamped 0 or L 4R 2 C

L 12H

dv

(b) v(0 ) 9V , t 0

2V / s

dt

Choose L = 13 H

1 1

166.67 s 1

2 RC 2 1000 3 106

1 1

0 160.128rad / s

LC 13 3 106

1 1

0 2 25641

LC 13 3 106

s1 2 0 2 120.43

s2 2 0 2 166.67 46.24 212.91

v(t ) A1e s1t A2e s2t

vR (t ) A1e 120.43t A2e 212.91t

v(0 ) 9V

9 A1 A2

dv

A1 ( 120.43) A2 ( 212.91) 2

dt t 0

A1 5.75, A2 3.25

vR (t ) 5.75e 120.43t 3.25e 212.91t

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2. L = 2 nH, C = 10 mF, the circuit source-free parallel RLC circuit.

1

0

LC

1

2 RC

1 L

For overdamped 0 or R

2 C

R<0.0002236

Choose R 0.00021

1 1

3

238095.2s 1

2 RC 2 0.00021 10 10

1 1

0 223606.8rad / s

LC 2 10 9 10 10 3

0

(b)iR (0 ) 13PA, diE / dt t 0

1nA / s

0 223606.8rad / s

227272.7 s 1

0 2 5 1010

2 5.165 1010

2 0 2 40620.2

s1 2 02 227272.7 40620.2 186652.5s 1

s2 2 02 227272.7 40620.2 267892.9s 1

iR (t ) A1e s1t A2e s2t

iR (0 ) 13 pA

A1 A2 13 pA

diE

t 0 1nA

dt

diR

A1 s1 A2 s2 1nA / s

dt t 0

A1 4.28 1011 , A2 2.98 1011

iR (t ) 4.28 1011 e 186652.5t 2.98 1011 e 267892.9t

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3. C = 16 mF, L = 1 mH, choose R such that the circuit is

1

2 RC

1 1

0 250rad / s

LC 110 16 103

3

1 L

R

2 C

R 0.125

R 0.124

252s 1

0

0

R 0.125

R 0.126

248s 1

0

(c) Critically damped.

0

R 0.125

(d) Does your answer for part (a) change if the resistor tolerance is 1%? 10%?

R 0.124 1%

R 0.124 0.01(0.124) 0.12524

249.52

0 underdamped

R 0.124 1%(0.124) 0.12276

254.56 0 overdamped

R 0.124 10%

R 0.124 0.0124 0.1364 229.1 0 underdamped

R 0.124 0.0124 0.1116 280 0 overdamped

So, yes the answer for part (a) will change if the resistor tolerance is 1% or 10%

(e) Increase the exponential damping coefficient for part (c) by 20%. Is the circuit now

underdamped, overdamped, or still critically damped? Explain.

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0

old 1

new 1.2

1.2 300 s 1

0 250

0

Since 0 the circuit now is overdamped.

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4. Calculate , 0, s1, and s2 for a source-free parallel RLC circuit if

(a) R = 4 , L = 2.22 H, and C = 12.5 mF;

= 10

0 6

s1 2 0

2

s1 2

s 2 2 0

2

s 2 18

(b) L = 1 nH, C = 1 pF, and R is 1% of the value required to make the circuit underdamped.

1

0 3.16 10 10 rad / s

LC

underdamped 0

R 15.82

1% R 0.1582

1

3.16 10 12 s 1

2 RC

0 overdamped

s1 2 0 158 10 6

2

s 2 2 02 6.3198 10 12

(c) Calculate the damping ratio for the circuits of parts (a) and (b)

10

a 1.667

0 6

3.16 1012

b 100

0 3.16 1010

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5. No 1 k_ resistors, C = 3 F, L>12H, 1 meter long piece of 24 AWG soft solid copper wire.

Replace the resistor with 1 meters of 24 AWG copper wire. From Table 2.4, 24 AWG soft solid

copper wire has a resistance of 25.7 /1000ft. Thus, the wire has a resistance of

R 1m 0.0843

1m 2.54cm 12in 1000 ft

1

1977066 s 1

2 RC

1 1

0 160rad / s

LC 13 3 10 6

0 overdamped

2 3.909 1012 , 0 2 25641

2 0 2 1977119

s1 2 0 1977066 1977119 53

2

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6. source-free parallel RLC circuit having 10 8 s 1 , 0 10 3 rad / s, 0 L 5.

(a)

V s

1H s

A

0 1 / s

1

0 L s

s

(b)

s1 2 0 10 8 1016 10 6 683.77 10 6

2

s 2 2 02 10 8 1016 10 6 131.62 10 7

(c)

v c (t ) A1 e s1t A2 e s2t

v c (t ) A1 e 683.7710 t A2 e 131.6210

6 7

t

1 2

wc Cv (t 0 ) 1 10 3 J

2

1

w L Li 2 (t 0 ) 1 10 3 J

2

t

v 1 dv

vdt , i (t 0 ) C 0

R L t0 dt

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7. R = 500 , C = 10 F, and L such that it is critically damped.

(a) Determine L.

L 4R 2 C

L 4 500 10 10 6 10 H

2

Yes, this value s large for a printed-circuit board mounted component. For example, 11H

inductor measuring 10cm (tall) 8 cm (wide) 8 cm (deep).

(b) Add a resistor in parallel to the existing components such that the damping ratio is equal to

10.

10

0

1 1

100

2 RC 2 500 10 10 6

1

0 100

LC

1

10 1000

0

1

1000 R 50

2 R 10 10 6

R 500

50 500 // R new 50 new

R new 500

R new 55.6

(c) Increasing the damping ratio further lead to an overdamped circuit since

0 When increasing the damping ratio we are increasing

0

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8. R=1K, L= 7mH, C= 1nF. L initially discharged and C strong 7.2mJ

(a)

1

5 10 5 s 1

2 RC

1 1

0 377964rad / sec

LC 7 10 3 1 10 9

0 overdamped

2 2.5 1011 , 0 2 1.429 1011

2 02 327261.4

s1 172738.6

s 2 827261.4

i R (t ) A1 e s1t A2 e s2t

i L (0 ) i L (0 ) 0

1 2 7.2 10 3

wC Cv C (0) 7.2 10 3 v C (0 ) 3.795 10 3 V v C (0 )

2

9

2 110

v C (t ) A1 e s1t A2 e s2t A1 e 172738.6t A2 e 827261.4t

v C (0 ) 3.795 10 3 V A1 A2

dv C iC 0

i R (0 ) i L (0 ) 3.795

172738.6 A1 827261.4 A2 3.79510 9

dt t 0 C C 110 9

A1 -1.0009 10 3 , A2 4.7956 10 3

v C (t ) -1.0009 10 3 e 172738.6t 4.7956 10 3 e 827261.4t

v C t

i R (t ) -1.0009e 172738.6t 4.7956e 827261.4t

R

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(c)

i R (10s) -0.1768A

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9. vC (t ) 10e10t 5e4tV

close all;

clc;

t=[0:0.01:1.5];

vc1=10*exp(-10*t);

vc2=5*exp(-4*t);

vc=vc1-vc2;

plot(t,vc1,'-ro')

hold on

plot(t,vc2,'-.b')

hold on

plot(t,vc,'.-g')

hleg1 = legend('10*exp(-10*t)','5*exp(-4*t)','vC(t)');

grid on

xlabel('t(s)')

ylabel('v(t)')

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(b)

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10. iL (t ) 0.20e 2t 6e 3t A

(a)

clear all;

close all;

clc;

t=[0:0.1:1.5];

il1=0.20*exp(-2*t);

il2=0.6*exp(-3*t);

il=il1-il2;

plot(t,il1,'-ro')

hold on

plot(t,il2,'-.b')

hleg1 = legend('0.20*exp(-2*t)','0.6*exp(-3*t)');

grid on

xlabel('t(s)')

ylabel('iL(t)')

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(b)

1 2

(c) wL (t ) Li L

2

s1 2 2 0

2

s 2 3 2 0 s1 s 2 5 2 2.5s 1

2

0 6rad / sec

1 1

letR 1 2.5 C 0.2 F

2 RC 2(1)C

1

overdamped 0 L 2 L 0.8 H L 1H

0 C

1 1

wL Li L [0.20e 2t 6e 3t ] 2

2

2 2

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t=[0:0.1:1.5];

il1=0.20*exp(-2*t);

il2=0.6*exp(-3*t);

il=il1-il2;

plot(t,il1,'-ro')

hold on

plot(t,il2,'-.b')

il=il1-il2;

hold on

plot(t,il,'*g')

ylabel('iL(t)')

hleg1 = legend('0.20*exp(-2*t)','0.6*exp(-3*t)','iL');

figure

wl=(0.5)*(il).^2;

plot(t,wl)

grid on

xlabel('t(s)')

ylabel('wL(t)')

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11.

(a)

i R (t ) 2e t 3e 8t , t 0

di R

2e t 3 8e 8t 0

dt

2e t 24e 8t 0

12 e 7 t m ln(7) 7t m t m 1.714s

i R (t m ) 2e ( 1.714) 3e 8(1.714)

i R (t m ) i R max 0.3603

(b)

i R max 0.3603

1% i R max 0.003603

0.003603 2e t s 3e 8t s

t s 6.319s

P i R R 5 2e t 3e 8t

2

2

2.5 5 2e t 3e 8t 2

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12.

1 1

20s 1

2 RC 2 0.1 250 10 3

2 400

1 1

0 5.1rad / s

LC 2 3

250 10

13

0 2 26.1

s1 2 0 20 400 26.1 0.66

2

s 2 2 02 39.34

0 overdamped

At t 0 replace the inductor with short crcuit and the capacitor with open circuit. The voltage

power supply will be on.

6

i L (0 ) 2.99 10 4 A

20k 0.1

0.1

v C (0 ) 6 2.99 10 5 V

20k 0.1

At t 0

v C (0 ) v C (0 ) 2.99 10 5 V

i L (0 ) i L (0 ) 2.99 10 4 A

v C (t ) A1 e s1t A2 e s2t

v C (t ) A1 e 0.66t A2 e 39.34t

v C (0) 2.99 10 5 A1 A2

dv C

0.66 A1 e 0.66t 39.34 A2 e 39.34t

dt

dv v (0 )

i C C C i C (0 ) i L (0 ) i R (0 ) (2.99 10 4 ) C 0

dt 0.1

dv C dv i C (0)

i C ( 0) C C t 0 0

dt dt C

0.66 A1 39.34 A2 0

A1 0.3 10 4 , A2 5.1 10 7

v C (t ) 0.3 10 4 e 0.66t 5.1 10 7 e 39.34t

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13.

(a)

i L (t ) A1 e s1t A2 e s2t , t 0 i L (t ) A1 e 0.66t A2 e 39.34t

i L (0) 2.99 10 4 A i L (0 )

i L (0) A1 A2 2.99 10 4

di L

0.66 A1 e 0.66t 39.34 A2 e 39.34t

dt

di

v L (t ) L L , v L (0 ) v C (0) 2.99 10 5 V

dt

2

v L (0) (0.66 A1 39.34 A2 ) 2.99 10 5 0.66 A1 39.34 A2 1.94 10 4

13

A1 2.99 10 4 , A2 7.7 10 8

i L (t ) 2.99 10 4 e 0.66t 7.7 10 8 e 39.34t

(b)

i R (t ), t 0

i R (t ) A1 e s1t A2 e s2t i R (t ) A1 e 0.66t A2 e 39.34t

t 0 i R (0 ) i L (0 ) 2.99 10 4 A, v C (0 ) 2.99 10 5 V

t 0 i L (0 ) i L (0 ) 2.99 10 4 A, v C (0 ) v C (0 ) 2.99 10 5 V

v C (0 )

i R (0 ) 2.99 10 4

R

i R (0) A1 A2 2.99 10 4

v C (t ) Ri R (t ) 0.1 A1 e 0.66t A2 e 39.34t

dv C

i C (t ) C

dt

250 10 3 0.1 0.66 A1 e 0.66t 39.34 A2 e 39.34t

i C (0 ) i L (0 ) i R (0 ) 0

i R (t ) 3.04 10 4 e 0.66t 5.1 10 6 e 39.34t

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(c)

di L

i L max 1.7 10 4 e 0.66t 3.03 10 6 e 39.34t 0 t max 0

dt

i L max 2.989 10 4 A

1% i L max 2.989 10 6 A

t s 6.978s

di R

i R max 2 10 4 e 0.66t 2 10 4 e 39.34t 0 t max 0

dt

i R max 2.989 10 4 A

1% i L max 2.989 10 6 A

t s 7.003s

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14. at t=0 both the 10 A source and the 48 are removed leaving the 2mF, 250 mH, and 1

resistor in parallel.

(a) iC (0 ) 0

0.009796

(b) i L (0 ) 2.04110 4 A

48

0.009796

(c) i R (0 ) 9.79 10 3 A

1

(d) vC (0 ) 48 // 1 10 10 3 A 0.9796 10 10 3 0.009796V

(f) i L (0 ) i L (0 ) 2.04110 4 A

v C (0 ) 0.009696

(g) i R (0 ) 0.009796 A

R 1

(h) vC (0 ) vC (0 ) 0.009796V

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15. v R (t ) for t>0

(a)

1 1

250s 1

2 RC 2 1 2 10 3

1 1

0 44.7 rad / s

LC 250 10 3 2 10 3

0 overdamped

v R (t ) A1 e s1t A2 e s2t

s1 2 0 250 (250) 2 44.7

2 2

s1 4

s 2 2 0 250 (250) 2 44.7

2 2

s 2 495.97

v R (t ) A1 e 4t A2 e 495.97t

v R (0 ) v C (0 ) 9.796 10 3

v R (0 ) v C (0 ) 9.796 10 3

v R (0) 9.796 10 3 V

A1 A2 9.796 10 3

dv C

v C (t ) A1 e 4t A2 e 495.97t

4 A1 e 4t 495.97 A2 e 495.97t

dt

dv C dv

t 0

4 A1 495.97 A2 iC (0 ) C C t 0 i L (0 ) i R (0 ) 0.01A

dt dt

4

4 A1 495.97 A2 5 A1 2.04 10 , A2 0.01

v R (t ) 2.04 10 4 e 4t 0.01e 495.97t

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v R (t ) 2.04 10 4 e 4t 0.01e 495.97t

dv R

v R max 8.16 10 4 e 4t 4.9597e 495.97t 0 t max 0

dt

(b) v R max 9.796 10 3 V

1% v R max 9.796 10 5 V

t s 9.33 10 3 s

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16.

(a) at t 0

i R (0 ) 0, i L (0 ) 5A

v C (0 ) 0

at t 0 vC (0 ) 0V

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1 1

3

625s 1

2 RC 2 0.2 4 10

1 1

0 500rad / s

LC

3

1 10 4 10 3

0 overdamped

v C (t ) A1 e s1t Ae s2t

s1 2 0 625 (625) 2 500

2 2

s1 250

s 2 2 0 625 (625) 2 500

2 2

s 2 1000

v R (t ) A1 e 250t A2 e 1000t

v C (0 ) v C (0 ) 0V

v C (0) 0V

A1 A2 0

dv C

250 A1 e 250t 1000e 1000t

dt

dv

iC C C

dt

iC (0 ) i L (0 ) i R (0 )

v C (0 )

i R (0 ) 0

R

i L (0 ) i L (0 ) 5A iC (0) i L (0 ) 5A

5 10 6 4 10 3 (250 A1 1000 A2 )

A1 1.67 10 6 , A2 1.67 10 6

v(t ) 1.67 10 6 e 250t 1.67 10 6 e 1000t

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(b)

i L (t ) A1 e s1t A2 e s2t

v C (t ) A1 e 250t A2 e 1000t

i L (0 ) i L (0 ) 5A i L (0) 5A

5A A1 A2

di L

250 A1 e 250t 1000 A2 e 1000t

dt

di

v L (t ) L L

dt

v L (0 ) v C (0 ) 0V

250 A1 1000 A2 0

A1 6.67 10 6 , A2 1.67 10 6

i L (t ) 6.67 10 6 e 250t 1.67 10 6 e 1000t

di L

250 6.67 10 6 e 250t m 1000 1.67 10 6 e 1000t m 0

dt

tm 0

i L (t m ) 5 10 6 A

(c)

i L max 5 10 6 A

1%i Lmax 0.05 10 6 A

0.05 10 6 6.67 10 6 e 250t s 1.67 10 6 e 1000t s

0.05 10 6 6.67 10 6 e 250t s

0.0075 e 250t s

ln(0.0075) 250t s

t s 19.57 10 3 s

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17.

1 1

99.2

2 RC 2 14 360 10 6

1 1

0 52.7 rad / sec

LC 1 360 10 6

0 overdamped

v(t ) A1 e s1t Ae s2t

s1 2 0 99.2 (99.2) 2 52.7

2 2

s1 15.16 s 1

s 2 2 0 99.2 (99.2) 2 52.7

2 2

s 2 183.24s 1

v(t ) A1 e 15.16t A2 e 183.24t

t 0

i L (0 ) i R (0 ) 310mA

v C (0 ) v R (0 ) 14 310 10 3 4.34V

t 0

i L (0 ) L (0 ) 310mA

v C (0 ) v C (0 ) 4.34V

v C (t ) A1 e 15.16t A2 e 183.24t v C (0) 4.34 A1 A2

dv C

15.16 A1 e 15.16t 183.24 A2 e 183.24t

dt

dv

iC C C

dt

i C (0 ) i L (0 ) i R (0 )

v C (0 ) 4.34

i R (0 ) 0.31A, i C (0 ) i L (0 ) i R (0 ) 0

R 14

dv C

t 0 15.16 A1 183.24 A2 0 A1 4.73, A2 -0.391

dt

v C (t ) 4.73e 15.16t 0.391e 183.24t

t t

1

i L vdt i L (0) [4.73e 15.16t 0.391e 183.24t ]dt 0.31 0.312e 15.16t 0.002e 183.24t A

L0 0

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18.

1 1

1388.9 s 1

2 RC 2 1 360 10 6

1 1

0 52.7rad / sec

LC 1 360 10 6

0 overdamped

v C (t ) A1 e s1t Ae s2t

s1 2 0 1388.9 (1388.9) 2 52.7

2 2

s1 1s 1

s 2 2 0 1388.9 (1388.9) 2 52.7

2 2

s 2 2776.8s 1

v(t ) A1 e t A2 e 2776.8t

i L (0 ) i R (0 ) 310mA

v C (0 ) v C (0 ) 4.34V

v C (t ) A1 e t A2 e 2776.8t v C (0) 4.34 A1 A2

dv C

iC C

dt

dv C

i C (0 ) i L (0 ) i R (0 ) 0 A1 2776.8 A2 0

dt

A1 4.34, A2 0.002

v C (t ) 4.34e t 0.002e 2776.8t

wC

1

2

1

Cv C 360 10 6 4.34e t 0.002e 2776.8t

2

2

2

180 10 6 4.34e t 0.002e 2776.8t

2

(b)

wC

1

2

1

Cv C 360 10 6 4.34e t 0.002e 2776.8t

2

2

2

180 10 6 4.34e t 0.002e 2776.8t 2

1

wC max 1.694 10 3 J

2

t 1 0.347 sec

wC max

2

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20. R1 0.752, R2 1.268

1

(a) wC Cv 2C

2

1.5 R1iA 0

iA i1 i2 1.5 0.752i1 0.752i2 0

Mesh two:

i1 , i2 i1 0.0315 A, i2 1.967 A

iA (0 ) i1 i2 2 A

t 0 vC (0 ) R2iA (0 ) 2iA (0 ) R1iA (0 ) 0

Solving for iA (0 ) 0

vLC

vLC R2 2(1) R1 0 vLC 0.02V RTh 0.02

1A

1 1

5s 1

2 RC 2 0.02 5

1 1

0 0.3162rad / sec

LC 5 2

0 overdamped

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vC (t ) A1e s1t Ae s2t

s1 2 0 2 5 (5) 2 0.3162

2

s1 0.01s 1

s2 2 0 2 5 (5) 2 0.3162

2

s2 9.99s 1

v(t ) A1e 0.01t A2 e 9.99t

iL (0 ) i2 (0 ) 1.967 A

vC (0 ) vC (0 ) 0V

vC (t ) A1e 0.01t A2e 9.99t vC (0) 0 A1 A2

dvC

iC C , iR (0 ) iA (0 ) 0

dt

dvC 1.967

iC (0 ) iL (0 ) iR (0 ) 1.967 A 0.01A1 9.99 A2 0.3934

dt 5

A1 0.03934,A2 0.03934

vC (t ) 0.03934e 0.01t 0.03934e 9.99t

1 1 2 2

wC CvC 2 5 0.03934e 0.01t 0.03934e 9.99t 2.5 0.03934e 0.01t 0.03934e 9.99t

2 2

(b)

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21. L = 8H, C = 2F

1 1

(a) , 0

2 RC LC

0 Critical damping

1 1 1 L 1 8

LC 4 R 2 C 2 R 1000 1k

2

4R C 2

LC 2 C 2 2 10 6

1 1

(b) 6

250s 1

2 RC 2 1000 2 10

(c) v Ri r

v e t ( A1t A2 )

v e 250t ( A1t A2 )

v 1 250t

ir e ( A1t A2 )

R R

1 t

(d) Show that i r e ( A1t A2 ) is a solution to

R

d 2 ir di r

2

2 2 ir 0

dt dt

dt R

1

R

e A1 e t ( A1t A2 ) A1 A1t A2 e t

di r 1 t

d ir

2

2

(2 A1 A1t A2 )e t

dt R

2

1

(2 A1 A1t A2 )e t 2 A1 A1t A2 e t 2 e t ( A1t A2 )

d ir di 1

2 r 2 i r

R

2

dt dt R R

1

R

2A1 2 A2 2 A1t 2A1 2 2 A1t 2 2 A2 2 A1t 2 A2 e t 0

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22. 0

L 4 R 2C

1H 1 2 F

V

1 1

A

A.s

1F 1

V

V .s

1H

A

V .s V 2 A.s V .s

L 4 R 2C 2

A A V A

1H 1 2 F

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23. R = 40, L = 51.2H, C = 8F

1 1

(a) 9

1.563 10 6 s 1

2 RC 2 40 8 10

1 1

0 1.563 10 6 rad / s

6 9

LC 51.2 10 8 10

(b) We could never make exactly equal to 0 because in practice it is unusual to obtain

components that are closer than 1 percent of their specified values.

1 2 1

wL Li w L 1mJ Li L (0)

2

2 2

2 110 3

i L (0) 6.25 A

51.2 10 6

v C (t ) e t ( A1t A2 )

v C (t ) A1 e 1.56310 t t A2 e 1.56310

6 6

t

v C (0) 0

0 0 A2 A2 0

v C (t ) A1 e 1.56310 t t

6

dv C

A1 e 1.56310 t A11.563 10 6 te 1.56310 t

6 6

dt

dv C

t 0 A1

dt

dv C iC (0)

t 0 , iC (0) i L (0) i R (0)

dt C

i R (0) 0 iC (0) i L (0)

dv C i L (0) 6.25

t 0 9

7.813 10 8 V / s

dt C 8 10

A1 7.813 10 V / s

8

v C (t ) 7.813 10 8 e 1.56310 t t

6

v C (500 10 9 ) 178.81V

t m 0.64 10 6 sec

V m 183.5V

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v C max 183.5V

1%v C max 1.835V

1.835 7.813 10 8 t s e 1.56310 t s

6

t s 4.9 10 6 s

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25. R = 40 , C = 2 pF.

(a) 0

1

2 RC

1

L 4 R 2 C 4 40 2 2 10 12

LC

L 1.28 10 8 H

(b) In practice it is unusual to obtain components that are closer than 1% of their specified

values.

(c) i L (0) 0, wC 10 pJ

1 2 1

wC Cv 10 10 12 2 10 12 v C (0) v C (0) 10V

2 2

1

v R (t ) e t ( A1t A2 ) 625 10 7 s 1

2 RC

v R (t ) e 62510 t ( A1t A2 )

7

10 0 A2 A2 10

v R (t ) e 62510 t ( A1t 10)

7

dv R dv

e 62510 t ( A1 625 10 7 A1t 6.25 1010 ) R t 0 A1 6.25 1010

7

dt dt

dv C iC (0) i (0) 0.25

t 0 , iC (0) i L (0) i R (0), i L (0) 0 C 12

2.083 1010 V / s

dt C C 2 10

dv R

t 0

A1 6.25 1010 2.083 1010

dt

A1 8.333 10 8

v R (t ) e 62510 t (8.333 10 8 t 10)

7

2 7

R 40

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26. i s (t ) 30u(t )mA

(a) R1 so that v 0 6V

At t 0 , the current source is on, the inductor can be treated as a short circuit, and C as an open

circuit. Thus v(0 ) appears across R1 and is given by

v 0 30mAR1

v0 v0 v0 6V

v0

R1 200

30 10 3

(b) v (2ms)

v e t ( A1t A2 )

At t 0 the current source has turned itself off and R1 is shorted. We are left with a parallel

RLC circuit comprised of R 5, C 200F , L 20mH

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1 1

6

500s 1

2 RC 2 5 200 10

1 1

0 500rad / sec

3 6

LC 20 10 200 10

0 critcallyd amped

v(t ) e t ( A1t A2 )

v(t ) A1te 500t A2 e 500t

t 0

i L (0 ) 30mA

v C (0 ) v C (0 ) 6V

v0 6 A2

v C (t ) A1te 500t 6e 500t

dv C

A1 e 500t 500 A1te 500t 3000e 500t

dt

dv C

t 0 A1 3000

dt

t 0

v C (0 ) 6

iC (0 ) i L (0 ) i R (0 ), i R (0 )

1. 2 A

R 5

3

i L (0 ) L (0 ) 30mA iC (0 ) 30 10 1.2 1.23 A

dv C dv (0 ) iC (0 )

iC C C

dt dt C

1.23

A1 3000 6150 A1 3150

200 10 6

v C (t ) 3150te 500t 6e 500t

v(2ms) 0.11V

(c) t s for v C

dv C

3150e 500t 3150 500 te 500t 6500 e 500t 0

dt

3150 1.575 10 6 t min 3000 0 t mn 3.9 10 3 sec

v C (t min ) V mi 0.8925V

v C max 6V t max 0

3150t s e 500t s 6e 500t s 0.00893

t s 0.0172s

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27. i s (t ) 10u(1 t )A R1 so that i L 0 2A

15

10

is(t)

5

0

-10 -8 -6 -4 -2 0 2 4 6 8 10

t

At t 0 , the current source is on, the inductor can be treated as a short circuit, and C as an open

circuit. Thus v(0 ) appears across R1 and is given by

5R1

v 0 10A( R1 // 5) 10A

R1 5

i L 0 i L 0 2A

v 0

R1

R1 20

v 0 40 10 6 V

1 1 1

6

500 s 1 , 0 500 s 1

2 RC 2 5 200 10 LC

i L (t ) e t A1 t A2 i L (t ) e 500t A1t A2

i L (0) 2 10 6 A 2 10 6 A2 i L (t ) e 500t A1t 2 10 6

di L

dt

e 500t A1 500 A1t 1 10 3

v C (0 ) 14 310 10 3 4.34V

t 0

v C (0 ) v C (0 ) 40 10 6 V

di L

v L (0) v C (0) 40 10 6 V L t 0

dt

(20 10 3 ) A1 1 10 3 40 10 6 A1 3 10 3

i L (t ) e 500t 3 10 3 t 2 10 6

i L (500ms) 0

i L (1.002ms) 3.033 10 6

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28.

0 L 4 R 2 C L 4142 360 10 6

L 0.282 H

1 1

(b) 6

99.21s 1

2 RC 2 14 360 10

t 0

i L (0 ) 310 10 3 A, i R (0 ) 310 10 3 A

v C (0 ) 14 310 10 3 4.34V

t 0

v C (0 ) v C (0 ) 4.34V

v C (0 )

i R (0 ) 310 10 3 A, i L (0 ) 310 10 3 A

R

i L (0) 310 10 3 A2

i L (t ) e 99.21t A1t 310 10 3

di L

e 99.21t A1 99.21A1t 30.755

dt

di

v L (0) v C (0) 4.34 L L t 0

dt

(0.282) A1 30.755 4.34 A1 15.365

i L (t ) e 99.21t 15.365t 310 10 3

wL

1

2

2

2

Li L (0.282) e 99.21t 15.365t 310 10 3

1 2

w L (10ms) 2.04 10 88 J

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v C (t ) e t A1t A2 v C (t ) e 99.21t A1t A2

t 0

i L (0 ) 310 10 3 A, i R (0 ) 310 10 3 A

v C (0 ) 14 310 10 3 4.34V

v C (0 ) v C (0 ) 4.34V

v C (0 )

i R (0 ) 310 10 3 A, i L (0 ) 310 10 3 A

R

v C (0) 4.34 A2

v C (t ) e 99.21t A1t 4.34

dv C

e 99.21t A1 99.21A1t 430.57

dt

dv

iC C C , iC (0) i L (0) i R (0) 0

dt

A1 430.57 0 A1 430.57

v C (t ) e 99.21t 430.57t 4.34

wC

1

2

2

2

Cv C (360 10 6 ) e 99.21t 430.57t 4.34

1 2

wC (10ms) 1.8499 10 3 J

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29. R1 R2 10

(a)

0

1 1

, 0

2 RC LC

v

RTh LC 80

1A

3125s 1

L 0.0512 H

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30. Underdamped

(a)

1 1

0 , , 0

2 RC LC

1 1

2 RC LC 4 R 2C 2 LC

2 RC LC

1 L

R

2 C

1 L 1 10 10 3

R R R 1581.14

2 C 2 110 9

R 1582

1

3.16055 10 5 s 1

2 RC

1

0 3.16227 10 5 rad / sec

LC

0

(c)

0

If the damping ratio increased the circuit becomes less underdamped since will be larger than 0

(d)

1

3.16055 10 5 s 1

2 RC

1

0 3.16227 10 5 rad / sec 0 11011

2

LC

d 11011 3.16056 10 5 10.42110 3 rad / s

2

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31. R 10k, L 72H , C 18 pF

(a) , 0 , d

1 1

2.78 106 s 1

2 RC 210 10 18 1012

3

1 1

0 2.78 107 rad / sec

LC 72 10 18 10

6 12

0 underdamped

d 0 2 2 27.66 106 rad / s

6

(c) wC 1nJ

1

wC Cv C (0) v C (0) 10.54V

2

2

v0 10.54 B1

v C (t ) e 2.7810 t (10.54 cos 27.66 10 6 t B 2 sin 27.66 10 6 t

6

dv C

t 0 29.3 10 27.66 10 B 2

6 6

dt

dv C iC

t 0 0

dt C

29.3 10 6 27.66 10 6 B 2 0 B 2 1.06

v C (t ) e 2.7810 t (10.54 cos 27.66 10 6 t 1.06 sin 27.66 10 6 t

6

v C (300ns) 1.551V

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32. R 1.5k, L 10mH , C 1mF

1 1

(a) 0.33s 1

2 RC 2 1.5 10 110

3

3

1

0 316.23rad / sec

10 10 3 110 3

d 0 2 2 316.23rad / s

(c) i L (0 ) 0, vC (0 ) 9V

i L (0 ) 0 B1

i t e 0.33t B 2 sin 316.23t

dit

316.23B 2 e 0.33t cos 316.23t 0.33B 2 e 0.33t sin 316.23t

dt

di

v L (t ) L , v L (0 ) v C (0 ) 9V

dt

v L (0) 10 10 3 316.23B 2 9 B 2 2.85

i L t 2.85e 0.33t

sin 316.23t

di L t

2.85 [316.23e 0.33t cos 316.23t 0.33e 0.33t sin 316.23t ] 0

dt

t m 4.96 10 3 s

i max 2.845 A

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0.33t

33. i(t ) 2.85 sin 316.23t for R = 1.5k

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For R = 15k

1 1

3

0.033s 1

2 RC 2 15 10 1 10

3

1

0 316.23rad / sec

LC

0 underdamped

d 0 2 2 316.23rad / s

i (t ) e t ( B1 cos d t B 2 sin d t )

i (t ) e 0.033t ( B1 cos 316.23t B 2 sin 316.23t )

i L (0 ) 0, v 0 9V

i (0) B1 0

i (t ) e 0.033t ( B 2 sin 316.23t )

di

t 0 B 2 316.23

dt

di v L (0)

t 0 , v L (0 ) v C (0 ) 9,

dt L

B 2 2.85

i L (t ) e 0.033t (2.85 sin 316.23t )

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For R = 150k

1 1

3

0.0033s 1

2 RC 2 150 10 1 10

3

1

0 316.23rad / sec

LC

0 underdamped

d 0 2 2 316.23rad / s

i (t ) e t ( B1 cos d t B 2 sin d t )

i (t ) e 0.0033t ( B1 cos 316.23t B 2 sin 316.23t )

i L (0 ) 0, v 0 9V

i (0) B1 0

i (t ) e 0.0033t ( B 2 sin 316.23t )

di

t 0 B 2 316.23

dt

di v L ( 0)

t 0 , v L (0 ) v C (0 ) 9,

dt L

B 2 2.85

i L (t ) e 0.0033t (2.85 sin 316.23t )

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34. vt , t 0

1 1

0.25s 1

2 RC 2 2 10 110 3

3

1 1

0 316.23rad / sec

LC 10 10 110

3 3

0 underdamped

d 0 2 2 316.23rad / s

v(t ) e t ( B1 cos d t B2 sin d t )

v(t ) e 0.25t ( B1 cos 316.23t B2 sin 316.23t )

iL (0 ) 0, v 0 9V

v(0) B1 9

v(t ) e 0.25t (9 cos 316.23t B2 sin 316.23t )

dv

t 0 9 0.25 B2 316.23

dt

dv iC (0)

t 0 , iL (0 ) 0,

dt C

dv

t 0 0 B2 0.0071

dt

v(t ) e 0.25t (9 cos 316.23t 0.0071sin 316.23t )

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(b) R = 2

1 1

250 s 1

2 RC 22 1 10 3

1 1

0 316.23rad / sec

LC

10 10 3 110 3

0 underdamped

d 0 2 2 193.65rad / s

v(t ) e t ( B1 cos d t B 2 sin d t )

v(t ) e 250t ( B1 cos 193.65t B 2 sin 193.65t )

i L (0 ) 0, v 0 9V

v(0) B1 9

v(t ) e .250t (9 cos 193.65t B 2 sin 193.65t )

dv

t 0 9 250 B 2 193.65

dt

dv iC (0)

t 0 , i L (0 ) 0,

dt C

dv

t 0 0 B 2 11.62

dt

v(t ) e 250t (9 cos 193.65t 11.62 sin 193.65t )

(c)

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35. at t=0 both the 3 A source and the 2 are removed leaving the 2.5F, 20 mH, and 50

resistor in parallel.

(a) iC (0 ) 0

v C (0 )

(b) i L (0 ) 2..88 A

2

5.76

(c) i R (0 ) 0.115 A

50

(f) i L (0 ) i L (0 ) 2.88 A

vC (0 ) 5.76

(g) i R (0 ) 0.115 A

R 50

(h) vC (0 ) vC (0 ) 5.76V

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36. v L (t ) for t > 0

1 1

4000s 1

2 RC 250 2.5 10

6

1 1

0 20 10 6 rad / sec

LC

3

20 10 2.5 10 6

0 underdamped

d 0 2 2 2000rad / s

v L (t ) e t ( B1 cos d t B 2 sin d t )

v L (t ) e 4000t ( B1 cos 2000t B 2 sin 2000t )

i L (0 ) 2.88 A, v L 0 v C 0 5.76V

v L (0) B1 5.76V

v L (t ) e 4000t (5.76 cos 2000t B 2 sin 2000t )

dv L

t 0 23.04 10 2000 B 2

3

dt

dv i C (0 ) 2.995

t 0

dt C 2.5 10 6

B 2 615.02

v L (t ) e 4000t (5.76 cos 2000t 615.02 sin 2000t )

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37.

5

vC (0 ) 2 1V

10

5

iL (0 ) 2.5 A

2

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1 1

125s 1

2 RC 2 2 2 10

3

1 1

0 158rad / sec

LC 20 103 2 103

0 underdamped

d 0 2 2 96.64rad / s

v(t ) e t ( B1 cos d t B2 sin d t )

v(t ) e 125t ( B1 cos 96.64t B2 sin 96.64t )

iL (0 ) 2.5 A, v 0 1V

v(0) B1 1

v(t ) e 125t ( cos 96.64t B2 sin 96.64t )

dv

t 0 125 B2 96.64

dt

dv iC (0)

t 0 , iL (0 ) 2.5 A, iR (0 ) 0.5 A iC (0 ) 2.5 0.5 2 A

dt C

dv

t 0 B2 1.2935

dt

v(t ) e 125t ( cos 96.64t 1.2935sin 96.64t )

v(t ) 0 t 0.0257 sec

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(b)

dvC

0

dt

vC max 0.0171V tmax 0.033sec

0.1 vC max 0.00171

ts 0.051s

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39. For t < 0 s, we see from the circuit below that the capacitor and the resistor are

- -

shorted by the presence of the inductor. Hence, i (0 ) = 2.5A and v (0 ) = 0 V.

L C

When the 2.5-A source turns off at t = 0 s, we are left with a parallel RLC circuit.

1 1

(a) 4s 1

3

2 RC 2 500 10 250 10 3

1 1

0 5rad / sec

LC 160 10 250 10

3 3

0 underdamped

d 0 2 2 3rad / s

(b)

iL (t ) e t ( B1 cos d t B2 sin d t )

iL (t ) e 4t ( B1 cos 3t B2 sin 3t )

iL (0 ) iL (0 ) 2.5

iL (0) B1 2.5

diL

iL (t ) e 4t (2.5cos 3t B2 sin 3t ) e 4t ( 10 cos 3t 7.5sin 3t 4 B2 sin 3t 3B2 cos 3t )

dt

diL

10 3 B2

dt t 0

diL vL (0)

t 0 , vL (0 ) vC (0 ) 0,

dt L

B2 3.33

iL (t ) e 4t (2.5cos 3t 3.33sin 3t )

1 2 1 2

(c) wL LiL (160 103 ) e4t (2.5cos3t 3.33sin 3t )

2 2

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40. R 500M

1 1

(a) 4 10 9 s 1

2 RC 2 500 10 250 10

6

3

1 1

0 5rad / sec

LC

160 10 3 250 10 3

0 underdamped

d 0 2 2 5rad / s

(b)

i L (t ) e t ( B1 cos d t B 2 sin d t )

i L (t ) e 5t ( B1 cos 5t B 2 sin 5t )

i L (0 ) i L (0 ) 2.5

i L (0) B1 2.5

di L

i L (t ) e 5t (2.5 cos 5t B 2 sin 5t ) e 5t (12.5 cos 5t 12.5 sin 5t 5 B 2 sin 5t 5 B 2 cos 5t )

dt

di L

t 0

12.5 5 B 2

dt

di L v L (0)

t 0 , v L (0 ) v C (0 ) 0,

dt L

12.5

B2 2.5

5

i L (t ) e 5t (2.5 cos 5t 2.5 sin 5t )

(c)

wL

1

2

1

Li L 160 10 3 e 5t (2.5 cos 5t 2.5 sin 5t )

2

2

2

10% w L max 0.05

t 10% wL max 0.267 sec

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41. C 160mF, L 250mH

2L

1 1

0 5rad / sec

LC

(250 10 ) 160 10 3

3

R

0 0

2L

R 2 L 0 5 2 250 10 3 2.5

0 R 2.5

1

0 5rad / sec

LC

1

2 RC

0 Critically damped

1

R

2C 0

R 0.625

1

0 5rad / sec

LC

1

2 RC

0 Underdamped

1

R

2C0

R 0.625

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42. R 2, C 1mF, L 2mH

vC (0 ) 1V , i L (0 ) 0

R

500 s 1

2L

1 1

0 707.11rad / sec

LC (2 103 ) 1103

0 underdamped

i (t ) e t ( B1 cos d t B2 sin d t )

d 0 2 2 500rad / s

i (t ) e 500t ( B1 cos 500t B2 sin 500t )

i (0) 0 B1 0

i (t ) e 500t ( B2 sin 500t )

di vL (0) vC (0) Ri (0) 1

t 0 500 B2

dt L L 2 103

B2 1

i (t ) e 500t sin 500t

3

i (1ms ) e 50010 sin 500 103 0.291A

3

i (2ms ) e 500210 sin 500 2 103 0.3096 A

3

i (3ms ) e 500310 sin 500 3 103 0.223 A

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43. R 2, C 1mF, L 2mH

Rnew 2 / /2 1

R

250 s 1

2L

1 1

0 707 rad / sec

LC

(2 103 ) 1103

0 underdamped

vC (t ) e t ( B1 cos d t B2 sin d t )

d 0 2 2 661rad / s

vC (t ) e 250t ( B1 cos 661t B2 sin 661t )

v(0) 1 B1 1

vC (t ) e 250t (cos 661t B2 sin 661t )

dvC iC (0)

t 0 250 661B2 0

dt C

B2 0.378

vC (t ) e 250t (cos 661t 0.378sin 661t )V , t 0

vC (4ms ) -0.2569V

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44. R 2, C 1mF, L 2mH

vC (0 ) 2V , i L (0 ) 1mA

R

500 s 1

2L

1 1

0 707.11rad / sec

LC (2 10 ) 1103

3

0 underdamped

i (t ) e t ( B1 cos d t B2 sin d t )

d 0 2 2 500rad / s

i (t ) e 500t ( B1 cos 500t B2 sin 500t )

i (0 ) 1mA B1 1103

i (t ) e 500t (1103 cos 500t B2 sin 500t )

di

vL (0) vC (0) Ri (0) 2 2 110

3

t 0 0.5 500 B2 999

dt L L 2 103

B2 1.999

i (t ) e 500t (1103 cos 500t 1.999sin 500t ) A, t 0

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45. R 1k, C 2mF, L 1mH

vC (0 ) 4V , i L (0 ) 0

(a)

R

5 10 5 s 1

2L

1 1

0 707.11rad / sec

LC (2 10 ) 110 3

3

0 overdamped

i (t ) A1 e s1t A2 e s2t , t 0

s1 2 0 0.5

2

s1 2 0 999999.5

2

i (t ) A1 e 0.5t A2 e 999999.5t

i L (0) 2.99 10 4 A i L (0 )

i (0) A1 A2 0

di

0.5 A1 e 0.5t 999999.5 A2 e 999999.5t

dt

di

0. 5 A 999999 .5 A

v L (0) v C (0) Ri (0) 4 0 110 3

4 10 3 A / s

t 0

110 3

1 2

dt L L

A1 0.004, A2 0.0004

i (t ) 0.004e 0.5t 0.004e 999999.5t A, t 0

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46. R 140, C 0.5F , L 12H

R 140

(a) 140s 1

2 L 2 0.5

1 1

(b) 0 0.41rad / sec

LC (12)0.5

(c) i(0 ) i(0 ) 0.5 A

(d)

0 overdamped

i (t ) A1 e s1t A2 e s2t , t 0

s1 2 0 6 10 4

2

s1 2 0 279.99

2

4

i (t ) A1 e 610 t

A2 e 279.99t

i (0) A1 A2 0.5

di 4

6 10 4 A1 e 610 t 279.99 A2 e 279.99t

dt

di 4 v L (0) v C (0) Ri (0) 70 1400.5

6 10 A 279.99 A 0

dt t 0

1 2

L L 12

(e)

A1 0.499, A2 1.07 10 6

4

i(t ) 0.499e 610 t

1.07 10 6 e 279.99t A, t 0

i(6s) 0.497 A

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50. R 1, C 20mF, L 10H

R 1

(a) 5 104 s 1

2 L 2 10 106

1 1

0 2236.1rad / sec

LC

(10 106 ) 20 103

(b) i s 3u(t ) 2u(t )mA

At t 0 i s 3mA

iL (0 ) 3mA

vC (0 ) vR (0 ) 3mV

At t 0 i s 2mA

iL (0 ) iL (0 ) 3mA

vC (0 ) vC (0 ) 3mV

iL () 2mA

vC () 2mA 1 2mV

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51.

iC (0 ) 0 A, i R (0 ) 10mA, i L (0 ) 10mA

v L (0 ) 0, v C (0 ) 10mA 20 10 3 200V , v R (0 ) 10mA 20 10 3 200V

During the interval from t = 0 to t = 0 , the left-hand current source becomes active.

+

vC (0 ) 200V , v R (0 ) 25mA 20 10 3 500V , v L (0 ) v R (0 ) vC (0 ) 500 200 300V

vL L

di L di

L t 0 L

v 0

300

500 A / s

dt dt L 0.6

dv C iC 0

15 10 3

3 10 6 V / s

9

dt t 0 C 5 10

At the left hand node:

15 10 3 i L i R 0, t 0

di L di R di di L

0 0 R t 0

t 0

500 A / s

dt dt dt dt

At the right hand node:

10 10 3 iC i R 0, t 0

diC di R di di

0 0 C t 0 R t 0 500 A / s

dt dt dt dt

dv di

v R Ri R R t 0 R R t 0 20 10 3 500 10 10 6 V / s

dt dt

v L v R vC 0 v L v R vC

dv L dv R dv C

t 0

t 0

t 0

10 10 6 3 10 6 7 10 6 V / s

dt dt dt

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52. vs (t ) 8 2u(t )V

(a) vC (0 )

At t 0

8

iR (0 ) 0.533 A

15

vR (0 ) (15)(0.53) 7.995V

vR (0 ) vC (0 ) 8V

vC (0 ) 8V

(b)

8

iL (0 ) iR 0.533 A

15

iL (0 ) 0.533 A

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53. vs 1 2u(t )V

At t 0 vs 1

(a)

v 1

iL (0 ) iR (0 ) s 2A

R 500 103

iL (0 ) iL (0 ) 2 A

(b)

vC (0 ) vR (0 ) RiR 1V

vC (0 ) vC (0 ) 1V

(c)

vs 1 2 1V

1

iL ()

500 103

iL () 2 A

(d)

1 1

3 3

200 s 1

2 RC 2 500 10 5 10

40000

2

1 1

0 182.57rad / s

LC 5 10 6 103

3

0 2 33333.33

s1 2 0 2 200 40000 33333.33 118.34 s 1

s2 2 02 281.65

0 overdamped

vC (0 ) vC (0 ) 1V

iL (0 ) iL (0 ) 2 A

vC (t ) 1 A1e s1t A2 e s2t

vC (t ) 1 A1e 0.66t A2e 39.34t

vC (0) 1 1 A1 A2 A1 A2 2

dvC

t 0

118.34 A1 281.65 A2 0

dt

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60. v(0) 0, i(0) 1mA

0 this is a series RLC with R=0, or a parallel RLC with R=

1 1

02 12 9

5 1019

LC 10 10 2 10

d 02 2 7.071109 rad / sec

The response form is as follow:

v(t ) A cos d t B sin d t

v(0 ) v(0 ) 0

v(t ) B sin d t

dv

d B cos d t

dt

dv

iC C iC (0 ) CBd iL (0 ) iL (0 ) 110 3

dt

1103

B 9

7.0711105

2 10 7.07110 9

In designing the op amp stage, we first write the differential equation:

t

1 dv

12

vdt ' 103 2 109 0, (iC iL 0)

10 10 0 dt

Take the derivative of both sides:

2

1 9 d v

v 2 10 0

10 1012 dt 2

d 2v 1 1

9 12

v v

dt 2

2 10 10 10 20 1021

dv

dt t 0

7.0711105 7.071109 4.99 105

One possible solution is:

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61. v(0) 0, i(0) 1mA

0 this is a series RLC with R=0, or a parallel RLC with R=

1 1

02 12 9

5 1019

LC 10 10 2 10

d 02 2 7.071109 rad / sec

The response form is as follow:

i (t ) A cos d t B sin d t

i (0 ) i (0 ) 1mA A 110 3

i (t ) A cos d t B sin d t

di

Ad sin d t d B cos d t

dt

di di

vL L 10 1012

dt dt

vL (0 ) vC (0 ) vC (0 ) 0 LBd

B0

i (t ) 103 cos 7.071109 t

In designing the op amp stage, we first write the differential equation:

t

1 dv

12

vdt ' 103 2 109 0, (iC iL 0)

10 10 0 dt

Take the derivative of both sides:

2

1 9 d v

v 2 10 0

10 1012 dt 2

d 2v 1 1

9 12

v v

dt 2

2 10 10 10 20 1021

di

0

dt t 0

One possible solution is:

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62. v(0) 0, i(0) 1mA, L 20H / /10PH , C 5 F

0 this is a series RLC with R=0, or a parallel RLC with R=

Leq 10 1012 / /20 110 11 H

1 1

02 11 9

2 1016

LC 110 2 10

d 02 2 1.41108 rad / sec

The response form is as follow:

i (t ) A cos d t B sin d t

i (0 ) i (0 ) 1mA A 110 3

i (t ) A cos d t B sin d t

di

Ad sin d t d B cos d t

dt

di di

vL L 1 1011

dt dt

vL (0 ) vC (0 ) vC (0 ) 0 LBd

B0

i (t ) 103 cos1.41108 t

In designing the op amp stage, we first write the differential equation:

t t

1 1 dv

12

vdt ' 103 vdt ' 2 109 0, (iC iL1 iL2 0)

10 10 0 20 0 dt

Take the derivative of both sides:

2

1 1 9 d v

v v 2 10 0

10 1012 20 dt 2

d 2v

2

25 106 v

dt

di

0

dt t 0

One possible solution is:

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63. RC circuit

R 1k , C 3.3mF

vC (0 ) vC (0 ) 1.2V

v dv

(a) 3.3 103 0

1000 dt

(b) One possible solution is

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64. RL circuit

R 20, L 5H

iL (0 ) iL (0 ) 2 A

(a)

vR vL

diL

20(iL ) 5

dt

diL

4iL

dt

(b)

iL (t ) Ae t / , L / R 0.25

iL (0 ) 2 A

iL (t ) 2e 4t

diL

t 0

8

dt

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

2. (a)

1.95sin t 92 1.95 cos( t 182)

2.7 sin 50t 5 10 cos 50t

2.7 sin 50t cos 5 2.7 cos 50t sin 5 10 cos 50t

2.6897 sin 50t 9.7647 cos 50t 10.13cos(50t 15.4)

(b)

66 cos(9t 10) 66 sin(9t 80)

4.15 cos10t 4.15sin(10t 90)

10 cos 100t 9 10 sin 100t 19

11.0195sin100t 13.1325 cos100t

17.14 cos(100t 40)

17.14 sin(100t 50)

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(d) 5sin(10t 19o) = 5cos(10t 19o) therefore v1 leads by -45 + 109 = 64o

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

4. v1 34 cos(10t 125)

(b) i1 5cos 10t 80 ; v1 lags i1 by 155 235 80

(c) i1 5cos 10t 40 ;v1 lags i1 by 195 235 40

(d) i1 5cos 10t 40 ;v1 lags i1 by 275 235 40

(e) i1 5sin 10t 19 =5cos(10t 109);v1 lags i1 by 126 235 109

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(b) the first is lagging by 80o

(c) the second is lagging by 80o

(d) the second is lagging by 88o

(e) Neither term lags

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

7.07 cos(3t 1.4289) 0

3t 1.4289 1.5708

3t 0.1419

t 0.0473 s

Also, 3t 0.1419

t 1.0945 s

and, 3t 0.1419 2

t 2.1417 s

10t 0.7854 t 0.0785 s

Also, 10t 0.7854 t 0.3927 s

and, 10t 0.7854 2 t 0.7069 s

(c) cos 5t sin 5t 0

5t 0.7854 1.5708

5t 0.7854 t 0.1571 s

Also, 5t 0.7854 t 0.7854 s

and, 5t 0.7854 2 t 1.4137 s

(d) cos 2t sin 2t cos 5t sin 5t 0

1.4142 cos(1.5t 0.7854) 0

1.5t 0.7854 1.5708

1.5t 2.3562 t 1.5708 s

Also, 1.5t 2.3562 t 3.6652 s

and, 1.5t 2.3562 2 t 5.7596 s

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

8. (a) v (t ) 2t ; 0 t 0.5s

v (0.25s ) 0.5 V

(b) Using the first term of the Fourier series only,

8

v(t ) sin t

2

8

v(0.25s ) sin 45 0.5732 V

2

(c) Using the first three terms of the Fourier series,

8 8 8

v(t ) sin t sin 3 t sin 5 t

2

3

2 2

5 2

2

v(0.25s) 0.4866 V

(d)

t=linspace(-1,3);

v = 8/(pi^2)*sin(pi*t);

figure(1);

plot(t,v);

xlabel('t(s)')

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

ylabel('v(t)V')

title('Plot of v(t)using first term of Fourier series','FontSize',11)

(e)

t=linspace(-1,3);

v = 8/(pi^2)*(sin(pi*t)-1/(3^2)*sin(3*pi*t));

figure(2);

plot(t,v);

xlabel('t(s)')

ylabel('v(t)V')

title('Plot of v(t)using first two terms of Fourier series','FontSize',11)

(f)

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

t=linspace(-1,3);

v = 8/(pi^2)*(sin(pi*t)-1/(3^2)*sin(3*pi*t)+ 1/(5^2)*sin(5*pi*t));

figure(3);

plot(t,v);

xlabel('t(s)')

ylabel('v(t)V')

title('Plot of v(t)using first three terms of Fourier series','FontSize',11)

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

9. (b) Vrms Vm

110 V 156 V

115 V 163 V

120 V 170 V

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

10. In this problem, when we apply Thevenins theorem with the inductor as the load, we get,

voc vs .

1

1 10

4.53cos 0.333 103 t 30

1

11

0.4118cos 0.333 103 t 30 V

1 10 10

Rth 0.909

1 10 11

Now for a series RL circuit with L 3mH , Rth 0.909 and a source voltage of

Vm L

iL (t ) cos t tan 1 30

Rth 2 2 L2 R

1

0.4118 0.333 103 3 103

cos 0.333 10 t tan

3

30

0.909 0.333 103 3 103 0.909

2 2

0.453cos 0.333 103 t 30 A

iL (t 0) 0.453cos 30 392.3 mA

Now,

diL

vL (t ) L 3 103 0.333 103 0.453sin 0.333 103 t 30

dt

0.4526 cos 0.333 103 t 120 V

vL (t 0) 0.2262 V

vL (t 0)

iR (t 0) 0.2262 A

R

is (t 0) iR iL 392.3 mA

Pspice Verification:

This has been verified using the phasor in Pspice.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

12. In this problem, when we apply Thevenins theorem with the inductor as the load, we get,

1 1 2

voc 25cos100t 2 12.5cos100t V

1 2

Rth 1 1 2 1

Now for a series RL circuit with L 10mH , Rth 1 and a source voltage of

12.5cos100t V , we get,

Vm L

iL (t ) cos t tan 1

Rth 2 2 L2 R

1

12.5 100 10 103

cos 100t tan

12 100 10 103 1

2

8.84 cos 100t 45 A

Now,

diL

vL (t ) L 8.84 10 103 100sin 100t 45

dt

8.84 cos 100t 45 V

Voltage across the 2 resistor is equal to vL (t ).

Power dissipated in 2 resistor is given by,

vR 2 vL 2

pR (t ) 39.07 cos 2 100t 45 W

R R

Pspice Verification:

This has been verified using the phasor in Pspice.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

14. Let i be the current flowing in the circuit in the clockwise direction. Then, on applying

KVL, we get,

15i vC 3cos 40t

dvC

Substituting, i iC C on the above KVL equation, we get,

dt

dvC

30 103 vC 3cos 40t

dt

Let us choose to express the response as,

vC (t ) A cos 40t

dvC

40 A sin 40t

dt

On rewriting the KVL equation, we get,

1.2 A sin 40t A cos 40t 3cos 40t

1.2 A

A2 1.2 A cos 40t tan 1

2

3cos 40t

A

On equating the terms, we get,

A 1.92

tan 1 1.2 50.19

vC (t ) 1.92 cos(40t 50.19) V

Energy stored in a capacitor is given by,

1

wC CvC 2 (t )

2

At t=10 ms,

1

wC (10ms) 2 103 1.712 2.92 mJ

2

At t=40 ms,

1

wC (40ms) 2 103 1.452 2.1 mJ

2

Pspice Verification:

Phasor method is used to verify the solution.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(b)

2.5 30 0.545 2.5cos(30) j 2.5sin(30) 0.5cos(45) j 0.5sin(45)

2.52 j 0.89

(c) 2 j 2 2 j 2 8 80

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(b) 1 90o

(c) 1 0o

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(b) 45 215 3.98 j 0.35 1.93 j 0.52 2.05 j 0.17 2.05 4.74

(c) 2 j 9 50 3 j 9 9.5108.44

j j

(d) 340 2 2.3 j1.93 2 0.34 j 2.01 2.03260.4

10 j 5 10 j 5

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

2 j3 2 j3

20. (a) 4 4 3.6 j 0.2 3.6183.18

1 890 1 j8

1025 315

j 2 235 0.52 44.04 290 1.58 j 4.02

(b) 5 10 3 j 5

4.32111.46

1 j 1 j 10 j

3 90

(c) j 5 45

90 0.2135 8.86 j 0.14 8.860.91

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

22. Let iL in the complex form be iL Ae j (35t ) A .

Given, is 5sin(35t 10) 5e j (35t 100 ) A

vL L

diL

dt

0.4

d

dt

Ae j (35t ) j14 Ae j (35t )

vR iL R 6 Ae j (35t )

vS vC vR vL A(6 j14)e j (35t )

iC C

dvC

dt

0.01

d

dt

A(6 j14)e j (35t ) A 4.9 j 2.1 e j (35t )

is iC iL

151.69 )

5e j (35t 100 ) 4.43 Ae j (35t

A 1.129 and 251.69 108.31

iL 1.129e j (35t 108.31 ) 1.129 cos(35t 108.31) A

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

23.

1/2 1.25

(62.5) 2 (1.25 ) 2 cos t 31.3 tan 1 mA

62.5

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

24. This problem can be easily solved by performing a source transformation which results in

a circuit with voltage source, resistance and inductance.

is 5e j10t

Given,

vs 10e j10t

Vm L

iL (t ) cos t tan 1

R L

2

2 2

R

10 10 0.4

cos 10t tan 1

22 102 0.42 2

2.24 cos 10t 63.44 A

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(b) 5 -42o

(c) 1 104o

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

2 j 2.24 26.56

28. (a) V 0.45 71.56 V

545 545

620

(b) j V 0.00564 j1 1 89.67 V

1000

(c) j 52.5 90 V 52.50 V

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

29. (a) 0; 11

(b) -11; 0

(c) 0; 11

(d) -3; -3

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

At t = 25 ms: v(t ) 9 cos 515 8.16 V

(b) v (t ) 2 cos(100 t 31) V

At t = 25 ms: v(t ) 2 cos 481 1.03 V

(c) v (t ) 22 cos(100 t 14) 8 cos(100 t 33) V

At t = 25 ms: v(t ) 22 cos 464 8cos 483 0.97 V

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

31. (a) 2 0o

(b) 400 -90o mV

(c) 10 90o V

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Using ohms law, we get:

VR IR

VR

I 130 A

R

(b) At =1 rad/s, the voltage across the capacitor-inductor combination is 0 as their

equivalent impedance is 0.

Z eq j j 0

VR

VC L

(c) At = 2 rad/s,

Z eq j 0.5 j 2 j1.5

VC L 130 1.590 1.5120 V

VR 130

0.67 90

VC L 1.5120

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

33. (a) 20 0o mV

(b) 31.8 -90o V

(c) 3.14 90o V

(d) 20 -0.1o V

(e) 3.14 89.6o

(f) 20 mV; 0; 0; 20 mV; 21.9 mV

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

I10 242 mA

V 40132 mV

1000 rad / s

V 40132

Z 2090

I10 242

The phase angle of 90degrees shows that it is an inductor.

(b) 1000 rad/s

Z L j L j 20

L 20 mH

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

36. (a) The equivalent impedance of a 1 resistor in series with a 10mH inductor as a

function of is given by,

Z eq R j L 1 j 0.01

(b)

w = logspace(1,5,100);

Z = 1+i*w*0.01;

mag = abs(Z);

semilogx(w, mag);

xlabel('w(rad/s)');

ylabel('Impedance Magnitude (ohm)');

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(c)

w = logspace(1,5,100);

Z = 1+i*w*0.01;

theta = angle(Z);

theta_degrees = angledim(theta,'radians','degrees');

semilogx(w, theta_degrees);

xlabel('w(rad/s)');

ylabel('Impedance Angle (degrees)');

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(b) 20 90o

(c) 20 88.8o

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

38. (a) The equivalent impedance of a 1 resistor in series with a 10mF capacitor as a

function of is given by,

j j100

Zeq R 1

C

(b)

w = logspace(1,5,100);

Z = 1-i*100*w.^-1;

mag = abs(Z);

semilogx(w, mag);

xlabel('w(rad/s)');

ylabel('Impedance Magnitude (ohm)');

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(c)

w = logspace(1,5,100);

Z = 1-i*100*w.^-1;

theta = angle(Z);

theta_degrees = angledim(theta,'radians','degrees');

semilogx(w, theta_degrees);

xlabel('w(rad/s)');

ylabel('Impedance Angle (degrees)'); .

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(c) 20 89.9o S

(d) 1 -89.9o mS

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

40. Looking into the open terminals we see that the parallel combination of 20 mH and 55

is in series with the series combination of 10 mF and 20 , this combination is in parallel

with 25 .

(a) = 1 rad/s

Z L j L j 0.02

j

ZC j100

C

55 j 0.02

55 j 0.02 20 j100 25

Z eq 22.66 j 5.19 23.24 12.9

55 j 0.02

55 j 0.02 20 j100 25

(b) = 10 rad/s

Z L j L j 0.2

j

ZC j10

C

55 j 0.2

55 j 0.2 20 j10 25

Z eq 11.74 j 2.88 12.08 13.78

55 j 0.2

55 j 0.2 20 j10 25

(c) = 100 rad/s

Z L j L j 2

j

ZC j

C

55 j 2

55 j 2 20 j 25

Z eq 11.14 j 0.30 11.14 1.54

55 j 2

55 j 2 20 j 25

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Zeq 3 j 4 553.13

V IZ 3 20 553.13 15 33.13 V

(b) 3 in series with 125F

Zeq 3 j 4 5 53.13

V IZ 3 20 5 53.13 15 73.13 V

Zeq 3 j 4 j 4 30

V IZ 3 20 3 9 20 V

(d) 3, 2mH and 125F in series but = 4 krad/s

Zeq 3 j8 j 2 6.7163.44

V IZ 3 20 6.7163.44 20.13 43.44 V

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(c) 30 + j0.013

(d) 30 + j1.310-5

(e) 30 + 1.310-8

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

44. One method is to use the current divider rule in order to calculate i(t). In the given circuit,

there are three parallel branches.

1

Z eq 2 j 0.67 2.1118.52

5 j10 2 j 2

1 1 1

Z 2 j 2 2.8345

I Is

Z eq

4 20 2.1118.52 2.98 46.48 A

Z 2.8345

i (t ) 2.98cos(100t 46.48) A

PSpice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

45. (a) One possible solution: A 1 resistor in series with 1 H and 10-4 F.

(b) One possible solution: A 6.894 resistor in series with 11.2 mH.

(c) One possible solution: A 3 resistor in series with 2.5 mF.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(a) At 10 rad/s, the equivalent admittance is given as, Y 1 S . We can construct this

using a 1 S conductance (1 resistor) in parallel with an inductor L and a capacitor C

1

such that C 0 . Selecting L as 5H arbitrarily yields the value of a capacitor as

L

2mF.

Thus, one design can be 1 resistor in parallel with 5H inductor and 2mF capacitor.

(b) At 10 rad/s, the equivalent admittance is given as,

Y 12 18 S = 11.4127 j 3.7082 S . We can construct this using a 11.4127 S

conductance (87.6 m resistor) in parallel with an inductor L such that

j

j 3.7082 S . This yields the value of the inductor as 26.9 mH.

L

Thus, one design can be 87.6 m resistor in parallel with 26.9 mH inductor.

(c) At 10 rad/s, the equivalent admittance is given as, Y 2 j mS . We can

construct this using a 2 mS conductance (500 resistor) in parallel with a capacitor C

such that j C j 0.001 S . This yields the value of the capacitor as 0.1 mF.

Thus, one design can be 500 resistor in parallel with 0.1 mF capacitor.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

v1(t) = 2.56cos(100t + 139.2o) V; v2(t) = 4.35cos(100t + 138.3o) V.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

48. (a)

In mesh 3, we have,

I3 I1 ZC I3 I 2 Z L 2I 3 0

I1ZC I 2 Z L 2.5 10 j 0.4545 1.1147 j1.0037 10 j

3 3

I

3

2 ZC Z L 2 j 0.4545 j

1.004 1.23

0.4843 16.48 mA

2.07315.25

i1 (t ) 2.5cos10t mA

i2 (t ) 1.5cos(10t 42) mA

i3 (t ) 0.4843cos(10t 16.48) mA

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

V1 I1 j 30 V2 55(I1 I 2 ) and

V1 I1 j 30 V3 I 2 j 20

On simplification. we get,

I1 55 j 30 55I 2 2.2635 j 9.848

I1 j 30 I 2 j 20 0.1045 j 9.0665

Solving for I1and I 2 , we get,

I1 0.6247 j 0.3339 0.7128.12 A

I 2 0.4838 j 0.4956 0.6945.69 A

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

2I1 j10 I1 I 2 2.59

I1 2 j10 I 2 j10 2.4692 j 0.3911 1

In mesh 2, we get,

j10 I 2 I1 j 0.3I 2 5I1 0

I1 5 j10 I 2 j 9.7 0 2

On solving eqns [1] and [2] we get,

I1 0.3421 j 0.0695 0.3511.48 A

I 2 0.3169 j 0.2479 0.438.04A

i1 (t ) 0.35cos(10t 11.48) A and

i2 (t ) 0.4 cos(10t 38.04) A

Pspice verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

54. Using node voltage analysis in phasor domain, we get the nodal equations as,

V1 V1 V2 V1 V2

I1 0 1

j2 j4 1 j 3.8

V2 V1 V2 V1 V2

I2 0 2

2 j4 1 j 3.8

I1 150 15 A

I 2 25131 16.4015 j18.8677 A

On simplifying the equations [1] and [2], we get,

V1 0.0648 j 0.4961 V2 0.0648 j 0.0039 15

V1 0.0648 j 0.0039 V2 0.5648 j 0.0039 16.4015 j18.8677

Matlab Verification:

>> syms v1 v2;

eqn1 = (15+v1/(2i)+(v1-v2)/(-4i)+(v1-v2)/(1+3.8i));

eqn2 = (-16.4015+18.8677i+(v1-v2)/(1+3.8i)+(v1-v2)/(-4i)-v2/2);

answer=solve(eqn1, eqn2, 'v1', 'v2');

digits(4);

V2 = vpa(answer.v2)

V2 = -29.52+29.74*i

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

56.

2I1 4.7 I1 I 2 j 2 I1 I 2 4

6.7 j 2 I1 4.7I 2 j 2I 3 4 1

In mesh 2, we get,

4.7 I 2 I1 j 0.0562I 2 2 I 2 I 3 0

4.7I1 6.7 j 0.0562 I 2 2I 3 0 2

In mesh 3, we get,

j 2 I 3 I1 2 I 3 I 2 I 3 0

j 2I1 2I 2 3 j 2 I 3 0 3

Here, Ix = I3. On solving we get,

I x I 3 1.1104 j 0.2394 1.13612.16 A

ix (t ) 1.136 cos(20t 12.16) A

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

71.7cos(14t + 50o) A.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

58.

Using node voltage analysis in phasor domain, we get the nodal equations as,

At node A,

V1 VA VA VB VA VB VA 0 1

0.8 0.4 j 0.02 j14

At node B,

V2 VB VA VB VA VB VB 0 2

0.6 0.4 j 0.02 j16

Given,

V1 0.0090.5 0.009 j 0.000078 V

V2 0.0041.5 0.004 j 0.0001 V

On simplifying the nodal equations [1] and [2], we get,

0.009 j 0.000078

VA 3.75 j 49.9286 VB 2 j 50

0.8

0.004 j 0.0001

VA 2 j 50 V2 4.1667 j 49.9375

0.6

and on solving, we get,

VA 0.00613 j 0.00033 0.006133.09 V

VB 0.00612 j 0.00040 0.006133.75 V

vA 0.00613cos(500t 3.09) V and

vB 0.00613cos(500t 3.75) V

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

59. (a)

Vo Rf

Vs R j

f C1 j

A C1

(b)

Vo R f C1

Vs 1 R C ( R C j ) ( R C j )

A

f 1 f f f f

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

60.

j 0.2 I1 I 2 3 I1 I 3 9

3 j 0.2 I1 j 0.2I 2 3I 3 9 1

In mesh 2, we get,

0.005I1 j1.4 I 2 I 3 j 0.2 I 2 I1 0

0.005 j 0.2 I1 j1.2I 2 j1.4I 4 0 2

In mesh 3, we get,

j 0.2 I 3 I 4 3 I 3 I1 I 3 j 9 0

3I1 3 j 0.2 I 3 j 0.2I 4 j 9 3

In mesh 4, we get,

5I 4 j 0.2 I 4 I 3 j1.4 I 4 I 2 j 9

j1.4I 2 j 0.2I 3 I 4 5 j1.2 j 9 4

On solving we get,

I1 18.33 j 20 27.13132.5 A

I 2 5.092 j 3.432 6.14 33.98 A

I 3 19.76 j 21.55 29.24132.5 A

I 4 1.818 j 0.02 1.82 0.63 A

Therefore,

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

i1 (t ) 27.13cos(20t 132.5) A

i2 (t ) 6.14 cos(20t 33.98) A

i3 (t ) 29.24 cos(20t 132.5) A

i4 (t ) 1.82 cos(20t 0.63) A

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Right hand source contributions: 1.29 -75.9o V; 9.08 -115o V

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

62. Using node voltage analysis in phasor domain, we get the nodal equations as,

At node 1,

V1 V2 V1 0

I1 I 2 1

j5 j3

At node 2,

V1 V2 V2

I2 0 2

j5 2

I1 33 103 3 mA

I 2 51103 91 mA

On simplifying the nodal equations [1] and [2], we get,

V1 j 0.1333 V2 j 0.2 I 2 I1

V1 j 0.2 V2 0.5 j 0.2 I 2

V1 0.4694 j 0.1513 493.18 162.14 mV

V2 0.0493 j 0.27 274.46 100.34 mV

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

7.995cos(40t + 2.4o) + 1.67cos(30t 180o) mV

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Zthevenin j 2 410 3.94 j 2.69 4.7734.32

Calculate Thevenin voltage:

V1 1.524 j 2 1.524 290 3114 V

V2 238 410 848 V

VTH V1 V2 3114 848 4.13 j8.68 9.6164.55 V

Z total 3.94 j 2.69 2 j 2 5.94 j 0.69 5.976.626

VTH 9.6164.55

I1 1.657.92 A

Z total 5.976.63

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

340 j120

Zthevenin 12 j 34 ( j10) 1.67 j13.33 13.4382.86

12 j 24

Using current divider to find the current through j10 branch,

2230 340 j120

I s .Z eq

I

Z 12 j 24

29.5522.87 A

VTH Voc 29.5522.87 1090 295.46112.87 V

Z norton Zthevenin 1.67 j13.33 13.4382.86

I N I sc 2230 A

(c) Current flowing from a to b

VTH 295.46112.87

I1 20.7260.3 A

Ztotal 14.2652.57

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Using node voltage analysis in phasor domain, we get the nodal equations as,

At node 1,

IS

V2 V1 V1 V1 V2

1 2 j1

V1 1.5 j V2 1 j j 3 1

At node 2,

V1 V2 V2 V2 V1

j1 j 1

V1 1 j V2 0 2

I S 3 90 A

V1I 0.9231 j1.3846 V

V2I 2.3077 j 0.4615 V

V1 V2I V1I 1.3846 j 0.9231 1.66146.3 V

v1I (t ) 1.66 cos(20t 146.3) V

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Vs 2.1

Is 1.1307 j1.4538 A

Z 2 j

j

3 j

Copyright 2012 The McGraw-Hill Companies. Permission required for reproduction or display. All rights reserved.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

I s .Z eq

I1 1.1307 j1.4538 0.7 j 0.1

ZR

V1V I1.Z R 0.6461 j1.1307 1.3119.74 V

v1V (t ) 1.3cos(20t 119.74) V

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

70. Using phasor analysis, we get the open circuit voltage as,

Voc 10 V

For finding the short circuit current through terminal a-b, we can apply KVL,

10 j 0.25I N j 2 I N j 2I N 0.5 j I N

10

IN 0.4 j 0.8 0.89 63.43 A

0.5 j

Now for finding the equivalent impedance,

VOC

ZN 0.5 j

IN

For a parallel combination of a resistor and a capacitor or an inductor,

1

Z eq 0.5 j

R ( jX ) 1

1

1 1

R 2.5 and X 1.25 from which at = 1 rad / s , we get,

0.4 0.8

the value of L 1.25 H

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

72. Taking 50 V = 1 inch, from the figure, we get the angle as 122.9. (The figure below

shows for the angle +122.9 only.)

100 140 120

100 140 cos j140sin 120

122.88

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

IR = 25.6 26o A

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Z1 4030

Z 2 50 j 30 58.31 30.96

Z 3 30 j 40 5053.13

VS 1200

I1 3 30 A

Z1 4030

VS 1200

I2 2.05 30.96 A

Z 2 58.31 30.96

VS 1200

I3 2.4 53.13 A

Z 3 5053.13

I S 6.2 22 A

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

76. (a)

ZTH 1 j 2 2 j 3

j2 j6

1 j 2 2 j3

18 j10

4 j 7

20.6150.94

8.06119.74

2.5531.2

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Thevenin voltage:

In order to find the thevenin voltage, after removing the capacitor and on applying node

voltage method, we can write the nodal equations as,

At node A,

5 78 VA' VA'

1

1 j2

At node B,

4 45 VB' VB'

2

2 j3

Solving the nodal equations [1] and [2], we get,

VA' 4.472 51.43 V and

VB' 3.328 11.31 V

4.472 51.43 3.328 11.31

0.4752 j 2.8437

2.88 99.49 V

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Calculate vc(t):

Z c j 3.33 3.33 90

Z total 2.18 j 2.01 2.96 42.67

VTH Z c

Vc

Z total

2.88 99.49 3.33 90

2.96 42.67

3.24 146.82V

vc (t ) 3.24 cos(20t 146.82) V

Pspice Verification:

(c) The current flowing out of the positive terminal of the voltage source is given by

5 78 VA

A. If we apply nodal voltage analysis, we get,

1

At node A,

5 78 VA VA VC

1 j 2 j 3.33

From (b), we have, VC 3.24 146.82 V

On solving, we get,

VA 2.0348 j3.057 3.67 56.35 V

I 0.995 j1.833 2.08 118.49 A

i(t ) 2.08cos(20t 118.49) A

Pspice Verification:

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

77. If both sources operate at 20 rad/s, vc(t) = 510sin(20t 124o) mV. However, in the

present case,

vc(t) = 563sin(20t 77.3o) + 594sin(19t + 140o) mV.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

78. (a)

j

90 tan 1

VO

VS 1 j 1 2

(c)

(d) From the plot of the gain, we see that the circuit transfers high frequencies more

effectively to the output.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

(d)

Vo 1

Vs 1 2

The circuit transfers low frequencies to the output more effectively, as the gain

approaches zero as the frequency approaches infinity.

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Engineering Circuit Analysis 8th Edition Chapter Ten Solutions

Here, the impedance is given as,

Z

22 j 7 4.618 25.65 4.1629 j 2

58

If Z 4.1629 j 2 is constructed using a series combination of single resistor,

j

capacitor and an inductor, then, R 4.16 and j 2 j L . Selecting L as 200nH

C

arbitrarily yields the value of the capacitor as 0.12pF.

Thus, one design will be 4.16 resistor in series with 200nH inductor and 0.12pF

capacitor.

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