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2574 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO.

4, OCTOBER 2013

DC Ring-Bus Microgrid Fault Protection


and Identification of Fault Location
Jae-Do Park, Member, IEEE, Jared Candelaria, Liuyan Ma, and Kyle Dunn, Student Member, IEEE

AbstractA fault protection and location method for a dc bus AC microgrids have a clear advantage when it comes to
microgrid system is presented in this paper. Unlike traditional ac system protection. AC power systems come with more than
systems, dc bus systems cannot survive or sustain high-magnitude
100 years of experience and well-defined standards (e.g.,
fault currents. And if a fault causes the dc bus to de-energize com-
pletely, it makes locating faults very difficult. The main goal of the ANSI/IEEE and IEC standards). All of this can be easily
proposed scheme is to detect and isolate faults in the dc bus without translated into an ac microgrid. Standards on the protection
de-energizing the entire system and identifying the fault location. of dc systems currently do not exist. Protection devices for ac
In order to achieve this, a ring-type bus was used in this paper. systems are very mature and they are generally much cheaper
The bus was segmented into overlapping nodes and links with cir-
cuit breakers (CBs) to isolate the segment in the event of a fault. than dc breakers since they are not specialty items. AC breakers
Backup protection is implemented for circuit breaker failures to rely on the natural zero crossings of the ac current; hence, these
improve system reliability. A noniterative fault-location technique breakers cannot be applied in dc systems due to the lack of
using a probe power is also presented in this paper. This probe zero crossing in the dc current. Modification to existing circuit
power can also be used for a pilot test before main CB reclosing to
breakers (CBs) is possible, but this drives up cost and lead
avoid system issues that can be expected when the reclosing fails
due to a permanent fault. The proposed algorithm can be imple- times [5]. DC switchgear and CBs are expensive and may not
mented and executed by an intelligent electrical device for indi- always be available for certain systems [5].
vidual node. The proposed concepts have been verified with com- A microgrid must have multiple terminals, and voltage-
puter simulations and hardware experiments. source converters (VSCs) are generally used to interface
Index TermsDC power systems, fault location, microgrid, individual sources to the dc bus because the classical line-com-
power system protection. mutated converters (LCCs) are very difficult to use in anything
but point-to-point systems [6]. But the insulated-gate bipolar
transistors (IGBTs) in a VSC lose control when a fault occurs
I. INTRODUCTION on the dc bus and the freewheeling diodes act as a bridge recti-
fier feeding the fault. The challenge associated with protection
of VSC-based microgrid systems is that the fault current must

C OMPARED TO high-voltage dc (HVDC) transmission


systems, the dc distribution system is a relatively new
concept in electric power systems. DC microgrids have many
be detected and extinguished very quickly as the fault current
withstand rating of typical VSCs is generally only twice the
converter full-load rating [6]. Semiconductor-based CBs have
advantages over traditional ac distribution systems. While ac been investigated and they have been used for fast dc current
and dc microgrids require power-electronic converters in order interruption and overcurrent limitation [5], [7], [8].
to connect a variety of sources to a common bus, dc systems In addition to the fault detection and interruption, locating the
need less stages of conversion for both ac and dc output sources fault in the bus is an important technique for fast recovery from
[1][3]. Furthermore, for a given cable, dc systems can deliver the fault. Although the line impedance method and traveling-
times more power than ac systems. This is because the us- wave method have been adopted as the industry standard for ac
able power is based on the rms values in an ac system, while systems [9], it is difficult to directly apply to dc systems due to
the dc power is based on constant current and voltage. DC sys- the inherent absence of frequency and phasor parameters.
tems do not suffer from skin effect, which allows the current to This paper proposes a dc bus microgrid fault protection
flow through the entire cable, and not just the outer edge. This method including backup protection that allows the fault to be
decreases losses and allows the dc system to use a smaller cable detected and isolated without de-energizing the entire system.
for the same amount of current [1], [4]. This is done through the use of a ring bus with overlapping
nodes and links controlled by intelligent electronic devices
(IEDs). Also proposed is a noniterative, deterministic fault-lo-
Manuscript received September 30, 2012; revised February 26, 2013, cation technique using a probe power unit. The information on
April 09, 2013, and May 13, 2013; accepted June 05, 2013. Date of publi- fault location is extracted from the probe current. The probe
cation July 02, 2013; date of current version September 19, 2013. Paper no.
TPWRD-01040-2012. power unit can also be used for a pilot test to determine whether
The authors are with the Department of Electrical Engineering, University of the fault is temporary before main CB reclosing to avoid system
Colorado, Denver, CO 80217-3364 USA damage that can be expected when the fault is permanent.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. The conceptual diagram of the proposed ring-bus dc micro-
Digital Object Identifier 10.1109/TPWRD.2013.2267750 grid system is shown in Fig. 1.

0885-8977 2013 IEEE


PARK et al.: DC RING-BUS MICROGRID FAULT PROTECTION AND IDENTIFICATION OF FAULT LOCATION 2575

Fig. 2. Schematic diagram of a fault in a dc bus. The fault current can have two
components from the sources and the bus capacitors.

Fig. 1. Ring-bus dc microgrid system with nodes and links.

II. DC BUS MICROGRID

A. Possible Faults
Fig. 3. Simulation: (Top) Fault current when the fault is 10% and 90% length
Two types of faults exist in dc bus systems: line-to-line and of the 2-km bus segment from the source. The fault current shows fast rising,
line-to-ground fault. A line-to-line fault occurs when a path be- peak oscillation that decays fast. (Bottom) Fault current with a fault resistance of
0.1 and 0.9 at 50% length of the 2-km bus segment. Oscillation is damped
tween the positive and negative line is created, short-circuiting with high fault path resistance.
the two together. A line-to-ground fault occurs when a path be-
tween either the positive or negative pole and ground is created.
A line-to-ground fault is the most common type of fault [10], of the fault path. The fault currents with different fault resis-
[11]. tance (0.1 and 0.9 ) at 50% length of a 2-km bus segment
VSCs may experience internal switch faults that can cause are also shown in Fig. 3. It can be seen that the oscillation is
a line-to-line fault. This is a terminal fault for the device that substantially damped with high fault path resistance.
cannot be cleared and, in most cases, it requires replacement
of the device. Hence, a dc fuse would be a proper protection B. Fault Protection Techniques
measure for this kind of fault. In ac systems, the ac-side CB Protection of dc systems has been done with dc protective
will trip for such faults. switchgear as well as conventional ac devices, such as CBs and
The fault current in a dc bus, which is shown in Fig. 2, consists fuses. Although ac devices have advantages, such as low cost,
of two components, current fed by sources and bus capacitors, maturity of technology, and shorter lead time, dc devices are a
and can be given as better option whenever possible. DC protective devices can in-
terrupt constant current faster than their ac counterparts to iso-
late faulted lines and maintain the operation of unfaulted lines
[6].
(1) Although ac CBs result in the longest interruption time be-
cause of their mechanical restrictions, using ac CBs on the ac
where is the line voltage, and are the equivalent system side of the VSC is the most economical way to protect the dc
resistance and inductance, and is the equivalent capacitance system [12]. Currently, the best interruption time for an ac CB
in the fault path. The equivalent impedance of the fault path, is two cycles [13]. In conjunction with ac CBs, differential pro-
including fault and bus impedance, determines the natural fre- tection can be used for back-to-back or two-terminal transmis-
quency and damping factor of the fault current. The simu- sion systems [14], [15]. One relay could monitor the ac current
lated fault currents are shown in Fig. 3. A 350-V dc bus that has at the sending VSC as well as the receiving VSC or a communi-
three sources and a load feeds the resistive fault. Fault currents cation link would be required for the current readings to be sent
when the fault occurs at 10% and 90% length of the 2-km bus between relays at two terminals. If the current entering does not
segment from the source are shown in the top figure. The fault match the current leaving, the differential relay will trip the ac
current shows fast rising and peak oscillation, and the amplitude CB. However, it is problematic because this scheme shuts down
and oscillation frequency depend on the equivalent impedance the entire system. It is especially so in the case of ground faults
2576 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 4, OCTOBER 2013

where the faulted line could be separated and rest of the system
could keep running in monopolar mode [16] or in loop-type bus
[17]. AC CBs are also inconvenient in multiterminal systems
[6]. Fuses on the ac side are generally not a good solution for dc
system protection because a fuse is a slow thermal device that
is generally not resettable.
To overcome the limitations of fuses and traditional ac CBs
in dc systems, solid-state CBs have been investigated. Power
devices, such as gate turn-off thyristors (GTOs), IGBTs, and
insulated-gate commutated thyristors (IGCTs) are used. Such
devices have different characteristics: GTOs have high blocking
capability and a low conduction loss, but switching speed is
slow [18], [19]. IGBTs are widely used in the low-voltage (LV)
systems [20]. IGBTs offer fast interruption time and an ability to
withstand short-circuit currents [19], but have high conduction
losses [18], [19], [21]. IGCTs have relatively low conduction
loss and high turnoff capability. The IGCTs switching speed is
lower than IGBT, but it may not be a concern for a CB [21]. The
solid-state CBs needs to be bidirectional to allow power flow in
either direction. The bidirectional CB generally consists of two
switches in series with one opposing the other.

C. Fault-Location Techniques Fig. 4. Detailed diagram of the proposed protection system. Each IED controls
node/link CBs, communication links, and probe power unit.
Several methods have been investigated for locating faults
in ac systems. Fault location can be determined using the com-
puted reactance based on recorded fault current and voltage
complete shutdown of the microgrid. Rather, only the affected
information at one terminal of a line [22], [23]. Fundamental
section is isolated and de-energized. This is demonstrated with
phasor information [24], phasor measurement unit (PMU)
[25], and fault voltage sag [26] can be used as well. The trav- a ring-bus configuration for the dc bus, creating several zones of
eling-wave method computes the difference in time of arrival protection that can be defined using overlapping nodes and links
for a transient wavefront at two or more locations connected within the bus. Each node consists of three CBs, and two CBs at
to a fault to locate the fault [27], [28]. The traveling-wave each end of a bus segment form a link. This can be implemented
method has gained popularity due to the commoditization of for the positive and negative pole in bipolar systems. At each
global positioning system (GPS) receivers for accurate time node, a probe power unit will be installed to locate the fault and
synchronization. However, the requirement of phasor infor- test the bus for reclosing. A detailed diagram for the proposed
mation, two-terminal measurements, high sampling rate, and system is shown in Fig. 4.
training data limit the practicality of the method. Also, there is The proposed protection scheme consists of the following
an inherent limitation for dc systems which lack frequency and components.
phasor information.
The existing dc fault-location techniques use rate of current A. Fault Detection and Isolation
rise, magnitude of current, current oscillation pattern [12], con- An IED monitors and controls the node and links. The cur-
tinuous wavelet transform [29][31], distributed parameter line
rents flowing through the assigned CBs are continually moni-
model [32], iterative estimation using reference voltages [33],
tored for fault detection. Predefined thresholds and current read-
and artificial neural networks [30], [34]. The accuracy of the
ings from adjacent IEDs will be used for overcurrent and differ-
aforementioned methods shows promise; however, the depen-
ential current fault detection. The goal of the fault detection unit
dence on two-terminal measurements restricts the practical uses.
The instrumental aspects, such as the impact of sensor error and is to detect the abnormal current in the bus segment and isolate
communication delay, have been investigated in [35]. Further- the fault as quickly as possible.
more, because the dc fault current rises so quickly, it may have Assuming a fault at the point A in Fig. 4, IEDs in Zone 7 and
to be interrupted before some useful information for the fault 8 will detect the abnormal currents, which can be seen in Fig. 5.
location can be obtained. Also, it may be difficult to extract the Since the current sensor in the faulted link will detect more cur-
necessary information for fault location at the time of the fault, rent due to the feeding current from the source, the IED will trip
because the fault current is determined by other bus segments the CB in the faulted link first to separate the faulted section
and components as well as fault impedance. only. However, for a low resistance fault [Fig. 5(a)], the fault
current can rise fast enough to trigger overcurrent fault for all of
III. PROPOSED FAULT PROTECTION METHOD the CBs in the node. In this case, a reclose and restore procedure,
Unlike other previously presented methods for dc systems which will be explained in Section III-C, will restore the intact
[12], [36], the proposed protection method does not require a bus segments. In case of the high fault resistance [Fig. 5(b)],
PARK et al.: DC RING-BUS MICROGRID FAULT PROTECTION AND IDENTIFICATION OF FAULT LOCATION 2577

Fig. 6. Schematic diagram of the probe power unit. A probe power unit consists
Fig. 5. Fault currents. (a) Low fault resistance case. (b) High fault resistance of probe capacitor, probe inductor, power source, and connection switches.
case. (c) Fault currents in load node.

proposed protection scheme, a probe power unit is used to test


the fault current may not exceed the threshold; however, this can the fault status of the bus segment before reclosing the main CB.
readily be detected by differential current. When a CB is tripped A circuit diagram of the probe power unit is shown in Fig. 6. The
by overcurrent, the CB in the other end of the link will trip by probe unit consists of a capacitor, reactor, power source (e.g., a
the status communication to separate the faulted segment, un- battery), and CBs. The power source applies a certain voltage
less it is already tripped by its own overcurrent threshold. that is just high enough to inject a probe current to see if the fault
persists. The IED will not detect the return current if the fault
B. Breaker Failure Detection
was cleared. The capacitance can be determined accordingly to
After a fault is detected and trip signals are sent, the IED en- extract the characteristics of the bus segment in the fault path.
ters the breaker monitoring mode to ensure that the faulted link Since the energy stored in the probe unit is finite, the probe
is de-energized. If the link has not been de-energized due to the current will be small and extinguished quickly. Therefore, the
CB open failure, the IED will open all of its breakers and broad- reclosing can be conducted much safer because the main CB
cast status signals through communication links. The adjacent will be closed only when no-fault status is confirmed.
IEDs will open the CB on the link to separate the faulted node. The location of the fault can be identified by the analysis on
The remainder of the sources and loads can continue to operate the return current when the fault is present. The proposed fault-
on the ring bus once the faulted segment is isolated. Even with location method using the probe power unit and selection of
multiple faulted segments, the system can operate partially if the probe unit components will be described in detail in Section IV.
segments from the main source to some loads are intact. The system will return to normal operation if the fault is
For example, if a fault is detected at point B in Fig. 4 but cleared, but in case a permanent fault is still detected, the IED
CB fails, a signal from the Zone 7 IED would be sent to will lock out the zone. The IED can identify a permanent fault
the Zone 8 IED after opening and . The Zone 8 IED by the re-closing sequence using the probe power unit. A se-
would trip . At this point, Zone 7 has been de-energized lected number of attempts will be made to reclose. The number
and locked out, meaning that the zone controller will not try to of retry depends on the bus configuration and related code. After
automatically reclose and restore the zone. Restoring the zones attempts without success, the IED determines that the fault is
after a lockout condition requires a manual restore, after the fault permanent and will not allow the breaker to close. A flowchart
has been removed from the system. of the protection logic can be seen in Fig. 7.

C. Reclose and Restore IV. PROPOSED FAULT-LOCATION METHOD


Once the faulted link was successfully separated and de-en-
A. Fault Segment Modeling With the Probe Power Unit
ergized, the IED will attempt to reclose and restore. Faults
are often temporary [37], caused by debris, animals, or other Once the faulted bus segment is isolated, a second-order RLC
transients (e.g., lightning) contacting an energized line or bus. circuit can be formed with the probe power unit through the fault
The temporary faults will clear themselves after current flows path as shown in the equivalent circuit shown in Fig. 8. When
the switch in the probe power unit is closed, the dynamics
through the fault path. The reclose and restore mode allows the
of the probe current can be expressed as
IED to autonomously restore power back to the de-energized
zone. This is done by waiting a certain amount of time after the
(2)
trip signals have been sent. After that, the IED will send close
commands to all of the breakers. The waiting time depends The equivalent resistance and inductance of the fault path will
on system configuration. For example, the minimum reclosing be given as the sum of line and fault resistances and the line and
time for the high-voltage ac CBs is 0.3 s in IEEE standard [38]. probe inductance, respectively. The line leakage capacitance
So far, the bus CBs have been reclosed without knowing the can be neglected because the capacitance of the probe capacitor
status of the fault. If the fault has not been cleared, the same fault is significantly larger. The probe capacitor and probe inductance
current would flow again and it could damage the system. In the will determine the frequency of the probe current. Because of
2578 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 4, OCTOBER 2013

Fig. 8. Equivalent circuit of the faulted bus segment with the probe power unit.

where and are the cable resistance and inductance to fault


location, which are defined as

(6)
(7)

where is the fault resistance, is the probe unit inductor,


is the probe unit capacitor, and and are the resistance
and inductance for unit cable length, respectively. The distance
to fault location and overall cable segment length is given as
and .
Since there is no driving voltage in the circuit except the ini-
tial probe capacitor voltage, the probe current can be given
as a zero-input response of the RLC circuit

(8)

where is attenuation and is the damped resonance fre-


quency that can be given as follows. and are constants
from boundary conditions, is the natural frequency, and is
the damping factor

(9)

(10)

(11)

(12)

Fig. 7. Flowchart of the proposed protection algorithm. The initial conditions for the line probe circuit are as follows:

(13)
the large ratio of power cable [39], the probe current will (14)
decay too fast without probe inductance. Hence, the fault circuit (15)
components, including the probing unit components, are given
as where , and are the initial current in the probe circuit,
probe power unit capacitor voltage, and its initial value, respec-
tively. Then, the constants in (8) become
(3)
(16)
(4)
(5) (17)
PARK et al.: DC RING-BUS MICROGRID FAULT PROTECTION AND IDENTIFICATION OF FAULT LOCATION 2579

D. Selection of Probe Capacitance and Inductance


Although the probe current will be underdamped if the probe
circuit meets the following criteria,

(23)

enough information for fault location cannot be obtained if the


probe current decays too fast. Hence, the damping factor should
be set to a low value to get a clear current oscillation lasting long
enough.
From (12), the capacitance and inductance ratio can be de-
Fig. 9. Probe current waveform. : Initial current in the probe circuit. : fined as follows as a function of damping ratio and resistance.
Probe current. : Probe current envelope. : Probing period.

(24)
An example of the probe current is shown in Fig. 9.
To determine , a full segment resistance is used because the
B. Identification of Fault Location damping factor is largest when a fault occurs at the length
with the given fault probe circuit capacitance and induc-
The underdamped response frequency (10) of the probe cur- tance . If a fault location is at will decrease
rent is a function of natural frequency and damping factor. If the times.
damping factor is small enough (controllable with the probe ca- From (21), the time period for the probe current to decrease to
pacitor and inductor), the damped response frequency becomes a reasonably small value, for example, 1 A, can be determined
very close to the natural frequency, which is a function of in- as
ductance of the faulted segment , probe inductance , and
probe capacitance .
(25)
(18)
(26)
Because the capacitance and inductance of the probe circuit (
and ) and unit inductance of the line are known parame- Therefore, the probe power unit inductance and capacitance
ters, the distance to the fault location can be readily calculated can be determined for a given probing period as follows:
from the probe current frequency using (18)
(27)
(19)
(28)
The damped resonance frequency can be obtained from sam-
pled current data using a fast Fourier transform (FFT) algorithm. E. Analysis Resolution
C. Identification of Fault Resistance The resolution of FFT analysis on probe current is critical for
an accurate fault-location result, because it is based on the fre-
When the probe current is sampled, the envelope of the cur-
quency measurement as can be seen in (19). The FFT resolution
rent can be extracted with the peak points of the sampled current.
is determined as
Then, the fault resistance can be identified using the envelope
waveform. From (8), the upper envelope of the current will be
given as (29)

(20) where is the unit frequency of FFT spectrum, is the sam-


pling frequency, and is the point number of FFT analysis.
where is the peak of the current envelope. Using the current Also, the number of data for fault resistance calculation (21)
envelope and sampled time data, the attenuation and the fault and (22) can be given as
resistance can be computed as follows:
(30)
(21)

Once the attenuation is identified, the fault resistance can be V. SIMULATION RESULT
calculated using (9)
Initial verification of the proposed protection scheme was
(22) performed with computer simulations using PSCAD and
2580 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 4, OCTOBER 2013

Fig. 10. Simulation: PSCAD model for the four-terminal microgrid that consists of three power sources and a load. The power sources are modeled with dc
voltage sources and a capacitor.

TABLE I
SIMULATION PARAMETERS

Fig. 11. Simulation: Bus currents and (Top) and and (Bottom) in
the Fig. 10 model. The difference in and can be used by IED for faulted
MATLAB. Simulation parameters and PSCAD model can be segment detection. The current that is close to the fault changes the direction
found in Table I and Fig. 10, respectively. because of low fault resistance, which can trigger the differential current fault.
After the separation of the fault segment, changes the direction to charge the
A low resistance fault [Fig. 5(a) case] simulation shows the capacitor in the source/load.
bus currents and voltage in Fig. 11. Bus currents and
(Top) and and (Bottom) in Fig. 10 are shown. In addi-
tion to the absolute current magnitude, the difference in and After the faulted segment is separated by IEDs, it is tested by
can be used by the IED for faulted segment detection and the probe power unit to confirm the fault status and location. A
isolation. The current changes the direction because of the line-to-line fault is simulated at a 1-km point in a 2-km bus seg-
low fault resistance, which triggers the differential current fault. ment. For the given cable parameters in Table I, the capacitance
Because of the high fault current and bus voltage drop, fast iso- and inductance value of the probe power unit components can
lation of the faulted segment is critical to minimize the effect of be computed using (27) and (28) as 27 F and 6.57 mH, respec-
the fault. tively, with 0.025 damping factor and 50-ms probing period
PARK et al.: DC RING-BUS MICROGRID FAULT PROTECTION AND IDENTIFICATION OF FAULT LOCATION 2581

Fig. 14. Simulation: Fault-location error in terms of fault position and fault
Fig. 12. Simulation: (Top) Probe current. (Bottom) FFT analysis result on resistance. The range of fault position and fault resistance range is 0%100%
the probe current. Probe power unit capacitance and inductance is 27 F of segment length and 00.5 , respectively.
and 0.6 mH, respectively. The FFT result clearly shows damped oscillation
frequency . The fault at 1 km is located with 0.02% error.

Fig. 15. Simulation: Fault-location error in terms of sampling frequency and


FFT points. The range of sampling frequency and FFT point is 10100 kHz
and 10100 times of switching frequency, respectively. It can be seen that the
Fig. 13. Simulation: (Top) Probe current envelope. (Bottom) Estimation of at- fault-location error becomes small if the sampling frequency is high enough.
tenuation . Attenuation and fault resistance (0.1 ) are identified with 0.01%
and 0.04% error, respectively.
zero to 0.5 of fault resistance, 10 to 100 kHz of sampling fre-
quency, and 10 to 100 of FFT points have been tested. The
. The minimum oscillation frequency of the probe current is fault position and fault resistance determine the probe current
593 Hz from (18). The damping factor and probing period are frequency and attenuation. The sampling frequency and FFT
design parameters. points affect the accuracy of the FFT analysis result. Fig. 14
The probe current flowing through the fault path by the shows that the fault-location error is small unless the fault path
voltage pulse applied by the probe power unit, 100 V in this is very short with large resistance. This is because the large fault
simulation, is shown in Fig. 12. The probe current decays as resistance makes the attenuation of probe current so high that the
designed and clearly shows the oscillation frequency . For enough data cannot be sampled for accurate frequency extrac-
the fault at 1 km on the bus segment, the frequency is 778.95 tion and, in turn, fault location. An example of high resistance
Hz. The FFT analysis extracts the frequency as 779.0 Hz and fault current can be seen in Fig. 3. It is also shown in Fig. 15 that
the fault location was identified using (19) with 0.02% error. the fault-location accuracy can be maintained small with a high
From the probe current waveform, the current envelope was enough sampling frequency and number of FFT points 40
extracted as shown in Fig. 13. The attenuation is computed kHz and in this simulation.
using (21) and it is used to calculate the fault resistance with
(22). The identification error for the attenuation and the fault VI. EXPERIMENTAL VALIDATION
resistance was 0.01% and 0.04%, respectively. The proposed fault detection, isolation, and location methods
The accuracy of the proposed fault-location method is tested have also been validated on a scaled-down hardware test bed. A
with respect to the wide range of variables, such as fault posi- 1-mH inductor has been used to implement the 1-km bus seg-
tion, fault resistance, sampling frequency, and FFT points. The ment. The line stray capacitances were neglected. The imple-
fault position varying from 10% to 100% of the bus segment, mented experiment setup has higher resistance (1.3 ) than ex-
2582 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 28, NO. 4, OCTOBER 2013

Fig. 18. Experiment: Contactor B71 open failure is simulated. (Top) Bus
voltage. (Middle) Fault current. (Bottom) Contactor control signals. It can be
Fig. 16. Experiment setup. (a) Current probes. (b) Contactor drivers. (c) DSP seen that the fault current keeps flowing after 0.04 s because of the failure of
control board. (d) Analog signal interface. (e) B83 contactor. (f) B71 contactor. B71. IED opens B73 and B74 after a predefined time to isolate the fault.
(g) B72 contactor. (h) B73 contactor. (i) Fault IGBT. (j) Line inductor .
(k) Probe power unit capacitor . (l) DC power switch . (m) Probe power
unit inductor .

Fig. 19. Experiment: (Top) Probe current sampled at 50-kHz frequency. De-
tected peak points and the current envelope drawn with the calculated are
Fig. 17. Experiment: Fault is triggered at 0.04 s. (Top) Bus voltage. also shown. (Bottom) Frequency analysis with the FFT algorithm implemented
(Middle) Fault current. (Bottom) Contactor control signals. It can be seen in the DSP-based control board.
that the fault current is interrupted and the bus voltage recovers after the fault
segment is isolated.

1-k resistor has been used for the probe power switch and
pected so the current decays too fast. Hence, the probe unit in- the current limiting resistor , respectively. A manual switch
ductance was reduced to 67 H to obtain enough frequency has been used for the probing mode switch . The experimental
and current data for analysis and 100-m line resistance and setup is shown in Fig. 16.
1.2- fault resistance were assumed. For the probe unit ca- A ground fault is triggered at 0.04 s and the dc power
pacitors , 27 F was selected. supply feeds about 3-A fault current with high peak transient. It
Two nodes and a link in Fig. 4 (B83, B71, B72, B73) have can be seen that the faulted link is quickly isolated by B83 and
been implemented using dc contactors (EV200, TE Connec- B71 in Fig. 17. The time to extinguish the fault current can be
tivity). In this experiment, one DSP-based (TMS320F28335, improved if solid-state CBs are used [40]. It is shown that the
Texas Instrument) controller controls both nodes using the cur- bus voltage is recovered to the normal level when the faulted
rent readings from current probes (A622, Tektronics and K100, segment is isolated. Fig. 18 also shows that the controller detects
AEMC). A ground fault at a 1-km point has been simulated that the current keeps flowing after B71 closes command and it
using an IGBT (IXGN60N60C2D1, IXYS). The probe power further opens B72 and B73 to isolate the fault and lockout the
unit in Fig. 6 has also been implemented using capacitors and zone when a breaker open failure is simulated in B71.
an autotransformer for a variable inductance. A two-channel The control mode was changed to probing mode from detec-
dc power supply (GPC-3030, Instek) has been used for sup- tion mode manually by switch in this experiment. In the fault
plying 24-V dc-bus power and for probing power instead of bat- probing mode, probing power switch is toggled by IED to
teries. A 24- resistor bank has been used to draw 1-A load cur- inject the probe current into the fault circuit. Fig. 19 shows the
rent in normal operation. A metaloxide semiconductor field-ef- probe current sampled at the falling edge of the probing pulse.
fect transistor (MOSFET) (IRFZ30, International Rectifier) and The natural frequency of the probe current is 952 Hz and 909
PARK et al.: DC RING-BUS MICROGRID FAULT PROTECTION AND IDENTIFICATION OF FAULT LOCATION 2583

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[35] H. Li, W. Li, M. Luo, A. Monti, and F. Ponci, Design of smart MVDC Jared Candelaria received the M.S.E.E. degree
power grid protection, IEEE Trans. Instrum. Meas., vol. 60, no. 9, pp. from The University of Colorado,. Denver, CO,
30353046, Sep. 2011. USA, in 2012.
[36] L. Tang and B. Ooi, Locating and isolating DC faults in multi-terminal He is a Protection Engineer with Schweitzer Engi-
DC systems, IEEE Trans. Power Del., vol. 22, no. 3, pp. 18771884, neering Laboratories in the Engineering Services Di-
Jul. 2007. vision, Golden, CO, USA. There he performs studies
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IEEE Standard C37.04-1999, 1999. Mr. Candelaria is a registered Professional Engi-
[39] A. Bergen and V. Vittal, Power Systems Analysis, 2nd ed. Upper neer in the State of California. His research interests
Saddle River, NJ: Prentice-Hall, 2000. include power systems applications, power system protection, and HVDC.
[40] J. D. Park and J. Candelaria, Fault detection and isolation in low-
voltage dc-bus microgrid system, IEEE Trans. Power Del., vol. 28,
no. 2, pp. 779787, Apr. 2013.
[41] J. Proakis and D. Manolakis, Digital Signal Processing, 3rd Liuyan Ma received the B.Eng. and B.Sc. degrees in
ed. Upper Saddle River, NJ: Prentice-Hall, 2000. management from Beijing Technology and Business
University, Beijing, China, in 2010 and is currently
pursing the M.Eng. degree in electrical engineering
from the University of Colorado, Denver, CO, USA.
Her research interests include smart grid, mi-
crogrid, distributed generation, and engineering
management. She was with General Mills, Beijing,
as a management trainee for about a year, where she
gained management skills and experience.
Jae-Do Park (M07) received the Ph.D. degree in
electrical engineering from the Pennsylvania State
University, University Park, PA, USA, in 2007.
Currently, he is an Assistant Professor of Elec-
trical Engineering, University of Colorado, Denver, Kyle Dunn (S08) received the B.S.E.E. degree with
CO, USA. Prior to his arrival at the University of an emphasis in power systems from the University of
Colorado, he was Manager of Software and Controls Colorado, Denver, CO, USA, in 2013.
with Pentadyne Power Corporation, Chatsworth, Mr. Dunn is a Substation Field Engineering Intern
CA, USA, where he took charge of control algorithm at Xcel Energy, Denver. His duties at Xcel include
design and software development for the high-speed large equipment replacements, substation automa-
flywheel energy storage system. He is interested in tion, supervisory control and data acquisition, and
energy and power system research and education, including electric machines analysis of historical equipment data for replacement
and drives, energy storage and harvesting systems, renewable energy sources, schedules. His research interests include power
grid-interactive distributed generation, microturbine control, and microgrid systems, embedded systems, and high-performance
systems. computing.

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