FPGA Implementation of High Speed 8bit Vedic Multiplier Using Barrel Shifter

IDL - International Digital Library Of
Technology & Research

Volume 1, Issue 2, Mar 2017 Available at: www.dbpublications.org
International e-Journal For Technology And Research-2017
FPGA Implementation of High Speed 8bit Vedic

Multiplier using Barrel Shifter
Sahana Raj B S Punith Kumar M B
Dept. of ECE, PESCE
Dept. of ECE, PESCE Mandya, India.
Mandya, India. punithpes@gmail.com
sahanagandhi@gmail.com
Abstract In todays world Vedic mathematics has Multiplication is an important fundamental function
proved to be the most robust technique for arithmetic in arithmetic operations. Multiplication-based operations such
operations. In contrast, conventional techniques for as Multiply and Accumulate(MAC) and inner product are
multiplication provide significant amount of delay in hardware among some of the frequently used Computation- Intensive
implementation of n-bit multiplier. Moreover, the Arithmetic Functions(CIAF) currently implemented in many
combinational delay of the design degrades the performance Digital Signal Processing (DSP) applications such as
of the multiplier. Hardware-based multiplication mainly convolution, Fast Fourier Transform(FFT), filtering and in
depends upon architecture selection in FPGA or ASIC. microprocessors in its arithmetic and logic unit. Since
A barrel shifter is a digital circuit that can shift a data word by multiplication dominates the execution time of most DSP
a specified number of bits in one clock cycle. It can be algorithms, so there is a need of high speed multiplier.
implemented as a sequence of multiplexers (mux.), and in Currently, multiplication time is still the dominant factor in
such an implementation the output of one mux is connected to determining the instruction cycle time of a DSP chip. The
the input of the next mux in a way that depends on the shift demand for high speed processing has been increasing as a
distance. result of expanding computer and signal processing
applications. Higher throughput arithmetic operations are
Keywords- Vedic Mathematics, Barrel Shifter, FPGA, Xilinx. important to achieve the desired performance in many real-
time signal and image processing applications. One of the key
I. INTRUDUCTION arithmetic operations in such applications is multiplication and
Arithmetic operations such as addition, subtraction the development of fast multiplier circuit has been a subject of
and multiplication are deployed in various digital circuits to interest over decades. Reducing the time delay and power
speed up the process of computation. Arithmetic logic unit is consumption are very essential requirements for many
also implemented in various processor architectures like applications.
RISC, CISC etc. Arithmetic operations unit is a fundamental
building block of the central processing unit CPU) of a Vedic mathematics covers explanation of several modern
computer, and even the simplest microprocessors contain one mathematical terms including arithmetic, geometry (plane, co-
for purposes such as maintaining timers. The processors found ordinate), trigonometry, quadratic equations, factorization and
inside modern CPUs and graphics processing units (GPUs) even calculus.
accommodate very powerful and very complex Arithmetic Vedic Mathematics is the name given to the ancient
operations unit; a single component may contain a number of system of Indian Mathematics which was rediscovered from
Arithmetic operations unit. In general, arithmetic operations the Vedas between 1911 and 1918 by Sri Bharati
are performed using the packed-decimal format. This means KrsnaTirthaji (1884-1960). According to his research all of
that the fields are first converted to packed-decimal format mathematics is based on sixteen Sutras, or word-formulae. For
prior to performing the arithmetic operation, and then example, 'Vertically and crosswise` is one of these Sutras.
converted back to their specified format (if necessary) prior to
placing the result in the result field. The objectives of this work are listed below:
IDL - International Digital Library 1|P a g e Copyright@IDL-2017

i. Design a method to put into effect a high speed Vedic design degrades the performance of the multiplier. Application
multiplier using barrel shifter. of the Sutras saves a lot of time and effort in solving the
problems, compared to the formal methods presently in vogue.
ii. Develop an algorithm to implement sutra by modified Though the solutions appear like magic, the application of the
design of Nikhilam Sutradue to its feature of Sutras is perfectly logical and rational
reducing the number of partial products.
iii. The barrel shifter used at different levels of design, III. PROPOSED WORK
drastically reduces the delay when compared to
conventional multipliers. The high speed implementation of such a multiplier
has wide range of applications in image processing, arithmetic
iv. The hardware implementation of Vedic multiplier logic unit and VLSI signal processing. The propagation delay
using barrel shifter contributes to adequate
of array multiplier and conventional Vedic multiplier
improvement of the speed in order to achieve high
outturn. implementation on FPGA is very high. Since
propogation delay is high it reduces the speed of the device. In
our design we reduce the propagation delay by implementing
II. LITERATURE SURVEY the vedic multiplier on FPGA using barrel shifter.
We assume that the multiplier is X and multiplicand
is Y. Though the designation of the numbers is different but
the architecture implemented is same to some extent for
Multiplication is one of the basic arithmetic operations and it
evaluating both the numbers. Mathematical we solve using
requires substantially more hardware resources and processing
nikhilam sutra.
time than addition and subtraction. In fact, 8.72% of all the
instruction in typical processing units is multiplication.
The hardware deployment is partitioned into three blocks.
Comparative study of different multipliers is done for low
i. Base Selection Module
power requirement and high speed. UrdhvaTiryakbhyam
ii. Power index Determinant Module
algorithm of Ancient Indian Vedic Mathematics which is
iii. Multiplier.
utilized for multiplication to improve the speed, area
The base selection module (BSM) is used to select
parameters of multipliers. Vedic Mathematics suggests one
the maximum base with respect to the input numbers. The
more formula for multiplication of large number i.e.
second sub-module power index determinant(PID) is used to
Nikhilam Sutra which can increase the speed of multiplier
extract the power index of k1 and k2. The multiplier
by reducing the number of iterations .
comprises of base selection module (BSM), power index
determinant (PID), subtractor, barrel shifter, adder/subtractor
Vedic mathematic is an ancient technique with
as sub-modules in the architecture.
unique approach and it has got different sutras. Here,
Nikhilam Navatascaramam DasatahSutra is used , which is
efficient in speed of the multiplier. The implementation of an IV. VEDIC MATHEMATICS
8-bit Vedic multiplier enhanced in terms of propagation delay
when compared with conventional multipliers. In our design
History of Vedic Mathematics:Vedic mathematics is part of
we have utilized 8-bit barrel shifter which requires only one
four Vedas (books of wisdom). It is part of Sthapatya- Veda
clock cycle for n number of shifts.
(book on civil engineering and architecture), which is an upa-
veda (supplement) of Atharva Veda. It covers explanation of
Vedic mathematics is an ancient technique which was used in
several modern mathematical terms including arithmetic,
the time of Vedas. It has got as many as 16 Sutras that can be
geometry (plane, co-ordinate), trigonometry, quadratic
used for different Arithmetic calculation. Vedic Sutras apply
equations, factorization and even calculus. His Holiness
to and cover almost every branch of Mathematics. They apply
Jagadguru Shankaracharya Bharati Krishna Teerthaji
even to complex problems involving a large number of
Maharaja (1884-1960) comprised all this work together and
mathematical operations. Vedic mathematics has proved to be
gave its mathematical explanation while discussing it for
the most robust technique for arithmetic operations. In
various applications.
contrast, conventional techniques for multiplication provide
significant amount of delay in hardware implementation of n-
Algorithms of Vedic Mathematics: Arithmetic operations
bit multiplier. Moreover, the combinational delay of the
such as addition, subtraction and multiplication are deployed
in various digital circuits to speed up the process of

computation. Arithmetic logic unit is also implemented in
various processor architectures like RISC, CISC etc.,Vedic
mathematics has proved to be the most robust technique for
arithmetic operations. In contrast, conventional techniques for
multiplication provide significant amount of delay in hardware
implementation of n-bit multiplier. Vedic Sutras apply to and
cover almost every branch of Mathematics.
Vedic Multiplication: The proposed Vedic multiplier is based

on the Vedic multiplication formulae (Sutras). These Sutras
have been traditionally used for the multiplication of two
numbers in the decimal number system. The multiplier is
based on an algorithm UrdhvaTiryakbhyam (Vertical &
Crosswise) of ancient Indian Vedic Mathematics.
UrdhvaTiryakbhyam Sutra is a general multiplication formula
applicable to all cases of multiplication. It literally means
Vertically and crosswise. It is based on a novel concept Figure 1: Base Selection Module
through which the generation of all partial products can be
done with the concurrent addition of these partial products. Power Index Determinant
V. METHODOLOGY
Assume that the multiplier is X and multiplicand is
Y. Though the designation of the numbers is different but the
architecture implemented is same to some extent for
evaluating both the numbers.
The mathematical expression for modified nikhilam sutra is
given below.
P=X*Y= 2k2 * (X+Z2*2k1-k2) + Z1*Z2....(1)
Where k1, k2 are the maximum power index of input numbers
X and Y respectively. Z1 and Z2 are the residues in the
numbers X and Y respectively.
Base Selection Module

The base selection module has power index
determinant (PID) as the sub-module along with barrel shifter,
adder, average determinant, comparator and multiplexer.
Operation: An input 8-bit number is fed to power index

determinant (PID) to interpret maximum power of number
which is fed to barrel shifter and adder. The output of the
barrel shifter is n number of shifts with respect to the adder The input number is fed to the shifter which will shift
output and the input based to the shifter. Now, the outputs of the input bits by one clock cycle. The shifter pin is assigned to
the barrel shifter are given to the multiplexer with comparator shifter to check whether the number is to be shifted or not. In
input as a selection line. The outputs of the average this power index determinant (PID) the sequential searching
determinant and the barrel shifter are fed to the comparator. has been employed to search for first 1 in the input number
The required base is obtained in accordance with the
multiplexer inputs and its corresponding selection line.
Figure 2: Power Index Determinant

starting from MSB. If the search bit is 0 then the counter index determinant are from base selection module of
value will decrement up to the detection of input search bit is respective input numbers. The sub-section of power index
1. Now the output of the decrementer is the required power determinant (PID) is used to extract the power of the base and
index of the input number. followed by subtractor to calculate the value. The outputs of
subtractor are fed to the multiplier that feeds the input to the
second adder or subtractor. Likewise the outputs of power
index determinant are fed to the third subtractor that feeds the
Multiplier Architecture input to the barrel shifter. The input number X and the
output of barrel shifter are rendered to first adder/subtractor
The base selection module and the power index
and the output of it is applied to the second barrel shifter
determinant form integral part of multiplier architecture. The
which will provide the intermediate value. The last sub-section
architecture computes the mathematical expression in
of this multiplier architecture is the second adder/subtractor
equation1.Barrel shifter used in this architecture.
which will provide the required result.
The two input numbers are fed to the base selection
module from which the base is obtained. The outputs of base
selection module (BSM) and the input numbers X and Y
are fed to the subtractors. The subtractor blocks are required to
extract the residual parts z1 and z2. The inputs to the power

Figure 3: Multiplier Architecture
VI. SIMULATION RESULTS AND DISCUSSION
Here we deals with results obtained by simulation,

synthesis and implementation of Vedic Multiplier module
and their sub modules. Simulation is done in Xilinx ISim
simulator. Synthesis results are obtained using ISE tool.
Implementation is done on Xilinx Spartan-6 CSG324
evolution kit and using ChipScope Pro.
Simulation results of Vedic Multiplier Top module, are

discussed below. Simulation Results of Vedic Multiplier is
shown Figure 4. Inputs a and b are forced to module each
of 8-bit. The output op is obtained which is of 16-bit after
simulation. The inputs values are forced to the module and
simulation is performed to obtain the output. In the above
figure the simulation result of input a=125 and b=75 is
shown. After simulation output op=9375 is obtained. For
different values of inputs, output is obtained after
simulation.
Figure 5: RTL Schematic of Vedic Multiplier
The total power utilization is shown in Figure 6.

After simulation and implementation, the power report is
obtained from Xilinx XPower Analyzer. The total power
utilization of the module obtained after simulation is
0.032W.
Figure 4: Simulation results of Vedic Multiplier module
Synthesis Report of Vedic Multiplier module are

synthesized using Xilinx XST synthesis tool for Xilinx
Spartan-6 CSG324 device. The RTL schematics of module
shown in Figure 5

Figure 6: Power Analysis Report
Figure 7: ChipScope Pro Result

[2] Shamsiahsuhaili and Othmansidek, Design and

The ChipScope Pro tool also interfaces with your
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This unique partnership between Xilinx and Agilent gives
you deeper trace memory, faster clock speeds, more trigger
options, and system-level measurement capability all while

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FPGA Implementation of High Speed 8bit Vedic Multiplier Using Barrel Shifter

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International e-Journal For Technology And Research-2017