Lab6

HW/SW System Debug Lab:

MicroBlaze
HW/SW System Debug Lab: MicroBlaze

Introduction
This lab guides you through the process of debugging the processor system. XPS and ChipScope
will be used to have visibility into both the Hardware and Software of the system.

Objectives
After completing this lab, you will be able to perform:
Add ChipScope Analyzers into a system
System Debugging

Procedure
This lab comprises several steps involving simulation. Below each general instruction for a given
procedure, you will find accompanying step-by-step directions and illustrated figures providing
more detail for performing the general instruction. If you feel confident about a specific
instruction, feel free to skip the step-by-step directions and move on to the next general instruction
in the procedure.

Note: If you are unable to complete the lab at this time, you can download the lab files
for this module from the Xilinx University Program site at http://university.xilinx.com

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 Opening the Project Step 1
Create a lab6mb folder under c:\xup\embedded\labs\. If you wish to continue
with your completed design from lab5 then copy the contents of the lab5mb
folder into the lab6mb folder, otherwise, if you wish to start with a known good
design, then copy the contents of c:\xup\embedded\mb_completed\lab5mb into
the lab6mb folder. Launch Xilinx Platform Studio (XPS) and open the project file
located in c:\xup\embedded\labs\lab6mb.

n Create a lab6mb folder in the c:\xup\embedded\labs directory. If you wish to continue with
your completed design from lab5 then copy the contents of the lab5mb folder into the
lab6mb folder, otherwise, if you wish to start with a known good design, then copy the
contents of c:\xup\embedded\mb_completed\lab5mb into the lab6mb directory.

o Open XPS by clicking Start Programs Xilinx Platform Studio 6.2i Xilinx
Platform Studio

p Click File Open Project and browse to the project which in the directory:
c:\xup\embedded\labs\lab6mb

q Click system.xmp to open the project

Compiler Optimization Step 2

In this section we will look at the performance differences of the compiler
optimization levels. To do this we will remove the timer interrupt service routine
and replace it with a delay loop.

n Using Project Software Platform Settings open the Software Platform Settings GUI

o Click on the Processor and Device Parameters tab

p Delete the timer_int_handler in the Current Value field so the field is blank.

q Copy the system_delay.c file from the c:\xup\embedded\lab_sources\lab6_sources

directory to the current project c:\xup\embedded\labs\labmb6\code.

r Remove system_timer.c from the MyProj project and add the new file system_delay.c

s Set the compiler optimization level to No Optimization by double clicking on the MyProj
title and selecting the Optimization Tab as shown in figure 14c.1, and select the option to
Create symbols for debugging as shown.

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 Figure 14c-1. Compiler Settings - Optimization

t Select Download so the sources are recompiled and loaded to the board. The LEDs should
display the counter still running at 0.1 seconds.

w Set the compiler optimization level to Level 2 and download the project again.

Notice the difference in speed of display increment due to compiler optimizations.

ChipScope Core Instantiation Step 3

Click Project Add/Edit Cores (dialog) and add the ChipScope cores to the
design. Configure the device and the design to the following ports, as shown in
the figure 14c-2.

OPB/IBA Core
CS_ICON_Conrol
SYS_RST
mb_halt dbg_stop
iba_trig_in iba_trig_out
(MicroBlaze) (MicroBlaze)
sys_clk_s OPB_CLK

ICON Core

control

Figure 14c-2. ChipScope Core Connections

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 n Click Project Add Cores (dialog)

o In the Peripherals tab, add the chipscope_icon and chipscope_opb_iba peripherals

p In the Bus connection tab, connect the chipscope_opb_iba as a BA (bus analyzer) device to
the OPB bus.

q In the Ports tab, connect the chipscope_cores as shown in Figure 14c-3.

Figure 14c-3. ChipScope Ports

r In the Parameters tab, configure the chipscope_cores

Choose the chipscope_icon_0 IP instance from the right hand side drop-down box
Select C_SYSTEM_CONTAINS_MDM and << ADD parameter to the list.
Set this value to 1 - This parameter indicates whether the system containing the
ChipScope Icon core contains the OPB MDM peripheral or not. The opb_mdm
debug module is used for communication between MicroBlaze and the
Xilinx.Microprocessor Debugger (XMD) interface.
Choose the chipscope_opb_iba_0 IP instance from the right hand side drop-down box
[CTRL-select] the following parameters from the list:
C_NUM_DATA_SAMPLES
C_ENABLE_TRIGGER_OUT
C_CONTROL_UNITS
C_ADDR_UNITS
C_DATA_UNITS
C_GENERIC_TRIGGER_UNITS
C_TRIGGER_UNIT_MATCH_TYPE
C_GENERIC_TRIGGER_IN_WIDTH
Add them to the parameters list by selecting << ADD.
Set their value as given here:
C_NUM_DATA_SAMPLES = 512 (default)
C_ENABLE_TRIGGER_OUT =1
C_CONTROL_UNITS =1
C_ADDR_UNITS =1
C_DATA_UNITS =1
C_GENERIC_TRIGGER_UNITS =1
C_TRIGGER_UNIT_MATCH_TYPE = basic with edges
C_GENERIC_TRIGGER_IN_WIDTH = 1

s Click Apply and OK

t Some control signals to the MicroBlaze processor are required to enable control and
triggering between the ChipScope Analyzer and the GDB Debugger. In the system.mhs
file add the following two ports under the Microblaze core parameter listing:
PORT MB_Halted = mb_halted

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 PORT DBG_STOP = dbg_stop

w Close and Save the file.

w Select Download to generate the new HW system and link in the SW. Operation should still
be the same.

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 GDB and ChipScope Operation Step 4
This portion of the lab will guide you through using the instantiated cores from
the above sections. Having successfully generated your design it is possible to
begin viewing it in operation using the Gnu debugger and ChipScope Pro tools.

Starting the Gnu debugger (Software Debug)

n In XPS select Tools XMD or using the XMD icon, launch the Xilinx Microprocessor
Debugger (XMD) tool.

o In the XMD dos-type window that opens type mbconnect mdm at the prompt in order to
connect between the processor and host computer using the JTAG port.

Figure 14c-4. XMD Connection Setup

Note: In the last line presented in XMD
Starting GDB server for mdm target (id = 0) at TCP port no 1234, note the port value it
may be necessary shortly.

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 p Return to XPS and select Tools Software Debugger or using the GNU debugger icon
launch the GNU debugger tool. Select the MyProj application in the popup window as
shown in figure 14c-5.

Figure 14c-5. GDB Application selection

q Select Run Connect to target or simply click on the running man

A Target Selection dialogue box will appear.

Select the Target to Remote/TCP : XMD

r Select
Target: Remote/TCP : XMD
Hostname: localhost
Port: 1234 (or the port value noted above)

And click OK

The software code will be downloaded to the evaluation board. Code operation will be halted
at the first line following the main( ) routine. Proper connection between GDB and the
evaluation board can be verified by noting that the colored highlight is green not purple. If
you see purple close the XMD and all GDB windows and return to Starting the Gnu
debugger.

s Select Control >> Continue or simply click on the continue icon

Note the LEDs flashing indicating proper system operation

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 Starting ChipScope Pro (Hardware Debug)

n Launch the ChipScope Pro Analyzer tool from the program group or desktop icon.

o Click on the Open Cable/Search JTAG chain icon. This will identify the devices on the
JTAG chain. Select OK. The ChipScope Pro Analyzer will open along with default Trigger
Setup and Waveform signal windows.

Figure 14c-7. ChipScope JTAG Device Order

p Select File Import. In the Signal Import dialogue click on the Select New File button.

q Browse to the XPS design directory and the select the following file
c:\xup\embedded\labs\lab6mb\implementation\chipscope_opb_iba_0_wrapper\
chipscope_opb_iba_0.cdc and click OK as shown in figure 14c.8

Figure 14c-8. ChipScope Signal Import

The signals associated with the OPB core should be listed in the Trigger Setup and Waveform
signal windows.

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 Trigger/Waveform SetUp Windows
Figure 14c-9 will be a reference for the ChipScope setup windows.

Figure 14c-9. ChipScope Waveform Windows

n Change the Radix of M0:M4 from binary (Bin) to Hexadecimal (Hex) by clicking on the
respective boxes and selecting Hex

o Set M1:TRIG1:OPB_ABUS == 8000_2A00 by selecting and adjusting the value box

p Set M0:TRG0:OPB_CTRL OPB_xferAck bit == 1.

q Adjust the Trigger Condition Equation by selecting the box in the TriggerCondition0
dialogue box that appears. Select M0 and Select M1. The Trigger Condition Equation should
now display M1 && M0. Click OK.

r Set the trigger window depth to 512 and position to 256

s Consolidate OPB_Abus signals by [Shift-Select]-ing OPB_Abus[31] : OPB_Abus[0]. Right

click Add to Bus New Bus.

t Change new bus name from BUS_0 to OPB_Abus[31:0] by right clicking on BUS_0
Rename.

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 u Repeat process for OPB_Dbus[31..0]

v Set up the Output Enable of the Trigger to Pulse (High). This will cross trigger the GDB
debugger.

w Setup the trigger by selecting Trigger Setup -> Run as shown below

The hardware should trigger and then this will cross trigger the SW asynchronous stop in GDB.
Basic ChipScope Pro Trigger settings along with simple waveforms are established.

HW/SW Debug Interaction Step 5

Conclusion
Chipscope HW debug modules can be added as IP modules in EDK, and the ChipScope analyzer
can be used in conjunction with GDB, the GNU debugger in EDK, to provide a debug
environment that allows cross triggering and debug between hardware and software using a shared
JTAG connection.

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