2016 2nd International Conference on Science in Information Technology (ICSITech)

Investigation of PV Balancer Architectures on

Practical Solar Photo Voltaic System
Dokala Udaykiran, P.V.R.L.Narasimham, N.Gouthamkumar and Darisi Sudheerkumar,
Electrical and Electronics Engineering Department
V R Siddhartha Engineering College, Vijayawada, India-520007
udaykiran.dokala@gmail.com, drpvrln@gmail.com, gowthamkumar218@gmail.com, sudhir.darsi@gmail.com

AbstractIn this paper, a trending concept of module-
integrated converter called as photovoltaic (PV) balancers
is presented and verified on a practical data of solar PV
system. This concept enables the maximum power point
tracking for each module, which historically reduces the
requirements for traditional power converters and
significant economical impact on overall configuration of
solar PV systems. In order to demonstrate the
performance of the two possible architectures of PV
balancers validated on a practical photovoltaic system and
compared with the traditional module integrated
converter presented in the literature. Thus, the obtained
simulation results with PV balancers are superior in terms
of power loss, rating, efficiency, regulation, and voltage
stress on switching device.
Keywordsphotovoltaic; maximum power point tracking;
module integrated converters; PV balancer
I. INTRODUCTION
Solar photovoltaic (PV) systems have become more popular
to generate electricity by utilizing solar irradiation under the
back ground of advocating energy conservation with low
emissions. Generally, the PV system consists of number of PV
modules with an appropriate control circuitry to interface with
the grid by means of centralized converters. This centralized
converters are having many shortcomings and for this reason
the string technologies have been brought into existence by
adding more number of strings, in which each string contain
an individual dc-dc converter and maximum power point
tracking (MPPT) to the common dcac inverter [1]. By
connecting individual PV modules into a longer string may
overcome the difficulty of insufficient voltage level but
impotent to maximize the instantaneous energy yield of each
module and also leads the overall system prone to detrimental
shading effects, thus, reducing the power output of the system.
In order to overcome these difficulties and replace the
centralized or string technologies, modulated integrated
converters have been developing in the recent trends of
photovoltaic systems [2].
Modulated Integrated Converters (MICs) can perform MPPT
well for the entire series of panels, which may give optimal
voltages and currents for obtained variations among panels or
variations in illumination of each panel and a permanent
defect or even a temporary shade to a single panel in an array
[3]. In this regard the three traditional structures of MICs
have been invented to achieve the independent MPPT for each
module. Firstly the micro inverter structure presented in Fig.
1(a) output is combined at an AC grid due to its high voltage
output compared to the low output voltage of PV module [4].
These inverters are popular but still having highest cost, low
efficiency and low-voltage transformation ratio. Secondly, the
parallel dc-dc converter structure outputs on each PV module
combined in parallel with a common DC bus, which is shown
in Fig. 1(b). This structure also require high-voltage
transformation ratio but it is somewhat less expensive
compared to micro inverter structure. Finally, the cascaded dc-
dc structure outputs are stacked up in series, which leads to
maintain desirable high voltage transformation ratio at inverter
side as shown in Fig. 1(c). However, these structures are
having one and the other limitations such as high initial
equipment cost, low electrical efficiency, compactness in
design and also unable to maintain inverter output voltage
whenever the mismatch conditions occur [5]. In order to
overcome these limitations of traditional topological structures
of MICs, PV balancer concept with two possible architectures
has been introduced and verified on a hardware testing of PV
system [6]. Consequently, this study has only compared the
cost and equivalent efficiency between PV balancers and
MICs, which are having the same electrical specifications of
low rated PV panel.
Fig. 1. Traditional structures of MICs (a) micro inverters (b) parallel
connection of dc-dc converter (c) series connection of dc-dc converter

978-1-5090-1721-8/16/$31.00 2016 IEEE 226

 2016 2nd International Conference on Science in Information Technology (ICSITech)

This paper presents the performance analysis and
investigations conducted on two possible architectures of PV
balancers through simulations for the practical PV panel of the
system. In this line of research, three modules of practical PV
panels are tested to verify the significance of PV balancer
architectures. The simulation results show that the PV
balancer prototype achieves better in terms of power loss,
efficiency, regulation, and voltage stress as compared to the
traditional MIC prototypes.
The remaining paper is organized as follows: section II
presents the design and operation of PV balancers with two
converter architectures. Section III consists of performance
analysis of the converter topologies. Section IV presents the
detailed simulation results to verify the architecture
prototypes. Section V conclude the investigations of the paper
and introduce the plane of future work.
voltages, an advanced concept of partial power processing in
associated with PV balancers are used. The basic connection
of PV balancer which differs from the traditional MIC is
shown in Fig. 3. In traditional MIC, the output voltage of PV
panel is input to traditional MIC. So, the power rating of MIC
should be designed as per the specifications of PV panel. This
might be a disadvantage for high power rating PV panels
when operating at practical PV systems and interns to lower
efficiency as well initial cost of equipment. A PV balancer is
serially-connected with each PV panel to compensate the
differential voltage between PV panel and DC bus. This
advantage of PV balancer reduces the power rating of about
five times smaller than the rating of traditional MIC.

II. PV BALANCERS
During harsh mismatch conditions the PV modules are
operating at different maximum power points. Compared to
the healthy PV panel the shaded PV panels are produced low
voltage and current. This will leads to voltage fluctuations at
input side of the inverter stage. Here the Fig. 2 shows the V-I
curves of three practical PV panels with different atmospheric
conditions. Due to partial shade the current varies from 0.76 A
to 4.23 A from curve G=150 W/m2 (Irradiation) to curve G=
Fig. 3. Traditional toplogy and PV balancer.
1000 W/m2 and where as the voltage varies from 21.24 V to
23.64 V. The noticeable observation from the Fig. 2 is that the
There are two possible architectures of PV balancers and
less voltage deviation compared to the current deviation [6].
their detailed design aspects mentioned below.
A. Architecture -I
The PV balancers are connected in series with the PV
module and this combination is connected in parallel, which is
positive grounded with the DC bus as shown in Fig. 4.

Fig. 2. V-I Curves of DSP-100M PV panel

Fig. 4. Architecure-I

Here, two possible solutions to reduce the mismatch
conditions due to the partial shade (i) compensating the
differential currents and (ii) compensating the differential
voltages. Compensating the differential currents is one of the
solutions, but due to the limitations of large current deviation,
high rating of compensating device, high power loss and
higher equipment cost [7-8]. For compensating the differential
The DC bus voltage is shared with the PV balancer and the
constant DC bus voltage feed to the inverter. To realize the PV
balancer concept in architecture-I flyback converter is used it
is given in Fig. 5. There are other types of converters also used
for PV balancers such as single-ended primary-inductor
converter, and forward converters [9].

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 2016 2nd International Conference on Science in Information Technology (ICSITech)
For ease of simple demonstration the flyback converter is
integrated into PV balancer in architecture-I.
Fig. 5. Basic flyback converter
The main advantage of this architecture-I is simple in design
and provided high efficiency but it has a disadvantage of high
voltage transformation ratio i.e. if the DC bus voltage is fixed
at 28 V and when the differential voltage is 3 V, the voltage
ratio is nearly about 9:1 for every balancer.
B. Architecture -II
This architecture is similar to the previous one but a simple
modification will differ these two architectures, i.e., the PV
balancer input is fed from the front end converter output. The
front end converter steps down the DC bus voltage to the
optimized value and the basic structure for architecture-II is
given in Fig. 6.
Fig. 6. Architecure-II
In this architecture-II, the flyback converter is used as front
end converter and flipped buck converter for PV balancer. The
basic circuit for flipped buck converter is depicted in Fig. 7.
Fig. 7. Basic flipped buck converter
Even the DC bus voltage is fixed at 28 V and the input of
the PV balancer is step down by the front end converter which
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is about 10 V. If the differential voltage is about 3 V the
voltage transformation ratio is 3:1. Thus the voltage
transformation ratio is reduced in architecture-II. The only
disadvantage of this architecture-II is complicated structure of
connections. With the help of these two architectures the DC
bus feeds the constant inverter input voltage. Generally the
fault tolerance of a PV balancer is also high. If the PV
balancer fails, the PV panel is automatically connected to dc
bus by short circuiting the PV balancer. But, the PV panel
doesnt operate at maximum power point. Suppose, if PV
panel is damaged, the PV balancer will disconnect the PV
module from DC bus.
III. PERFORMANCE ANALYSIS
In order to critically analyze the PV balancer architectures,
the fundamental performance metrics are presented and
mathematically expressed below. The power drawn from the
PV panel under maximum power point condition is expressed
as (1) [6].
PMPP = VMPP I MPP (1)
where, PMPP is power at maximum power point, VMPP is
voltage at maximum power point, and IMPP is current at
maximum power point.
The PV balancer could compensate the differential voltage
between PV panel output voltage and DC bus voltage. Hence
the output voltage of PV balancer VOUT is represented as (2).
VOUT = VDC VMPP (2)
The voltage transformation ratio of PV balancer will
depends up on the DC bus voltage. If the DC bus voltage is
too high, then the voltage transformation ratio is low, but the
power rating of the device will increase and intern decrease
the efficiency of PV system. When the DC bus voltage is
nearer to module output voltage, the voltage transformation
ratio reaches high and the power rating of the device will be
very low. The minimum and maximum voltage transformation
ratio of architecture-I is (3).
VDC VPV max
( RV )min = VDC
(3)
( R ) = VDC VPV min
V max VDC
The minimum and maximum voltage transformation ratio of
architecture-II is (4).
VDC VPV max
( RV )min = VFD
(4)
( R ) = DC VPV min
V
V max VFD
 2016 2nd International Conference on Science in Information Technology (ICSITech)

where, VDC is the DC bus voltage, VPV min is the minimum IV. SIMULATION RESULTS AND DISCUSSION
panel voltage, VPV max the maximum panel voltage and VFD is In order to verify the performance analysis, the two possible
the frontend converter output voltage. architectures of PV balancers are applied on a practical
Here, the PV balancer is connected in series with the PV system. This system consists of three PV module practical
module, so the same current will flow through PV module and data, which has been taken from [10] and is shown in Table I.
PV balancer, which is represented as (5).
TABLE I. MODULE SPECIFICATIONS (DSP-100M PV PANEL)
I OUT = I MPP (5)
VOC I SC VMPP I MPP PMPP Irradiation
S.NO (W/m2 )
where I OUT is the output current of PV balancer. (V) (I) (V) (I) (W)
1 27.99 4.51 23.64 4.23 100 1000
The power processed by the PV balancer is partial power 2 26.79 2.56 22.63 2.40 54.34 500
over the full power of a PV panel. The output power delivered 3 25.15 0.76 21.24 0.71 15.14 150
from PV balancer ( POUT ) is expressed as (6).
The simulation works are implemented on MATLAB 2015a
and executed on a PC (core i3, 2.67GHZ, 4GB RAM). To
POUT = VOUT I OUT = (VDC VMPP ) I MPP (6) compare the performance of PV balancers three other MICs
are also simulated on the same domain. The comparative
where, POUT is output power. The ratio of the output power analysis of PV balancer with traditional MIC topologies is
of a PV balancer ( RPOWER ) is written as (7). presented in Table II. It is clear from Table II that the PV
balancers having high voltage transformation ratio among the
other modules which dramatically reduces the power rating of
POUT VOUT VDC the PV balancers. The comparative simulation result in Table
RPOWER = = = 1 (7)
PMPP VMPP VMPP II are verified that the PV balancer architectures could result
in a drastic improvements. Consequently, the architecture-II
The DC bus voltage should be greater than the maximum has gained supremacy in terms of efficiency (98%), rating
output voltage, and also it should be closer to VMPP . So, RPOWER (18.44 W) voltage transformation ratio (3:1), voltage stress on
is less than 20%. If the DC bus voltage is too low the current switching devices (10 V) over the other methods. The overall
flowing through the DC bus is very high thus the DC bus loss specifications of the power converters for both architectures
is more. By increasing the DC bus voltage the current flowing under three different solar irradiations such as 150 W/m2, 500
through the DC bus is reduced. Thus, the DC bus loss is W/m2, and 1000 W/m2, are shown in Table III.
minimized as (8). TABLE II. COMPARISION OF TRADITIONAL MIC AND PV BALANCER
DC bus loss = I 2 R (8)
Micro PV balancer in PV balancer in
where, I is the current and R is the resistance of DC bus. Inverter
MIC
architecture-I architecture-II
The efficiency of PV balancer is represented mathematically VMPP VMPP VDC VFD
as (9): Input voltage

Voltage
P PLOSS P transformation High High High Low
= OUT = 1 1 LOSS (9) ratio
PIN POUT + PLOSS POUT Voltage stress on
High High High Low
switching devices
where, Pin is input power of a balancer and as the Power Rating High High Low Low
efficiency of a PV balancer. To get the equivalent efficiency Power loss Low High Low Low
with the MIC, the power loss should be normalized with Equivalent
High Low High High
Efficiency
module output power PMPP (It is equal to the input power of
the traditional MIC). TABLE III. SPECIFICATIONS OF POWER CONVERTERS
Input Output Output Output
The equivalent efficiency of PV balancer is calculated using voltage voltage current Power
(10) 28 V 4.36 V 4.23 A 18.44 W
Flyback in
28 V 5.37 V 2.40 A 12.88 W
Architecture-1
28 V 6.76 V 0.71 A 4.79 W
PLOSS P
E = 1 = 1 RPOWER LOSS (10) Frontend flyback
PMPP POUT converter
28 V 10V 3.61 A 36.11 W

4.36 V 4.23 A 18.44 W

Since RPOWER is less than the 20% the equivalent efficiency Buck converter
10 V 5.37 V 2.40 A 12.88 W
Architecture-II
6.76 V 0.71 A 4.79 W
of PV balancer is high.

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In order to balance the power rating and transformation ratio

of PV balancers, the DC bus voltage and the output voltage of
frontend converter is set to 28 V and 10 V, respectively. From
the given practical data of PV panels, the operating points at
different atmospheric conditions are depicted in PV curves,
which are shown in Fig. 8. The output voltages and currents at
maximum power point of a PV panels are shown in Fig.9 and
Fig. 10.

Fig. 11. PV balancer output voltages for architecture-I

Fig. 8. PV Curves for DSP-100M panel

Fig. 12. PV balancers output currents for architecture-I

The output voltages and currents of PV balancer for

architecture-II are shown in Fig. 13 and Fig. 14 and observed
to be same as that of architecture-I but vary in terms of voltage
transformation ratio and power rating of the PV balancers.

Fig. 9. PV panel output currents

Fig. 13. PV balancer output voltages for architecture-II

Fig. 10. PV panel output voltages

The output voltages of PV balancers for architecture-I is

shown in Fig. 11, which represents the compensated
differential voltage between DC bus and PV module output.
Since PV balancer is connected in series with the PV module
output, so the output currents of PV balancers are same as that Fig. 14. PV balancers output currents for architecture-II
of PV module output currents, which is depicted in Fig. 12.

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Even though the disturbances occur in the modules, the
constant DC output voltage is supplying to the inverter, which
is 28 V as shown in Fig. 15. Since the simulation results are
better explained with and without PV balancers in bar charts
and are depicted in Fig. 16. From this bar chart, the output
voltage of PV balancers compensates the differences in DC
bus voltage and PV module voltages by considering that the
output currents of PV balancers are equal to the corresponding
output currents of PV modules.
Fig. 15. DC bus voltage
Fig. 16. Comparison of output voltages with and without PV balancers
V. CONCLUSION
This paper investigated the new concept of MIC called PV
balancer with two possible architectures and demonstrated on
a practical three module PV panels of PV systems. The
investigations shows that the PV balancer has better
efficiency, lower power rating, desirable voltage
transformation ratio, low DC bus loss and good regulation
ability as compared to the other commercial MIC. Among the
two possible architectures, architecture-II provides the
maximum power point tracking and decreases the few
electrical requirements for overall photovoltaic systems. The
work will be extended to propose different architectures on
practical water pumping photovoltaic system with converter
optimization, DC bus voltage control and developing a
hardware testing module.
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