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Chapter 2
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
OR
The Pentium processor includes features to support multi-processor systems, namely an onchip
Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports
multiprocessor interrupt management (with symmetric interrupt distribution across all processors),
multiple I/O subsystem support, 8259A compatibility, and inter-processor interrupt support.
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
D1 D2 WB
F EX
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
5) Write Back (WB): In the WB stage, the processor updates the registers and flags with the
instructions results. All exceptional conditions must be resolved before an instruction can advance to
WB.
The branch instructions occur frequently while running any application. These instructions change the
normal sequential control flow of the program and may stall the pipelined execution in the Pentium
system. Branches may be of two types: Conditional branch and unconditional branch. In case of
conditional branch, the CPU has to wait till the execution stage to determine whether the condition is
met or not.
The Pentium processor makes the dynamic branch prediction using a Branch Target Buffer (BTB). To
efficiently predict branches, the Pentium uses two prefetch buffers. One buffer prefetches code in linear
fashion, while the other prefetches instructions based on address in the branch target buffer. As a result
the needed code is prefetched before it is required for execution. The Pentium processors prediction
algorithm not only forecast the simple branch choices but also supports more complex branch prediction
for example, within nested loops.
The prediction mechanism is implemented using 4 way set associative cache with 256 entries referred as
branch target buffer. Whenever branch is taken CPU enters the branch instruction address & the
destination address in BTB. When an instruction is decoded CPU searches the BTB to determine
presence of entry. If it is present, CPU uses previous history to decide to take the branch. The history bits
can indicate one of the four possible stages & updated as follows.
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
Floating-point Exceptions:
An in the case of integer arithmetic, there are six possible floating-point exceptions in Pentium. These
are:
1. Divide by zero,
2. Overflow,
3. Underflow,
4. Denormalized operand and
5. Invalid operation.
These exceptions carry their usual meanings. The divide by zero exception, invalid operation
exception and denormalized operand exception can be easily detected even before the actual floating-
point calculation. A mechanism known as Safe Instruction Recognition (SIR) has been employed in
Pentium. This mechanism determines whether a floating-point operation will be executed without
creating any exception. In case an instruction can safely be executed without any exception, the
instruction is allowed to proceed for final execution. If a floating-point instruction is not safe then the
pipeline stalls the instruction for three cycles and after that the exception is generated.
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
10) Integrated high performance 16KB instruction and 16KB data, non-blocking, level one cache
11) 512KB Integrated Full Speed level two cache allows for low latency on read/store operations
12) Quad Quad-word Wide (256 bit) cache data bus provides extremely high throughput on read/ store
operations.
13) 8-way cache associativity provides improved cache hit rate on reads/store operations.
14) Error-correcting code for System Bus data
15) Data Prefetch Logic
What is MMX?
Intel introduced the MMX (multimedia extension) technology at a time when there was a tremendous
need to improve the 2-D and 3-D imaging for multimedia applications.
Most of the algorithms in multimedia applications involve operations on several pixels (picture cell)
simultaneously. A pixel of an image may be represented by a 24-bit quantity. Similarly, in case of a
black and white image, a pixel may be represented by an 8-bit number.
Most of the image processing algorithms and images compression techniques required for involves
operations on multiple numbers of pixels simultaneously. Thus most of the multimedia applications
require SIMD (single Instruction stream Multiple Data Stream) kind of architecture. This is precisely
what Intel provides through a set of the 57 MMX instructions. These instructions help the programmer to
write efficient programs for image filtering, image enhancement, coding and other algorithms.
Using conventional CPUs, we can operate on two pixels at the most, concurrently. Using MMX
instruction set, on the other hand, we can load eight pixels simultaneously and perform concurrent
operations on them.
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
Summer 2015
1. a) Attempt any THREE of the following : 12
(ii) What is multimedia extension ?
b) Attempt any ONE of the following : 6
(ii) With neat sketch describe the branch prediction logic in pentium processor.
Winter 2015
1. a) Attempt any THREE of the following: 12
(ii) List any four salient features of pentium processor.
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
a) Describe the general purpose registers and their functions in pentium processor with neat
diagram.
c) State and describe the significance of separate code and data cache in pentium processor.
Summer 2016
1. Attempt any FIVE of the following: 20
c) List any eight saliant features of Pentium.
d) Describe fire state pipelining mechanism of Pentium with neat diagram.
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Computer Department, Jamia Polytechnic (0366) Advanced Microprocessor (AMI 17627)
Winter 2016
1. Answer any FIVE of the following: 20
c) Explain branch prediction in pentium.
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