design

Edited by Bill Travis

ideas
DPP adds versatility to VFC
Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA
he basic VFC (voltage-to-frequen-

T cy converter) in Figure 1
comprises an integrator
(IC1) and a Schmitt-trigger circuit (IC2).
F i g u r e 1
VIN
R2

The integrator converts the dc input volt- R1 C1 R3 R4

age, VIN, to a linear voltage ramp, and the

_
Schmitt trigger sets the limits of the in- +
IC1 IC2
tegrators output voltage. Feedback VOUT
+ _
around both circuits provides the condi- SCHMITT
INTEGRATOR
tion for oscillation. The DPP (digitally TRIGGER
programmable potentiometer) in Figure
2 adds programmable limits to the
Schmitt trigger and adds two powerful This schematic depicts a basic voltage-to-frequency converter.
features to the VFC. First, the scale or
conversion factor is programma-
ble, and, second, for a fixed dc-in- Figure 2 D1 R2<<R1
1k, 1% 5V
put voltage, the converter is a program-
mable oscillator. The frequency, f0, of the pR3 (1p)R3
8
1
single-supply converter in Figure 2 is: VIN
6 3 CAT5113
R1 C1 10k 2 DIGITAL
(1p ) (VIN 2.5V ); 0.01 F
20k, 1%
5 7 CONTROLS
f o f BASE 5V
5V
p 5V 510 4
2 _ 7 2 + 8
0 p0.5, and 2.5V VIN 5V , IC1 6 IC2 7
LT1097 V1 LM211 V0UT
where fBASE1/2R1C1, and p is the rela- 3
+ 4
3 _
4
tive position of the wiper from one end
(0) of the DPP to the other end (1). For 1
the100-tap Catalyst (www.catsemi.com)
2.5V

DPP adds versatility edn021031dix30741

to VFC................................................................99
Power circuit terminates
DDR DRAMs..................................................100
Circuit protects bus
from 5V swings ............................................102
Use a 555 timer as a
switch-mode power supply........................104
VCO uses programmable logic................106
Controlling slew times tames
EMI in offline supplies ................................108
Publish your Design Idea in EDN. See the
Whats Up section at www.edn.com.
www.edn.com
Using a digitally programmable potentiometer, you can vary the scale factor of this voltage-to-fre-
Heather
quency converter.
5113 potentiometer, the range of the rate resistors and capacitors. The scale
scale-factor term (1-p)/p is 1 to 99 with factor relates to the ratiometric temper-
a resolution and accuracy of approxi- ature coefficient of the DPP and hence is
mately 1%. For the values shown in Fig- minimally temperature-dependent. You
ure 2, the practical range of frequencies can use the circuit as a programmable os-
is 500 Hz to 25 kHz. Higher bandwidth, cillator when VIN is fixed and the poten-
rail-to-rail CMOS versions of IC1 and tiometers wiper setting changes the lim-
IC2, and a greater R1/R2 ratio can extend its of the Schmitt trigger.
the accuracy and range of the circuit. The
automated, accurate setting ofedn021031dix30742
the scale
factor saves manufacturing test time and Is this the best Design Idea in this
Heather
eliminates the need for expensive, accu- issue? Select at www.edn.com.
November 14, 2002 | edn 99
 design
ideas
Power circuit terminates DDR DRAMs
Ron Young, Maxim Integrated Products, Sunnyvale, CA
DR (double-data-rate) SDRAMs put current as high as 6A. IC1 includes a an inverting amplifier. This amplifier

D find use in high-speed memory sys-

tems in workstations and servers.
The memory ICs operate with 1.8 or 2.5V
supply voltages and require a reference
voltage equal to half the supply voltage
(VREFVDD/2). In addition, the logic out-
puts terminate with a resistor to the ter-
mination voltage, VTT, which equals and
tracks VREF. VTT must source or sink cur-
rent while maintaining VTTVREF
0.04V. The circuit of Figure 1 provides
the termination voltage for both 1.8 and
2.5V memory systems and delivers out-
step-down controller and two linear-reg-
ulator controllers and operates with in-
put voltages of 4.5 to 28V.
IC1s fixed-frequency, 200-kHz PWM
controller maintains the output voltage
by sourcing and sinking current. Maxi-
mum sink current equals the maximum
source current, though the sink current
has no current limiting. When sinking
current, the device returns some current
to the input supply. To implement the
tracking function, one of IC1s extra lin-
ear-regulator controllers is configured as
compares VDD/2 (created by R1 and R2)
with VREF from IC1 and generates an er-
ror signal that connects via R3 to IC1s FB
pin, thereby forcing VOUT to track VDD/2.
A 10-mA load, R4, is necessary to bias the
inverting amplifier for accurate tracking.
VOUT can track VDD/2 for VDD in the range
1 to 4V.
Is this the best Design Idea in this
issue? Select at www.edn.com.

Figure 1
5V
INPUT 1200 F
4.7 F 10V
CMPSH-3
10V MV-AX

22 F
16 15 10V (4)
VP VL 14
9 BST
ILIM
15k 2 0.1 F
COMP 13 FDS6690A EC31
DH QS03L
4.7 1.5 H
22 nF 12 DO5022P
1000 pF 1.25V
LX
6A
11 EC31
FDS6690A
DL QS03L + 1200 F
IC1
10 4.7
MAX1864T 2.5V
GND
5V OS-CON
3
OUT
1OOk R5
4 10k
1 FB
POK POK

B2 5 R3 5V
10k
R7
FB2 6 CMPT 1 F
+ 220 330 pF
3906 10V
1.24V B3 7
22.1k
8 R4
FB3 22 F 100
22.1k 10V
R1
1k
2.5V
0.1 F R2
1k

This circuit generates the termination voltage for DDR synchronous DRAMs.

100 edn | November 14, 2002 www.edn.com

design
ideas
Circuit protects bus from 5V swings
Said Jackson, Equator Technologies Inc, Campbell, CA
C
1
he circuit in Figure 1 auto-

T
0.01 F
5V
matically detects voltage 5 3
Figure 1
and protects a bus, such VCC GND
2 IC 4
as a 3.3V-limited PCI bus, from 5V 1+ PCI_SERR#
signal-level swings.You can also use 1
NC7SZ125

the circuit to determine bus-voltage 5V

swings within one bus-cycle for set- 4 10

2 D PR Q 5 PR
ting appropriate termination volt- 12
D Q
9
IC2A IC
ages of protection diodes or termi- 5V PCI_CLK
3
CLK Q 6 11 CLK
2B
Q
8
nation resistors. Todays deep- R1
CL CL
3.3 1 74LVC74A 13
74LVC74A
submicron VLSI-manufacturing PLACE CLOSE
TO PCI BUS 0603 PCI_RST#
techniques sometimes require cir- PCI
1
Q VCC
5 R4
AD10 R2 0603 R3 0603 2 C2 LS1 12V 1.5k
cuits to limit I/O voltages to 3.3V GND IC3 0.1 F + C3 0603
10 F P9948-ND 1
2k 2k 3 4 0805
signal swings. Connecting such cir- PCI_AD[31..0] 1% 1% IN+ IN 0805 PANSONIC
EFB-CB37C11 2
METAL METAL
cuits to a bus with 5V level-swing MAX999 C
TOP VIEW 5V BUS B
cards could damage the circuitry. 1.88V5% WARNING
Q1
5V
The circuit in Figure 1 can accu- R5 C4 R6
BUZZER E FMMT4123CT-ND
0.1 F 9k SOT-23
rately andwithin one bus cycle 15k
0805 1% METAL JP1
1% METAL
detect a level swing larger than 3.3V 0603 0603
1 ENABLE
on any bus and, upon a fault situa- 2 PROTECTION

tion, generate a reset signal and an HEADER2

alarm output to notify the user and This circuit provides both an audible alarm and an error flag when an overvoltage condition exists.
the system of this fault. Some of the
novel circuit features include a highly ac- The circuit generates a signal that can PCI_AD10. Every PCI device asserts this
curate synchronous-detection capability reset the system, or it can generate a sys- signal at least once during PCI enumer-
to avoid false alarms arising from large tem-error signal. Because the alarm-reg- ation, but you can monitor other signals
signal overshoots, high impedance and ister memory, IC2B, serves as an asyn- if necessary. This method guarantees
low capacitive loading of the bus, auto- chronous register, you can switch the recognition of a 5V PCI device shortly af-
matic system shutdown during fault con- alarm off only by removing power from ter the BIOS starts enumerating the PCI
ditions, and a single-cycle response time. the system or by asserting the reset signal. bus during system boot. IC2A then latch-
This circuit successfully operates in To avoid false triggering by signal over- es the comparators, IC3, Q-output Pin 1
products using the high-performance shoot and undershoot, a flip-flop-based during the rising edge of the PCI clock.
3.3V MAP-CA processor family from register, IC2A, samples the comparator This action asserts flip-flop IC2B, which
Equator Technologies (www.equator. output only during the rising edges of the in turn enables buzzer LS1 and generates
com), but you can use it in other high- bus clock. This method allows for a gen- an open-collector, low-active, system-er-
speed 3.3V or even lower voltage systems. erous 33-nsec period at 33 MHz for the ror signal through IC1. You could use this
Equators latest generation chips are 5V- bus signal to settle down before being error signal to automatically remedy the
tolerant, but you can adjust the circuit to sampled. Lowpass filtering by sensor re- fault condition by disabling the offend-
protect other 1.8 and 2.5V chips. The cir- sistors R2, R3 and the 3- to 5-pF parasitic ing circuit on the bus. The sense and ref-
cuit uses IC3, an ultrahigh-speed Maxim capacitance on Pin 3 of IC3 limit the max- erence resistors R2, R3, R5, and R6 should
(www.maxim-ic.com) MAX999 com- imum clock speed of this circuit. The be metal-film 1% types. The 5V reference
parator with 4.5-nsec propagation delay, traces connecting to Pin 3 of IC3, R2, and voltage connected to R5 determines the
TPD, to constantly compare a signal line, R3 thus must be as short as possible and accuracy of the trip voltage, and todays
PCI_AD10 in case of a PCI bus, to a ref- may limit the bus speed to approximate- power regulators have sufficient accura-
erence level of 3.8V. This reference volt- ly 40 to 50 MHz. Symmetrically lower- cy so that you can use a 5V system-pow-
age is an optimal compromise between ing the resistance of R2 and R3 increases er line as the reference voltage, obviating
5V signals clamped by 3.3V protection the maximum bus speed to a theoretical the need for a special 5V-reference gen-
diodes and the normal-operation 3.3V 7-nsec cycle time (greater than 140 MHz) erator. Removing jumper JP1 disables the
signals. Once the voltage exceeds this ref- at the expense of a higher signal-loading circuit.
erence level for an entire bus clock peri- current on the bus.
od, the system turns on an alarm buzzer In the case of monitoring a PCI bus, Is this the best Design Idea in this
connected to Q1. Pin 3 of comparator IC3 monitors signal issue? Select at www.edn.com.
102 edn | November 14, 2002 www.edn.com
 design
ideas
Use a 555 timer as a switch-mode power supply
Aaron Lager, Masterwork Electronics, Rohnert Park, CA
ost switch-mode power supplies continuous-trigger source. The input IC3, R1, R2, and V1 form the feedback cir-

M rely on a PWM (pulse-width-

modulated) output that is con-
trolled via voltage feedback. A 555-timer
IC can inexpensively perform PWM. The
circuit in Figure 1 shows how to turn a
555 PWM circuit into an switch-mode
power supply with only one simple equa-
tion. The design uses two 555s. IC1, in
astable mode, triggers IC2 in PWM mode.
IC1 is set to oscillate at approximately 60
kHz at a high duty cycle. The output is
low for only approximately 2.5 sec to
trigger the PWM circuit and then goes
high for the rest of the period. The PWM
circuit has a maximum pulse width of ap-
proximately 85 sec, and it becomes
shorter, depending on the control voltage
from the feedback circuit. You can reduce
the chip count by using a 556 or another
must be (1.5VOUTMargin), so for 5V
output you need 9V minimum input. If
you use CMOS chips and small timing
capacitors C1 and C2, you can keep the
operating current low. Thus, you can use
a simple zener-diode regulator for the
555 and increase the input voltage to
more than 30V. The input-voltage limit is
a function of how much power the zen-
er supply can handle while delivering 5 to
10 mA to the 555s.
Q1 has low RDS(ON) and low VGS and can
handle more than 40V. D1 clamps any
voltage spikes, such as those that occur
when a large current flow ceases, causing
a large magnetic field to be left in the in-
ductor. You should select D1 according to
the output voltage you need. For 5V out-
put, use a 5.6V zener diode, for example.
cuit to set the output voltage. The output-
voltage equation is VOUTV1(R1/R21).
The TL431 is a popular part for setting a
voltage reference and can easily create the
1.25V shown for V1. You can supply 5V at
1.5A with an input of 9 to 40V. At volt-
ages higher than 12V, you can add a 10V
zener-diode supply for the chips. The
zener supply only slightly reduces the ef-
ficiency. With 12V input, 5V, 1.5A out-
put efficiency is approximately 70%, and
it drops to 65% with a 40V input and a
zener circuit. The zener diodes influence
is more noticeable at lower current levels;
at a 50-mA load the efficiency drops to
approximately 50%.
Is this the best Design Idea in this
issue? Select at www.edn.com.

POWER
ASTABLE TRIGGER PWM

8
10k VCC 0.1 F 4 8 4.7k
2 TRIGGER
RESET VCC
+ 100 7
UNREGULATED 4 RESET 3 DISCHARGE
SUPPLY IC1 OUTPUT
2 6
5 CONTROL 555 TRIGGER THRESHOLD
83 IC2 5 C1
6 THRESHOLD 555 CONTROL 0.01 F
7 DISCHARGE 3
Figure 1 GND
OUTPUT
GND
C2 1 1
0.001 F 0.01 F

0 POWER

3
Q1 7 1
2
ZVN4210G/ZTX 3
+
VOUT V+
1 IC3
6
REGULATED LF411/NS OUT
L1 SUPPLY
2 V
R1
68 H 5
+ 10k + V1
1
1N5817 100 F D1 RLOAD 1.25 4
1N4734 R2 _
3.33k
FEEDBACK
VOUT1.25(1R1/R2).
0
0

Heres one more use for the ubiquitous 555 timer: a switch-mode power supply.

104 edn | November 14, 2002 www.edn.com

design
ideas
VCO uses programmable logic
Susanne Nell, Breitenfurt, Austria
VCO (voltage-controlled oscilla-

A tor) is an analog circuit, so

you cannot find it in the li-
braries for the design of digital pro-
Figure 1

STEERING
5V

R1
6.8k 27k
R3 R4
27k
5V

R2
6.8k J2
grammable chips. When you need such VOLTAGE OUTPUT
a circuit for synchronization or clock 1 1
multiplication, you need to find a circuit ICST 2 D1 2 Q
that works with the standard digital func- 1N4148 3 Q
D2
tions, such as AND and NAND. Several 1N4148

possibilities exist for building variable- F F

1 4
frequency oscillators. For example, you IC1A IC1B
can change the frequency using a varac- 74HC02 74HC02
tor diode. Unfortunately, these diodes 2 3 5 6
have a small change of frequency per volt.
C1 C2
So, the standard Pierce oscillator with 1 nF 1 nF
one inverter and capacitors is not useful
for these applications. Another idea is to
use a Schmitt-trigger inverter and to vary This unique VCO, implemented with discrete logic, has a wide tuning range.
the charging resistor. This method can
work, but the hysteresis of the IC usual- NOT NOT
1 2 2 1
ly has a wide tolerance, so the selected in-
verter chip has a large influence
Figure 2
on the frequency.
For these reasons, this design modifies 1
1 4
1
NOR2
a two-NOR-gate RC oscillator (Figure 1)
TRISTATE TRISTATE
to function as a VCO. For almost all pure- BUFFER
NOR2
BUFFER
CMOS circuits, the switching point be- 2 2 3 5 6 2
tween high and low states is approxi-
mately VCC/2. This point does not depend
PAD5 PAD6 PAD2
on the device. Using this circuit, you can BIDIRECTIONAL OUTPUT BIDIRECTIONAL
obtain a wide frequency-tuning range. 1
The output is a square wave with a 50% Q
1
2 Q
duty cycle. At power-on, both capacitors ICST 2 R4
R4 C1 1k C2 OUTPUT
C1 and C2 are uncharged, and IC1A has a 1k 1 nF 1 nF
STEERING
low output. Thus, the output of IC1B is VOLTAGE
high, and C2 charges with the time con- VST

stant R2C2. The additional charging cur-

rent from ICST and R4 also influences this This VCO uses an EPLD and has high gain, expressed in kilohertz per volt.
charging time. When the voltage on C2
reaches VCC/2, IC1B switches to a low state. VCOs gain. The circuit uses an Altera grammable-logic devices with CMOS in-
Now, the output of IC1A switches high, (www.altera.com) EPLD (erasable pro- puts. You can also use steering voltages
and C1 charges with time constant R1C1, grammable-logic device), the EPM3032. much higher then the supply voltage of
influenced by ICST and R3. The low sig- Tristate buffers replace the diodes in Fig- the programmable chip, because the volt-
nal at the output of IC1B forward-biases ure 1, and the charging resistors connect age on the input of the chip never goes
D2 and quickly discharges C2. directly to the steering voltage. This con- higher then VCC/2. This fact makes the
This circuit produces a 50% duty cy- figuration produces the highest possible circuit suitable as a voltage-to-frequency
cle if C1C2, R1R2, and R3R4. The val- VCO gain: approximately 700 kHz/V for converter with a high input-voltage
ues of R4 and R3 and the steering voltage, the component values shown. You can range.
VST, determine the VCOs gain in kilo- switch off the VCO by using a steering
hertz per volt. The circuit in Figure 2 voltage lower then VCC/2. You can imple- Is this the best Design Idea in this
yields the highest possible value for the ment this circuit using almost all pro- issue? Select at www.edn.com.

106 edn | November 14, 2002 www.edn.com

 design
ideas
Controlling slew times tames
EMI in offline supplies
David Canny, Linear Technology Corp, Milpitas, CA
MI from offline switching power that typically suppress this noise. The ab- pin. Q2, Q3 and their associated circuitry

E supplies typically causes all sorts of

problems for power-supply design-
ers. You may need a large EMI filter to
meet FCC emission requirements.
Switchers for high efficiency produce
high-frequency switching noise that can
propagate through the rest of the system
and cause problems. Board layout is crit-
ical, requiring considerable experimen-
tation, even for experienced designers.
The low-noise circuit in Figure 1 signif-
icantly reduces the complexity of these is-
sues by continuous, closed-loop control
of the voltage and current slew rates.
High-frequency noise suppression is par-
ticularly important for medical devices
because they dont require the ac-line-to-
earth ground capacitors (Y capacitors)
sence of these capacitors allows medical
devices to easily comply with the more
stringent low-leakage-current health-
provide undervoltage lockout with hys-
teresis. During start-up, the SHDN pin
stays low until C5 charges to 12V via R1.
care specifications of UL544, UL2601, The LT1738 then turns on and subse-
and CSA22.2. quently obtains most of its operating
Figure 1 shows a 30W (12V output at power from T1s auxiliary winding. The
2.5A) offline power supply. IC1, an feedback goes directly to the LT1738s VC
LT1738 low-noise switching regulator in pin rather than to the FB pin because the
a flyback topology, drives Q1 and contin- optocoupler provides the feedback gain
uously controls the current slew using the that the LT1738s internal feedback am-
resistor at the RCSL pin. The IC controls plifier typically provides. C6 and L1 at-
the voltage slew using the resistor at the tenuate the low-frequency harmonics of
RVSL pin and the capacitance at the CAP the LT1738 switching frequency.
pin. IC2, an LT1431 programmable ref- You can see the benefits of the circuit
erence, and the optocoupler close the iso- by measuring its ac-line-conducted EMI
lated loop back to the LT1738. The circuit and then comparing these measured re-
achieves current limit by sensing the cur- sults with those for basically the same cir-
rent through a 68-m resistor at the CS cuit with the LT1738 replaced with a

DANGER: HIGH VOLTAGE

L1 C1 + P6KE200A
X1 100 F
400V 510 200 pF
1M C6 BR1
90 TO 2W T1 11 200V 10
0.1 F 1
264V
250V AC 220 pF
AC 1M "X2" D1
K A A1 VOUT
X3 12V
3 7 A2 2.5A
MUR160 C4
10 6 12 C2 + C3 + +
100k 330 F 330 F
Figure 1 R1 330 F
2W 25V 25V
BA521 25V
5 8
VOUT
17 19 10
+ C5 470 pF
510k VIN NFB
56 F NC
15 pF
35V 600V
7.5V 14
SHDN
IN755A
5
V5 15 pF
IC1
6 2
SYNC LT1738 CAP Q1
510k MTP2N60E 0.1 F 1k VOUT
7 1
CT GATE
51k
1.5 nF
8 4 1k
165k RT CS
19.6k 16 0.068 ISO1
Q2 RVSL 18 CNY17-3 1k
NC 0.5W 38.3k
3.9k 15 3 1 3 2 1%
2N2222 20
RCSL 6
PGND V+ COMP 8 0.22 F
3.9k
9 12 5 REF
FB VC
IC2
2 COLL LT1431 RTOP 4
SS GND GCL
2N2222 7
Q3 13 11 3 RMIO 10k
51k 10 nF 0.1 F 4
G-F G-S 1%
6 5

NOTES:
UNLESS OTHERWISE NOTED, D1: MBR20300CT.
ALL RESISTORS: 1206,5%. L1: HM18-10001.
BR1: GENERAL INSTRUMENTS WO6G. T1: PREMIER MAGNETICS POL-15033.
C2, C3, AND C4: SANYO MV-GX.

A 30W offline power supply passes FCC Class B emission requirements without line-to-earth-ground capacitors.

108 edn | November 14, 2002 www.edn.com

design
ideas
generic switcher. The only circuit-pa-
rameter difference is that, unlike the
LT1738, the generic switcher doesnt ac-
tively control the switching current and
voltage slew rates. Figure 2 shows the fre-
quency spectra for both circuits. You can
see by the respective frequency spectra
that the LT1738-based circuit generates
emissions well within FCC Class B re-
quirements, whereas the circuit with the
generic part results in emissions that ex- (a) (b)
ceeds FCC Class B allowable emissions by
a significant margin. In these 50-MHz-wide spectral plots, areas under horizontal lines indicate acceptable
Another benefit of the circuit Figure 2 FCC Class B emission requirements. The spectral plot for the LT1738-based circuit (a)
in Figure 1 is that the output voltage shows emissions well within FCC Class B requirements, unlike the plot for the generic switcher (b).
noise comprises the fundamental ripple
with practically no high-frequency com- the output with little attenuation through in medical devices because the absence of
ponents. You can attenuate this ripple the parasitic capacitance of the output fil- Y capacitors results in low leakage current
voltage if desired to less than 300 V us- ters inductor. The circuit in Figure 1 to earth ground in compliance with
ing a 100-H, 100-F LC filter on the minimizes noise and EMI by controlling health-care specifications.
output. The generic switcher, on the oth- the voltage and current slew rates of the
er hand, produces more output noise be- external n-channel MOSFET. This circuit Is this the best Design Idea in this
cause the high-frequency noise passes to is well-suited for offline power supplies issue? Select at www.edn.com.

110 edn | November 14, 2002 www.edn.com