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II.
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9. .

65
 NI ELVIS
. 2.2. .
2.2
NI ELVIS

1 2 3
ACH<0..5>+
05 .
ACH<0..5>
05 .
AISENSE -
,
.
AIGND
DAQ.
CH<A..B>+ -
A B.
CH<A..B> -
A B.
TRIGGER
AIGND.
PFI<1..2>, -
PFI<5..7> 1 2 5 7 DAQ.
SCANCLK / SCANCLK
DAQ.
RESERVED EXTSTROBE* -
DAQ.
3-WIRE -
-
.
CURRENT HI -
, -
.
CURRENT LO -
,
.
VOLTAGE HI
.
VOLTAGE LO
.
DAC<0..1> 0, 1
DAQ
FUNC_OUT .
SYNC_OUT -
AM_IN -
.

66
 1 2 3
FM_IN -
.
BANANA<A..D>
/ AD.
BNC<1..2>+ (+) BNC- 1 2.
BNC<1..2> (-) BNC- 1 2.
SUPPLY+
0 12 .
SUPPLY
12 0 .
GROUND .
, .

+15 V 15
NI ELVIS GROUND.
15 V 15
NI ELVIS GROUND.
+5 V +5
DO<0..7> 07
WR ENABLE / , , -
.
LATCH , , -
,
.
GLB RESET Global Reset ( ) , -

/.
RD ENABLE Read Enable ( ) ,
/ ,
.
DI<0..7> 07
ADDRESS<0..3> 03 .
CTR0_SOURCE 0
GPCTR0_SOURCE DAQ.
CTR0_GATE 0
GPCTR0_GATE
DAQ.
CTR0_OUT 0
GPCTR0_OUT DAQ.
CTR1_GATE 1
GPCTR1_GATE
DAQ.
CTR1_OUT 1
GPCTR1_OUT DAQ
FREQ_OUT
FREQ_OUT DAQ.

67
 DAQ . 2.2 -
, ELVIS
.
-
, -
. NI ELVIS
- NI ELVIS GROUND. NI ELVIS
GROUND ,
.

CURRENT VOLTAGE,
. -
, , VOLTAGE HI
VOLTAGE LO. -
CURRENT HI CURRENT
LO.

CH<A..B>+, CH<A..B> TRIGGER. CH<A..B>
ACH3 ACH4 DAQ .

FUNC_OUT. , SYNC_OUT -
, -
. AM_IN FM_IN -
.

.
,
0 +12
SUPPLY+ 12 0 SUPPLY. GROUND -
68
 ,
.

1. Elec-
tronics Workbench?
2. - Circuit De-
sign Suite.
3. Mul-
tisim?
4.
Multisim?
5. -
Multisim?
6.
Multisim?
7.
?
8. -
Multisim?
9. ELVIS?

1. Multisim. . / . . National In-
struments , , , 2006. 38 .
2. 2.001-93. .
.
3. 2.702-75. .
.
4. 2.701-84. .
. . .
5. 2.710-81. .
- .

69
6. 2.721-74. .
.
.
7. . . IBM PC. 1. -
. .: -, 2006.
. 3104.
8. .., .., .. OrCAD 10. -
. .: - ,
2005. 454 .
9. ..
. .: - , 2003. 224 .
10. .. -
DesignLab 8.0. .: -, 2003. 704 .
11. . PSPICE. :
. . .: , 2005. 336 .
12. .. Multisim 7: -
. / . .
.. .: -, 2006. . 133.
13. Multisim. User Guide. National Instruments Corporation, Electronics
Workbench Group, 2007.
14. Multisim. Component Reference Guide. National Instruments Corpora-
tion, Electronics Workbench Group, 2007.

70
 III.

3.1.
Multisim -
. -
, Simulate / Analyses
.
. 3.1. :
DC Operating Point ;
-
.
AC Analysis - -
.
Transient Analysis .
Fourier Analysis .
Noise Analysis .
Distortion Analysis -
.
DC Sweep
.
Sensitivity

(AC)
(DC).
Parameter Sweep -
.
Temperature Sweep .
Pole-Zero -
.
71
 Monte Carlo -.

. 3.1.

:

, -
.

72

. -
SPICE. -
.
-

, .
.
, , -
,
(audit trail), -
.

Grapher. View / Grapher. -
Graph Chart.
,
.
,
. ,
,
.
Edit /
Page Properties. , , -
, .

3.2.
-
,
.
73
 ,
C=470 -
L=2
r=10 .

1 1
f0 = = 5,2[ ] (3.1)
2 LC 3
2 3,14 2 10 470 10 9

L/C 2 10 3 / 470 109

Q= = 6,5 (3.2)
r 10
Multisim . 3.2 .
XBP1

IN OUT

0
L1 1 R1 2
2mH 10
10% 5%
3 XFG1
C1
470nF
20%
0 0

. 3.2.

-
Function Generator XFG. -
- -
Bode plotter XBP.
. -
, Run . -
,
74
 . 3.3.
-
.

. 3.3.

. 3.3 , -
-
: f0=5,186 ; Q=6,457.

Multisim .
. -
Simulate / Analysis / AC Analysis -
- - .
Frequency Parameters:
(Start frequency) 1 kHz;
(Stop frequency) 10 kHz;
(Sweep type) Decade;
(Number of points...) 100;
(Vertical scale) Linear.
Output (
. 3.1 V2).
75
 Summery.
, Simulate.
Grapher View (. 3.4).

. 3.4. Grapher View

Edit/Properties. , , ,
.
Excel MathCAD
.

3.3. ELVIS
Multisim
ELVIS. -

.
, -
ELVIS.
76

Tools / Show Breadboard.
, (left
strip), (right strip), (bottom strip) (top strip) -
. .3.5.

.3.5. ELVIS

Options / Breadboard Settings. -
3D
Options Options / Preferences.
Background Color, Color
.
Info Box. Left, Center Right,

, . -
Info Box, .
-
:
1. -
.

77
 2. Tools/Show Breadboard.

, .
3.
.
90
Ctrl-R. , -
. ,
. -

. .
4. ,
, -
.
5.
. -
.
6. , -
, , -
-
. ,
, -
. -
, , -
, , -
.
.
7. . -
, , -
78
. , . -
,
, -
.
8. Tools / Show Breadboard Netlist.
Breadboard Netlist
. ,
, .
Tools/DRC and Connectivity Check. -
Results Spreadsheet
View.
Design Rule Errors ,
, .
Connectivity Errors -
, ,
, .

3.4. ELVIS
ELVIS
,
ELVIS.
Virtual ELVIS
File / New / NI ELVIS Schematic.
(. 3.6).

, -
NI ELVIS .

79
 . 3.6. ELVIS

-
Multisim. -
,
ELVIS .
-
ELVIS.
.
. -
, -
, .
:
CH A+ A;
CH A- A;
CH B+ B;

80
 CH B- B;
TRIGGER .

Oscilloscope ,
-
.
.
-
DMM.
Virtual ELVIS Schematic, -
.
. -
,
.
-
. (
, ),
DMM -
.
. -
Function Generator
:
FUNC OUT ;
SYNC OUT ,
;
AM IN ;
FM IN .

Function Generator,
.
81
 .
. -
DC Power Supplies
+15 , -15 , +5
Variable Power Supplies -
+12 -12 . -
Variable Power Supplies.
.
-
. Virtual ELVIS -
, .

+15 , -15 +5 . -
.
, -
-
, . -
Tools/Show Bread-
board , .

1. -
Multisim?
2. Multisim
?
3.
Multisim?
4. Multisim -
?
5. ELVIS?

82
6.
ELVIS Multisim?
7. -
ELVIS?
8.
ELVIS?
9.
ELVIS?

1. Multisim. . / . . National In-
struments , , , 2006. 38 .
2. . . IBM PC. 1. -
. .: -, 2006.
672 .
3. .. Multisim 7: -
. / . .
.. .: -, 2006. 488 .
4. MultiSIM 9. . . /
. . National Instruments
. National Instruments, 2006.
113 .
5. Multisim. User Guide. National Instruments Corporation, Electronics
Workbench Group, 2007.
6. NI Educational Laboratory Virtual Instrument Suite (NI ELVIS). User
Manual. National Instruments Corporation, 2004.

-
http://www.ni.com/ National Instruments.

83
 IV.

4.1.
()
. -
,
, , , ,
.. -
.
-
,
, .
-
, -
-
.

-
.
.

. -
, -
-
, . -
-
.
-
. 4.1. (
84
 ) ( -
). , .
, 180 -
,
. ,
, . ,
, , . -
.

FC
+U FC
-U NC
NC

. 4.1.

-
-
, -
, . -
-
.
, -

. -
,

.
,
, -
.

85
 , -
. -
15 , ,
,
.

11,5 .
30 -
. , -
.
:
;
;
;
;
;
;
, .

:
;
;
.

:
;
;
;
- .

86
 ,
, -
, ,
, ,
, .. f1, -
.

:
K0
KU = , (4.1)
1 + j ( f / f0 )
K0 -
, f0 -
3 . . 4.2 -
- ,
.

. 4.2. -

, f0 -
20 /.
-
. -
, :

87
 a)
(
103 107);

b) , .. -
-
( -
1 50 );

c) (
);

d) ( -
);

e) .

-
,
.

4.2.
4.2.1.
. 4.3. -
, , -
.

. 4.3.

88
 -
:
KU = U out / (U in U no ) , (4.2)
U in , U no -
.
(a) -
-
, ..
U in = U no (4.3)
U1 U no

(c)
R3 R4 :
U no / U1 = R4 / ( R3 + R4 ) (4.4)
I1
I1 = (U 2 U in ) / R1 (4.5)
,

I 2 = I1 (4.6)

U out = U no I1R2 (4.7)
(4.5) (4.7) (4.4),
( R1 + R2 ) R4 R
U out = U1 2 U 2 (4.8)
R1 ( R3 + R4 ) R1
R1 R4 = R2 R3

U out = (U1 U 2 ) R2 / R1 (4.9)

89
 (4.8) (4.9) , -
,
.

4.2.2.
-
(. 4.4).

. 4.4.

(4.8), :
U out = U 2 R2 / R1 (4.10)
(4.9) ,
-
.
-
R1 R2 , -
.
.
, .. -
. (4.3).
.
.
:

90
 I1 = U 2 / R1 (4.10)
,
R1 .

4.2.3.
-
, -
R1 R2 (. 4.5).

U1 Uout
R2

R1

. 4.5.

. -
(4.8) , U 2 = 0 , R3 = 0 ,
R4 = .
U out R
K= =1+ 2 (4.11)
U1 R1
, , -
.
, -
K = 1 . .

. ,
.

91
 4.3.

,
, , -
, .
, , , -
, -
.
, -
.

4.3.1.

. -
(. 4.6).

. 4.6.

,
, , -
:
92
 U U U
U out = 1 + 2 + ... + n R0 (4.12)
R1 R2 Rn

, () -
-
. ,

-
. , n
n -
.

4.3.2.
-
, . 4.7.

. 4.7.

. , I R = U in / R I R = IC ,
:
t
1
U out (t ) = U C (t ) = U C (0) + I C (t )dt (4.13)
C0

93
 t
1
RC 0
U out (t ) = U out (0) U in (t )dt (4.14)

U out (0) -
.

4.3.3.
, -
, . 4.8.

. 4.8.

-
:
dU in (t ) U out (t )
C + =0 (4.15)
dt R
:
dU in (t )
U out (t ) = RC (4.16)
dt

, -
.
,
. -
.

94
 4.4.
4.4.1.
, , -
.
, -

, .. .
,
, , -
. -
-
.
-
, , , -
. , ,
.


, -
, . 4.9. -

.

. 4.9.

95
 , ,
. -
, -
.
-
, . 4.10.
S
C

Iin R

Qin
Uout

. 4.10.

Qin . , -
C
I in . -
R . -
-
. .
, -
, C S.
- -
, -
, ,
.

96
 4.4.2. ( )

. -
, . 4.11.

. 4.11.

. A1
, A2
. -
: . Uin
C U1, VD -
A1 -
. VD -
Uout C.
A2
, ,
.
R
A1, . S -
.

4.4.3.

. -
. p-n -
97
, -
-. -
p-n , -
.
, : -
.
, . -
, -
, . 4.12.

. 4.12.

, ,
,
. , -

-
.
6 .

, -
, , .
7
.
p-n .
98
 4.4.4. ()

. U in ,
U ref , -

U out :

U out
1
U in > U ref
U out = 0 , (4.17)
U out U in < U ref
0
U out (
1
) , U out -
.

-
. ,
, ,
- .
-

.
, -
, . -
, U in U ref . -

, ,
.
, -
.

99
 -
.
. 4.13.

Vout

Vref -Vin

. 4.13.

-
, ,
VD1 VD2 . ,
R1 = R2 . Vin Vref > 0 , VD2 Vout

.
Vin Vref < 0 , ,

. ,
,
, . R3 R4
, -
. -
.

100
 4.5. Multisim
Multisim
. -
Multisim , -
. 4.14.
XSC1
XFG1
Ext T rig
+
_
A B
0 + _ + _

VCC VCC 12V 0

5 8
0 3
U1A LM358AN
1 4
R1 2

4 VCC2
10k
5% 1 VCC2
V1 -12V

2 R3 R2
0
10k 10k
0V 5% 5%

. 4.14.
,

-
, -
. -
, LN358N.
-
. VCC VCC2. -
, VCC POWER_SOURCES -
Sources Master Database. -
,
(Value) +12V 12V.

101
 ,
(Label) -
This net has virtual and/or off-page connections. Do
you want to change all instances No.

10 . XFG1 -
1 ,
1 . XSC1 -
. -
, .
-
. -
. 4.15.

. 4.15.

102
 ,
,
1.
, -
.

10 -
5. -
,
-
5.
R2
200 , 20 .
, -
20 , -
(4.12).
, -
,
( , -
4.1).
: -
.
-
R2.
Parameter Sweep
Simulate / Analyses.
Analyses Parameters -
:

103
 a) Sweep Parameters: Sweep Parameter Device Parameter;
Device Type Resistor; Name rr2; Parameter resistance.
b) Points to sweep: Sweep Variation Type Decade; Start
10 ; Stop 100 .
c) More Options: Analyses to sweep AC Analyses.
Edit Analyses
.
d) Output Add
.

Simulate. Gra-
pher View (. 4.16).

. 4.16. -

104
 - ,
.
.4.16 -
R2 -
K . -
, -
, -
.
700 . -
LM358N.

1. -
?
2. -
.
3.
.
4. .
?
5. -
?
6.
.
7. . -
, .
8. -
. ?
9. .
10.
.
11. ? -
?

105

1. .., .., .. LabVIEW:
: -
. .: , 2005. 182 .
2. .. - -
. .: -XXI, 2007. 528 .
3. .., .. :
. . .: , 2006. 799 .
4. .., . -
. .: , 1994. 352 .
5. .. . .: ,
2006. 232 .
6. .. Multisim 7: -
. / . .
.. .: -, 2006. 488 .

-
http://www.gaw.ru/ .

106
 V.

5.1.
, -
.
-
. , . -
, -
, : -
, . -
, ,
, ( 1)
( 0).

, -
. -
, n .
F ( X 1 , X 2 ,..., X n ) , F -
X 1 , X 2 ,..., X n .
-
. , , -
, . -
-
.
: , -
.
( , )
F = X , , -
().
107
 ( , )
F = X 1 X 2 ,
, . -
: F = X 1 + X 2 .
( , ) -
F = X 1 X 2 ,
, . -
:
F = X 1 X 2 F = X 1 & X 2 .
:
() , -
, -
, . : F = X 1 X 2

F = X 1 X 2 .
( ) ,
,
. : F = X 1 X 2 .
( -) , -
,
. : F = X 1 X 2 .
() , -
, -
. : F = X 1 X 2 .
() ,
,
, . : F = X 1 X 2
F = X1 X 2 .

108
 ( -) ,
,
. : F = X 1 / X 2 .
-
. -
:
( ):
X1 + X 2 = X 2 + X 1 ; X1 X 2 = X 2 X1 (5.1)
( ):
X1 + ( X 2 + X 3 ) = ( X 1 + X 2 ) + X 3 ; X1 ( X 2 X 3 ) = ( X1 X 2 ) X 3 (5.2)
( ):
X 1 ( X 2 + X 3 ) = X 1 X 2 + X 1 X 3 ; X 1 + X 2 X 3 = ( X 1 + X 2 )( X 1 + X 3 ) (5.3)
( ):
X + X + X = X ; XXX = X (5.4)
:
X1 + X 1 X 2 = X1 ; X1 ( X1 + X 2 ) = X 1 (5.5)
:
X 1 X 2 + X 1 X 2 = X 1 ; ( X 1 + X 2 )( X 1 + X 2 ) = X 1 (5.6)
, :
X1 + X 2 = X1 X 2 ; X1 X 2 = X 1 + X 2 (5.7)
, -
:
X + X = 1; X + 0 = X ; X +1 =1 (5.8)
X X = 0 ; X 1 = X ; X 0 = 0 (5.9)
X1 + X 1 X 2 = X1 + X 2 ; X1 ( X1 + X 2 ) = X1 X 2 (5.10)
-
: , ,

109
 , , -
.

, . -
. 5.1.
5.1

X1 X2 F = X1 + X 2 F = X1 X 2
0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1

F ( X 1 , X 2 )
: F = 1 X 1 X 2 = 1 F = 0 , X 1 X 2 = 0 . -
, . 5.1.

. 5.1.

. 5.2. -
, .
, .
() , -
. , -
. , -

110
 ,
, .
5.2

F=X

F=X

2 F = X1 + X 2

2 F = X1 X 2

2- F = X1 + X 2

2- F = X1 X 2

F = X1 X 2

F = X1 X 2

, F = X1 + X 2

F = X1 X 2

111

, , -
.
, -
.
-
, . -
, .
, , , -
.

5.2.
-
.
,
, , -
.
,
. -
,
, , -
, .
,
.

. -
. 5.3.

112
 5.3

X1 X2 F = X1 X 2
0 0 0
0 1 1
1 0 1
1 1 0

, -
, ( X 1 , X 2 ) = (0,1) ( X 1 , X 2 ) = (1,0) . -
, :
X1 X 2 = X1 X 2 + X1 X 2 (5.11)
. 5.2.a.
, 2 2.
-
. ,
X 1 X 1 = X 2 X 2 = 0 , -
, :
X1 X 2 = X 1 X1 + X 2 X 2 + X1 X 2 + X1 X 2 =
= X1 ( X1 + X 2 ) + X 2 ( X1 + X 2 ) = X1 ( X1 X 2 ) + X 2 ( X1 X 2 ) = (5.12)
= ( X 1 + X 2 )( X 1 X 2 )
-
, . 5.2.b.
2, 2 2-, .. .

. 5.2.
113
 , -
.
-
,
. -
n 6 . -
2n .
,
,
.
, , -
.
.
, -
, , .. , -
, . ,
, .


F = X 1 X 2 + X 1 X 2 + X1 X 2 (5.13)
. 5.3
.
, (5.13),
.
,
22=4 . -
. -
.
114
 . 5.3. (5.13)

. 5.4, -
.

. 5.4. (5.13)

, , X 1

X 2 X 2 . X 2

X 2 .
X 1 .

X 1 X 1 , ,
X 2 . ,
, :

115
 F = X1 + X 2 (5.14)
, (5.13)
2.
,
. , -
.

5.3.
-
. -
, , -
. , -

.
. -
-
, -
A, B, C, D, E F.
.
,
.
.

:
k
An = ai n i , (5.15)
i =0

n , ni , ai -
, i=0, 1, 2,, k .

116

. , -
,
, -
0 1. -
.

-
.

2 , .

. -
, -
.
.
29 , -
.
. 5.5. -
.

. 5.5. 29
,

117

.
. , 210=1024, .

.
:
() -
() -
.
-
. -
. .
-
, , -
.

-
, .
, , -
. -
8, 16 32 .
, -
. -
.
.
,
. 0, -
1. -
.
118
 5.4.
, -
, .
,
.
, -
Q. ( )

.
:
(RS, JK, D, T);
( );
(, );
.
.
() -
. -
. -
.
.
RS- (
) R Q -

Q Q . Q -
Q . RS- -
Reset () Set (). S
1 R = 0 Q = 1. , R
1 S = 0 Q = 0. -

119
 S = 1 R = 1 RS- ,
.
RS- :

Qt +1 = R + ( S + Q) , (5.15)

Q Q t + 1 .
RS- -
- . 5.6.
R
1 Q

S T Q

R Q
1 Q
S

. 5.6. RS-

RS- .
-
. -
, RS-
-, (5.15)

S R CS CR :

Qt +1 = CR + (CS + Q) = C + R + (C + S + Q) (5.16)
RS- . 5.7.
C = 0 S = 0 , -
CS , 1,
1. C = 0 R = 0 CR -
1, 0.

120
 C = S = R = 0 , -
.
R CR
1 1 Q

C S T Q
C
R Q
1 1 Q
S CS

. 5.7. RS-

JK- -
J K, -
1
0. RS-, -
J = 1 K = 1
Q .
JK- :
Qt +1 = KQ + J Q (5.17)
JK-
- . 5.8.

. 5.8. JK-

121
 D- -
, D- -
C-. D-
:
Qt +1 = CD (5.18)
, Qt+1
D-,
C-, .. -
. D-
.
D-
- . 5.9.

D
& & Q

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C Q
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. 5.9. D-

T- ,
() T. -
Q .
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Qt +1 = TQ + T Q (5.19)
T-
- . 5.10.
122
 . 5.10. T-

D-,
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U = U in0 U in1 , -
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-
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, . 5.11.

123
 . 5.11. ,

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.
,
U U E ( R1 / R2 ) , U E , ,
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.

, -
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5.5. Multisim
Multisim ,
, .
Logic Converter XLC.

Multisim

XLC1
AB

124

, .

-
. ,
.
,
(. 5.12) -
Conversions .

.

. 5.12.

Conversions -
, .
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, -

125
 . -
, , ,
.
, -
.
-
, .
,
.
,
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.
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-
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. Multisim
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(A B), -
(. 5.3).
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. : AB + AB .
-
NAND.
2-.
. 5.13.

126
 A B

1 2
& 3
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5
&

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. 5.13. ,

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, .

1. ?
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.
4. .
5.
.
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?
11. ?
12. Multisim -
?

127

1. .., .. . .: -
-I, .: -, 2007. 480 .
2. .., .., .. LabVIEW:
: -
. .: , 2005. 182 .
3. ., ., . .
. .: -, 2004. 506 .
4. .., .. :
. . .: , 2006. 799 .
5. .. .
.: , 2005. 336 .
6. .. Multisim 7: -
. / . .
.. .: -, 2006. 488 .

128
 VI.

6.1.
-

,
.
:
(TTL) - ;
(CMOS) -
--.

.

155, 74.
, -

.
. -
555 (74LS), -
,
,
.
-
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2 .
1533 (74ALS).

129

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.
,
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. 176 CD4000A.
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561 1561 (CD4000B) -
U 3
15 .
3 .

1554 (74ACxxx)
150 . 2 6 .

.

0,9 U, 0,1 U.
, -
U.

130
 , -
, . 6.1. -
: t ; F -
; P ,
.
6.1
t, F, P,
K155 74xxx 10 20 12
K555 74LSxxx 10 20 2
K1533 74ALSxxx 3 80 1
K176 CD4000A 100 1 0.001
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KP1554 74ACxxx 3,5 150 0,5

:

-
10
2-3 ;
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-
;
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;
,
;
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. :
(
2 2S);
131
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(. 6.1.b),
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(. 6.1.c),
,
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,
E OE (Output Enable ).

132
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.

. 6.1.

-
,
.
. 6.2.

. 6.2.
(a), (b), (c)
(d)

-
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. -
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.
-
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.
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133
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6.2.

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-
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:
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.
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134

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, . 6.3
C.

. 6.3. 5552

. 6.3 5552 D-
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1. R -
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S R . ,
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135
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5552 . 6.4.

. 6.4. ,
D-
5552

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D0-D1. C -
. -
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D-. Q0-Q1.
R.

.
, .. .

136
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.

.
, D- 5552 -
. 6.5.

. 6.5. 5552

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C, R- .
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C -
,
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Q0Qn.
-
, .
. -
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. ,
137
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,
.
.
,

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K-.
-
:
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() ;
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,
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. 6.6. 5552

D- ,
D-. ,
. -
, .
D-. C -
138
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, D- -
,
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. -
. ,
.

, . -
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. , -

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( -
).
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6.3.

. -
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139
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-
: ; -;
; ; .

140
 . 6.7. 5553 (a),
5556 (b), 1555 (c)

6.4.
-
. -
,
. -
.
, -

1. , -
-
360o.
-

. . ,

, , -
. -

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141
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.
-
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C

DD 1 R DD 2
1 1 Uout

. 6.8.

R
DD1, -
DD2 , . -
C -
, -
.

f 1 / RC (6.1)
, ,
.

. 6.9.

,
, -
. R1 -
. R1/ R2 -
. Z -
142
 1 2 -
. - -
10 30 .

.6.9.

,
0,01%. -
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0,5%.

6.5. - -
- -
.
- ()
,
. :
.
, -
.
. , n-
:
Y = AK ( X 0 20 + ... + X i 2i + ... + X n1 2( n1) ) , (6.2)
143
 A ; K ; i -
; 2-i i- ; Xi 0 1.
, ,
. 6.10.
n-1

2 2 n-1 R

1
2 2R R/2

20 R
Uref
Uout

. 6.10.

-
.
(), -
, . -
, ,
.
2 . -
, .
, :
n 1
U out = U ref X i 2i (6.3)
i =0

,
. , 10-
0,1%.
, 12.

144
 , , -
. 6.11, .
n-1
2
2R 2R

R
1
2
2R

0
R
2
2R R
Uref

Uout

. 6.11.

.
: R 2R.

. - -
,
.
(6.2).

.

.
- -
, . 6.12.

145
 . 6.12.

-
f S. -
-. -
,
= f
n 1
= X i 2i (6.4)
i =0

() , -
. -
:
n1
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i =0

. -
. ,
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2n . , 12-
1 -
4 .
- ()
( )
.
.
146

-

.

-
, .
( --
) t
t = 1/ 2 Fmax , (6.6)
Fmax .
, -
.

, . 6.13.
Uref

= 20
R
21

U in =

n-1
= 2
R . 6.13. -

, -

, . -
147
 .
, ,
, , -
.
.
, , -
.


, 2n, n .
-
,
.
1/2,
1/4, 1/8 .. .
. 6.14.

U in D

R
U

n-1
2 22 21 20

. 6.14.

, , -
. Uin
.

148
 ,

.
-
Uin ,
.
: Uin > U, -
; Uin < U, .
,
.
, t=NT+1,
N , T -
.
-
16. - , -
.
: -
( ,
). -
- . 6.15.

.6.15. -

149
 Uin -
, -
. ,
.
, -
D- Uref.
, -
. -
-
Uin. D-
, .
, - -
.
-
.
.
, . -
, -
, .
- 24
.

6.6. Multisim
Multisim
. -
- -
74160N ( 1559).
. 6.16.

150
 . 6.16.
- 74160N

, -
:
a) Digital Power (VCC) -
Power_Sources Sources;
b) Digital Ground (DGND)
Power_Sources Sources;
c) Clock_Voltage 1 -
Signal_Voltage_Sources Sources;
d) Switch (SPDT) Switch -
Basic, -

;
e) dip- DSWPK_4 Switch -
Basic;

151
 f) 1X4SIP RPACK
Basic;
g) Probe Digital Red -
Probe Indicators;
h) DCD_HEX
HEX_Display Indicators.
74LS160N -
74LS_IC TTL.

. 0 CLR -

0.
CLR,
ENP, LOAD
ENT.
,
CLK.
LOAD
, A, B, C
D.
CLK, -
.
-
Logic Analyzer XLA, -
Multisim.
-
. -
-
Set Clock Clock
152
setup, Clock Source External.
C . -
,
.
(. 6.17).

. 6.17. -
74160N

,
,
, .

153

1. ?
2. ?
3. ?
4.
, ?
5.
?
?
6. -
?
7.
?
8. ? .
9. D-?
10. D-?
11. .
12. ?
?
13. -
?
14.
?
15. ?
?
16.
. .
17. -
, .
18. -
.
19. -
.
20. -
? ?

154
21.
- ?
22. - .
23. - -
. ?
24. -
.
25. - .

1. .., .. . .: -
-I, .: -, 2007. 480 .
2. .., .., .. LabVIEW:
: -
. .: , 2005. 182 .
3. ..
. .: - , 2000. 240 .
4. .. - -
. .: -I, 2007. 524 .
5. .., .. :
. . .: , 2006. 799 .
6. .. - - -
. . .: ; .: -, 2003.
224 .
7. .. .
. . .: , 2001. 379 .
8. .. . .: ,
2001. 224 .
9. .. . .: -,
2007. 800 .
10. .. Multisim 7:
. / . .
.. .: -, 2006. 488.
11. .. . . .:
, 1988. 352 .

155
 VII.

7.1.
,
-
. () -
. -
, ,
. , -
,
(). -
-
, , -
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-. -
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.
.
.
, -
, .
.
:
8- ;
16- 32- ;
.
-
8- , , -
. -

156
 -
, -
. -
8-
, , , -
,
. 8-
-
, , Intel, Microchip,
Atmel, Motorola .
8- , -
, :
,
( ) , -
, -
, , ;
, -

;
,
-
.

, -
, , ,
, - .
. 7.1.
,
,
157
 , ,
.

. 7.1.

:
;
;
;
;
.
,
- (),
, . -
. (-
) -
. , , -
. , ,
.
-
. . ,
( ), ROM (read only memory),
.
-
158
. , ( -
), RAM (random access memory),
.
.
-
. :
.
,
Run Mode, .
.
, Wait
Mode, , -
,
. -
. -
.
Stop Mode.
, -
. -

.

. -

. -
, , -
.

/.
159
 ,
. , -
-
, " ".
-
, .
-
. -
, -
. -
.

. ,
, -
, -
.
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-
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.
-
/. :
,
;
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;
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.
160
 -
, - -
.
-

:
CISC- (Complicated Instruction Set
Computer), ;
RISC- (Reduced Instruction Set Computer),
.
CISC- -
, -
-
.
. -
1 12 .
RISC-
. RISC -
,
.

-
.
. -
, 8, 12 16 .

-
: - .

161
 - ( -
) -
(. 7.2).

. 7.2. -

- -
,
. ,

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. ,
-
.
- -
x86.

, -
. 7.3.

. 7.3.
162
 -

. , -

- -
. -
, -
. -

, -
.
8-
,
, -
. ,
, -
.

7.2. MCS-51
MCS-51 -
8051, Intel
1980 . Intel 50
Intel 8051. ,
Atmel, Philips -
, MCS-51.
-
:

163
 8- - ,
;
12 ;
4;
128 ;
;
-;
(
);
;
8- /, -
/
.

64.
MCS-51 -
, , ;
, , ,
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, . -
- , , -
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,
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.
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255 , 111 .

164
 -
, 12 .
12 1 . -
,
, . -
.

.
8051
-
128 . ,
-
.
, -
,
.
MCS-51 -
CHMOS (Complementary
High Metal-Oxide Semiconductor) -
-,

, , -
.
MCS-51
Intel 8xC51FX,

(PCA). PCA
,
, -
165
 ,
, . -
PCA , -
8xC51FX - , PCA -

.
-
-
, ,
.

7.3. PIC- Microchip

Microchip PIC (Periphe-
ral Interface Controller) 80-

MCS-51
CISC . 8-
PIC RISC -
, . -
PIC-
. -
, -
. , ,

.
, , -
. , ,
. 4 .

166
 PIC--
[]:
PIC12CXXX , -
8- . -
12- (33 ), 14- (35 -
) . ,
-, , -
. 8-
;
PIC16C5X 12-
(33 ), 18-, 20- 28- -
.
. -
( 2 ) -
;
PIC16CXXX 14-
(35 ). -
, -
, -
, - , -
, -, -
, - , ,
;
PIC17CXXX -
16- (58 -
), 33 , -
16 . , 16-
,
-
167
 88,
;
PIC18CXXX -
16- (75 -
) 10- ,
40 . 31- , -
32 4 -
2 .

Microchip
-
8- .
PIC-
, -

FLASH-, -
, .
PIC-
. 8- , -
-
-
. . 12 -
(SFR), -
,
. 0 1.
128 .
.
,
.
168
 . . -

.
-
, -
MPLAB.

7.4. AVR Atmel

AVR Atmel
1997 . -
- ATMEL

.
, -
AVR, RISC
. -
AVR
,
. -
.
AVR
, 32 ,
-,
. -
16- -
,
.

16 . AVR 120 ,
169
 AVR
CISC .

, 1
MIPS (Millions Instructions per Second) -
. , MCS-51
1 -
12 , PIC-
4 , AVR
.
AVR -
:
Mega AVR 4-6 MIPS
, ;
tiny AVR 8-
;
Classic AVR
16 MIPS, FLASH ROM 28 ,
EPROM 64-512 , SRAM 128-512 . -
Classic AVR -
.
AVR :
1 4 - 8 16 ;
10- - ;
;
- ;
3 48 /, ;
UART SPI;

170
 /
( 40 ),
-
.
( , 8- -
),
/, -
-
.
AVR ,
.
AVR.
-
. , -
, ,
. ,
-
16- -,
. -
, .
- -
-
/. 10 , -
.
-
, .
- -
, -

171
 , .
.
AVR -
. -
, , -, -
.
, -
, -
,
. -
. AVR -
, -
.
AVR

, , ,
. ATMEL
AVR-Studio,
-
, -
. -
, -, , -
AVR.

1. .
2. 8-
.
3. ?
4. CISC-?
172
5. RISC-?
6. - -
?
7. .
8.
?
9. MCS-51.
10. PIC--
?
11. 8- AVR?
12. 8- -
AVR?

1. .. . .: -
, 2007. 256 .
2. .., .. AVR: -
. .: -, 2006. 304 .
3. .. AVR Mega. -
. .: -XXI, 2007.
592 .: . ( ).
4. .., .. -
. .: -
, 2006. 440 .
5. : , -
, , ./ . -
. . : , 1998. 272 .
6. .. . .: -,
2007. 800 .
7. .. Microchip. -
. .: - , 2005. 280 .

-
http://www.gaw.ru/ .

173
 VIII. AVR

8.1. AVR
AVR
,
, . -
AVR . 8.1.

. 8.1. AVR

FLASH- -
.
16- 512
64000 . FLASH-,
, ,
.
FLASH -
, , . -

174

. AVR -
, , 1000 FLASH-.
-
,
. AVR -
.
,
.
-
. ,
, -
.
,
,
. -
, , , -
.
AVR
FLASH SRAM ,
,
. -
,
. -
-
.
8-
, . -
AVR : SRAM EEPROM.
175
 SRAM
4K .
64 . SRAM -
.
EEPROM ( 4K ),
, FLASH-. -
. , -
, -
. EEPROM -
,
.
AVR
64
0x000 0xFFFF. -
(. 8.2):
, ;
, /;
, .
-
, . 32
. -
, : R0,
R1, ... , R30, R31. , (R26-
R31) -
, ,
X, Y Z.
.
, , -
, .., -
176
. R0-R15
, /.

0xFFFF

RAMEND+1 SRAM
RAMEND
SRAM
0x0060 SRAM
0x005F 0x5F

...
/
...

0x0020 0x00
0x001F R31
R30
...
R1
0x0000 R0
. 8.2. AVR

/ 64 , -
, -
, , , -
- , /.
/
.
,
. .
, ,
0x0060, -
, , -
177
 . SRAM
. -
. -
, ..
64.
0xFFFF.
, -
-
.
LIFO (Last In, First Out), .. , -
. , , -
, , . -
:
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, .

, -
- .
.
, , -
SRAM,
,
.
AVR-
32 -
.
. ,
, -
, .
178
 8.2. AVR
,
. -
.
(-
) . -
. -
.
-
, , , -
.
, -
-
, .
, AVR -
RISC-, -
-. -
-
, / .
, -
. -
, , -
, .
.
,

/.
.include.
179
 :
;
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-
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, -
-
.

, .
, , -
,
.
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.
180

.
AVR -
.

8.3. AVR Studio

AVR Studio -
Atmel -
AVR. -
-
. , AVR Studio -

, , -
.
AVR Studio , -
:
Create New Pro-
ject;
Open;
, -
.
Project type -
:
Atmel AVR Assembler AVR-;
AVR GCC .
, -
.
.asm, .aps.

181

, .
.
AVR Studio . 8.3.
.

. 8.3. AVR Studio

-
. . ,
, , ,
, .
(), .
Project -
. .
, -

182
, , ,
.
I/O View -
:
- (Timer_Counter);
/ (Port);
(Analog_Comparator);
(AD_Converter);
(Register) ..

. .
- , -
. -
-.
Message -
.
, -
.
, -
, .
.hex.
,
Build. -
. -
Build, (Error),
(Warning) .
.
, -
. , -
183
 .
(), -
.
, -
- .
,
. ,
, ..
-
.
Start
Debugging Debug.
AVR Studio I/O
View, ,
-
-
(. 8.4).

. 8.4. AVR Studio

184
 -
:

Run AutoStep
, -
.

.
. 8.1.
8.1
AVR Studio


Debug

Step into F11


Step over F10

-
Step out Shift+F11


Run to cursor Ctrl+F10

Step into
, ( )
. -
. I/O View.
, , -
, .
,
..

185

.
, .

, .
,
, ,
- .
, -
.
, -
.
, -
, Debug -
Toggle Breakpoint ( ). -

(. 8.4). -
, ,
Toggle Breakpoint, .
, , -
-
Run (). -
, ,
. -
,
.

, Reset.

186
 -
. Stop Debugging
( ).

.hex -
.

8.4. AT STK500
Atmel -
AVR. -
. -
-
.
, ,

"": , -
, ,
. -

.
-
, , RS-232,
. ,
-
.
Atmel -
STK500 AVR, DIP-
. , STK500

187
 -
. STK500 . 8.5.

RS232

. 8.5. AT STK500

STK500 :
DIP;
-
;

;

;

RS232;
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STK500 COM-
RS232. -

188
 AVR Studio Tools ().
STK500 , , -
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STK500. 6 ,
. -

. -
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Program Device -
. -
Erase Device
.
189
 Programming Mode .
STK500 -
: ,
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Erase Device Before Programming
, -
Verify Device After Programming

.
STK500 AVR
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- Flash Use Current
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/ -) - -
AVR Studio Flash Memory view.
hex- ,
Input HEX File ( hex-) .
Fuses -
. Read -
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, -
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190
 .

.
LockBits ,
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Read Signature
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Oscillator Calibration Byte -
RC-. -
-
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RC-. -
Value Read
Cal. Byte.
Flash EEPROM -
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191
 Board
STK500:
VTarget ;
ARef ;
Oscillator .
,
STK500 .
,
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Closest Attainable Freq. -
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192
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Start. -
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193
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ATMega16 STK500.
ATMega16 -
:
DIP-40 (. 8.8);
0 16 ;
16 Flash ;
RC-;
4 - 32 ;
16- 8- -;
10- ;
4 .

194
 . 8.8. ATMega16 DIP

D, -
B.
STK500.
B . -
:
PORTB ($18, $38),
DDRB ($17, $37);
PINB ($16, $36).

D -
. -
3 :
PORTD ($12, $32),
DDRD ($11, $31);
PIND ($10, $30).
PINx
, -
, .

195
 DDxn DDx
-. 1, n-
, 0
.
PORTxn PORTx .
(DDxn=1), -
. 1, -
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AVR.

196
 ;
; STK500
;***********************************************************
.include "m16def.inc";
.list;
.def Temp =r16 ;
.def Delay =r17 ; 1
.def Delay2 =r18 ; 2
;******************
ser temp ; 1
out DDRB, temp ; (PORTB)
;****************** /
LOOP:
out PORTB,temp ;
sbis PIND,0x00 ; PortD.0 = 0,
inc temp ; 1 ,
sbis PIND,0x01 ; PortD.1 = 0,
dec Temp ; 1 ,
sbis PIND,0x02 ; PortD.2 = 0,
ror Temp ;
; 1
sbis PIND,0x03 ; PortD.3 = 0,
rol Temp ;
; 1
sbis PIND,0x04 ; PortD.4 = 0,
com Temp ;
sbis PIND,0x05 ; PortD.5 = 0,
neg Temp ; 1
sbis PIND,0x06 ; PortD.6 = 0,
swap Temp ;
;**** ,
;****
DLY:
dec Delay
brne DLY
dec Delay2
brne DLY
rjmp LOOP ;

-
:
.include
.
.include m16def.inc -
ATMega16. ,
.
197
 .list .
, -
-
.
.def (), -
.
.
Ser Rd 1 Rd.
Out A, Rr Rr
- A.
Sbis A, b b - A
, -
.
Inc Rd Rd .
Dec Rd Rd .
Ror Rd Rd .
Rol Rd Rd .
Com Rd ,
Rd, .
Neg Rd , -
Rd.
Swap Rd
Rd.
Brne k
k.
Rjmp k k.

.
. -
, ,

198
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. -
DDRB .
LOOP:
.
temp B.
D,
temp .
Delay Delay2 -
DLY: .
, -
, -
B .
rjmp LOOP LOOP:
.

199

1. AVR?
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12.
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13.
AT STK500?
14.
AT STK500?
15.
AT STK500?
16. -
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17. -
AVR?

1. AVR STK500. User Guide. Atmel Corporation, 2003. 61 p.
2. .. AVR. .: -
, 2006. 287 .
200
3. .. . .: -
, 2007. 256 .
4. .. . .:
, 2007. 304 .
5. .. . .:
, 2005. 256 .
6. .., .. AVR: -
. .: -, 2006. 304 .
7. .. AVR Mega. -
. .: -XXI, 2007.
592 .: . ( ).
8. AVR PIC . /
. .. . .: -, 2006. 400 .
9. . AVR. . /. .
.: -XXI, 2006. 272 .: . ( -
).

201
 : AVR

1 2 3 4

AND Rd, Rr Logical AND Registers Rd Rd Rr
ANDI Rd*, K Logical AND Register and Constant Rd Rd K
OR Rd, Rr Logical OR Registers Rd Rd v Rr
ORI Rd*, K Logical OR Register and Constant Rd Rd v K
EOR Rd, Rr Exclusive OR Registers Rd Rd Rr
COM Rd Ones Complement Rd $FF Rd
NEG Rd Twos Complement Rd $00 Rd
CLR Rd Clear Register Rd Rd Rd
SER Rd Set Register Rd $FF
TST Rd Test for Zero or Minus Rd Rd Rd

ADD Rd, Rr Add without Carry two Registers Rd Rd + Rr
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C
ADIW Rdl, K Add Immediate to Word Rdh:Rdl Rdh:Rdl+K
SUB Rd, Rr Subtract without Carry two Regis- Rd Rd - Rr
ters
SUBI Rd*, K Subtract Constant from Register Rd Rd - K
SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C
SBCI Rd*, K Subtract with Carry Constant from Rd Rd - K - C
Register
SBIW Rdl, K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K
INC Rd Increment Rd Rd + 1
DEC Rd Decrement Rd Rd 1
SER Rd Set Register Rd $FF

RJMP k Relative Jump PC PC + k + 1
IJMP Indirect Jump to (Z) PC Z
JMP k Jump PC k
RCALL k Relative Subroutine Call PC PC + k + 1
CALL k Call Subroutine PC k
ICALL Indirect Call to (Z) PC Z
RET Subroutine Return PC STACK
RETI Interrupt Return PC STACK
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr)PC PC + 2 or 3
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0)PC PC + 2 or 3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1)PC PC + 2 or 3
SBIC P*, b Skip if Bit in I/O Register Cleared if (P(b)=0)PC PC + 2 or 3
SBIS P*, b Skip if Bit in I/O Register is Set if (P(b)=1)PC PC + 2 or 3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then
PCPC+k + 1
BRBC s, k Branch if Status Flag Cleared If (SREG(s) = 0) then
PCPC+k + 1
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1

202
 1 2 3 4
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then
PC PC + k + 1
BRLT k Branch if Less Than Zero, Signed if (N V= 1) then
PC PC + k + 1
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1
BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1

CP Rd, Rr Compare Rd Rr
CPC Rd, Rr Compare with Carry Rd Rr C
CPI Rd*, K Compare Register with Immediate Rd K

MOV Rd, Rr Move Between Registers Rd Rr
LDI Rd*, K Load Immediate Rd K
LD Rd, X Load Indirect Rd (X)
LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1
LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X)
LD Rd, Y Load Indirect Rd (Y)
LD Rd, Y+ LDLoad Indirect and Post-Inc. Rd (Y), Y Y + 1
LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y)
LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q)
LD Rd, Z Load Indirect Rd (Z)
LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1
LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z)
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q)
LDS Rd, k Load Direct from SRAM Rd (k)
ST X, Rr Store Indirect (X) Rr
ST X+, Rr Store Indirect and Post-Inc. ST (X) Rr, X X + 1
ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr
ST Y, Rr Store Indirect (Y) Rr
ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1
ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr
STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr
ST Z, Rr Store Indirect (Z) Rr
ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1
ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr
STS k, Rr Store Direct to SRAM (k) Rr
LPM Load Program Memory R0 (Z)
ELPM Load Program Memory R0 (RAMPZ: Z)
IN Rd, P In Port Rd P
OUT P, Rr Out Port P Rr
PUSH Rr Push Register on Stack STACK Rr; SP SP-1
POP Rd Pop Register from Stack SP SP+1, Rd STACK
203
 1 2 3 4

SBR Rd*, K Set Bit(s) in Register Rd Rd v K
CBR Rd*, K Clear Bit(s) in Register Rd Rd ($FF - K)
SBI P*,b Set Bit in I/O Register I/O(P,b) 1
CBI P*,b Clear Bit in I/O Register I/O(P,b) 0
LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0
LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),
CRd(7)
ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),C
Rd(0)
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6
SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),
Rd(7..4)Rd(3..0)
BSET s Flag Set SREG(s) 1 SREG(s)
BCLR s Flag Clear SREG(s) 0 SREG(s)
BLD Rd, b Bit load from T to Register Rd(b) T
BST Rr, b Bit Store from Register to T T Rr(b)
SEC Set Carry C1
CLC Clear Carry C0
SEN Set Negative Flag N1
CLN Clear Negative Flag N0
SEZ Set Zero Flag Z1
CLZ Clear Zero Flag Z0
SEI Global Interrupt Enable I1
CLI Global Interrupt Disable I0
SES Set Signed Test Flag S1
CLS Clear Signed Test Flag S0
SEV Set Twos Complement Overflow V1
CLV Clear Twos Complement Overflow V0
SET Set T in SREG T1
CLT Clear T in SREG T0
SEH Set Half Carry Flag in SREG H1
CLH Clear Half Carry Flag in SREG H0
NOP No Operation None
SLEEP Sleep None
WDR Watchdog Reset None

204


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219


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