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Lecture 23: Intro to

Microprogramming
Microprogramming
Microprogramming Definition Microprogramming is a method of
implementing the behavior of
Machine Architecture Review machine instructions (produced by
Control Unit our assembler) by means of more
elementary operations, in direct
Instruction Cycle correspondence with the functions of
Microprogramming the physical components of the
computer.
Microprogramming sees the
computer at a greater level of detail
than the computer architecture level.
It needs to be able to specify state
changes in the components of the
physical structure.

Computer Organization Components


CPU Control Unit fetches instructions,
decodes instructions, causes
Control Unit instructions to be carried out.
Arithmetic logical unit (ALU)
performs arithmetic operations
ALU
(addition, etc.) on data.
Registers
Registers high speed memory cells
(dont need to go through the bus to
access). They vary in number and
Output purpose on different machines.
Input
Buses communication pathways
connecting different
devices/components.
Memory

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8086 Block Diagram
Memory Operation Clock
Control Unit
Control Bus

Interrupt
Flags R
MAR (Memory Address
Register) drives the address
IP
bus ALU
Address
MBR (Memory Buffer Register) AX AH AL Instruction Bus
drives the data bus. BX BH BL
Bus
CX CH CL
Data Interface
DX DH DL
Unit
Figure 4-6, Tannenbaum 3rd Data Registers
Data
Edition Index Registers
Bus
+5V
SI CS
DI DS
BP SS
SP ES

Control Unit

What weve seen: We need to get from the


ALU (combinational circuit) machine code down to the
Registers (sequential circuits) control signals that regulate the
Memory (sequential circuits) gates and circuits.
Early computers hardwired this.
What we havent seen: RISC machines do as well.
Control Unit Microprogramming is an
alternative that allows for
simpler machine hardware.

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Hardwired vs. Hardwired vs.
Microprogrammed Microprogrammed
Control Control (cont.)
Hardwired: Microprogrammed:
composed of combinatorial and design is simpler problem of
sequential circuits that generate timing each instruction is broken
complete timing that corresponds down. Microinstruction cycle
with execution of each handles timing in a simple and
instruction. systematic way.
time-consuming and expensive to easier to modify
design slower than hardwired control
difficult to modify
but fast

Instruction Cycle Micro-Operations

Operation of a computer consists of Each step of the instruction


a sequence of instruction cycles, one
machine code instruction per cycle.
cycle can be broken down
Instruction cycles can be subdivided
further into MicroOperations
into: ( Ops or Operations)
fetch* - retrieving the instruction
indirect retrieving indirect operands
(if any)
execute* - executing the instruction
interrupt handling any interrupts that
may have occurred
*always occur
well look mostly at the fetch-execute
portion

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Fetch-Execute Cycle Fetch (steps 1-3)

1. extract the instruction from Brings the instructions in from


memory
memory to the IR (Instruction
2. calculate the address of the next
instruction, by advancing the PC
Register). Involves four
(program counter) registers:
3. decode the opcode MAR specifies address of
4. calculate the address of the read/write operation
operand (if any) MBR contains value to be
5. extract the operand from memory read/written
6. execute PC contains address of next
7. calculate the address of the result instruction to fetch
8. store the result in memory

Fetch (steps 1-3)


Execute (Steps 4-8)
Sequence of events (at start,
address of next instruction is in the
PC) Unlike Fetch, which is the same
1. latch the address onto the MAR. for all machine instructions, for a
The address can remain set on the machine with N different opcodes
address bus for the entire time
required for the read operation, while there will be N different sequences
it is possible to change the contents of of Ops that can occur!


the PC. Also, not all of the five steps apply


2. bring in the instruction in each case:
address in MAR placed on address bus 4. calculate the address of the operand (if
control unit issues RD signal on control any)
bus 5. extract the operand from memory (if any)
result appears on data bus, is copied into 6. execute
MBR 7. calculate the address of the result (if
3. increment PC to get ready for the storing)
next instruction 8. store the result in memory (if storing)
4. move contents of MBR to IR (frees
up MBR for execute portion of the
cycle)

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Execute Example Putting it All Together

ADD instruction: Our Micro-Ops need to be put


1. MAR = address portion of IR together in an order that makes
sense!
2. MBR = contents of memory at
that address The microprogram implements
3. ACC (Accumulator) = ACC + an algorithm responsible for
MBR sequencing the micro-ops
(ensuring that they are executed
in the proper order) and
executing the micro-ops
(carrying out the state changes
involved in the instruction)

The Microprogram

We need to be able to express the


sequence of steps required to carry
out our instruction cycle.
Heres a set for fetch:
0: MAR = PC; RD;
1: PC = PC +1; RD;
2: IR = MBR;
The semicolon indicates Ops that


are issued at the same time.


The carriage return (different lines)
indicate operations that occur in
sequence.
Why two reads? (RD) read (and
write) takes two instruction cycles.