TRKS-64D805R Power System Controllers

Slave Controller Master and Slave Configuration

Features
Digital Signal Processors (DSP) based with Bel Firmware
Provides power up and power down sequencing
Fault detection and reporting
Analog input monitoring
Voltage margining via closed loop trim
Comparator function
I2C, SMBus, or PMBus compatible serial interface
Configurable through serial interface, Customizable through software
Programmed parameters saved in non-volatile memory
Intelligent configuration capability
Power-down data log for identifying fault conditions
Boot loader for in-system upgrading
3V3 logic levels
Master/slave configuration for support of large power systems
64-pin 10mm x 10mm TQFP package (slave)

Applications
Data storage servers
Networking
Telecommunications

Description
These on board power system controllers provide a cost effective high performance solution for controlling,
monitoring, and sequencing multiple Point of Load (PoL) converters on system boards. The sequencers use a digital
signal processor (DSP) engine and Bels firmware to implement a portfolio of board level control features typically
required in a multiple voltage power system. The master and slave part configuration allows control of large power
systems, either on one system board or separate boards with minimal I/O required between the parts.

The TRKS-64D805R slave part can monitor active trim control and monitoring of up to 8 analog PoL converters and
enable and monitor an additional 5 digital PoLs, VRMs, or other analog inputs.

Figure 1 provides a block diagram of the master/slave system.

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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration
Digital I/Os
Enable, Margin Up/Down, Reset In,
Power Good Out, Reset Out, etc.

Master
Power System Controller MUX select for additional analog voltages

Analog External Reference

Digital I/O Voltage Vin Monitor
Control Monitoring Additional Analog Voltages to Monitor
(analog inputs)
APoL Vout Monitors

I2C Active Trim

Main APoL Trim PWMs
I2C Engine Control Vin
Clock Engine Trim
(PWM outputs)
Data Trim APoL
Circuit Converters
Vout

Internal Enable
Sequence GND
Flash
(board Up/Down
configuration Control PIF Enables
data, (digital outputs)
fault log)

Slave Part
Communication

Digital I/O SPI

(Enable, Power Good) (SS, Clock,
MOSI, MISO)

Master Part
Communication

Digital I/Os Analog External Reference

Digital I/O Voltage Vin Monitor
Control Monitoring Additional Analog Voltages to Monitor
Margin Up/Down, (analog inputs)
Reset In,
Reset Out , etc . APoL Vout Monitors

Clock Active Trim APoL Trim PWMs

I2C Main Vin
I2C Engine Control Trim
Data Engine (PWM outputs) Trim
Circuit APoL
Converters
Vout
Internal Sequence Enable
Flash Up/Down GND
(board configuration Control
data , fault log )
(digital outputs)
PIF Enables
Slave
Power System Controller

Figure 1 Functional Block Diagram

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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration

Theory of Operation
Each part is individually configured to define the rail parameters and sequencing order of the voltages for which each
controller is responsible. Board ID inputs are used to define specific boards so that single code releases can be
deployed across different system configurations.

Though the controllers function independently, their operation is integrated through digital I/O handshaking to handle
enabling and fault detection of the slave controller. When the main controller is enabled, it then enables and monitors
the slave controller like it handles other rails. That is, it asserts the slave enable signal, delays for the configured time,
and then monitors the slave digital power good signal. If a fault occurs on the slave, the master also faults off (if so
configured) with the fault log indicating the slave fault.

SPI communication between the master and slave allows the system host controller a single point of contact to query
and manage the controllers. The system host controller communicates with the master using I2C. If the system host
accesses rails that are managed by the slave, the master passes through the commands to the slave through the SPI
communication between the two parts. The master-slave communication also provides slave fault log details to the
master. There is also an I2C interface in the slave which is used for system boot loading and debugging.

The remainder of this document provides details of the slave part.

I/O Assignment Summary

I/O Type Quantity Signals
Analog Input 15 Vin, APoL 1-8, Analog A-E, Analog Board ID
Digital Input 9 AVS Selection, Enable, Mfg Mode, Margin (2), Reset, Board ID (3)

Digital Output 13 APoL 1-8 Enable, Power Good, Warning, Reset (2), IO PIF En/OVP Trip

PWM Trim 8 APoLs 1-8

External Reference
I2C Communication
SPI Communication
Power
Programming
1 VREF+ (VREF- uses AVSS)
2 I2C Data, I2C Clock
3 SDO, SDI, SCK, (SS not used)
10 VDD, VSS, AVDD, AVSS, VCAP/VDDCORE
3 MCLR, PGD, PGC

I/O Definitions
Pin # Signal Description I/O Type or Function 5V Tolerant
1 APoL 7 Enable Digital Output N
2 APoL 8 Enable Digital Output N
3 Reset B Out Digital Output N
4 Mfg Mode Digital Input Y
5 Margin Low Digital Input Y
6 Margin High Digital Input Y
7 MCLR Programming Y
8 Slave Enable Digital Input Y

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Slave Controller Master and Slave Configuration
Pin # Signal Description I/O Type or Function 5V Tolerant
9 VSS Power N
10 VDD Power N
11 APoL 5 Monitor Analog Input N
12 APoL 4 Monitor Analog Input N
13 APoL 3 Monitor Analog Input N
14 APoL 2 Monitor Analog Input N
15 APoL 1 Monitor Analog Input N
16 VREF+ External Reference N
17 APoL 6 Monitor Analog Input N
18 APoL 7 Monitor Analog Input N
19 AVDD Power N
20 AVSS Power N
21 APoL 8 Monitor Analog Input N
22 Analog A Monitor Analog Input N
23 Analog B Monitor Analog Input N
24 Analog C Monitor Analog Input N
25 VSS Power N
26 VDD Power N
27 Analog D Monitor Analog Input N
28 Analog E Monitor Analog Input N
29 Vin Monitor Analog Input N
30 Analog Board ID Analog Input N
31 Board ID 2 Input Digital Input Y
32 AVS Selection Digital Input Y
33 SDO SPI Communication Y
34 SDI SPI Communication Y
35 SCK SPI Communication Y
36 I2C Data I2C Communication Y
37 I2C Clock I2C Communication Y
38 VDD Power N
39 IO PIF Enable / OVP Trip Digital Output N
40 APoL 1 Enable Digital Output N
41 VSS Power N
42 Power Good Digital Output Y
43 Warning Digital Output Y
44 Reset A Out Digital Output Y
45 Reset In Digital Input Y
46 APoL 1 Trim PWM Trim Y
47 PGD input for ICD Programming N
48 PGC input for ICD Programming N
49 APoL 2 Trim PWM Trim Y
50 APoL 3 Trim PWM Trim Y
51 APoL 4 Trim PWM Trim Y

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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration
Pin # Signal Description I/O Type or Function 5V Tolerant
52 APoL 5 Trim PWM Trim Y
53 APoL 6 Trim PWM Trim Y
54 APoL 7 Trim PWM Trim Y
55 APoL 8 Trim PWM Trim Y
56 VCAP/VDDCORE Power N
57 VDD Power N
58 Board ID 0 Input Digital Input Y
59 Board ID 1 Input Digital Input Y
60 APoL 2 Enable Digital Output N
61 APoL 3 Enable Digital Output N
62 APoL 4 Enable Digital Output N
63 APoL 5 Enable Digital Output N
64 APoL 6 Enable Digital Output N

The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section.
5V tolerant digital output pins can be configured with the open-drain feature which allows the generation of outputs
higher than VDD by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the
maximum VIH specification defined in the Electrical Specifications.

Signal Definitions
Signal Type Definition
Analog Board ID Analog Input Analog voltage for specifying unique board ID. See Board ID below.
Analog Monitor Analog Input Analog input monitor (must be scaled using attenuating resistors if
voltage exceeds reference voltage).
APoL Enables Digital Output Enable signal for the analog PoL converters. Asserted during
sequence up and de-asserted during sequence down.
APoL Monitor Analog Input Analog PoL output voltage monitor (must be scaled using attenuating
resistors if voltage exceeds reference voltage).
APoL Trim PWM Output PWM outputs for actively trimming the analog PoLs to their desired set
points. See Using the PWM Trim Outputs below.
AVS Selection Digital Input When asserted the alternate voltage limits will be used for converters
configured for dual set-points. Any analog POL converters configured
for dual set-points will be trimmed to the alternate set-point.
When de-asserted the normal voltage set-points and limits will be
used.
Board ID Digital Input These three digital inputs along with the Analog Board ID define a
board identification number for controlling which board specific
configuration data is loaded.
I2C Clock I2C Synchronous serial clock input/output for I2C communication. Since
Communications this is an I2C slave device, the master drives the clock. Clock
stretching may occur if necessary according to the I2C specification.
I2C Data I2C Synchronous serial bi-directional data line for I2C communication.
Communications
IO PIF Enable / OVP Trip Digital Output If this pin is configured as the IO PIF Enable, it is the enable signal for
the IO PIF circuit. Asserted during sequence up and de-asserted
during sequence down. If an OVP fault is detected (any monitored

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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration
Signal Type Definition
output voltage is greater than the power good upper limit), the IO PIF
Enable is de-asserted first at power down. If no OVP fault occurs, the
IO PIF Enable is de-asserted last at power down.
If this pin is configured as OVP Trip, it is asserted when an OVP fault
is detected (any monitored output voltage is greater than the power
good upper limit).
Manufacturing Mode Digital Input Enable signal for the hardware margin signals. When asserted the
margin high/low inputs will cause the analog PoLs to be margined to
their configured high/low margin values.
Margin High Digital Input See Manufacturing mode above.
Margin Low Digital Input See Manufacturing mode above.
MCLR* Programming Master Clear (Reset) input. This pin is an active-low Reset to the
device.
PGC Programming Clock input pin for in-circuit programming.
PGD Programming Data I/O pin for in-circuit programming.
Power Good Digital Output Asserted after the configured power good delay after all of the outputs
have been sequenced up and are operating within their configured
power good limits. De-asserted prior to sequencing down due to a
fault or commanded to do so.
Reset In Digital Input When asserted, causes Reset outputs to assert.
Reset Out Digital Output Asserted when Reset In is asserted. De-asserted when any outputs in
configured reset masks are outside of power good limits. Reset
outputs can also be controlled by PMBus commands.
SCK SPI Serial communications clock signal from master to slave.
Communications
SDI SPI Serial communications data signal between master and slave (connect
Communications master SDI to slave SDO).
SDO SPI Serial communications data signal between master and slave (connect
Communications master SDO to slave SDI).
Slave Enable Digital Input Input signal to slave from master. When asserted, the slave will then
sequence up the rails it controls.
When de-asserted, the slave will sequence down the rails it controls.
Vin Monitor Analog Input System input voltage monitor (must be scaled using attenuating
resistors if voltage exceeds reference voltage).
VR Hot Digital Input When asserted, the configured VR Hot action occurs.
Warning Digital Output This output is asserted when any of the monitored output voltages are
less than their configured warning lower limit or greater than their
configured warning upper limit.
AVDD Power Positive supply (filtered VDD) for analog modules. See Powering the
Sequencer below.
AVSS Power Analog ground reference. See Powering the Sequencer below.
VCAP/VDDCORE Power Core decoupling capacitor. See Powering the Sequencer below.
VDD Power Positive supply (3.3V) for peripheral logic and I/O pins. See Powering
the Sequencer below.
VSS Power Ground reference for logic and I/O pins. See Powering the Sequencer
below.
VREF+ External Analog voltage reference (high) input.
Reference

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Slave Controller Master and Slave Configuration
Powering the Sequencer
VDD Core

C8
2.2 uF
10v
X5R

Microchip P/N
D1 MCP1702T-3302I/MB
BAT54
+12Vin or Equivalent
In Out VDD
R1
20 Ohm
1206
C1
C2
3V3 Output LDO C4 C5 C6 C7
1000uF
1uF 1uF 1uF 1uF 1uF
+12Vin Return 25V
16v GND 16v 16v 16v 16v VSS
X5R X5R X5R X5R X5R
R2
4.64 Ohm

AVDD

C3
2.2 uF
10v
X5R

AVSS

R3
1 Ohm

Figure 2 VDD Interface

Figure 2 is a schematic of the typical VDD interface to the sequencer ICs. A Microchip LDO, P/N MCP1702T-
3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most
applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V source.
Capacitors C4, C5, C6, and C7 are the decoupling capacitors and they should be located directly across each pair of
VDD and VSS pins on the IC. The device has a VDD core pin which is used to decouple the internally generated core
voltage. Capacitor C8 is the decoupling capacitor for the VDD core. This decoupling capacitor should be a low ESR
ceramic capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog VDD (AVDD)
and it should be located directly across the AVDD and AVSS pins on the IC. Resistor R2 in combination with C3
provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the input
decoupling capacitor for the LDO and it should be connected directly across the LDOs input and ground pins.
Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and maintain a
stable VDD for a short period after the +12Vin source is removed. The Schottky diode D1 prevents C1 from being
discharged after +12Vin is removed. Resistor R1 is used to protect D1 during the inrush event associated with the
application of the +12Vin. The single pulse peak current rating for a typical BAT54 diode is approximately 600mA. If
the rise time of the +12V source is slow enough to limit the peak charging current into C1 it is possible to eliminate
R1. Assuming a 40mA current draw C1 will provide approximately 188 us of hold up time per uF of capacitance.

Monitoring via ADC Channels

The imbedded ADC channels are converted as 12-bit results with full scale equal to a chosen reference. The device
is intended to be powered from a 3V3 source and can be configured to use this source as the ADC reference or to
use an externally provided reference. Closed loop margining and set point adjustments always use the entire 12-bit
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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration
result to trim the output voltages to specified values. Monitored voltages are reported via I2C communication using
PMBus data formats as defined in the separate communication manual. The voltage range reported is determined by
the entered set points. Any monitored output that is greater than the ADC reference or that can be margined above
this reference should have a voltage divider to limit the maximum input to the corresponding ADC channel to a value
equal or less than the ADC reference. Monitored voltages below the chosen ADC reference do not require this
voltage divider. A four sample moving average is used to filter the ADC results. In most cases this will eliminate the
need for external filtering.

The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value less
than the maximum value of the ADC reference.

Connecting the Control and Monitor Signals

The three primary control interface signals to the attached PoL converters are an enable signal, a voltage monitoring
signal, and trim control signal. The enable signals are labeled <APoL x Enable>. The Monitoring signals are labeled
<APoL x Monitor>. The trim signals are labeled <APoL x Trim>. Each APoL converter is required to share the
corresponding enable, monitor, and trim signals. The firmware assumes that the connections are made this way
when controlling the system.

Communication with the Device

Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus command
set and is defined in a separate communications manual. The communications manual (TRKS-64D805R Protocol)
also define the protocol for device programming via embedded boot loader software.

The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus page
mode as described in the communications manual.

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Slave Controller Master and Slave Configuration

Absolute Maximum Ratings

Parameter Limits
Ambient temperature under bias -40C to +85C
Storage temperature -65C to +150C
Voltage on VDD with respect to VSS -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V -0.3V to 3.6V
Maximum current out of VSS pin 300 mA
Maximum current into VDD pin 250 mA
Maximum current sourced/sunk by any I/O pin 4 mA
Maximum current sunk by all ports 200 mA
Maximum current sourced by all ports 200 mA

Electrical Specifications
Parameter Symbol Min Typ Max Units Notes
Input Voltage Range VDD 3.0 3.30 3.6 VDC
Typical is at 3.3V, 25C, 20 MIPS
Input Current (64-pin slave) IDD 46 55 mA
Max is at 3.3V, 85C, 20 MIPS
Logic Low Input Level VIL VSS 0.2*VDD VDC
VDD VDC Non 5V tolerant pins
Logic High Input Level VIH 0.7*VDD
5.3 5V tolerant pins
Logic Low Output Level VOL 0.4 VDC VDD = 3.3V, IOL 3.0mA
Logic High Output Level VOH 2.4 VDC VDD = 3.3V, IOH -3.0mA
VDD Rise Rate SVDD 0.3 V/ms 0 to 3.0V in 100ms
Capacitance I/O Pin to GND CIO 50 pF
I2C Bus Capacitance CB 400 pF SCL and SDA
PWM Series Resistor RPWM 1 k External Series Resistor
Margin PWM Frequency FPWM 15 kHz
AVSS +
Reference Input VREFH AVDD VDC
2.5
Program Flash Memory Cell EP 10,000 E/W
Endurance cycles

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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration

Mechanical Outline

Bel 64-pin 10x10x1mm TQFP Sequencer

64-Lead Plastic Thin-Quad Flatpack, 10x10x1mm Body
Units Millimeters
Dimension Units Min Nom Max
Number of Leads N 64
Lead Pitch e 0.50 BSC
Leads per side n1 16
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle f 0 3.5 7
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.17 0.12 0.27
Mold Draft Angle Top a 11 12 13
Mold Draft Angle Bottom b 11 12 13
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Champers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

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TRKS-64D805R Power System Controllers
Slave Controller Master and Slave Configuration

Revision History

Date Revision Change Detail

2015-3-13 A First preliminary draft.
2015-4-17 B Updated I/O definitions on pins 32, 39, 47, 48.
2015-04-23 C Minor updates to Signal Definitions.

Errata
Refer to the TRKS-64D805R Errata document for additional information specific to each code release.

RoHS Compliance
Complies with the European Directive 2002/95/EC, calling for the elimination of lead and other
hazardous substances from electronic products.

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