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Modern Physics Letters B

Vol. 27, No. 8 (2013) 1350051 (9 pages)

c World Scientic Publishing Company
DOI: 10.1142/S0217984913500516

THE EFFECT OF ETCHING TIME ON RECTIFYING

CHARACTERISTIC IN SnO2 /p-Si AND SnO2 /p-PoSi
HETEROJUNCTION SCHOTTKY DIODES
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ALIREZA BIARAM and HOSEIN ESHGHI

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Department of Physics, Shahrood University of Technology, Shahrood, Iran

h eshghi@shahroodut.ac.ir

Received 22 November 2012

Revised 10 January 2013
Accepted 16 January 2013
Published 4 March 2013

We have fabricated SnO2 /p-Si and SnO2 /p-PoSi heterojunction diodes by spray pyrol-
ysis method. To prepare porous Si substrates, the etching time was varied from 10 to 20
and 30 mins. In these samples, the SEM micrographs showed a distributed pore areas
surrounded by columnar walls with various height. The data analysis of the rectied
IV characteristic, using thermionic emission Schottky diode theory, showed that al-
though the barrier height is about 0.50.6 eV in all samples other two important diode
parameters, i.e. the ideality factor n and the series resistance rs , are strongly etching
time-dependant and are increased with increasing the etching time.

Keywords: SnO2 /porous silicon diode; IV characteristic; Schottky diode; interface

states.

PACS Number(s): 85.30.Hi, 85.30.Kk, 81.05.Rm, 73.20.-r

1. Introduction
Physical and optical properties of porous silicon (PS) have attracted much attention
in the past few years. The advantages of PS over its crystalline form include large
surface to volume ratio, quantum connement eects, ease of tuning bandgap for
ecient light emission, and high sensing capabilities. Therefore, porous silicon has
been widely used in various industries such as:
(i) Optoelectronics: as light emitting diode (LED) (ecient electroluminescence-
as its key property), waveguide (tunability of refractive index), eld emitter
(hot carrier emission) and optical memory (nonlinear properties).
(ii) Micro-optics: as FabryPerot lters (refractive index modulation), photonic
bandgap structures (regular macro-pore array) and all optical switching
(highly nonlinear properties).

Corresponding author.

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A. Biaram & H. Eshghi

(iii) Micro-electronics: as Micro-capacitor (high specic surface area), Insulator

layer (high resistance).
(iv) Energy conversion: as antireection coatings (low refractive index).
(v) Environmental monitoring: as Gas sensing (ambient sensitive properties).1
On the other hand, tin oxide (SnO2 ) is an interesting material for a wide variety
of special and novel applications, such as gas sensors, thin lm transistors, MIS and
MOS Schottky barrier diodes, opto-electronic devices, and so on. Various methods
such as sputtering, solgel, electron beam evaporation, chemical vapor deposition
and spray pyrolysis have been used to deposit these lms. Among these, the spray
deposition process presents an easy way to integrate SnO2 devices into the Si tech-
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nology, since it oers the possibility of good control on the deposition parameters,
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low processing temperatures and low production costs.

Tin oxide/silicon (smooth crystalline and/or porous), i.e. SnO2 /p-Si and
SnO2 /p-PoSi, with TEAMS (Tunable Electronically Anisotropic Material on
Semiconductor) and TEMPOS (Tunable Electronic Material in Pore on Oxide on
Semiconductor) structure respectively, have special properties such as local negative
dierential resistance (NDR),2 therefore these devices have been studied extensively.
The fact behind these studies is that there is no satisfactory understanding of the
details of electrical transport mechanisms. Furthermore, the formation and charac-
terization of SiO2 insulator layers on Si still remains a basic problem. Until now,
the literature has included several reports on the current transport mechanism of
tunnel MIS diodes and solar cells.3 7 In the case of SnO2 /p-Si interface, it is pro-
posed that the structure behaves like a Schottky barrier diode.8 It appears that
SnO2 layer plays a much signicant role than serving as a contact and is likely to
inuence the currentvoltage characteristics of the SnO2 /Si interface and leads to
increase the series resistance of the diodes.3,9 The IV characteristics of Schottky
diodes which are made from porous silicon (PoSi) covered with a metal oxide thin
lm are reported in some articles.10,11 Due to the complicated structure of porous
silicon, there is not a complete and detailed description of the electrical transport
properties in such devices.
In this paper, we have studied the electrical properties of SnO2 /p-Si and SnO2 /p-
PoSi heterojunctions considering the applied voltage drops across the interfacial
oxide layer. Through this study, we have tried to analyze the forward IV data
by using the standard formulas to nd out the main transport mechanism and the
reasons for the variations of the ideality factor and the series resistance in these
devices, mainly based on the role of the interfacial density of states and the presence
of SiO2 insulator layer.

2. Experimental Details
Pure SnO2 thin lms were deposited using spray pyrolysis method on Si(100)
monocrystal wafer with p-type conductivity and low resistivity of 0.01 cm. We
applied 0.1 M SnCl4 solution with ethanol as its solvent at substrate temperature

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The Eect of Etching Time on Rectifying Characteristic

A
SiO2 SnO2

PoSi

V
p-type Si
Al
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Fig. 1. A schematic device structure together with the IV measurement setup.

of 400C and the spraying rate was kept at 50 ml/min by controlling the carrier gas
ow meter. The spraying time was 1 min that led to a 180 nm tin oxide thin lms
with (110) as the preferred orientation plan and minimum electrical resistivity of
5.31 103 cm.12 Prior to etching a 200 nm aluminum layer was evaporated on
the back of the Si wafer with an annealing process of 500 C for 30 min in N2 am-
bient atmosphere, achieving a low resistance back ohmic contact. Four Si samples
were prepared, one with a smooth face (sample S0) and the others (S10, S20 and
S30) with pore faces by the electrochemical etching method at constant current
density of 45 mA/cm2 for 10, 20 and 30 mins, respectively. The etching electrolyte
solution was a 1:1 volume ratio combination of hydrouoric acid (HF 40%) and
pure ethanol. Electrical and optical measurements were conducted to characterize
the device performance. The IV characteristics of these devices were measured
using HIOKI-3805-50 multimeter with an accuracy of 103 A and 1 mV, in
a simple device structure illustrated in Fig. 1. For Si surface micrographs we have
used the scanning electron microscope (SEM), JEOL:JXA-840 model.

3. Results and Discussions

Figures 2(a)2(c) show the top and the cross-section views of the SEM micrographs
of our prepared porous silicon samples with 10 (S10), 20 (S20) and 30 min (S30)
etching times, respectively. These micrographs (the top views, i.e. the upper images)
show a distribution of black dots (the pores areas) with various diameters of 25 m
wide surrounded by white walls (the columns) with various heights of < 4 m in
S10, 5 m in S20 and 7 m in S30, according to the side views, i.e. the lower
images. The variation in the diameter and the depth of a silicon pore is shown
schematically in Fig. 3. These variations could aect the eective surface of the
silicon/SnO2 interface, which in turn as expected aect the IV characteristic of
the devices, as discussed below.

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A. Biaram & H. Eshghi


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Fig. 2. The top and the cross-sectional views of the SEM micrographs of our p-PoSi samples
with dierent etching times, (a) 10, (b) 20 and (c) 30 mins, respectively.

Fig. 3. A schematic view of the variation in the diameter and the depth of a silicon pore by
increment in the etching time.

Figures 4(a) and 4(b) show the rectifying IV characteristic of the studied
samples between 12 to +12 V in linear and semi-logarithm diagrams, respectively.
As it is obvious compared with S0, in the etched samples the electric current has
considerably decreased, by a factor of 20. A theoretical modeling could help to
nd out the reason behind these treatments. It is well known that the forward IV
characteristic for such realistic diodes could be treated as a thermionic emission
Schottky diode that follows the equation:13,14
 
q(V I rs )
I = Is exp , (1)
nkT
where n is the ideality factor, rs the series resistance of the junction and Is the

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The Eect of Etching Time on Rectifying Characteristic

(a) (b)
0.20 0.04

S0 10-1
0.15 S10 0.03
S20 10-2
S30
Current (A)

Current (A)

Current (A)
0.10 0.02 10-3

10-4
0.05 0.01
10-5 S0
S10
0.00 0.00 10-6 S20
S30
10-7
-0.05 -0.01
-15 -10 -5 0 5 10 15 -10 -5 0 5 10

Bias (V) Bias (V)

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Fig. 4. (Color online) The IV characteristics of our SnO2 /p-Si and SnO2 /p-PoSi heterojunction
devices in (a) linear and (b) semi-log scale diagrams.

diode saturation current which is given by

 q 
B0
Is = AA T 2 exp , (2)
kT
where A is the diode area, A is the eective Richardson constant [= 32 A/cm2 K2
for p-type Si (Ref. 14)], k is the Boltzmann constant, q is the electronic charge, T
is the absolute temperature and B0 the zero bias barrier height.
To solve Eq. (1) in order to determine the various diode parameters such as n,
B0 and rs we have followed Cheung et al. procedure.15 Using Eq. (1), it can be
rewritten as:
dV nkT
= + I rs , (3)
d(ln I) q
where dV/d (ln I) can be calculated by the forward bias IV characteristic exper-
imental data (Fig. 4). Plotting these variations versus diode current I results to
a straight line that its slope and y-axis intercept will give rs and nkT/q values,
respectively (Fig. 5). The results of our calculations are listed in Table 1.
Also from Eqs. (1) and (2), a function called H(I) can be written as:
 
nkT I
H(I) = V ln , (4)
q AA T 2
which simply can be rewritten as:
H(I) = nB0 + Irs . (5)
Similarly, H(I) can also be obtained by the forward bias IV characteristic data.
Figure 6 shows the variations of H(I) versus the diode current, I. As it is obvious
according to Eq. (5), the extrapolation of the best tted straight line with the
y-axis, and its slope provides nB0 , and rs values, respectively. The results of these
calculations are also presented in Table 1. According to these results, there is a
good consistency between the two considered approaches for the evaluations of rs
values.

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A. Biaram & H. Eshghi

10
S0
S10
8 S20
S30
dV / d ( ln I ) 6

4
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2
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0
0.00 0.01 0.02 0.03 0.04

I (Ampers)
Fig. 5. (Color online) The experimental dV /d(ln I) versus I plots for S0, S10, S20 and S30
samples.

Table 1. Calculated electrical parameters of the studied diodes.

n rs () rs () B0 (V) Ds (cm2 )
Sample ID using Eq. (3), Fig. 5 using Eq. (5), Fig. 6 using Eq. (6)

S0 6.2 17 16 0.50 6.59 1013

S10 11.6 220 235 0.58 1.40 1014
S20 12.8 288 274 0.53 1.57 1014
S30 16.1 339 319 0.55 2.02 1014

The results of our data analysis could be summarized as following:

(i) Thermionic emission theory can successfully predict the IV characteristics in

these devices.
(ii) As it is evident, both the ideality factor n and the series resistance rs of the
junctions are increased with increase in the anodizing time. These variations
could be interpreted as:
(a) The relatively big n values in these samples, as seen in other reports
(Table 2), could be explained by the fact that this quantity is mainly
related to the density of interface states and the possible thin insulator
layer at the at junction interface, given by:16
s qDs
n=1 + , (6)
W i i
where Ds is the density of localized states at the interface boundary, W is
the space charge width ( 0.01 m),14 is the thickness of insulator SiO2

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The Eect of Etching Time on Rectifying Characteristic

20
S0
S10
S20
15
S30
H (Volts)
10

5
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0
0.00 0.01 0.02 0.03 0.04

I (Ampers)

Fig. 6. (Color online) The variations of H(I) versus I in various samples.

layer ( 30 A),9,17,18 and nally s and i (= 70 ) are the permittivity of

the semiconductor and the interface layer, respectively.9 Considering the
same parameters in porous silicon samples we have estimated the Ds values
in our studied samples. The results of these calculations for the density of
localized states together with the variations of the ideality factors in these
samples (as given in Table 1) are shown in Fig. 7. According to these
variations, the increment ( 2 to 3 times) in the ideality factor of the
porous devices compared to S0 are directly proportional to the increment
of the eective area at SnO2 /Si interface junction, as proposed by Xu
et al.19 proportional to the localized density of interface states.
(b) Compared with S0, in etched samples rs has increased by a factor of 13
20. This range of increment is consistent with the range of 10100 as
reported by others.19,20 The relatively high rs values in these samples,
especially in the porous ones, could be due to either higher eective junc-
tion surface area at the interface,19 or the presence of thicker insulator
native oxide layer more likely to occur at the interface of these samples
grown by spray deposition at relatively high temperature and the ambient
atmospheric pressure conditions,21 or the lower carrier density in Si-
columns,20 which are evident in our samples (Fig. 2).

(iii) Although the surface porosity has considerably aected on n, rs and Ds values,
it has little eect on the Schottky barrier height (B0 ) of the samples, which
is about 0.55 0.05 eV.

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A. Biaram & H. Eshghi

Table 2. A comparison between the results of

ideality factors reported for various transpar-
ent conductive oxide (TCO)/p-PoSi grown by
spray pyrolysis method, and our work.

Junction n Ref.

SnO2 /p-Si 6.2

this work
SnO2 /p-PoSi 11.616.1

SnO2 /p-Si 1.92.6 3

FTO/p-PoSi 410 10
ITO/p-PoSi 3.8 11
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Density of Localized States, Ds (cm-2)

1015
16
n
Ds
Ideality Factor, n

12

4 1014

0
S0 S10 S20 S30
Sample ID

Fig. 7. The calculated variations for the density of localized states and the ideality factor in the
studied samples.

4. Conclusion
In this paper, we studied the eect of dierent anodizing etching times (10, 20
and 30 mins) on the IV characteristics of SnO2 /p-Si and SnO2 /p-PoSi diodes
fabricated by spray pyrolysis method. We found that all the prepared samples
show a rectifying characteristic. The forward bias data analysis, using thermionic
emission Schottky diode theory, indicated that compared with the smooth face Si
sample, in porous samples with increase in etching time although the barrier height
does not change very much, 0.50.6 eV, the ideality factor and the series resistance
of the junctions are increased by the factors of 2 to 3 and 1320, respectively. These
variations in the former parameter could be due to the increment in the density
of localized states as a result of higher eective surface area at the interface; and
for the latter one, not only the increment in the eective surface area but also the
thicker insulator native oxide layer and/or resistive Si columns are eective.

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The Eect of Etching Time on Rectifying Characteristic

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