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High Frequency VCO Design

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Outline

VCO fundamentals
Low-noise LC VCO topologies
VCO design methodology
Examples of VCOs above 10 GHz
CMOS VCO Design Scaling over Frequency

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VCO Fundamentals: oscillator model

Vi Vo
A resonator

resistance
generator
Negative
RL
b
1<G L <1
Amplifier with selective (positive) feedback or
Negative resistance single-port in parallel with resonant tank

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Oscillation condition: linear feedback model

Amplifier with (selective) feedback model Barkhausen's (or


Nyquist's) criterion
A V osc ,
V osc= Vi
1 V osc , A V osc ,

osc A 0 1 ;osc A V osc =1 ; PHASE[ osc A ]=3 6 0o

The amplitude of the oscillation is stabilized by the


nonlinearity of the transistors in the amplifier

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Example: Cross-coupled oscillator

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A osc =g m R p gm R p =1 osc= g m RP1
L C
gm g 'm W g 'm
1 g m RP= = =
1 1 1
g o g ' o W g ' o
Q osc L Q osc L W Q osc L
1
W
g ' m g ' o Q osc L
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Example: 60 GHz in 65-nm CMOS

Jopt = 0.15 mA/m,


g'm = 1mS/m; go=0.2mA/m,
L=50 pH, Q =10
Note: In reality Q= 2-3 at 60 GHz

1 1
C= 2
= 11 10 2
=141fF
L2 f osc 510 6.28610
1 1
W = =6.63 m
g ' m g ' o Q osc L 0.00081 06.2861 01 051 01 1

IDS >= 1mA


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Oscillation condition: negative resistance model

Negative resistance single-port model


RG 0 3 RL osc ; RG V osc RL osc =0 ; X G V osc , osc X L osc =0

GG 0 3 GL osc ; GG V osc GL osc =0 ; BG V osc , osc BL osc =0

The amplitude is stabilized by the nonlinearity of the negative


resistance device

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Methods to generate negative resistance

L
R<0
L R<0
C
R<0
2
1 LB T
R R
gm T 2 C
2
1 L 1
R L
g m T 1 2 Cg d L 2
Cg dCg s
Adding reactive elements at appropriate transistor terminals
(three topologies above)
Cross-coupled structure with positive feedback

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Example: 60-GHz VCO in 65-nm CMOS

Assume W=50m, gm= 50mS, Cgs =30fF, Cgd=15fF


Calculate L min for Gate-GND inductance

1
L 10 2 1 5
=156.51 p H
6.286 1 0 1 53 01 0

L =0.3nH => R=-50.77 Ohm (but Rs+Rg = 8 Ohm)

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VCO Fundamentals: resonators
High Q (>1000) but not yet integrated in ICs

Dielectric puck (high R) -add varactor

ferroelectric materials hot for tunable resonators

Magnetic & widely (octave) tunable:

Ferrite YIG (yittrium-iron-garnet) sphere

MSW (magnetostatic wave) thin film

Low Q (<100) affording integration in ICs

Lumped LC - tunable with varactor C

T-line with varactor loading for tunability


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Resonator models
C

L L Cm RP

C RP C L
Lm
RS
Cp
t-line k t-line
RS

LC-tank Quartz crystal Dielectric resonator

2
RpRs Q

For inductor: Rp= 1LQ

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VCO Fundamentals: phase noise definition

Phase noise is a measure of oscillator stability and refers to


short-term random fluctuations in f or
Phase noise is defined as the single-sideband power at a
frequency offset fm from the carrier frequency fo measured in a
1Hz band compared to the carrier power

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Phase noise as frequency modulation

The output voltage of the oscillator can be expressed as:


v o t =V osc cos[osc t t ]
where (t) represents the random phase fluctuation
Small phase fluctuations can be represented as:

f
t = sin m t =p sin m t
resulting in fm

v o t =V osc {cososc t cos[p sinosc t ]sinosc t sin[p sinosc t ] }

v o t V osc { p
cososc t {cos[oscm t ]cos [oscm t ] }
2 }
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Phase noise as noise mixing

Noise mixes with oscillator


harmonics

I n f , I n f
*

1/f noise
fm

fm fm fm
0 fosc 2fosc 3fosc Freq
f
fOSC 2fOSC 3fOSC
G
S V 0 G1
G2
fm
G3

f
fOSC 2fOSC 3fOSC

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VCO Fundamentals: Leeson's phase noise
model (Pozar Ch. 12.3, pp.594-599)

f corner

Sm(m)

m , m =FkT f 1
Sm() Sout () FkT f fm
m out P AVS

+ A=1 corner m f m = f f OSC


Vi Vout
Noise-free
amplifier H(m)
o u t f m H f m m =o u t f m
H()

Bandpass filter
m

1 1
H j f = hence H j f m


f OSCf 2 f m QL
1 jQ 1 j
f OSC f f OSC
2 f m QL
1 j
o u t f m =
m
1 Hf m
=m
j
f OSC
2 f m QL
=m 1 j
f OSC
2 f m QL
f OSC
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Leeson's phase noise formula

[ ]
2
f OSC
Pnoise =o u t , o u t =m , m 1
2 f m QL


2
1 V osc p

[ ]
2
Pnoise 2 2 2p 2r m s FkT f f osc f corner
L (fm)= PAVS
=
1 2
= =
4 2
=
2 Pavs
1
2QL f m
1
fm
V osc
2
QL = resonator loaded Q; Pavs = average signal power

Pnoise = noise power in a single sideband of 1 Hz

fm = frequency offset from fosc

F = transistor (amplifier) noise factor with respect to resonator


impedance @ resonance
fcorner = flicker noise corner frequency

f = noise measurement bandwidth = 1 Hz


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Leeson's phase noise formula

Indicates that there can be 4 regions in the L(f) characteristics:


1/f
1/f2
1/f3
0 1/f3 1/f3
f
1/f2 1/f
kTF/Pa v s kTF/Pa v s

Low Q high Q

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Phase noise contributors
Resonator Q. Higher is better.

Oscillation amplitude. Higher is better.

Transistor noise. Lower is better.

Amplitude limitation mechanism (linearity). Avoid HBT


saturation.

Bias supply, current tail & tuning control noise. (differential


control and topology is better).

Buffer amplifier (load) noise. Loading the tank directly is bad


for noise.

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VCO Fundamentals: frequency tuning

Want tunable oscillators:


osc
osc=0 K VCO V cont
2 - 1 = tuning range 2
V2 - V1 = control range

KVCO= VCO gain (sensitivity) 1

2 1
K VCO
V2 V1
Vcont
V1 V2

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VCO Fundamentals: specification
Center frequency: fosc

Tuning range: (f2 f1)/fosc

large to cover process variation


small to reduce phase noise
KVCO increases with center frequency and lower supply
voltage. So does phase noise.
Want constant KVCO over tuning range in PLL design
Tuning linearity (important for PLLs)
Can use linearization techniques

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RF VCO Fundamentals: specification
Phase noise (dBc/Hz)
translates in jitter
easier to measure than jitter
Output amplitude/power
larger is better to reduce noise
trade-off with supply voltage and power
May vary across tuning range (bad)
Power dissipation

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RF VCO Fundamentals: specification
Supply rejection: pushing osc
lower is better V supply

differential topology helps


Common mode rejection helps
Load mismatch rejection: pulling osc
L
lower is better
Improved by better transistor isolation and/or buffer
amplifier between VCO and load
VCO figures of merit


2 2
f osc 1 f osc PAVS
FoM1 = FoM2 =
fm L f PDC fm L f PDC

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Outline

VCO fundamentals
Low-noise LC VCO topologies
VCO design methodology
Examples of VCOs above 10 GHz
CMOS VCO Design Scaling over Frequency

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LC VCO topologies
Selective feedback (L, C, Transformer):
Colpitts (2C + 1L)
Clapp (2C+1LC)
Armstrong (1C + xfmr)
Hartley (1C + 2L)
Negative gm or cross-coupled with tuned amplifier and unity
feedback.

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LC VCO topologies: Selective feedback
Y3 Y3

2 2
1 1 gmV13

Y1 Y2 Y1 Y2
3 3

[ ][ ] [ ]
Y1 Y3 Y3 Y1 V1 0
Gm Y3 Y2 Y3 Gm Y2 V 2 = 0 V1, V2, or V3=0
Gm Y1 Y2 Gm Y1 Y2 V 3 0

[ Gm Y3 Gm Y2
Gm Y1 Gm Y1 Y2 ]
=0 Gm Y3 Y1 Y2 Y1 Y3 Y2 Y3 =0

Gm
G0
= 1

B1 B1
=
B3 B2
1 1 1
=0
B1 B2 B3
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Colpitts topology
Use feedback or negative resistance model
RS is the loss resistance of the inductor

Cgd
In
C1 V1
L
VOSC
C2
V1 VOSC RS

R<0

gm osc L
R= 2 RS=
C1 C2 Q
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Colpitts topology
Analysis at oscillation condition is carried out using large
signal equivalent model for transistor
Gm is the large signal transconductance 2IBIAS
Gm
V1 is the amplitude of the voltage across C1 V1

IBIAS is the transistor bias current

2
Gm
osc C1 C2
=RS or Gm RP=
C1 C2 2
C C
1 2
4
1
f osc [
=2 L Cg d
C1 C2
C1 C2]
2
L C1 C2
C1 C2

2
In
1 1
C1 C Cg s to avoid pushing L f m = 2 2


2
V osc f m 2 C1
C1 1
C2
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LC VCO topologies: Selective feedback
To reduce noise, V1 and V2 should be as large as possible
(limited by transistor breakdown)
VOSC can be larger than the supply voltage but not larger than
the transistor breakdown voltage
V1 depends on inductor (tank) Q and bias current

Gm

1 2 IBIAS Q C1 2IBIAS Q
= V 1
osc C1 C2 Q osc C1 C2 V osc=V 1 1 =
C2 C2 osc

2 2 2
In 1 1 n osc
I C2 2 1
L f m = 2 2 =


2 2 2 2 2 2
V osc f m 2 C1 I f 4Q C1
BIAS m C1
C1 1 1
C2 C2
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Other selective feedback topologies

Clapp

Armstrong

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SiGe HBT: differential Colpitts topology
Negative resistance transistors Q1,2

also act as buffer -> low noise.

HBT sized and biased for optimal noise

Emitter degeneration RE for linearity

Operation on 2nd. harmonic of the LC-


varactor tank is possible (push-push)

L. Dauphinee, M.Copeland, ISCC 1997.

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LC VCO topologies: Cross-coupled
Works well with both MOSFETs and HBTs
4 IBIAS M1
Favoured in MOSFET implementations Gm
V out
Oscillation condition: (gmRP)2 >1

Yo u t =
Gm
2
j
2

Cg s Cd b
2
2 Cg d
Oscillation frequency:

1
f osc=
2 L CCg sCd b 4 Cg d

Use feedback or negative conductance model

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Cross-coupled VCO topology (cont.)

Two stage selective amp. with


positive feedback. Gain per
stage at osc is -gmRp

Needs lower gm than Colpitts to

oscillate. Negative gm increases

with current.

Transistors sized & biased at minimum noise current density and


optimal noise match to tank impedance. In HBT case must use
de-coupling caps for separately biasing the bases of M1 and M2
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MOS cross-coupled VCO topology (cont.)

ISS

Vosc=ISSRp, No built-in load buffering. Buffer amplifier loads tank.

Differential tuning control to reduce noise.

Highest frequency: 300 GHz in 65-nm CMOS [B. Razavi JSSC 2011].

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Cross-coupled VCO topology: symmetrical

p-MOSFET and n-MOSFET cross-


coupled pair to balance the output
signal shape and reduce 1/f noise
which is severe in MOSFET
2L
implementations

Swing is (almost) rail to rail.

Maximum frequency limited by p-


MOSFET performance.

Poor power supply rejection unless


current source is introduced.

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SiGe HBT Colpitts topology improvements
(C. Lee et al. CSICS-2004)

Add inductive peaking to improve gain at HF.


Replace current source tails with resistor RB and
capacitor CB to reduce noise at DC and 2fosc
(Winkler, ISSCC-2003, and RFIC 2003)
Replace resistive RE with inductive emitter
degeneration and add LE 2 to reduce noise at fosc
and 2fosc respectively (Li et al. JSSC Feb. 2003)

1 1
f osc and f osc
2 LE1 Cvar 2 L E2 Cvar

Add common base output buffer to improve


isolation to load (Li et al. JSSC Feb. 2003)
Apply control voltage differentially.

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Quadrature VCOs: Cross-coupled

Two, weakly-coupled VCOs.

0 180 Output signals are 90o out of phase (in


theory): inv. with inductive load
Both tanks operate slightly off
resonance hence noisier than single
tank VCOs
Frequency control implemented in
current tails such that amplitude does
not change with oscillation frequency
90 270
Coupling must be at least 25%
8-phase topologies possible (see J.Lee
& Razavi ISSCC 2003)

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High Q resonator VCO topologies (hybrid ICs)

Reflection line
negative resistance
(common base/gate)
transistor
resonator magnetically
coupled to emitter/source
t-line
R<0
Negative resistance
model is preferred in
analysis
LB
2
1 LB
R
R<0 g m T

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High Q resonator VCO topologies (hybrid ICs)

Feedback
DR= dielectric resonator
MSW=magnetostatic
wave
resonator

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Clapp, crystal, DR oscillator topology

OUT
~~ ~~
t-line Z0 DR
C1 -R DR
C1 C1
BIAS
C2 C2
BIAS t-line Z0
C2

Infineon, IEEE BCTM 2008

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Outline

VCO fundamentals

Low-noise LC VCO topologies

VCO design methodology

Examples of VCOs above 10 GHz.

CMOS VCO design scaling over frequency

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Colpitts VCO design methodology (as LNA)

Design philosophy
Maximize oscillation amplitude Vosc on tank at resonance
because it will minimize phase noise.
i.e. set Vosc as the largest possible voltage allowed by the
technology/power supply I
2
1 1 n
Tradeoff: L f m =


2
f 2m 2
V 2 C1 osc
Low-power (maximum L, lowest bias current) or C1 1
C2
Low-phase noise (lowest L, high bias current)

2
2 2
n osc 2
I C 1
L f m =


2 2 2 2
I BIAS 4Q C1 C1
1 Nallatamby et al., IEEE-trans. MTT, 2003
C2 where In is the total noise current of transistor

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VCO design methodology: Low power

PDC is known, hence, in addition to VOSC, IBIAS is set.


(1)Bias transistor at JOPT to minimize phase noise:
W = IBIAS/JOPT; AE= IBIAS/JOPT
(2)RPMIN LMIN can now be calculated (cross-coupled)

V OSC RPMIN V OSC


RPMIN= L MIN= =
2 I BIAS Q OSC 2 I BIAS Q OSC

(3) Calculate Ceq 1


Ce q =
2OSC L

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VCO design methodology: Low phase noise

(1) Select L as small as possible.


(2) Once L is selected, Ceq is known and assuming Q determined by
the back-end, Rp is also known.
(3) Since RP and VOSC are known, the minimum value of Gm can be
estimated Gm RP C1 C2
2

2
= 2 = > G m RP = 4
osc C1 C2 Q C1 C2
and an initial guess on IBIAS can be made assuming C1= C2 = 2Ceq

Gm
2IBIAS
=

2 I BIAS 1
C1
C2
=2
IBIAS 2
C1 L osc
V1 V OSC V OSC
(4) Bias at JOPT for minimum phase noise => W, AE

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VCO design methodology: Low phase noise (ii)

(5) Select C1 = C'1 + Cgs(be) >> Cgs (be)

C' 1 C' g s W C' 2 C' s b W


Ce q =C' g d W
C' 1 C' 2 C' g sC' s b W

C' 1 Cb e C' 2
Ce q =Cb c
C' 1 C' 2 Cb e

(6) Iterate (3) (5) to account for layout parasitics.

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Colpitts VCO Design (continued)

Choose LS large (AC open)


Add RSS, CSS and LSS for bias and
noise de-coupling
VCTRL can be digital (DCO)

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Design Example: 80-GHz Colpitts DCO

C=C ' ACC W u n i t

C fF
CMIN C' ACC1.5
2 m

CT =2 n 1 CMINCCMIN b 0 b 1 2 1 b 2 2 2 ...b n1 2 n1

[M. Khanpour, M.A.Sc. Thesis, Univ. of Toronto, 2008]


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Design optimization

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Simulated vs. meas. tuning curve

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DCO Measurements: PN, Pushing
Phase noise: -85 dBc/Hz to -92 dBc/Hz @1MHz Pushing < 100
MHz/V

For VDD=1.1-1.3V
Pushing < LSB=31MHz

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Cross-coupled VCO Design

Choose LTANK

Bias transistors at optimum noise


current density (0.15 mA/ m)

Size transistors to provide


adequate negative resistance

Calculate CVAR from operating


frequency
Provide buffer to shelter tank

VCTRL can be digital (DCO)

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Frequency scaling

1
f OSC
LC

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Frequency Scaling
But...
LT A N K/k transistor R-parasitics do
not scale since W/k: (Rs+Rg ) k

C1 /k
k fOSC
CVAR /k
1
f OSC
LC
Same applies to cross-coupled VCO
For the same VOSC, transistor size and bias current must remain
constant

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VCO test structures in 180-nm, 90-nm, 65-nm
CMOS (digital back-end)
8 2 1.6
Colpitts 90-nm 90-nm 180-nm 180-nm 90-nm 90-nm 65-nm
VCO 10 GHz 80GHz 25 GHz 50 GHz 50 GHz 80 GHz 80 GHz

LTANK [pH] 435 50 200 100 100 60 40


C1 [fF] 800 100 100 50 50 35 80
CVAR [fF] 800 100 100 50 50 35 80
Wf [um] 1 1 2 2 2 2 0.8
Nf 100 60 40 20 20 16 76

Nf does not scale with L and C at very high frequency


because of parasitic gate and source resistances

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VCO test structures (ii)
8 2 1.6
Colpitts 90-nm 90-nm 180-nm 180-nm 90-nm 90-nm 65-nm
VCO 10 GHz 80GHz 25 GHz 50 GHz 50 GHz 80 GHz 80 GHz

fosc (GHz) 10-12 74-80 23-24.5 49-50.5 49-54 80-85 79-84


Wf ( m) 1 1 2 2 2 2 0.8
PDC (mA) 36 37.5 86.4 57.6 50 37.5 74(32)
POUT(dBm) 4 -13.6 -1 -9 -12 -17 -3
PN 1MHz -117.5 -100.3 -98.8 -92.6 -76 -80 -95.7

Wf has a dominant impact on phase noise

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Cross-coupled VCO test structures

Cross-coupled 90-nm 90-nm 180-nm


VCO 10 GHz 12 GHz 17 GHz

LTANK [pH] 435 273 70


CVAR [fF] 260 260 70
Wf [um] 1 1 2
Nf 24 24 40

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10-GHz Colpitts VCO
Tuning range:
9.2 10.4 GHz
(11.8%)

Record phase noise:


-117.5 dBc/Hz @ 1 MHz (100 avg.)

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77-GHz Colpitts VCO
Record tuning range:
73.8 80.0 GHz (8.3%)

Record phase noise:


-100.3 dBc/Hz @ 1 MHz (100 avg.)
20log(8) 17dB higher than
10-GHz VCOs phase noise!

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10-GHz Cross-coupled VCO
Tuning range:
9.3 10.9 GHz (15.8%)

Phase noise:
-109.2 dBc/Hz @ 1 MHz (100 avg.)

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77-GHz 90-nm CMOS cross-coupled VCO

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Colpitts VCOs in SiGe BiCMOS and 65-nm CMOS
( S. Nicolson et al. BCTM-2006, E.Laskin et al. ISSCC-2008)

76 GHz, 96 GHz and 104 GHz, 90 GHz, quad + buffers, PDC= 86.4 mW,

PDC= 120 mW, 2.5V 1.2V,

3% tuning range 80-GHz DCO, PDC= 60 mW, 1.1V,

3.5%-5% tuning range


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90-GHz 65-nm CMOS vs. 104-GHz SiGe HBT
Colpitts VCO phase noise

-95 dBc/Hz @ 90 GHz -101 dBc/Hz @104 GHz

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VCO and Buffers
150m

Symmetry is maintained throughout VCO

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VCO Tuning & Output Power

88.2 91.2GHz tuning range for all


temperatures
+3dBm to -4dBm total VCO output power

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60-GHz Colpitts-Clapp DCO

PDC= 25.8 mW, Pout = 3dBm


PN @ 1MHz : -110 dBc/Hz
[E. Laskin et al. RFIC 2011]

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110-GHz Armstrong VCO

PDC= 36 mW, Pout = 1dBm


PN @ 1MHz : -104 dBc/Hz
E. Laskin, Ph.D. Thesis 2010
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120-GHz Colpitts VCO

PD C= 76 mW, Pout = 6dBm


PN @ 1MHz : -111 dBc/Hz
E. Laskin, Ph.D. Thesis 2010

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Summary
VCOs are critical blocks in both radio and optical fiber systems
VCO design methodology involves a combination of PA and LNA
design techniques
Maximum allowed voltage in a technology is critical in VCOs
VCOs can be algorithmically scaled in frequency and ported across
technology nodes
Colpitts topology exhibits lower noise and higher output power than
cross-coupled topology at mm-wave frequencies

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