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9, SEPTEMBER 2015
AbstractMultiple-output Switched Mode Power Sup- the neutral current in the distribution system increases if these
plies (SMPSs) for personal computers (PCs) normally PCs are used in large numbers which creates serious problems
depict extremely bad power quality indices at the utility like overloading the neutral conductor, noise, de-rating of the
interface such as total harmonic distortion of the input
current being more than 80%, power factor being lower than transformer, and voltage distortion [3][5].
0.5 and output voltage regulation being very poor. They To end these problems, improved PQ SMPSs that are ca-
violate the limits of harmonic emissions set by interna- pable of drawing a sinusoidal input current at unity power
tional power quality standards. In this paper, a nonisolated factor (UPF) and yielding stiffly regulated output voltages,
power factor corrected (PFC) converter is being proposed are extensively being researched. Employing various power
to be used at the front end to improve the power quality
of an SMPS for a PC. The front-end converter is able to factor corrected (PFC) single-stage and two-stage converters
reduce the 100-Hz ripple in its output that is being fed to effect a perceivable PQ improvement in these SMPSs [6][10].
the second stage isolated converter. The performance of PQ improvement is visible in the form of low total harmonic
the front-end Zeta converter is evaluated in three different distortion (THD) in the ac mains current and power factor
operating conditions to select the best operating condition being close to unity at the point of common coupling (PCC).
for the proposed SMPS system. The performance of the
proposed SMPS is simulated and a laboratory prototype This is achieved even under varying loads and supply voltage
is developed to validate its performance. Test results are conditions. In a single-stage SMPS, ac supply is connected to a
found to be in line with the simulated performance under DBR whose output is processed by a multi-output PFC isolated
varying input voltages and loading conditions and all the dc-dc converter for obtaining dc voltages. The reliability of this
results demonstrate its enhanced performance. single-stage SMPS is good; however, the output capacitors used
Index TermsMultiple outputs, power factor corrected are of very high value to reduce the 100 Hz ripple content. So,
Zeta converter, power quality, switched mode power supply the rating of any single-stage SMPS is limited to about 200 W
(SMPS), unity power factor. to avoid prohibitively high capacitance value.
For medium power ratings, two-stage SMPS is a commonly
I. I NTRODUCTION accepted solution in the SMPS market for PCs. The first stage
is meant for improving the power quality at the PCC and for
I N the present era, personal computers (PCs) have become a
part of our day-to-day activities from business to education
to infotainment. Switched Mode Power Supply (SMPS) is an
providing regulated dc output voltage to the isolated (second)
stage. The selection of operating mode of the front-end con-
integral part of the computer that converts ac to multiple numbers verter may be in Discontinuous Conduction Mode (DCM) if the
of suitable dc voltages to impart power to different parts of the cost is a major consideration; if not, Continuous Conduction
PC. It contains a diode bridge rectifier (DBR) with a capacitor Mode (CCM) is adopted that reduces device stresses, despite
filter followed by an isolated dc-dc converter to achieve multiple the fact that CCM uses two voltage and one current sensors
dc output voltages of different ratings. The uncontrolled charg- which naturally makes it costlier. Therefore, a DCM operation
ing and discharging of the capacitor result in a highly distorted, of the front-end PFC converter is preferred in PCs where only
high crest factor, periodically dense input current at the single one voltage sensor is needed for sensing and control.
phase ac mains; this violates the limits of international power A boost converter is a common choice as a PFC in various
quality (PQ) standards such as IEC 61000-3-2 [1], [2]. Further, industrial applications. However, it cannot be used if a wide
range of ac mains voltage is to be taken care of [11]. Similarly,
Manuscript received July 21, 2014; revised October 29, 2014 and due to limited output voltage range buck converters are not
January 11, 2015; accepted February 16, 2015. Date of publication preferred for computer power supply [12]. Nonisolated buck-
March 23, 2015; date of current version August 7, 2015. This work boost PFC converter configurations are the best suited for
was supported by the Department of Science and Technology (DST),
Government of India, under Grant RP02506. maintaining a constant dc output voltage irrespective of wide
The authors are with the Department of Electrical Engineering, variations in ac supply voltages. Different buck-boost convert-
Indian Institute of Technology Delhi, New Delhi 110 016, India (e-mail: ers configurations and their application to SMPS are reported in
ishikha.singh@gmail.com; bsingh@ee.iitd.ac.in; bhuvan@ee.iitd.ac.in;
vashist.bist@gmail.com). the literature [13][19]. A conventional buck-boost converter
Digital Object Identifier 10.1109/TIE.2015.2415752 has a low component count. However, the output current is
0278-0046 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
SINGH et al.: PFC ZETA CONVERTER BASED IMPROVED POWER QUALITY SMPS 5423
Fig. 5. Operating modes of the isolated converter in one half of the switching cycle.
Therefore, the instantaneous value of duty ratio, D(t) is B. Output Inductor Selection
expressed as
The critical value of output inductor is estimated as
Vdc
D(t) = . (2) (1 D(t)) TVdc Vdc DT Rin Vdc D(t)T
Vin (t) + Vdc Lz2 min = (t) = =
2Idc 2Iin (t) 2Vin (t)
A. Input Inductor Selection Vd2 TVdc Vdc
=
2Vin (t)Pin Vin (t) + Vdc
The critical inductance value of the input inductor is
(153.1 V)2 50 S 300 V 300 V
D(t)TVin (t) Rin D(t)T V2 D(t)T =
Lz1 min = = = d 2 350 W 1.414 170 V 1.414 170 V+300 V
2Iin 2 2Pin
2
= 1.15 mH. (5)
V T Vdc
= d
2Pin Vin (t) + Vdc The maximum current ripple in this inductor occurs at the
(153.1 V)2 50 S 300 V maximum power and for minimum value of supply voltage
= (170 V). So, the minimum inductance value for operating the
2 350 W (1.414 170 V) + 300 V
output inductor in DCM is estimated as 0.7 mH.
= 0.92 mH (3) Similarly, Lz2 while operating in CCM is expressed as
where Vd is the uncontrolled dc voltage, D is the duty ratio, T (1 D(t)) TVdc Vdc DT
is the total switching time in one switching cycle (here, 50 s). Lz2 min = =
Io Iin (t)
The critical value of input inductor Lz1 is proportional to the
rms value of supply voltage. Therefore, the worst case design Vdc T Vdc
=
occurs for the minimum value of supply voltage of 170 V. Iin (t) Vin (t) + Vdc
The minimum input inductor value from (1) is 0.92 mH. The
300 V 50 S 300 V
selected value of inductor Lz1 is 0.2 mH for maintaining it in =
0.5 2.05 A 1.414 170 V 1.414 + 300 V
DCM under all operating condition.
To design the input inductor in CCM, its minimum value is = 5.75. mH. (6)
expressed as
The selected value of inductor Lz2 is 6 mH for maintaining it
D(t)TVin (t) Vin (t)T Vdc in CCM.
Lz1 min = =
iin (t) iin (t) Vin (t) + Vdc
C. Intermediate Capacitor Selection
1.414 170 V 50 S 300 V
=
0.50 2.05 A 1.414 1.414 170 V + 300 V The capacitor is used to transfer energy from the input to the
= 4.6 mH. (4) output in a controlled manner. The intermediate capacitor C1
experiences two conflicting constraints, namely, it should have
Hence, a 5 mH is selected for CCM operation of the input nearly a constant value of voltage within one PWM cycle and
inductor. also follows the input voltage profile in line frequency period.
SINGH et al.: PFC ZETA CONVERTER BASED IMPROVED POWER QUALITY SMPS 5427
D(t)TVdc TVdc
C1 = Rdc =
2VC1 2 {Vdc + Vin (t)} (Vdc
2 /P )
in
Vdc TPin
=
Vdc +Vin (t) 2(Vdc +Vin (t))2
50 S 350 W
= = 18.8 nF. (7)
2(300 V + 270 V 1.414)2
D(t)TVdc
C1 = The filter inductor to maintain low ripple is calculated as
2VC1 Rdc
1
TVdc Vdc Ld = (11)
= 4 2 fc2 Cd
2 { (Vdc + Vin (t))} (Vdc
2 /P ) V
in dc + Vin (t)
where fc is the cutoff frequency which is selected such that it is
TPin
= more than the fundamental frequency (f = 50 Hz) and less than
2 { (Vdc + Vin (t))} (Vdc + Vin (t)) switching frequency fs (20 kHz). Therefore, it is taken as 2 kHz
50 S 350 W here. Ld from the above equation is calculated as 3.1 mH and
=
2{0.3 (300 V+270 V 1.414)}(300 V+270 V 1.414) the selected value in hardware is 3 mH. The selected component
values are tabulated in Table I.
= 0.0628 F (8)
V. C ONTROL OF THE P ROPOSED PC SMPS
where, is the permitted ripple in the intermediate capacitor
voltage. The selected value of intermediate capacitor is of the Two independent controllers are used to control the dc out-
order of 0.066 F for maintaining it in CCM under all operating put voltages of the PFC converter and the isolated converter
conditions. [21], [23]. The front-end converter is controlled using voltage
follower approach while the isolated converter utilizes average
current control.
D. Output Capacitor Selection
The input capacitor(s) of the isolated converter also works A. Control of PFC Converter
as the output capacitor of the Zeta converter. It is selected such The control of the front-end PFC converter generates pulses
that it eliminates the second order harmonic voltage introduced according to the output voltage error, which is the voltage
due to the single phase ac mains. The output capacitor value is difference between the desired voltage and sensed voltage. The
selected as voltage error signal (Ve ) at nth instant is
Idc Ve (n) = Vdcref (n) Vdc (n). (12)
Ch = . (9)
2Vdc
Ve is fed to the proportionalintegral (PI) controller to generate
The estimated output capacitors are calculated as 400 F for a controlled output voltage (Vco )
a 9V ripple. The selected value of output capacitors Ch1 = Ch2
are taken as 330 F in hardware. Vco (n) = Vco (n1)+kp Ve (n)Ve (n1)+ki Ve (n) (13)
TABLE II
D ESIGN S PECIFICATIONS OF THE Z ETA C ONVERTER B ASED SMPS
VII. H ARDWARE V ERIFICATION performance of the proposed Zeta PFC converter based SMPS
is described in this section.
The design and simulated performances of the proposed
SMPS given in the previous section are validated through
A. Comparison With Conventional SMPS
developed hardware when the front-end Zeta converter is oper-
ating with Lz2 in DCM. The output voltage is controlled and Recorded test results for a conventional SMPS at rated
regulated by means of a Digital Signal Processor (DSP). A voltage are shown in Fig. 9. The THD of input current is
20-kHz switching frequency is used to gate the switch of the 83.5% and the PF is as low as 0.48 [Fig. 9(b) and (c)]. The
Zeta converter for effective control and reduction in component SMPS draws periodically dense, peaky, harmonic rich input
size. Test results are recorded by using a digital storage os- current. Thus, the performance of conventional SMPS grossly
cilloscope and single phase power analyzer. The experimental violates the international PQ standards set by IEEE and IEC.
5430 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 9, SEPTEMBER 2015
VIII. C ONCLUSION
A DCM operated front-end PFC converter cascaded with a
multiple output isolated converter has been used for the design
of an SMPS for PCs. It has been designed, modeled, simulated
and developed for input power quality improvement and output
voltage regulation. All the dc output voltages are regulated
by controlling only one output voltage. Three different modes
of operation of the front-end converter have been carried out
in simulation to select the best possible operation especially
based on device stresses. Finally, the best suited mode of
operation for the front-end converter has been implemented
in an experimental prototype. Test results obtained from the
prototype conform to the ones obtained via simulations. From
the recorded test results, it is evident that the proposed power
Fig. 14. Performance of the proposed SMPS at light load. (a) ac mains supply is able to mitigate power quality problems that are
voltage/current. (b) Input power and PF. (c) Input current harmonic
spectrum. present in the conventional SMPS systems. Based on these
results, it is concluded that the proposed SMPS configuration
in PCs is expected to yield improved THD of ac mains cur-
rent with almost unity PF under wide range of input voltages
and loads.
A PPENDIX
A. Design of Input Capacitor for Proposed Power Supply
The input capacitor is designed to reduce the 100 Hz ripple
which is reflected from the single phase ac mains. The input
power Pin for a single phase ac mains is expressed as [6]
Vin Iin
ic (t) = cos 2t (15)
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SINGH et al.: PFC ZETA CONVERTER BASED IMPROVED POWER QUALITY SMPS 5433
Shikha Singh (S11) received the B. Tech. de- G. Bhuvaneswari (SM99) received the B.Tech.
gree in electronics and communication engi- degree in electrical engineering from the Col-
neering from Uttar Pradesh Technical University, lege of Engineering Madras, India, in 1977 and
Lucknow, India, in 2008 and the Ph.D. degree the M. Tech. and Ph.D. degrees from the Indian
from the Indian Institute of Technology Delhi Institute of Technology (IIT), Madras, India, in
(IIT-D), New Delhi, India, in 2014. 1988 and 1992, respectively.
Since 2014, she has been an Assistant She is a Professor in the Department of Elec-
Professor in the Department of Electrical and trical Engineering, IIT Delhi, New Delhi, India.
Electronics Engineering, National Institute of Her fields of interest include power electronics,
Technology Delhi, New Delhi. Her areas of in- electrical machines and drives, active filters,
terest include power electronics & SMPS. and power conditioning.
Dr. Bhuvaneswari is a Fellow of the Institution of Electronics and
Telecommunication Engineers (IETE).
Bhim Singh (SM99F10) received the B.Eng.
degree in electrical engineering from the Uni-
versity of Roorkee, Roorkee, India, in 1977, and
the M.Tech. degree in power apparatus and sys-
tems and the Ph.D. degree from Indian Institute
of Technology Delhi (IIT-D), New Delhi, India, in
1979 and 1983, respectively.
In 1983, he joined the Department of Elec-
trical Engineering, University of Roorkee, as a Vashist Bist (M13) received the Diploma and
Lecturer. He became a Reader there in 1988. B.E. degree in instrumentation and control en-
In December 1990, he joined the Department gineering from Sant Longowal Institute of En-
of Electrical Engineering, IIT-D as an Assistant Professor, where he gineering and Technology (SLIET Longowal),
became an Associate Professor in 1994 and a Professor in 1997. Punjab, India, in 2007 and 2010, respectively. He
Dr. Singh is a Fellow of the Indian National Academy of Engineering is currently working toward the Ph.D. degree in
(INAE), the National Science Academy (NSc), the Indian Academy of the Department of Electrical Engineering, Indian
Science (IASc), the Institute of Engineering and Technology (IET), the Institute of Technology Delhi, New Delhi, India.
Institution of Engineers (India) (IE(I)), and the Institution of Electronics His areas of interest include power electron-
and Telecommunication Engineers (IETE). ics, electrical machines, and drives.