Part3 (2 Files Merged)

WOMEN SAFETY USING IOT
2.1 Literature Survey
Existing System
Keeping the same concern in mind many developers have come up with
innovative applications. Few of such applications are as follows-
1. VithU app:
This is an emergency app initiated by a popular Indiancrime television series
Gumrah aired on Channel in this app when the power button of the Smartphone is
pressed twice consecutively, it will begin sending out alert messages with a link to the
location of the user every two minutes to the contacts fed into the app.
2. SHE (Society Harnessing Equipment):
It is a garment designed by three engineers from Chennai. This garment has an
electric circuit that can generate 3800kv of current which can help the victim to
escape. In case of multiple attacks, it can send up to 82 electric shocks. Since the
fabric is bilayer, the user is not affected. It can also send emergency messages.
3. ILA security:
The co-founders of this system, McGivern, James Phillips, and Neil Munn,
have designed three personal alarms that can shock and disorient potential attackers
and draw attention to dangerous situations.
4. Using Pressure Sensors:
The proposed system is to designa portable device which resembles a normal
belt. It consists of Arduino Board, threshold of the pressure sensor crosses, the device
will get activated automatically. Immediately the location of the victim will be tracked
with the help of GPS and emergency messages will be sent to three contacts and one
to police control room every two minutes with updated location. The screaming alarm
unit will be activated and will send out sirens to call out for help.
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3.1 BLOCK DIAGRAM
Fig: 3.1 BLOCK DIAGRAM
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3.2 POWER SUPPLY

The input to the circuit is applied from the regulated power supply. The A.C
input i.e., 230V from the mains supply is step down by the transformer to 12V and
is fed to a rectifier. The output obtained from the rectifier is a pulsating D.C
voltage. So in order to get a pure D.C voltage, the output voltage from the rectifier
is fed to a filter to remove any A.C components present even after rectification.
Now, this voltage is given to a voltage regulator to obtain a pure constant dc
voltage.
Step supply
Bridge Filter
down Regulator
Rectifier Circuit
T/F
Power to all sections
Fig:3.2 Power supply
Transformer:
Usually, D.C voltages are required to operate various electronic equipment
and these voltages are 5V, 9V or 12V. But these voltages cannot be obtained
directly. Thus the A.C input available at the mains supply i.e., 230V is to be
brought down to the required voltage level. This is done by a transformer. Thus, a
step down transformer is employed to decrease the voltage to a required level.
Rectifier:
The output from the transformer is fed to the rectifier. It converts A.C. into
pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this
project, a bridge rectifier is used because of its merits like good stability and full
wave rectification.
Filter:
Capacitive filter is used in this project. It removes the ripples from the
output of rectifier and smoothens the D.C. Output received from this filter is
constant until the mains voltage and load is maintained constant. However, if either
of the two is varied, D.C. voltage received at this point changes. Therefore, a
regulator is applied at the output stage.
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Voltage regulator:
As the name itself implies, it regulates the input applied to it. A voltage
regulator is an electrical regulator designed to automatically maintain a constant
voltage level. In this project, power supply of 5V and 12V are required. In order to
obtain these voltage levels, 7805 and 7812 voltage regulators are to be used. The
first number 78 represents positive supply and the numbers 05, 12 represent the
required output voltage levels.
Overview of Embedded System Architecture
Fig: 3.3 Layered Architecture of Embedded System
Every embedded system consists of custom-built hardware built around a

Central Processing Unit (CPU). This hardware also contains memory chips onto
which the software is loaded.
The software residing on the memory chip is also called the firmware. The
embedded system architecture can be represented as a layered architecture as shown
in Fig.
The operating system runs above the hardware, and the application software
runs above the operating system. The same architecture is applicable to any
computer including a desktop computer. However, there are significant differences.
It is not compulsory to have an operating system in every embedded system. For
small appliances such as remote control units, air conditioners, toys etc., there is no
need for an operating system and you can write only the software specific to that
application.
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Now, let us see the details of the various building blocks of the hardware of an
embedded system.
Central Processing Unit (CPU)

Memory (Read-only Memory and Random Access Memory)
Input Devices
Output devices
Communication interfaces
Application-specific circuitry
Fig: 3.3.1 Building Blocks
Central Processing Unit (CPU):

The Central Processing Unit (processor, in short) can be any of the
following: microcontroller, microprocessor or Digital Signal Processor (DSP). A
micro-controller is a low-cost processor. Its main attraction is that on the chip itself,
there will be many other components such as memory, serial communication
interface, analog-to digital converter etc. So, for small applications, a micro-
controller is the best choice as the number of external components required will be
very less. On the other hand, microprocessors are more powerful, but you need to
use many external components with them. D5P is used mainly for applications in
which signal processing is involved such as audio and video processing
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Memory:
The memory is categorized as Random Access 11emory (RAM) and Read
Only Memory (ROM). The contents of the RAM will be erased if power is switched
off to the chip, whereas ROM retains the contents even if the power is switched off.
So, the firmware is stored in the ROM. When power is switched on, the processor
reads the ROM; the program is program is executed.
Input devices:
Unlike the desktops, the input devices to an embedded system have very
limited capability. There will be no keyboard or a mouse, and hence interacting with
the embedded system is no easy task. Many embedded systems will have a small
keypad-you press one key to give a specific command. A keypad may be used to
input only the digits. Many embedded systems used in process control do not have
any input device for user interaction; they take inputs from sensors or transducers
1fnd produce electrical signals that are in turn fed to other systems.
Output devices:
The output devices of the embedded systems also have very limited
capability. Some embedded systems will have a few Light Emitting Diodes (LEDs)
to indicate the health status of the system modules, or for visual indication of
alarms. A small Liquid Crystal Display (LCD) may also be used to display some
important parameters.
Communication interfaces:
The embedded systems may need to, interact with other embedded systems
at they may have to transmit data to a desktop. To facilitate this, the embedded
systems are provided with one or a few communication interfaces such as RS232,
RS422, RS485, Universal Serial Bus (USB), IEEE 1394, Ethernet etc.
Application-specific circuitry:
Sensors, transducers, special processing and control circuitry may be
required fat an embedded system, depending on its application. This circuitry
interacts with the processor to carry out the necessary work. The entire hardware
has to be given power supply either through the 230 volts main supply or through a
battery. The hardware has to design in such a way that the power consumption is
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minimized.
Introduction to Microcontrollers:
Microprocessors and microcontrollers are widely used in embedded systems
products. Microcontroller is a programmable device. A microcontroller has a CPU
in addition to a fixed amount of RAM, ROM, I/O ports and a timer embedded all on
a single chip. The fixed amount of on-chip ROM, RAM and number of I/O ports in
microcontrollers makes them ideal for many applications in which cost and space
are critical.
The Intel 8052 is Harvard architecture, single chip microcontroller (C)
which was developed by Intel in 1980 for use in embedded systems. It was popular
in the 1980s and early 1990s, but today it has largely been superseded by a vast
range of enhanced devices with 8052-compatible processor cores that are
manufactured by more than 20 independent manufacturers including Atmel,
Infineon Technologies and Maxim Integrated Products.
8052 is an 8 -bit processor, meaning that the CPU can work on only 8 bits of
data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be
processed by the CPU. 8052 is available in different memory types such as UV-
EPROM, Flash and NV-RAM.
The present project is implemented on Keil uVision. In order to program the

device, proload tool has been used to burn the program onto the microcontroller.
The features, pin description of the microcontroller and the software tools
used are discussed in the following sections.
FEATURES
Compatible with MCS-51 Products
8K Bytes of In-System Programmable (ISP) Flash Memory
Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
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32 Programmable I/O Lines

Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
3.3 INTRODUCTION TO AT89S52

DESCRIPTION:
The AT89S52 is a low- power, high-performance CMOS 8-bit
microcontroller with 8K bytes of in-system programmable Flash memory.
The device is manufactured using Atmels high-density nonvolatile memory

technology and is compatible with the industry- standard 80C51 instruction set and
pinout. The on-chip Flash allows the program memory to be reprogrammed in-
system or by a conventional nonvolatile memory programmer. By combining a
versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the
Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and
cost-effective solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash,

256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port,
on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with
static logic for operation down to zero frequency and supports two software
selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue functioning. The Power- down mode
saves the RAM contents but freezes the oscillator, disabling all other chip functions
until the next interrupt or hardware reset.
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Fig: 3.4 Pin Configurations

BLOCK DIAGRAM
Fig: 3.4.1 BLOCK DIAGRAM of AT89S52 microcontroller

PIN DESCRIPTION
VCC : Supply voltage.
GND: Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each
pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be
used as high impedance inputs. Port 0 can also be configured to be the multiplexed
low order address/data bus during accesses to external program and data memory. In
this mode, P0 has internal pull- ups. Port 0 also receives the code bytes during Flash
programming and outputs the code bytes during program verification. External pull-
ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the
low-order address bytes during Flash programming and verification.
Table1: PIN DESCRIPTION of PORT1 PINS

Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins,
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source current (IIL) because of
the internal pull-ups. Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data memory that use 16-
bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull
-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function
Register. Port 2 also receives the high-order address bits and some control signals
during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins
that are externally being pulled low will source current (IIL) because of the pull-
ups. Port 3 also serves the functions of various special features of the AT89S52, as
shown in the following table. Port 3 also receives some control signals for Flash
programming and verification.
Table2: PIN DESCRIPTION of PORT3 PINS

RST
Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device. This pin drives High for 96 oscillator periods after the
Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to
disable this feature. In the default state of bit DISRTO, the RESET HIGH out
feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse
input (PROG) during Flash programming. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency and may be used for external timing or
clocking purposes. Note, however, that one ALE pulse is skipped during each
access to external data memory. If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or
MOVC instruction.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When
the AT89S52 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device
to fetch code from external program memory locations starting at 0000H up to
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally
latched on reset. EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash
programming.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.
XTAL2

Output from the inverting oscillator amplifier. XTAL1 and XTAL2 are the input and
output, respectively, of an inverting amplifier that can be configured for use as an on-
chip oscillator, as shown in Figure.
Either a quartz crystal or ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as
shown in the below figure. There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry is through a divide-by-
two flip-flop, but minimum and maximum voltage high and low time specifications
must be observed.
Fig: 3.4.2 Oscillator Connections

8052 MICROCONTROLLER MEMORY ORGANIZATION
The microcontroller memory is divided into Program Memory and Data Memory.
Program Memory (ROM) is used for permanent saving program being executed,
while Data Memory (RAM) is used for temporarily storing and keeping
intermediate results and variables. Depending on the model in use (still referring to
the whole 8052 microcontroller family) at most a few Kb of ROM and 128 or 256
bytes of RAM can be used.
However,All 8052 microcontrollers have 16-bit addressing bus and can address 64
kb memory. It is neither a mistake nor a big ambition of engineers who were
working on basic core development. It is a matter of very clever memory
organization which makes these controllers a real programmers tidbit .

Program Memory
The oldest models of the 8052 microcontroller family did not have any internal
program memory. It was added from outside as a separate chip. These models are
recognizable by their label beginning with 803 (for ex. 8031 or 8032) . All later
models have a few Kbytes ROM embedded, even though it is enough for writing
most of the programs, there are situations when additional memory is necessary. A
typical example of it is the use of so called lookup tables. They are used in cases
when something is too complicated or when there is no time for solving equations
describing some process. The example of it can be totally exotic (an estimate of
self-guided rockets meeting point) or totally common (measuring of temperature
using non-linear thermos element or asynchronous motor speed control). In those
cases, all needed estimates and approximates are executed in advance and the final
results are put in the tables (similar to logarithmic tables).
Fig: 3.4.3 ROM Internal Structure
EA=0 In this case, internal program memory is completely ignored, only a program
stored in external memory is to be executed.
EA=1 In this case, a program from built-in ROM is to be executed first (to the last
location). Afterwards, the execution is continued by reading additional memory.
In both cases, P0 and P2 are not available to the user because they are used for data
and address transmission. Besides, the pins ALE and PSEN are used too.

Fig: 3.4.4 ROM BLOCK DIAGRAM
Data Memory
As already mentioned, Data Memory is used for temporarily storing and
keeping data and intermediate results created and used during microcontrollers
operating. Besides, this microcontroller family includes many other registers such as:
hardware counters and timers, input/output ports, serial data buffers etc. The previous
versions have the total memory size of 256 locations, while for later models this
number is incremented by additional 128 available registers. In both cases, these first
256 memory locations (addresses 0- FFh) are the base of the memory. Common to all
types of the 8052 microcontrollers. Locations available to the user occupy memory
space with addresses from 0 to 7Fh. First 128 registers and this part of RAM is
divided in several blocks.
Additional Memory Block of Data Memory

In order to satisfy the programmers permanent hunger for Data Memory,
producers have embedded an additional memory block of 128 locations into the latest
versions of the 8052 microcontrollers. Naturally, its not so simpleThe problem is
that electronics performing addressing has 1 byte (8 bits) on disposal and due to that it
can reach only the first 256 locations. In order to keep already existing 8 -bit
architecture and compatibility with other existing models a little trick has been used.
Using trick in this case means that additional memory block shares the same
addresses with existing locations intended for the SFRs (80h- FFh). In order to
differentiate between these two physically separated memory spaces, different ways

of addressing are used. A direct addressing is used for all locations in the SFRs,
while the locations from additional RAM are accessible using indirect addressing.
Fig: 3.4.5 Internal Bus Architecture
Fig: 3.4.6 Microcontroller Internal Structure

How to extend memory?

In case on -chip memory is not enough, it is possible to add two external
memory chips with capacity of 64Kb each. I/O ports P2 and P3 are used for their
addressing and data transmission.
Fig: 3.4.7 Interfacing RAM with Microcontroller
From the users perspective, everything functions quite simple if properly

connected because the most operations are performed by the microcontroller itself.
The 8052 microcontroller has two separate reading signals RD#(P3.7) and PSEN#.
The first one is activated byte from external data memory (RAM) should be read,
while another one is activated to read byte from external program memory (ROM).
These both signals are active at logical zero (0) level. A typical example of such
memory extension using special chips for RAM and ROM is shown on the previous
picture. It is called Hardware architecture.
When the program during execution encounters the instruction which resides in
external memory (ROM), the microcontroller will activate its control output ALE
and set the first 8 bits of address(A0- A7) on P0.

In this way, IC circuit 74HCT573 which "lets in" the first 8 bits to memory address
pins is activated. A signal on the pin ALE closes the IC circuit 74HCT573 and
immediately afterwards 8 higher bits of address (A8-A15) appear on the port. In this
way, a desired location in additional program memory is completely addressed. The
only thing left over is to read its content.
Pins on P0 are configured as inputs, the pin PSEN is activated and the
microcontroller reads content from memory chip. The same connections are used
both for data and lower address byte.
Similar occurs when it is a needed to read some location from external Data
Memory. Now, addressing is performed in the same way, while reading or writing is
performed via signals which appear on the control outputs RD or WR.
Addressing
While operating, processor processes data according to the program
instructions. Each instruction consists of two parts. One part describes what should
be done and another part indicates what to use to do it. This later part can be data
(binary number) or address where the data is stored. All 8052 microcontrollers use
two ways of addressing depending on which part of memory should be accessed:
Direct Addressing
On direct addressing, a value is obtained from a memory location while the
address of that location is specified in instruction. Only after that, the instruction
can process data (how depends on the type of instruction: addition, subtraction,
copy). Obviously, a number being changed during operating a variable can reside
at that specified address. For example: Since the address is only one byte in size
(the greatest number is 255), this is how only the first 255 locations in RAM can be
accessed in this case the first half of the basic RAM is intended to be used freely,
while another half is reserved for the SFRs.
Indirect Addressing
On indirect addressing, a register which contains address of another register
is specified in the instruction. A value used in operating process resides in that
another register. For example: Only RAM locations available for use are accessed
by indirect addressing (never in the SFRs). For all latest versions of the

microcontrollers with additional memory block (those 128 locations in Data

Memory), this is the only way of accessing them. Simply, when during operating,
the instruction including @ sign is encountered and if the specified address is
higher than 128 (7F hex.), the processor knows that indirect addressing is used and
jumps over memory space reserved for the SFRs.
SFRs (Special Function Registers)

SFRs are a kind of control table used for running and monitoring
microcontrollers operating. Each of these registers, even each bit they include, has
its name, address in the scope of RAM and clearly defined purpose (for example:
timer control, interrupt, serial connection etc.). Even though there are 128 free
memory locations intended for their storage, the basic core, shared by all types of
8052 controllers, has only 21 such registers. It also enables the use of programs
written a long time ago for the microcontrollers which are out of production now.
Fig: 3.4.8 Special Function Registers
A Register (Accumulator)
Fig: 3.4.9 Accumulator Register

This is a general-purpose register which serves for storing intermediate

results during operating. A number (an operand) should be added to the accumulator
prior to execute an instruction upon it. Once an arithmetical operation is performed
by the ALU, the result is placed into the accumulator. If a data should be transferred
from one register to another, it must go through accumulator. For such universal
purpose, this is the most commonly used register that none microcontroller can be
imagined without (more than a half 8052 microcontroller's instructions used use the
accumulator in some way).
B Register
Fig: 3.4.10 Bit Register
B register is used during multiply and divide operations which can be

performed only upon numbers stored in the A and B registers. All other instructions
in the program can use this register as a spare accumulator (A). During
programming, each of registers is called by name so that their exact address is not
so important for the user. During compiling into machine code (series of
hexadecimal numbers recognized as instructions by the microcontroller), PC will
automatically, instead of registers name, write necessary addresses into the
microcontroller.
R Registers (R0-R7)
Fig: 3.4.11 RAM Architecture

This is a common name for the total 8 general purpose registers (R0, R1, R2
... R7). Even they are not true SFRs, they deserve to be discussed here because of
their purpose. The bank is active when the R registers it includes are in use. Similar
to the accumulator, they are used for temporary storing variables and intermediate
results. Which of the banks will be active depends on two bits included in the PSW
Register. These registers are stored in four banks in the scope of RAM.
3.4 INTRODUCTION TO GPS (GLOBAL POSITIONING SYSTEM):

The Global Positioning System, usually called GPS, and originally named
NAVSTAR, is a satellite navigation system used for determining one's precise
location almost anywhere on Earth. A GPS unit receives time signal transmissions
from multiple satellites, and calculates its position by triangulating this data. The
GPS was designed by and is controlled by the United States Department of Defense
and can be used by anybody for free. The cost of maintaining the system is
approximately $400 million per year.
Measurement uncertainty of the majority of commercial GPS receivers

varies from 10-11 to 10-13 by the frequency scale, and from 100 ns to 50 ns by the
time scale, being dependent on the receiver design. The main sources of uncertainty
in GPS measurements are the GPS receiver position error, the orbital error, the
satellite and receiver clock errors, the ionosphere and the troposphere delays, the
receiver internal delay, the satellite antenna and cable delay, the receiver noise, and
the multipath error. The frequency uncertainty for a GPS receiver is larger than that
for Cs-standard by 2- 3 orders within a short -time interval (1 1000 s), and by one
order within a long-term interval of about one week.
It may help to think of a GPS receiver as similar to a standard radio. Like the
radio in your car, a GPS receiver is collecting radio signals from the ether and
magically turning these signals into information we can use. In the case of a GPS
receiver the stations are satellites broadcasting 11,000 miles away in space and
the music is a binary code, but the antenna and radio hardware are subject to similar
kinds of interference that affect your car radios ability to produce a clear sound. In
your car speaker we hear this interference as static; in your GPS receiver the
interference may result in positional static, i.e., degradation of accuracy.

A better radio receiver and antenna system, fewer terrain obstructions, a

stronger connection to the broadcasting station all result in better sound quality for
your car radio and better positional quality for your GPS radio. A GPS receiver
derives its location or positional fix with distance measurements (called pseudo
ranges) from multiple satellites at precisely the same time, a measurement epoch.
Attributes collected and stored with the position for each feature can be used in GIS
map making and analysis. While there are only so many things you can do to
improve your car radios performance, by contrast there are many more things users
can do to influence GPS positional quality.
Satellites
The United States Global Positioning System (GPS) is the first fully
operational Global Navigation Satellite System (GNSS). Each satellite broadcasts a
signal that is used by receivers to determine precise position anywhere in the world.
The receiver tracks multiple satellites and determines a pseudo range measurement
(a range measurement based on time) that is then used to determine the user
location. A minimum of four satellites is necessary to establish an accurate three-
dimensional position.
The Department of Defense (DOD) is responsible for operating the GPS

satellite constellation and monitors the GPS satellites to ensure proper operation.
Every satellite's orbital parameters (ephemeris data) are sent to each satellite for
broadcast as part of the data message embedded in the GPS signal. The GPS
coordinate system is the Cartesian earth-centered earth -fixed coordinates as
specified in the World Geodetic System reference system 1984 (WGS-84).
24 GPS satellites are currently in orbit around the earth. the first was
launched in 1972 and the latest satellite was launched in 2012. The maximum
available at any time from a point in Oregon is generally between 4 to 11. The
satellites send out radio signals that are collected and read by the GPS receiver.

Fig: 3.5 Working of GPS modem

The GPS is made up of three parts:
1. Satellites orbiting the Earth
2. Control and monitoring stations on Earth
3. The GPS receivers owned by users.
GPS satellites broadcast signals from space that are picked up and identified
by GPS receivers. Each GPS receiver then provides three-dimensional location
(latitude, longitude, and altitude) plus the time.
SPACE SEGMENT:
24+ satellites
20,200 km altitude
55 degrees inclination 12-hour
orbital period
5 ground control stations
Each satellite passes over a ground monitoring station every 12 hours

Fig: 3.5.1 GPS Satellite System
The space segment is composed of the orbiting GPS satellites or Space

Vehicles (SV) in GPS parlance. The GPS design originally called for 24 SVs, this
was modified to six planes with four satellites each. The orbital planes are centered
on the Earth, not rotating with respect to the distant stars. The six planes have
approximately 55 inclination (tilt relative to Earth's equator) and are separated by
60 right ascension of the ascending node (angle along the equator from a reference
point to the orbit's intersection.
The full constellation of 24 satellites that make up the GPS space segment
are orbiting the earth about 20,200 km above us. They are constantly moving,
making two complete orbits in less than 24 hours. These satellites are travelling at
speeds of roughly 7,000 miles an hour.
GPS satellites are powered by solar energy. They have backup batteries
onboard to keep them running in the event of a solar eclipse, when there's no solar
power. Small rocket boosters on each satellite keep them flying in the correct path.
Here are some other interesting facts about the GPS satellites (also called
NAVSTAR, the official U.S. Department of Defense name for GPS):
The first GPS satellite was launched in 1978. A full constellation of 24

satellites was achieved in 1994. Each satellite is built to last about 10 years.
Replacements are constantly being built and launched into orbit. A GPS satellite
weighs approximately 2,000 pounds and is about 17 feet across with the solar panels
extended. Transmitter power is only 50 watts or less. The orbits are arranged so that at
anytime, anywhere on Earth, there are at least four satellites "visible" in the sky. All

satellites broadcast at the same two frequencies, 1.57542 GHz (L1 signal) and 1.2276
GHz (L2 signal). The satellite network uses a CDMA spread- spectrum technique
where the low-bitrate message data is encoded with a high-rate pseudo-random (PRN)
sequence that is different for each satellite.
The receiver must be aware of the PRN codes for each satellite to reconstruct
the actual message data. The C/A code, for civilian use, transmits data at 1.023
million chips per second, whereas the P code, for U.S. military use.
Control and monitoring stations on Earth:

These stations monitor the GPS satellites, checking both their operational
health and their exact position in space. The master ground station transmits
corrections for the satellite's ephemeris constants and clock offsets back to the
satellites themselves. The satellites can then incorporate these updates in the signals
they send to GPS receivers. There are five monitor stations: Hawaii, Ascension
Island, Diego Garcia, Kwajalein, and Colorado Springs.
The GPS Receivers:

Receiver determines location, speed, direction, and time 3 satellite signals are
necessary to locate the receiver in 3D space 4th satellite is used for time accuracy
Position calculated within sub-centimeter scale Individuals may purchase GPS
handsets that are readily available through commercial retailers. Equipped with these
GPS receivers, users can accurately locate where they are and easily navigate to
where they want to go, whether walking, driving, flying, or boating.
Today's GPS receivers are extremely accurate, thanks to their parallel multi-
channel design. Garmin's 12 parallel channel receivers are quick to lock onto
satellites when first turned on and they maintain strong locks, even in dense
foliage or urban settings with tall buildings. Certain atmospheric factors and other
sources of error can affect.
The user segment is composed of hundreds of thousands of U.S. and allied

military users of the secure GPS Precise Positioning Service, and tens of millions of
civil, commercial and scientific users of the Standard Positioning Service. In
general, GPS receivers are composed of an antenna, tuned to the frequencies

transmitted by the satellites, receiver-processors, and a highly stable clock (often a

crystal oscillator).
Fig:
3.5.2 Newer Garmin GPS Receivers with WAAS
The Global Positioning System is vast, expensive and involves a lot of

technical ingenuity, but the fundamental concepts at work are quite simple and
intuitive.
When people talk about "a GPS," they usually mean a GPS receiver. The
Global Positioning System (GPS) is actually a constellation of 24 Earth-orbiting
satellites The U.S. military developed and implemented this satellite network as a
military navigation system, but soon opened it up to everybody else.

3.5 INTRODUCTION TO WI-FI

Your ESP8266 is an impressive, low cost WiFi module suitable for adding
WiFi functionality to an existing microcontroller project via a UART serial
connection. The module can even be reprogrammed to act as a standalone WiFi
connected devicejust add power! The feature list is impressive and includes: 802.11
b/g/n protocol Wi-Fi Direct (P2P), soft-AP Integrated TCP/IP protocol stack This
guide is designed to help you get started with your new WiFi module so lets start
3.6 Wifi Module
The hardware connections required to connect to the ESP8266 module are fairly
straight-forward but there are a couple of important items to note related to power:
The ESP8266 requires 3.3V powerdo not power it with 5 volts! The ESP8266 needs
to communicate via serial at 3.3V and does not have 5V tolerant inputs, so you need
level conversion to communicate with a 5V microcontroller like most Arduinos use.
However, if youre adventurous and have no fear you can possibly get away with
ignoring the second requirement. But nobody takes any responsibility for what
happens if you do. :) Here are the connections available on the ESP8266 WiFi
module: ESP8266 WiFi Module

3.6 INRODUCTION TO PUSH BUTTON

A push-button or simply button is a simple switch mechanism for controlling
some aspect of a machine or a process. Buttons are typically made out of hard
material, usually plastic or metal. The surface is usually flat or shaped to
accommodate the human finger or hand, so as to be easily depressed or pushed.
Buttons are most often biased switches, though even many un-biased buttons (due
to their physical nature) require a spring to return to their un-pushed state. Different
people use different terms for the "pushing" of the button, such as press, depress,
mash, and punch.
USES:
In industrial and commercial applications, push buttons can be linked
together by a mechanical linkage so that the act of pushing one button causes the
other button to be released. In this way, a stop button can "force" a start button to be
released. This method of linkage is used in simple manual operations in which the
machine or process have no electrical circuits for control.
Red pushbuttons can also have large heads (called mushroom heads) for easy
operation and to facilitate the stopping of a machine. These pushbuttons are called
emergency buttons and are mandated by the electrical code in many jurisdictions for
increased safety. This large mushroom shape can also be found in buttons for use
with operators who need to wear gloves for their work and could not actuate a
regular flush push button. The source of the energy to illuminate the light is not
directly tied to the contacts on the back of the pushbutton but to the action the
pushbutton controls. In popular culture, the phrase the button (sometimes
capitalized) refers to a (usually fictional) button that a military or government leader
could press to launch nuclear weapons.
Fig: 3.7 Push Switch

3.6 INTRODUCTION TO SERIAL COMMUNICATION:

The main requirements for serial communication are:
1. Microcontroller
2. PC
3. RS 232 cable
4. MAX 232 IC
5. HyperTerminal
TIMERS:
The 8052 has two timers: Timer 0 and Timer 1. They can be used either as
timers to generate a time delay or as counters to count events happening outside the
microcontroller. Lower byte register of Timer 0 is TL0 and higher byte is TH0.
Similarly, lower byte register of Timer1 is TL1 and higher byte register is TH1.
TMOD (timer mode) register:

RS232 CABLE:
To allow compatibility among data communication equipment, an interfacing
standard called RS232 is used. Since the standard was set long before the advent of
the TTL logic family, its input and output voltage levels are not TTL compatible.
For this reason, to connect any RS232 to a microcontroller system, voltage
converters such as MAX232 are used to convert the TTL logic levels to the RS232
voltage levels and vice versa.
3.7 INTRODUCTION TO MAX 232:

Max232 IC is a specialized circuit which makes standard voltages as
required by RS232 standards. This IC provides best noise rejection and very reliable
against discharges and short circuits. MAX232 IC chips are commonly referred to
as line drivers. To ensure data transfer between PC and microcontroller, the baud
rate and voltage levels of Microcontroller and PC should be the same. The voltage
levels of microcontroller are logic1 and logic 0 i.e., logic 1 is +5V and logic 0 is 0V.
But for PC, RS232 voltage levels are considered and they are: logic 1 is taken as -
3V to -25V and logic 0 as +3V to +25V. So, in order to equal these voltage levels,
MAX232 IC is used. Thus this IC converts RS232 voltage levels to microcontroller
voltage levels and vice versa.

Fig: 3.8 Pin diagram of MAX 232 IC

SCON (serial control) register:
3.8 INTRODUCTION TO LIQUID CRYSTAL DISPLAY:
LCD stands for Liquid Crystal Display. LCD is finding wide spread use
replacing LEDs (seven segment LEDs or other multi segment LEDs) because of the
following reasons:
1. The declining prices of LCDs.
2. The ability to display numbers, characters and graphics. This is in contrast to
LEDs, which are limited to numbers and a few characters.
3. Incorporation of a refreshing controller into the LCD, thereby relieving the
CPU of the task of refreshing the LCD. In contrast, the LED must be
refreshed by the CPU to keep displaying the data.
4. Ease of programming for characters and graphics.
These components are specialized for being used with the microcontrollers,
which means that they cannot be activated by standard IC circuit

Fig: 3.9 LCD Display Board

A model described here is for its low price and great possibilities most
frequently used in practice. It is based on the HD44780 microcontroller ( Hitachi)
and can display messages in two lines with 16 characters each. It displays all the
alphabets, Greek letters, punctuation marks, mathematical symbols etc. In addition,
it is possible to display symbols that user makes up on its own. Automatic shifting
message on display (shift left and right), appearance of the pointer, backlight etc.
are considered as useful characteristics.
Pins Functions
There are pins along one side of the small printed board used for connection
to the microcontroller. There are total of 14 pins marked with numbers (16 in case
the background light is built in). Their function is described in the table below
Table 9 functionality of pins

LCD screen:
LCD screen consists of two lines with 16 characters each. Each character
consists of 5x7 dot matrix. Contrast on display depends on the power supply
voltage and whether messages are displayed in one or two lines. For that reason,
variable voltage 0- Vdd is applied on pin marked as Vee. Trimmer potentiometer is
usually used for that purpose. Some versions of displays have built in backlight
(blue or green diodes). When used during operating, a resistor for current limitation
should be used (like with any LE diode).
Fig: 3.9.1 Functioning of LCD

TABLE -10: COMMANDS USED IN LCD

CONTRAST CONTROL:
To have a clear view of the characters on the LCD, contrast should be
adjusted. To adjust the contrast, the voltage should be varied. For this, a preset is
used which can behave like a variable voltage device. As the voltage of this preset is
varied, the contrast of the LCD can be adjusted.
Fig: 3.10 Variable resistor
Potentiometer:
Variable resistors used as potentiometers have all three terminals connected.
This arrangement is normally used to vary voltage, for example to set the switching
point of a circuit with a sensor, or control the volume (loudness) in an amplifier
circuit. If the terminals at the ends of the track are connected across the power
supply, then the wiper terminal will provide a voltage which can be varied from
zero up to the maximum of the supply.
Fig: 3.11 Potentiometer Symbol
Presets:
These are miniature versions of the standard variable resistor. They are
designed to be mounted directly onto the circuit board and adjusted only when the
circuit is built. For example, to set the frequency of an alarm tone or the sensitivity
of a light-sensitive circuit. A small screwdriver or similar tool is required to adjust

presets. Presets are much cheaper than standard variable resistors so they are
sometimes used in projects where a standard variable resistor would normally be
used.
Multiturn presets are used where very precise adjustments must be made.
The screw must be turned many times (10+) to move the slider from one end of the
track to the other, giving very fine control.
Fig: 3.12 Preset symbol Fig: 3.12.1 Preset
MEMORY:
In the design of all microprocessors-based systems, semiconductor memories
are used as primary storage for code and data. Semiconductor memories are
connected directly to the CPU and they are the memory that the CPU first asks for
information (code and data). For this reason, semiconductor memories are
sometimes referred to as primary memory.
Important Terminology common to all Semiconductor Memories:
Memory capacity:
The number of bits that a semiconductor memory chip can store is called
chip capacity. It can be in units of Kilobits, Megabits and so on. This must be
distinguished from the storage capacity of computer system. While the memory
capacity of a memory IC chip is always given in bits, the memory capacity of a
computer system is given in bytes.
Memory organization:
Memory chips are organized into a number of locations within the IC. Each
location can hold 1 bit, 4 bits, 8 bits or even 16 bits, depending on how it is

designed internally. The number of bits that each location within the memory chip
can hold is always equal to the number of data pins on the chip. i.e., the total
number of bits that a memory chip can store is equal to the number of locations
times the number of data bits per location.
Speed:
One of the most important characteristics of a memory chip is the speed at
which its data can be accessed. The speed of the memory chip is commonly referred
to as its access time. The access time of memory chip varies from a few
nanoseconds to hundreds of nanoseconds, depending on the IC technology used in
the design and fabrication process.
The different types of memories are RAM, ROM, EPROM and EEPROM. RAM
and ROM are inbuilt in the microprocessor.
For this purpose, we prefer EEPROM in our project.
3.10 INTRODUCTION TO EEPROM (Electrically Erasable Programmable

Read only memory)
EEPROM has several advantages over other memory devices, such as the
fact that its method of erasure is electrical and therefore instant. In addition, in
EEPROM one can select which byte to be erased, in contrast to flash, in which the
entire contents of ROM are erased. The main advantage of EEPROM is that one can
program and erase its contents while it is in system board. It does not require
physical removal of the memory chip from its socket. In general, the cost per bit for
EEPROM is much higher when compared to other devices.
The EEPROM used in this project is 24C04 type.
Features of 24C04 EEPROM:

1 million erase/write cycles with 40 years data retention. Single supply
voltage: - 3v to 5.5v for st24x04 versions. - 2.5v to5.5v for st25x04 versions.
Hardware write control versions: st24w04 and st25w04.
Programmable write protection.

Two wire serial interface, fully i2c bus compatible. Byte and multibit write (up
to 4 bytes) .
Page write (up to 8 bytes).
Byte, random and sequential read modes Self-timed programming cycle
Automatic address incrementing
Enhanced ESD/Latch up performances.
Fig: 3.13.1 DIP Pin Connections Fig: 3.13.2 SO Pin Connection
TABLE-11: Signal Names

Fig: 3.13.3 Logic Diagram

DESCRIPTION:
The 24C04 is a 4 Kbit electrically erasable programmable memory
(EEPROM), organized as 2 blocks of 256 x8 bits. They are manufactured in ST
Microelectronics Hi- Endurance Advanced CMOS technology which guarantees an
endurance of one million erase/write cycles with a data retention of 40 years. Both
Plastic Dual-in-Line and Plastic Small Outline packages are available. The
memories are compatible with the I2C standard, two wire serial interface which
uses a bi-directional data bus and serial clock. The memories carry a built-in 4 bit,
unique device identification code (1010) corresponding to the I2C bus definition.
This is used together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices
may be attached to the I2C bus and selected individually. The memories behave as a
slave device in the I2C protocol with all memory operations synchronized by the
serial clock. Read and write operations are initiated by a START condition
generated by the bus master. The START condition is followed by a stream of 7 bits
(identification code 1010), plus one read/write bit and terminated by an
acknowledge bit.
TABLE-11: Device Select Modes

TABLE-12: Operating Modes

When writing data to the memory it responds to the 8 bits received by

asserting an acknowledge bit during the 9th bit time. When data is read by the bus
master, it acknowledges the receipt of the data bytes in the same way. Data transfers
are terminated with a STOP condition.
Power On Reset: VCC lock out write protect

In order to prevent data corruption and inadvertent write operations during
power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage
has reached the POR threshold value, the internal reset is active, all operations are
disabled and the device will not respond to any command. In the same way, when
VCC drops down from the operating voltage to below the POR threshold value, all
operations are disabled and the device will not respond to any command. A stable
VCC must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL):
The SCL input pin is used to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC to act as a pull up.
Serial Data (SDA):

The SDA pin is bi -directional and is used to transfer data in or out of the
memory. It is an open drain output that may be wire-ORed with other open drain or
open collector signals on the bus. A resistor must be connected from the SDA bus line
to VCC to act as pull up.
Chip Enable (E1 - E2):

These chip enable inputs are used to set the 2 least significant bits (b2, b3) of
the 7-bit device select code. These inputs may be driven dynamically or tied to VCC
or VSS to establish the device select code.
Protect Enable (PRE):

The PRE input pin, in addition to the status of the Block Address Pointer bit
(b2, location 1FFh as in below figure), sets the PRE write protection active.

Fig: 3.14 Memory Protection
Mode (MODE):
The MODE input is available on pin 7 and may be driven dynamically. It
must be at VIL or VIH for the Byte Write mode, VIH for Multibit Write mode or
VIL for Page Write mode. When unconnected, the MODE input is internally read as
VIH (Multibit Write mode).
Write Control (WC):

A hardware Write Control feature (WC) is offered only for ST24W04 and
ST25W04 versions on pin 7. This feature is useful to protect the contents of the
memory from any erroneous erase/write cycle. The Write Control signal is used to
enable (WC = VIH) or disable (WC =VIL) the internal write protection. When
unconnected, the WC input is internally read as VIL and the memory area is not
write protected.
DEVICE OPERATION
I2C Bus Background
The ST24/25x04 supports the I2C protocol. This protocol defines any device
that sends data onto the bus as a transmitter and any device that reads the data as a
receiver. The device that controls the data transfer is known as the master and the
other as the slave. The master will always initiate a data transfer and will provide
the serial clock for synchronization.

The ST24/25x04 is always slave devices in all communications.
Fig: 3.14.1 I2C Protocol

Start Condition:
START is identified by a high to low transition of the SDA line while the
clock SCL is stable in the high state. A START condition must precede any
command for data transfer. Except during a programming cycle, the ST24/25x04
continuously monitor the SDA and SCL signals for a START condition and will not
respond unless one is given.
Stop Condition:
STOP is identified by a low to high transition of the SDA line while the
clock SCL is stable in the high state. A STOP condition terminates communication
between the ST24/25x04 and the bus master. A STOP condition at the end of a Read
command, after and only after a No Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK):

An acknowledge signal is used to indicate a successful data transfer. The bus
transmitter, either master or slave, will release the SDA bus after sending 8 bits of
data. During the 9th clock pulse period the receiver pulls the SDA bus low to
acknowledge the receipt of the 8 bits of data.
Data Input:
During data input the ST24/25x04 sample the SDA bus signal on the rising
edge of the clock SCL. Note that for correct device operation the SDA signal must
be stable during the clock low to high transition and the data must change ONLY
when the SCL line is low.
Memory Addressing:
To start communication between the bus master and the slave ST24/25x04,
the master must initiate a START condition. Following this, the master sends onto
the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits)
and a READ or WRITE bit. The 4 most significant bits of the device select code are
the device type identifier, corresponding to the I2C bus definition. For these
memories the 4 bits are fixed as 1010b. The following 2 bits identify the specific
memory on the bus. They are matched to the chip enable signals E2, E1. Thus up to
4 x 4K memories can be connected on the same bus giving a memory capacity total

of 16 Kilobits. After a START condition any memory on the bus will identify the
device code and compare the
following 2 bits to its chip enable inputs E2, E1. The 7th bit sent is the block
number (one block = 256 bytes).
The 8th bit sent is the read or write bit (RW), this bit is set to 1 for read and
0 for write operations. If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus during the 9th bit time.
Fig: 3.14.2 AC Waveforms

Write Operations:
The Multibit Write mode (only available on the ST24/25C04 versions) is
selected when the MODE pin is at VIH and the Page Write mode when MODE pin
is at VIL. The MODE pin may be driven dynamically with CMOS input levels.
Following a START condition the master sends a device select code with the RW bit
reset to 0. The memory acknowledges this and waits for a byte address. The byte
address of 8 bits provides access to one block of 256 bytes of the memory. After
receipt of the byte address the device again responds with an acknowledge. For the
ST24/25W04 versions, any write command with WC = 1 will not modify the
memory content.
Byte Write:
In the Byte Write mode, the master sends one data byte, which is
acknowledged by the memory. The master then terminates the transfer by
generating a STOP condition. The Write mode is independent of the state of the
MODE pin which could be left floating if only this mode was to be used. However,
it is not a recommended operating mode, as this pin has to be connected to either
VIH or VIL, to minimize the stand-by current.
Multibit Write:
For the Multibit Write mode, the MODE pin must be at VIH. The Multibit
Write mode can be started from any address in the memory. The master sends from
one up to 4 bytes of data, which are each acknowledged by the memory. The
transfer is terminated by the master generating a STOP condition. The duration of
the write cycle is Tw = 10ms maximum except when bytes are accessed on 2 rows
(that is have different values for the 6 most significant address bits A7-A2), the
programming time is then doubled to a maximum of 20ms. Writing more than 4
bytes in the Multibit Write mode may modify data bytes in an adjacent row (one
row is 8 bytes long). However, the Multibit Write can properly write up to 8
consecutive bytes as soon as the first address of these 8 bytes is the first address of
the row, the 7 following bytes being written in the 7 following bytes of this same
row.

Page Write:
For the Page Write mode, the MODE pin must be at VIL. The Page Write
mode allows up to 8 bytes to be written in a single write cycle, provided that they
are all located in the same row in the memory: that is the 5 most significant
memory address bits (A7 -A3) are the same inside one block. The master sends
from one up to 8 bytes of data, which are each acknowledged by the memory. After
each byte is transferred, the internal byte address counter (3 least significant bits
only) is incremented. The transfer is terminated by the master generating a STOP
condition. Care must be taken to avoid address counter roll-over which could
result in data being overwritten. Note that, for any write mode, the generation by the
master of the STOP condition starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and the memory will not respond to
any request.
Minimizing System Delays by Polling on ACK

During the internal write cycle, the memory disconnects itself from the bus
in order to copy the data from the internal latches to the memory cells. The
maximum value of the write time (Tw) is given from the AC Characteristics, since
the typical time is shorter, the time seen by the system may be reduced by an ACK
polling sequence issued by the master.
Fig: 3.14.3 Write Cycle Polling using ACK

Data in the upper block of 256 bytes of the memory may be write protected.
The memory is write protected between a boundary address and the top of memory
(address 1FFh) when the PRE input pin is taken high and when the Protect Flag (bit
b2 in location 1FFh) is set to 0. The boundary address is user defined by writing it
in the Block Address Pointer. The Block Address Pointer is an 8 bit EEPROM
register located at the address 1FFh. It is composed by 5 MSBs Address Pointer,
which defines the bottom boundary address and 3 LSBs which must be programmed
at 0. This Address Pointer can therefore address a boundary in steps of 8 bytes.
The sequence to use the Write Protected feature is:

Write the data to be protected into the top of the memory, up to, but not
including, location 1FFh;
Set the protection by writing the correct bottom boundary address in the
Address Pointer (5 MSBs of location 1FFh) with bit b2 (Protect flag) set to
0. Note that for a correct functionality of the memory, all the 3 LSBs of the
Block Address Pointer must also be programmed at 0. The area will now
be protected when the PRE input pin is taken High. While the PRE input pin
is read at 0 by the memory, the location 1FFh can be used as a normal
EEPROM byte.
Fig: 3.14.4 Write Modes Sequence

Read Operations:
Read operations are independent of the state of the MODE pin. On delivery,
the memory content is set at all "1s" (or FFh) .
Current Address Read:

The memory has an internal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address Read mode, following a
START condition, the master sends a memory address with the RW bit set to 1.
The memory acknowledges this and outputs the byte addressed by the internal byte
address counter. This counter is then incremented. The master does NOT
acknowledge the byte output, but terminates the transfer with a STOP condition.
Random Address Read:

A dummy write is performed to load the address into the address counter.
This is followed by another START condition from the master and the byte address
is repeated with the RW bit set to 1. The memory acknowledges this and outputs
the byte addressed. The master has to NOT acknowledge the byte output, but
terminates the transfer with a STOP condition.
Sequential Read:
This mode can be initiated with either a Current Address Read or a Random
Address Read. However, in this case the master DOES acknowledge the data byte
output and the memory continues to output the next byte in sequence. To terminate
the stream of bytes, the master must NOT acknowledge the last byte output, but
MUST generate a STOP condition. The output data is from consecutive byte
addresses, with the internal byte address counter automatically incremented after
each byte output. After a count of the last memory address, the address counter will
roll - over and the memory will continue to output data.
Acknowledge in Read Mode:

In all read modes the ST24/25x04 wait for an acknowledge during the 9th bit
time. If the master does not pull the SDA line low during this time, the ST24/25x04
terminate the data transfer and switches to a standby state.

Fig: 3.14.5 Read Modes Sequence

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WOMEN SAFETY USING IOT

2.1 Literature Survey

DEPT OF ECE 3 AKITS

3.1 BLOCK DIAGRAM

Fig: 3.1 BLOCK DIAGRAM

DEPT OF ECE 4 AKITS

3.2 POWER SUPPLY

Fig:3.2 Power supply

DEPT OF ECE 5 AKITS

Overview of Embedded System Architecture

Fig: 3.3 Layered Architecture of Embedded System

Every embedded system consists of custom-built hardware built around a

DEPT OF ECE 6 AKITS

Central Processing Unit (CPU)

Fig: 3.3.1 Building Blocks

Central Processing Unit (CPU):

DEPT OF ECE 7 AKITS

DEPT OF ECE 8 AKITS

The present project is implemented on Keil uVision. In order to program the

DEPT OF ECE 9 AKITS

32 Programmable I/O Lines

3.3 INTRODUCTION TO AT89S52

The device is manufactured using Atmels high-density nonvolatile memory

The AT89S52 provides the following standard features: 8K bytes of Flash,

DEPT OF ECE 10 AKITS

Fig: 3.4 Pin Configurations

DEPT OF ECE 11 AKITS

Fig: 3.4.1 BLOCK DIAGRAM of AT89S52 microcontroller

DEPT OF ECE 12 AKITS

Table1: PIN DESCRIPTION of PORT1 PINS

DEPT OF ECE 13 AKITS

Table2: PIN DESCRIPTION of PORT3 PINS

DEPT OF ECE 14 AKITS

DEPT OF ECE 15 AKITS

Fig: 3.4.2 Oscillator Connections

DEPT OF ECE 16 AKITS

Fig: 3.4.3 ROM Internal Structure

DEPT OF ECE 17 AKITS

Fig: 3.4.4 ROM BLOCK DIAGRAM

Additional Memory Block of Data Memory

DEPT OF ECE 18 AKITS

Fig: 3.4.5 Internal Bus Architecture

Fig: 3.4.6 Microcontroller Internal Structure

DEPT OF ECE 19 AKITS

How to extend memory?

Fig: 3.4.7 Interfacing RAM with Microcontroller

From the users perspective, everything functions quite simple if properly

DEPT OF ECE 20 AKITS

DEPT OF ECE 21 AKITS

microcontrollers with additional memory block (those 128 locations in Data

SFRs (Special Function Registers)

Fig: 3.4.8 Special Function Registers

Fig: 3.4.9 Accumulator Register

DEPT OF ECE 22 AKITS

This is a general-purpose register which serves for storing intermediate

Fig: 3.4.10 Bit Register

B register is used during multiply and divide operations which can be

Fig: 3.4.11 RAM Architecture

DEPT OF ECE 23 AKITS

3.4 INTRODUCTION TO GPS (GLOBAL POSITIONING SYSTEM):

Measurement uncertainty of the majority of commercial GPS receivers

DEPT OF ECE 24 AKITS

A better radio receiver and antenna system, fewer terrain obstructions, a

The Department of Defense (DOD) is responsible for operating the GPS