ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / OVERVIEW

Session 27 Overview: Biomedical Circuits

IMMD SUBCOMMITTEE

Session Chair: Gert Cauwenberghs, Session Co-Chair: Michiel Pertijs,

University of California, San Diego, La Jolla, CA Delft University of Technology, Delft, The Netherlands

Subcommittee Chair: Makoto Ikeda, University of Tokyo, Tokyo, Japan

Advances in biomedical circuits and systems are essential technology drivers in addressing critical societal needs to increase the
effectiveness and reduce the cost of healthcare. This session highlights the latest circuit innovations that contribute to advances in
medical devices, sensing and imaging. For implantable and unobtrusive devices, ultrasonic power delivery and telemetry, and
improved neural sensing and stimulation are addressed. Advanced medical sensing increasingly combines multiple modalities in a
single device, several examples of which are also featured in this session. Finally, circuit innovations enabling improved ultrasonic
and magnetic resonance imaging and optical spectroscopy are presented.

1:30 PM
27.1 A 2.8W 80mVpp-Linear-Input-Range 1.6G-Input Impedance Bio-Signal Chopper Amplifier Tolerant
to Common-Mode Interference up to 650mVpp
H. Chandrakumar, University of California, Los Angeles, CA
In Paper 27.1, the University of California, Los Angeles, presents a 2.8W chopper amplifier optimized for
neural recording during stimulation in 40nm CMOS. It has an 80mVpp linear-input-range, 76dB harmonic
distortion, and 81dB dynamic range, while handling up to 650mVpp common-mode interference.

2:00 PM
27.2 A 25.2mW EEG-NIRS Multimodal SoC for Accurate Anesthesia Depth Monitoring
U. Ha, KAIST, Daejeon, Korea
In Paper 27.2, KAIST, together with K-Healthwear and Korea University Guro Hospital, demonstrates a combined
EEG and Near-Infrared Spectrometry (NIRS) readout, implemented in 65nm CMOS, for continuous quantitative
anesthesia depth level monitoring during surgery. The EEG readout achieves an NEF of 3.59 and a LogTIA with
a dynamic range up to 60dB is presented for the NIRS readout.

446 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 1:30 PM

2:30 PM
27.3 All-Wireless 64-Channel 0.013mm2/ch Closed-Loop Neurostimulator with Rail-to-Rail DC Offset
Removal
H. Kassiri, York University, Toronto, Canada
In Paper 27.3, York University, together with the University of Toronto, GlaxoSmithKline, and Toronto Western
Hospital, present a 64-channel wireless closed-loop neurostimulator with a compact (0.013mm2/ch) and energy-
efficient (630nW/ch) channel architecture that merges both amplification and digitization in a single D2S-based
neural ADC. The design, implemented in 0.13m CMOS, yields 1.13mVrms IR noise and an NEF of 2.86.

3:15 PM
27.4 A Sub-1dB NF Dual-Channel On-Coil CMOS Receiver for Magnetic Resonance Imaging
B. Sporrer, ETH Zurich, Zurich, Switzerland
In Paper 27.4, ETH Zurich presents a fully integrated CMOS receiver for medical MRI that can be placed directly
on the coil eliminating any RF cabling. The RX features sub-1dB NF and 0dBm IIP3.

3:45 PM
27.5 A Pixel-Pitch-Matched Ultrasound Receiver for 3D Photoacoustic Imaging with Integrated Delta-Sigma
Beamformer in 28nm UTBB FDSOI
M-C. Chen, Stanford University, Stanford, CA
In Paper 27.5, Stanford University and STMicroelectronics present a 28nm ultrasound receiver for 3D
photoacoustic imaging with the front-end and the modulator integrated within a 250250m2 pixel. The
beamformer achieves 59.9dB SNR with a 7.4 area reduction over comparable prior-art solutions.

4:15 PM
27.6 Single-Chip 3072ch 2D Array IC with RX Analog and All-Digital TX Beamformer for 3D Ultrasound
Imaging
S. Kajiyama, Hitachi, Kokubunji, Japan
In Paper 27.6, Hitachi presents a 2D array ASIC with 3072 channel analog RX/TX beamformers for volumetric
ultrasound imaging. It features 138Vpp output capability on 0.09mm2/ch. The IC is fabricated in 0.18m HV-
CMOS, and the echo imaging consumes 0.7mW/ch.

4:45 PM
27.7 A 30.5 mm3 Fully Packaged Implantable Device with Duplex Ultrasonic Data and Power Links Achieving
95kb/s with <10-4 BER at 8.5cm Depth
T. C. Chang, Stanford University, Stanford, CA
In Paper 27.7, Stanford University demonstrates simultaneous ultrasonic wireless power and duplex data
communication for implantable applications. It operates at a depth of 8.5cm tissue phantom at a data rate of
95kb/s. The system consumes 405W, while receiving power and delivering -9dBm to the transmitter.

5:00 PM
27.8 Fully Integrated Optical Spectrometer with 500-to-830nm Range in 65nm CMOS
L. Hong, Princeton University, Princeton, NJ
In Paper 27.8, Princeton University presents a fully integrated CMOS-based optical spectrometer in a 65nm
bulk CMOS process that requires no external optical components. It achieves nearly 10nm resolution and 1.4nm
27
accuracy in peak prediction of continuous-wave excitation in the visible and near-IR range between 500 and
830nm.

DIGEST OF TECHNICAL PAPERS 447

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.1
27.1 A 2.8W 80mVpp-Linear-Input-Range 1.6G-Input
Impedance Bio-Signal Chopper Amplifier Tolerant to
Common-Mode Interference up to 650mVpp
Hariprasad Chandrakumar, Dejan Markovi
University of California, Los Angeles, CA
Closed-loop neuromodulation with simultaneous stimulation and sensing is
desired to administer therapy in patients suffering from drug-resistant
neurological ailments. However, stimulation generates large artifacts at the
recording sites, which saturate traditional front-ends. The common-mode (CM)
artifact can be ~500mV, and the differential-mode (DM) artifact is 50 to 100mV.
This work presents a neural recording chopper amplifier that can tolerate 80mVpp
DM and 650mVpp CM artifacts in a signal band of 1Hz to 5kHz. To digitize a 2mVpp
neural signal to 8b accompanied by an 80mVpp DM artifact requires a linearity of
80dB. Neural recording front-ends also need to function within a power budget
of 3 to 5W/ch, input-referred noise of 4 to 8Vrms, DC input impedance Zin>1G
and high-pass cutoff of 1Hz [1,2]. Prior work has addressed power and noise [2-
6], but has low Zin and limited input signal range, making them incapable of
performing true closed-loop operation.
The chopper amplifiers in [2,3,5,6] are vulnerable to large CM artifacts (Fig.
27.1.1). The CM signals appearing at the recording sites propagate unattenuated
to the input Vin,CM of the opamp gm, leading to severely distorted outputs. We
propose a common-mode cancellation (CMC) path to attenuate the CM signals
appearing at Vin,CM (Fig. 27.1.1). The opamp gma is used to sense the input CM
signal, which is amplified by Acm = 2Ca/Cb, and then subtracted from Vin,CM through
capacitors Ccm. By sizing Ccm=Cin/Acm, the CM signal is cancelled at Vin,CM. Since
gm is immune to small CM signals (~20mV), a cancellation accuracy of 2% is
sufficient. Increasing Ccm leads to increased noise from gm, hence Ccm is kept small
by increasing Acm. However, increasing Acm leads to larger swings at the output
of gma, which causes saturation. We integrate a 50%-efficient charge-pump to
generate a 1.8V supply for gma from the available 1.2V supply. Thus, the CMC path
can cancel a 650mVpp CM input with Acm=2, and the noise contribution of gm is
kept low.
The duty-cycled resistor (DCR) is used in [6] as a large linear resistor to realize a
low-pass filter (LPF) with bandwidth (BW) 0.2Hz (Fig. 27.1.1). However, the
parasitic capacitance Cp at node n1 forms a switched-cap resistor which limits the
maximum resistance to Rp=1/(f1Cp), where f1 is the switching frequency of the
DCR. Larger resistors would result in smaller chip area for a given corner
frequency and lower in-band (1Hz to 5kHz) noise. For Cp=5fF and f1=25kHz, Rp is
8G. Reducing Cp further is impractical, and f1 should be twice the input signal
bandwidth to avoid aliasing. We propose to use an anti-alias filter (AAF) with
BW10Hz formed by cap C1 and a DCR switching at f1, followed by a DCR
switching at f2 (Fig. 27.1.1). The AAF allows for a significantly reduced frequency
f2, enabling this multi-rate DCR (MDCR) to increase the maximum realizable
resistance by f1/f2, which is 32 in this work.
The auxiliary-path used in [6] charges the input caps Cin at the beginning of every
chopping phase using aux-buffers (Fig. 27.1.2), reducing the charge provided by
the input Vel to zero, thus boosting Zin. However, a positive feedback loop is formed
around the aux-buffers, leading to the aux-buffer DC offset and flicker noise
(modeled by Voff) being amplified and appearing at Vel. From Fig. 27.1.2, for typical
electrode DC impedance of Rel=200M, Cin=1pF and Ts=40s, Vel/Voff is 10, leading
to large DC offsets at Vel and increased flicker noise contribution from the aux-
buffers. Such large offsets, if left unchecked, can saturate the front-end. Since
Vel/Voff rolls off with frequency, we up-modulate Voff to fc/4 by using mixers M1
and M2 (Fig. 27.1.2), where fc is the chopping frequency. For fc=23.44kHz and
Cel=1nF, Voff generates a ripple at Vel with amplitude Voff(4/)2(Cin/Cel) Voff/616.
Hence, Voff=5mV creates a benign ripple of 8.1V at 5.86kHz instead of a 50mV
DC offset at Vel. Keeping the aux-buffer input devices small ensures negligible
reduction in Zin. Storage capacitors Caux=8pF assist the aux-buffers at the
beginning of the pre-charge phase (Fig. 27.1.2) by charge-sharing with Cin, and
448 2017 IEEE International Solid-State Circuits Conference
are disconnected for the remainder of the pre-charge phase. Hence, the input caps
Cin are accurately charged to Vin by the end of the pre-charge phase. Thus the
settling error in the pre-charge phase is reduced, leading to higher input
impedance without increasing power consumption. When 1,2=0, the aux-buffer
bias currents are reduced to 25nA to save power while ensuring that Caux tracks
Vel till the next pre-charge phase.
The chopper amplifier for spike and local field potential (LFP) recording is shown
in Fig. 27.1.3. The chopping frequency fc is 23.44kHz. The mid-band gain is set
by Cin/Cf = 20, and DC-blocking caps Cr are used to avoid chopper ripple at Vout
[6]. The servo-loop uses multi-rate duty-cycled resistors with a 10Hz anti-alias
filter, Ton=5ns, f1=23.44kHz and f2=732.5Hz, which boosts a 350k poly-resistor
to Rint=90G. Since Cint=12pF, the servo-loop integrator BW is 0.15Hz. The
chopper amplifier is fabricated in a 40nm CMOS technology. Figure 27.1.7 shows
the chip micrograph. The area is 0.069mm2/ch, and the total power drawn from
a 1.2V core supply is 2.8W. The mid-band gain is 25.7dB, the LP corner is 5kHz,
and the HP corner is programmable from 0.12 to 0.3Hz (Fig. 27.1.4) by varying
Ton in the MDCRs. The input-referred noise is 1.8Vrms (1 to 200Hz) and 5.3Vrms
(200Hz to 5kHz). Zin at DC is 1.6G, which is 76 higher than the input impedance
when the aux-path is disabled. Off-chip coupling caps would be needed if
Zin<1G. When the assistance from storage caps Caux was disabled, Zin reduced
to 600M.
When aux-chopping is disabled, a 45mV offset is observed at Vel and the input-
referred noise increases from 1.8Vrms to 4.5Vrms (1 to 200Hz) due to increased
flicker noise contribution from the aux-buffers. When aux-chopping is enabled,
no discernible offset is present at Vel, and a 5.4V ripple is observed at 5.86kHz.
Rel=250M and Cel=1nF are used for all measurements.
The total harmonic distortion (THD) for an 80mVpp input at 1kHz is 76dB (Fig.
27.1.5). A two-tone test was performed (Fig. 27.1.5) in the presence of a 650mVpp
CM interferer. When CMC is disabled, the signal-to-interferer ratio (SIR) is 7dB,
which improves to 38dB when CMC is enabled. For an 80mVpp input, the dynamic
range of the front-end is 74dB in the spike band and 81dB in the LFP band. Figure
27.1.6 compares the performance of our work with the current state of the art.
Our work significantly improves Zin (5.3), linear input range (2), introduces
tolerance to large CM interferers, increases the maximum resistance of DCRs
(32), requires no off-chip caps and solves the positive-feedback problem in the
auxiliary path, while achieving comparable power and noise performance.
Acknowledgements:
The authors thank Yuta Toriyama and Dr. Vaibhav Karkare for reviewing the
manuscript, Vahagn Hokhikyan for testing support, Dr. Itzak Fried and Prof.
Richard Staba for human LFP and spike data, and Lawrence Livermore National
Lab for electrodes. This research was developed with funding from the Defense
Advanced Research Projects Agency (DARPA). The views, opinions, and/or
findings expressed are those of the authors and should not be interpreted as
representing the official views or policies of the Department of Defense or the
U.S. Government.
References:
[1] T. Jochumand, et al., IC Amplifiers for Multi-electrode Intracortical
Recording," IOP J. Neural Eng, vol. 6, no. 1, 2009.
[2] T. Denison, et al., "A 2W 100nV/Hz Chopper-Stabilized Instrumentation
Amplifier for Chronic Measurement of Neural Field Potentials," IEEE JSSC, vol.
42, no. 12, pp. 2934-2945, Dec. 2007.
[3] Q. Fan, et al., "A 1.8W 60nV/Hz Capacitively-Coupled Chopper
Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes," IEEE JSSC,
vol. 46, no. 7, pp. 1534-1543, July 2011.
[4] R. Muller, et al., A 0.013mm2, 5W, DC-Coupled Neural Signal Acquisition
IC with 0.5V Supply," IEEE JSSC, vol. 47, no. 1, pp. 232-243, Jan. 2012.
[5] R. Muller, et al., "A Miniaturized 64-ch 225W Wireless ECoG Neural Sensor,"
ISSCC, pp. 412-413, Feb. 2014.
[6] H. Chandrakumar, et al., A 2W 40mVpp Linear-Input-Range Chopper-
Stabilized Bio-Signal Amplifier with Boosted Input Impedance of 300M and
Electrode-Offset Filtering, ISSCC, pp. 96-97, Feb. 2016.
978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 1:30 PM

Figure 27.1.2: Conventional auxiliary path amplifies aux-buffer offset (top).

Figure 27.1.1: CM cancellation in chopper amps (left) preserves linearity. Proposed auxiliary path technique (bottom) mitigates the offset and achieves
Multi-rate resistor (right) increases maximum realizable resistance by 32. higher Zin.

Figure 27.1.4: Chip measurements: gain with programmable HP corner (top),

Figure 27.1.3: Complete implementation of the chopper amplifier. input-referred noise (center), input impedance (bottom).

27
Figure 27.1.5: Measured linearity (top). Measured outputs for 2-tone tests with
a CM interferer (bottom). The DM and CM tones at 900Hz emulate the stim
artifact, and the 1kHz tone is the signal of interest. Figure 27.1.6: Comparison with current state of the art.

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 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.1.7: Chip micrograph (top) of 8-channel IC, and single-channel

amplifier (bottom).

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.2
27.2 A 25.2mW EEG-NIRS Multimodal SoC for Accurate
Anesthesia Depth Monitoring
Unsoo Ha1, Jaehyuk Lee1, Jihee Lee1, Kwantae Kim1, Minseo Kim1,
Taehwan Roh2, Sangsik Choi3, Hoi-Jun Yoo1
1
KAIST, Daejeon, Korea
2
K-Healthwear, Daejeon, Korea
3
Korea University Guro Hospital, Seoul, Korea
There has been recent research into continuous monitoring of the quantitative
anesthesia (ANES) depth level for safe surgery [1]. However, the current ANES
depth monitoring approach, bispectral index (BIS) [3], uses only EEG from the
frontal lobe, and it shows critical limitations in the monitoring of ANES depth such
as signal distortion due to electrocautery, EMG and dried gel, and false response
to the special types of anesthetic drugs [3]. Near-infrared spectroscopy (NIRS)
is complementary to EEG [2], and can not only compensate for the distorted depth
level, but also assess the effects of various anesthetic drugs. In spite of its
importance, a unified ANES monitoring system using EEG/NIRS together has not
been reported because NIRS signals have widely different dynamic ranges (10pA
to 10nA), and also signal level variations from person to person and environment
are not manageable without closed-loop control (CLC).
In this paper, a multimodal head-patch system that simultaneously measures EEG
and NIRS on the frontal lobe is proposed for accurate ANES depth monitoring. A
60dB dynamic range logarithmic TIA (logTIA) is adopted to amplify the photodiode
(PD) signal and a CLC driver is used to compensate for the human-to-human
variations. Also, an LNA with high Zin (1G) and wide electrode DC-offset (EDO)
cancelation range (350mV) is integrated to obtain reliable EEG signals.
Figure 27.2.1 illustrates the ANES depth monitoring system. On the bottom side
of the head-patch, 2-ch EEG/EMG electrodes (each 3.14cm2) and a 1-ch NIRS
module composed of a red(=670nm)/infrared(IR)(=850nm) vertical-cavity
surface-emitting laser (VCSEL) and a PD on silicon holder are integrated on the
polyethylene terephthalate (PET) film. The SoC, BLE module and battery are
assembled on the flexible-PCB. Compact (263.5cm2) and lightweight system
(<10g) enables the practitioner to measure signals with high convenience. The
system is applied on the patients forehead/temple and all the acquired signals
are pre-processed in the SoC and then sent to an external device through
Bluetooth. The device can display the ANES depth level with the help of a deep
neural network to help the anesthesiologist adjust the drug dosages for safe ANES.
Figure 27.2.2 shows the overall block diagram of the SoC. It consists of: (1) a 2-
ch EEG/EMG readout for high input impedance (Zin) and large EDO tolerance, (2)
a 1-ch NIRS readout for wide dynamic range, (3) a Red/IR VCSEL driver for CLC,
(4) a 12b SAR ADC, and (5) a digital module for pre-processing and
communication through BLE module.
Figure 27.2.3 shows the circuit schematics and the measurement results of the
LNA. The EDO usually increases up to 300mV almost like the dry electrode [4]
due to very long sedation time, sometimes >24 hours [1]. To eliminate the EDO
with low noise, a mixed-mode dc-servo loop (MM-DSL) is proposed. The MM-
DSL is composed of digital (CD,DSL) DSL for wide range and low noise, and analog
(CA,DSL) DSL for fine resolution. Initially, with the help of SAR, digital DSL cancels
EDO coarsely with a 5b CDAC (10.9mV LSB). Then, analog DSL (up to 21mV) is
activated to decrease the remaining EDO. CD,DSL is updated according to VDSL,int to
remove the temporal EDO drift. Right after the start and whenever the value of
CD,DSL changes, fp1 is increased to >50Hz to reduce the settling time from >60s to
<50ms. In this work, a 130ms window is assigned to ensure enough margin. With
the help of MM-DSL, the LNA shows 3.59 NEF with 350mV EDO cancellation
range. The impedance-boosting loop [2] enhances Zin about 50 (>1G) at 60Hz.
450 2017 IEEE International Solid-State Circuits Conference
Figure 27.2.4 shows the logTIA with ambient light rejection (ALR) and its
measurement results. Since the NIRS has wide dynamic range and contrast-
sensitive characteristics [6], the logTIA is employed. When SW1 is ON, the
ambient light (AL) voltage is sampled on C1 and then it is subtracted from Itot
through a 1st replica circuit when SWEN is ON for the ALR. fp2,3 are shifted to higher
frequency along with fp1 through 2nd replica by adjusting Itail1,2 (250nA-10A)
depending on Vout,TIA to maintain stability of the TIA. Vout,TIA shows the voltage
output of AL with SW1 ON and NIRS signal with SWEN ON. Measured waveforms
show stable VCSEL Vout,TIA with <1mV fluctuation even though AL fluctuates
>400mV. The Isig vs. Vout,TIA transfer curve shows an R-squared value of 0.998.
Figure 27.2.5 shows NIRS CLC for adaptive duty-cycling. Since Cin and input
current are variable, the turn-on time of VCSEL should be adaptively controlled
for TIA output (VT) settling. At the P period with SW2 ON, VT is sampled on V+
node and at E period with SW1 ON, VT is sampled on V- node. When the input
voltage difference is <Vth,c (0.25mV), the comparator delay time increases
drastically. If comparator delay is longer than the E period, VCSEL is turned off to
save power. As a result, VCSEL turns on during 8.75ms at the moment and its
driving current can be controlled from 0 to 17.2mA (6b). A differential difference
amplifier (DDA) buffer is used to compensate for the different common-mode
voltage of comparator input.
Figure 27.2.6 shows the clinical results for propofol-induced general ANES and
ketamine-induced general ANES. First, the estimated ANES depth values of the
system are compared with BIS values, during the same surgical operation.
Proposed depth index trends such as sudden drop after the propofol sedation
and steady increase after the reduction of inhalational anesthetic are almost the
same as the index of reference. During intubation, which causes intense EMG,
and electrocautery step, a sudden 10-15 BIS index rise is observed but the system
generates stable results. Second, ketamine, for which BIS gives a false result, is
used to test the operation of the system. Its output clearly shows the clinically
important transition from the awake to deep state but BIS cannot detect the
transition.
Figure 27.2.7 shows the chip micrograph and performance summary table. The
16mm2 chip is fabricated in 65nm CMOS. It dissipates 25.2mW peak power. The
LNA shows a state-of-the-art NEF of 3.59 at the 300mV EDO input. Zin is over
1G. LogTIA can reject AL to maximize the dynamic range up to 60dB. According
to the comparator output, NIRS driver duty-cycle can be adjusted from 0.625m
to 50ms adaptively. As a result, the compact ANES depth monitoring head-patch
enables more accurate ANES depth monitoring even under special drugs which
the BIS cannot detect for safe surgery in operating room.
References:
[1] J. Johansen, et al., Development and Clinical Application of
Electroencephalographic BIS Monitoring, JASA, pp. 1336-1344, vol. 93, no. 5,
pp. 1097-1108, Nov. 2000.
[2] U. Ha, et al., A Wearable EEG-HEG-HRV Multimodal System with
Simultaneous Monitoring of tES for Mental Health Management, IEEE TBioCAS,
pp. 758-766, vol. 9, no. 6, pp. 758-766, Dec. 2015.
[3] L. Duarte, et al., When the BIS Can Give False Results, Revista brasileira de
anestesiologia, vol. 59, no. 1, pp. 99-109, Jan. 2009.
[4] C. Lin, et al., Novel Dry Polymer Foam Electrodes for Long-Term EEG
Measurement, IEEE Trans. Biomed. Eng., vol. 58, no. 5, pp. 1200-1207, May
2011.
[5] P. Tallgren, et al., Evaluation of Commercially Available Electrodes and Gels
for Recording of Slow EEG Potentials, C. Neurophysiology, vol. 116, no. 4, pp.
799-806, Nov. 2005.
[6] E. Kamrani, et al., State-of-the-Art LogTIA With Automatic Gain Control and
ALR for fNIRS, SPIE MIOMD-XI, pp. 58-59, Dec. 2012.
978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 2:00 PM

Figure 27.2.1: Proposed anesthesia depth monitoring system. Figure 27.2.2: Overall block diagram of the monitoring IC.

Figure 27.2.3: EEG low-noise amplifier with Mixed-Mode DSL. Figure 27.2.4: NIRS log TIA with ambient light rejection.

27

Figure 27.2.5: NIRS closed control loop for adaptive duty-cycling. Figure 27.2.6: System measurement results in the clinical trials.

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Figure 27.2.7: Chip micrograph and performance summary.

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.3
27.3 All-Wireless 64-Channel 0.013mm2/ch Closed-Loop
Neurostimulator with Rail-to-Rail DC Offset Removal
Hossein Kassiri1, M. Reza Pazhouhandeh2, Nima Soltani2,
M. Tariqus Salam3, Peter Carlen2,4, Jose Luiz Perez Velazquez2,
Roman Genov2
1
York University, Toronto, Canada
2
University of Toronto, Toronto, Canada
3
GSK (GlaxoSmithKline), Stevenage, United Kingdom
4
Toronto Western Hospital, Toronto, Canada
Accurate capture and efficient control of neurological disorders such as epileptic
seizures that often originate in multiple regions of the brain, requires neural
interface microsystems with an ever-increasing need for higher channel counts.
Addressing this demand within the limited energy and area of brain-implantable
medical devices necessitates a search for new circuit architectures. In the
conventional designs [1-5], the channel area is dominated by the bulky coupling
capacitors and/or capacitor banks of the in-channel ADC, both unavoidable due
to the channel architecture, and unscalable with CMOS technology. Additionally,
channel power consumption, typically dominated by the LNA, cannot be reduced
lower than a certain limit without sacrificing gain and/or noise performance. In
this paper, we present a 64-channel wireless closed-loop neurostimulator with a
compact and energy-efficient channel architecture that performs both
amplification and digitization in a single -based neural ADC, while removing
rail-to-rail input DC offset using a digital feedback loop. The channel area and
power consumption depend only on the active components and switching
frequency, respectively, making the design both technology- and frequency-
scalable.
Figure 27.3.1 (top) shows the block diagram of the 2 (+) neural ADC.
Because of the added stage, the output bit-stream (Y) of modulator is
equivalent to the derivative of the input signal. Consequently, after feeding Y to
the feedback integrator, a reconstructed version of the previous sample of the
input signal (VIN[n-1]) is obtained. As a result, the output of the first stage (dVIN)
is the difference between the two consecutive samples of the input signal, which
means any DC offset value (0 to VDD) is removed. Figure 27.3.1 (bottom) depicts
how the architecture is made differential for an array of 64 channels. As shown,
by dedicating a single copy of the described architecture as the reference channel,
the derivative of the reference signal is taken (dVREF) and subtracted from the
derivative of input signal of each recording channel. Moreover, given the high
oversampling ratio (OSR) and due to operating on signal derivatives only, this
configuration has virtually no upper-limit for the input signal amplitude in the LFP
range (<500Hz).
Figure 27.3.2 shows the recording channel circuit schematic. Positive-gain and
negative-gain parasitic-insensitive integration are used to implement the stage
of the modulator for the input and reference signals, respectively. In each
clock cycle, one integrator pulls and the other pushes charge to the shared
accumulating capacitor (C2), resulting in differential integration. Correlated double
sampling is implemented using CCDS and one extra switch to remove the flicker
noise and offset of the two-stage 10T amplifier A. The compact IMDAC (I-mode
multiplying DAC) in the feedback integrator is comprised of two segments of 4b
binary-weighted programmable push/pull current sources. The segments are
biased by two currents, different by a factor of 16 for a total of 8b of resolution.
The output bit-stream, which is a derivative of the input signal, is fed to a
resettable (decimating) and a non-resettable (integrating + decimating) up/down
counters, to obtain digital equivalents of the input signal (MDOUT) and its
derivative (MDOUT), respectively. The 90 phase difference between the two
outputs that comes at the cost of only one additional counter, makes them
quadrature signals ideal for neural signal phase calculation in the digital signal
processing backend. In-channel low-overhead digital-analog multiplication (M)
eliminates expensive signal weighting for tone-selecting FIR filters in the digital
backend.
Figure 27.3.3 depicts the system VLSI architecture of the fabricated responsive
neurostimulator SoC. It includes 64 closed-loop neuro-stimulators, a low-power
DSP with a compact mixed-signal FIR filter, two UWB transmitters, and an
inductive power and command receiver. The on-chip DSP calculates the phase
synchrony among channels to detect an upcoming epileptic seizure. Five out of
452 2017 IEEE International Solid-State Circuits Conference
six animal subjects have become seizure-free in a recent study using phase
synchrony [6], as compared to the 1-out-of-10 seizure-free outcome using
conventional neurostimulators. Once a detection is made, an arbitrary-waveform
current-mode biphasic stimulation is applied to a subset of the electrodes with a
spatio-temporal profile specifically chosen for a given subject. During stimulation,
the previously-introduced in-channel programmable IMDAC is reused for current-
mode biphasic pulse generation. Thus, arbitrary-waveform stimulation enabled
by analog-digital multiplication is performed at almost no extra area cost, and
6464-tap power-hungry and area-inefficient digital multipliers are once again
avoided. The recorded intracranial EEG/ECoG data and status signals are also
transmitted out transcutaneously using either a low-power delay-based short-
range (d<10cm) or a VCO-based long-range (d<2m) UWB transmitters. Energy
is received by a single coil through a multi-coil cellular inductive link at 1.5MHz
frequency. The power receiver outputs 30mW maximum power for the 15cm
transmission distance with the overall power transfer efficiency of 40%. An ASK-
demodulating command receiver reuses the same inductive link to recover
transmitted commands and the clock.
Figure 27.3.4 depicts experimentally measured data for the neurostimulation
channel. Figure 27.3.4 (top) shows the experimentally measured FFT of the ADC
output with a 130Hz input sampled at 1MHz (with the input signal bandwidth of
500Hz). The measured input impedance remains above 100M (sufficient for
implantable intracranial recording), even with the maximum sampling frequency
of 1MHz. The channel yields SNDR and ENOB of 72.2dB and 11.7b, respectively.
Figure 27.3.4(middle) shows the input-referred noise spectrum with and without
correlated double-sampling. Figure 27.3.4(bottom) shows three examples of
waveforms generated by the arbitrary-waveform current-mode stimulator with a
1k load.
Figure 27.3.5 (left, top and middle) shows the quadrature outputs of the channel
for a multi-tone input, the phase error as compared to the ideal 90 phase
difference, and the calculated phase using the on-chip processor. Figure 27.3.5
(top, right) shows how the power consumption of all the blocks scales linearly
with the input signal bandwidth. As shown, the recording channel dissipates a
total of 630nW for the ECoG band, the band used for seizure prediction. Figure
27.3.5 (middle, right) shows how the active-component-dominated channel area
scales with the technology compared to a conventional AC-coupled channel [1].
Figure 27.3.5 (bottom) shows the power spectral density of the two UWB
transmitters.
The 0.13m CMOS SoC was validated in both early detection (experiment 1) and
control (experiment 2) of seizures in temporal lobe epilepsy (rat model). Figure
27.3.6 (top, left) shows an example of in vivo online on-chip real-time seizure
detection without stimulation. In the second experiment, the SoC was configured
to automatically trigger the closed-loop electrical stimulation for the purpose of
suppressing upcoming seizures. Figure 27.3.6 (top, right) illustrates the SoC-
triggered stimulation upon a seizure onset detection. The SoC is compared with
the state of the art both in terms of the channel performance (Fig. 27.3.6 (bottom))
and the system performance (Fig. 27.3.7(bottom)). The chip micrograph and the
channel floorplan are shown in Fig. 27.3.7 (top).
References:
[1] K. Abdelhalim, et al.,64-channel UWB Wireless Neural Vector Analyzer SOC
with a Closed-Loop Phase Synchrony-Triggered Neurostimulator, IEEE JSSC,
vol. 48, no. 10, pp. 2494-2510, 2013.
[2] W.M. Chen, et al., A Fully Integrated 8-channel Closed-loop Neural-prosthetic
CMOS SoC for Real-time Epileptic Seizure Control, IEEE JSSC, vol. 49, no. 1, pp.
232-247, 2014.
[3] R. Muller, et al., A minimally invasive 64-channel wireless ECoG implant,
IEEE JSSC, vol. 50, no. 1, pp. 344359, Jan. 2015.
[4] K. Ng, et al., A Multi-Channel Neural-Recording Amplifier System with 90dB
CMRR Employing CMOS-Inverter-Based OTAs with CMFB Through Supply Rails
in 65nm CMOS, ISSCC, pp. 206-207, Feb. 2015.
[5] H. Kassiri, et al., Battery-Less Tri-Band-Radio Neuro-Monitor and Responsive
Neuro-Stimulator for Diagnostics and Treatment of Neurological Disorders, IEEE
JSSC, vol. 51, no. 5, pp. 1274-1289, 2016.
[6] M.T. Salam, et al., Rapid Brief Feedback Intracerebral Stimulation Based on
Real-time Desynchronization Detection Preceding Seizures Stops the Generation
of Convulsive Paroxysms, Epilepsia, vol. 56, no. 8, pp. 1227-1238, 2015.
978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 2:30 PM

Figure 27.3.1: Block diagram of the -based neural recording channel in both Figure 27.3.2: Circuit schematic of the recording channel (top); the input
single-ended (top) and differential (bottom) configurations. integrator during the two phases of a single clock cycle (bottom).

Figure 27.3.4: Experimentally measured performance characteristics of the

Figure 27.3.3: Block diagram of the fabricated neurostimulator SoC. neurostimulator channel.

27
Figure 27.3.5: Experimentally measured performance: the on-chip phase Figure 27.3.6: In vivo seizure detection and closed-loop stimulation results for
calculation, power scalability with bandwidth, area scalability with technology, a rat epilepsy model (top), neurostimulator channel performance comparison
and wireless transmitters output spectra. (bottom).

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 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.3.7: Chip micrograph and channel floorplan (top), and a system-level
comparison table (bottom).

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.4
27.4 A Sub-1dB NF Dual-Channel On-Coil CMOS Receiver
for Magnetic Resonance Imaging
Benjamin Sporrer1, Lianbo Wu1, Luca Bettini1, Christian Vogt1,
Jonas Reber2, Josip Marjanovic2, Thomas Burger1, David O. Brunner2,
Klaas P. Prssmann2, Gerhard Trster1, Qiuting Huang1
1
ETH Zurich, Zurich, Switzerland
2
University and ETH Zurich, Zurich, Switzerland
Magnetic Resonance Imaging (MRI) is a widely used medical imaging technique.
It employs a strong static magnetic field (1.5 to 10.5T for human imaging) to split
the spin states of the 1H nuclei in the body, and RF excitation to induce transitions
and coherence among them. Gradient fields are superimposed to modulate the
1
H resonance frequency, which enables spatially distinguishable signals to be
picked up by RF receive coils. A high-field MRI provides better sensitivity and
resolution but requires better receivers (RX), as signal DR and 1H resonance
increase (128MHz for 3T, 300MHz for 7T). Overall sensitivity and imaging speed
can be enhanced by closely surrounding the target anatomy with tens of RX coils
(as in MIMO) [1], at the expense of as many shielded RF cables to carry the
information out of the field. Progress in PCB size has allowed multi-channel RX
to be placed inside the magnetic field (in-bore), reducing the RF cable length to
less than 1m [2,3]. Ultimately, the RX should be placed directly on-coil to avoid
bulky coaxial cables and improve patient comfort and safety by acquiring data in-
bore and sending them digitally to the MRI scanner via an optical fiber link. The
latter is cheap, flexible and insensitive to magnetic fields. The immediate vicinity
of the coils and the patient is, however, a hostile as well as sensitive
electromagnetic environment, which tolerates only the smallest of PCBs and
virtually no magnetic material in its components. Integration of the full RX chain
in a CMOS chip, which is small, non-magnetic and low power, holds the key to
the next wave of compact MRI coil arrays for advanced medical imaging. This
paper presents a fully integrated dual-receiver RFIC for coil arrays intended for
(ultra-) high field (1.5 to 10.5T and 64 to 450MHz) scanners for clinical MRI,
where requirements are considerably stricter than previously reported transceiver
ICs [4,5] on palm-held NMR devices for spectroscopy or lab-on-chip applications.
Figure 27.4.1 shows the overview of an MRI system with on-coil RX, and
associated timing diagrams for a receiving slot. The RFIC integrated in 130nm
CMOS is preceded by switchable matching networks, which alternate the coil
resonances (detune) to prevent the RF excitation pulse from destroying the RFIC,
and followed by a serializer for interfacing to optical fibers. The on-coil PCB
depicted in upper Fig. 27.4.1 is completed by a small FPGA that choreographs
the RFIC according to the optical control line from the MRI scanner shown on the
left of Fig. 27.4.1, to which the receiver output is sent in an optical data stream
on a 2nd fiber. A 3rd optical fiber supplies the reference clock to the RFIC, for
reasons to be discussed below.
The quality of an MRI image is critically dependent on the phase accuracy and
the SNR of acquired samples, so the receiver noise figure (NF) and local oscillator
(LO) phase jitter can be demanding to an extent considerably exceeding those of
advanced wireless communications [6]. Sub-dB NF and picoseconds jitter are
hard specs even for circuits with substantial power budget, intended for use
outside strong magnetic fields, but an on-coil RFIC design is compounded by the
highly mismatched source impedance seen by the LNA and corruption of clock
reference for its phase-locked-loop (PLL). A frequency reference directly derived
from an on-coil crystal lacks the long-term stability required by wide receive
windows (50 to 100ms) necessary to hold down the number of necessary RF
excitations and save scan time. Furthermore, several receive-windows should be
acquired within one single excitation cycle, which further increases the
requirements on the long-term stability of the PLL. Its short term stability, on the
other hand, suffers from strong modulation by powerful gradient fields (crystal
packaging is typically sensitive to magnetic field). A highly stable oven-controlled
crystal oscillator (OCXO), necessarily outside bore, can provide the required
reference, but its phase characteristics get corrupted if supplied via a noisy fiber
link to the on-coil receiver. Our solution to this long-standing challenge is a two-
stage cascaded PLL architecture for LO generation, as shown in the lower half of
the receiver block diagram in Fig. 27.4.2. The reference to the (2nd-stage) RF PLL
is provided by an on-coil digitally-controlled crystal oscillator (DCXO), which is
in turn phase-locked by way of another on-chip (1st-stage) PLL to the OCXO via a
fiber link. The input to the 1st-stage PLL is noise-corrupted above 500Hz offset
454 2017 IEEE International Solid-State Circuits Conference
but this is cleaned up by its digital loop filter with a cutoff frequency set low
enough to clean up the noise added by the fiber link but high enough to preserve
resilience to gradient fields. Figure 27.4.3 shows measured LO phase noise under
five different combinations of conditions. We see that the 1st-stage digital PLL
introduced in this chip improves jitter performance by 100, when in-bore with
gradient field on, by rejecting the in-band noise due to interference and out-of-
band noise added by the fiber link.
Sub-dB NF is achieved by a noise-cancelling broadband LNA, covering the full
range of targeted field strengths (Fig. 27.4.4). Its fully differential architecture
rejects common-mode noise as opposed to traditional single-ended designs. The
LNA input impedance Zin needs to be highly mismatched to the source impedance
RS to avoid noise coupling to nearby coils, which can degrade the effective SNR
of an array receiver. Controlled by a programmable divider formed by capacitors
CL and Cfb, Zin can be tuned (real part from 25 to 100) in accordance with RS,
whose variation due to placement or target anatomy can be compensated to
preserve both low NF and sufficient mismatch. An IIP3 of 0dBm and an input
0.1dB compression point of -23dBm from the LNA and the subsequent mixing
stage keep distortion low at peak input powers. Down-conversion is performed
by means of a harmonic-reject mixer to minimize the impact of the LNA broadband
noise on the system NF. The remaining receiver chain (mid-Fig. 27.4.2) consists
of baseband filters that support 42dB of gain programmability in 1dB steps, to
accommodate varying input power and trade NF for linearity in case of large peak
signals. A well-controlled range of the band-limited input at the ADC means the
latters 12b ENOB resolution at 2MS/s provides equal or better overall
performance than typical discrete solutions sub-sampling a wideband LNA output
with a 16b ADC at 100+ MHz, as shown at the top of Fig. 27.4.2.
Figure 27.4.5 summarizes the overall RFIC performance, with reference to prior-
art discrete solutions where applicable. Salient features include low power
consumption, which improves patient safety and makes energy supply by fiber
link a more realistic prospect, low noise (in the discrete solution LNA NF will be
degraded by the rest of the chain) and, particularly, a low phase jitter insensitive
to powerful gradient field switching.
A proof-of-concept, single-coil experimental PCB assembly, based on Fig. 27.4.1,
is constructed for use inside a commercial MRI scanner (providing 3T static field).
Figure 27.4.6 shows two scanned images taken of a wrist, along with a photo of
the setup, on which the RF coil measures 100cm2. Figure 27.4.7 shows the
micrograph of the 22mm2 RFIC.
Acknowledgments:
The authors would like to thank ACP Advanced Circuit Pursuit AG for supporting
the chip implementation. This research is funded by the Swiss Nano-Tera project
WearableMRI.
References:
[1] K.P. Pruessmann, et al., SENSE: Sensitivity Encoding for Fast MRI, Magnetic
Resonance in Medicine, pp. 952-962, 1999.
[2] J. Reber, et al., In-Bore Broadband Array Receivers with Optical
Transmission, Proc. Intl. Soc. Mag. Reson. Med., p. 619, 2014.
[3] C. Possanzini, et al., dStream Architecture, 2011. Accessed on Nov. 15,
2016. <http://clinical.netforum.healthcare.philips.com>.
[4] A. Hassibi, et al., A Spectral-Scanning Nuclear Magnetic Resonance Imaging
(MRI) Transceiver, IEEE JSSC, pp. 1805-1813, June 2009.
[5] K. Lei, et al., A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with
B-Field Stabilization for Multi-Type Biological/Chemical Assays, ISSCC, pp. 474-
475, Feb. 2016.
[6] B. Sporrer, et al., Integrated CMOS receiver for wearable coil arrays in MRI
applications, IEEE DATE, pp. 1689-1694, Mar. 2015.
978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 3:15 PM

Figure 27.4.1: Block diagram of the on-coil PCB and receiver states during MRI Figure 27.4.2: Fully integrated CMOS direct-conversion receiver with reflective
operation. LNA and 2-stage PLL for system synchronization.

Figure 27.4.3: Measured phase noise of divided LO (64MHz) in a 3T MRI Figure 27.4.4: Noise-cancelling LNA with configurable low input impedance
scanner. Influence of 1st stage digital PLL is illustrated. (Re(Zin)RS). Re(Zin) can be set between 25 and 100.

27

Figure 27.4.5: MRI receiver benchmark and measured RX IC performance for a Figure 27.4.6: Acquired images from a human wrist with an on-coil receiver in
7T setup (300MHz). Jitter is measured in 3T. a one channel setup shown in the bottom right corner.

DIGEST OF TECHNICAL PAPERS 455

 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.4.7: Integrated MRI receiver chip micrograph.

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.5
27.5 A Pixel-Pitch-Matched Ultrasound Receiver for 3D
Photoacoustic Imaging with Integrated Delta-Sigma
Beamformer in 28nm UTBB FDSOI
Man-Chia Chen1, Aldo Pea Perez1, Sri-Rajasekhar Kothapalli1,
Philippe Cathelin2, Andreia Cathelin2, Sanjiv Sam Gambhir1,
Boris Murmann1
1
Stanford University, Stanford, CA
2
STMicroelectronics, Crolles, France
A variety of emerging applications in medical ultrasound rely on 3D volumetric
imaging, calling for dense 2D transducer arrays with thousands of elements. Due
to this high channel count, the traditional per-element cable interface used for 1D
arrays is no longer viable. To address this issue, recent work has proven the
viability of flip-chip bonding [1] or direct transducer integration [2]. This shifts
the burden to a CMOS substrate, which must provide dense signal conditioning
and processing before the massively parallel image data can be pushed off chip.
A common approach for data reduction is to employ subarray beamforming (BF),
which applies delay and sum operations within a group of pixels. To implement
such functionality within the tight pixel pitch, prior works have implemented the
delays using simple S/H circuits [2] or analog filters [3], and typically suffer from
a combination of issues related to limited delay, coarse delay resolution and
limited SNR.
This work leverages the integration density of modern CMOS to demonstrate a
pitch-matched digital subarray beamforming receiver (RX) with signal
conditioning and modulator (M) integrated within a pixel area of BF power of 2.99mW/channel, which lies between [2] and [3]. In summary, we
250250m2 (see Fig. 27.5.1). Our proof-of-concept IC supports a subarray of
44 pixels and is flip-chip bonded to a Capacitive Micromachined Ultrasound
Transducer (CMUT) chip that is similar to the one used in [1]. Since our
application is photoacoustic imaging (receive-only using external laser pulses),
we did not integrate a transmitter interface. However, in a large-scale array
implementation of our concept, it is conceivable to add this functionality using a
subset of the pixels for transmit [2].
Figure 27.5.2 compares our approach with prior art: analog BF [2-3] and digital
BF using a per-channel Nyquist ADC. The latter approach is popular for 1D arrays,
but difficult to integrate within a pitch-constrained 2D array. In addition, the
Nyquist ADC must typically oversample to provide sufficient timing resolution,
which further exacerbates the integration issue. The work of [4] combines analog
and digital Nyquist-rate BF, but the area per element is ~5 larger than our pixel
size. To enable area-efficient digital BF, this work uses a approach similar to
[5]. The oversampling of the M naturally provides sufficient timing resolution
for BF, enables low-complexity analog design with small passives, and simplifies
the signal routing (1b outputs). In our chip, the 16 bitstreams are routed to a
global digital block for decimation filtering (DF1) and beamforming (BF = FIFO +
summation), followed by a final decimation filter (DF2) off chip. Within the on-
chip block, the BF is placed after DF1, which was identified as the preferred option
due to the lower FIFO clock speed and the commensurate reduction in power (see
Fig. 27.5.3). Placing the BF before DF1 (as in [5]) would lead to a slightly lower
gate count (since DF1 is shared), but the savings are insignificant due to the
relatively low complexity of the employed cascaded integrator comb (CIC) filter.
We expect the advantages of the DF-first option to become more pronounced for
larger arrays, where early clock rate reduction is critical. Despite the decimation
by DF1, the delay resolution is still 8.33ns, which is sufficient for a 5MHz CMUT
center frequency. The implemented FIFOs have a depth of 27, providing the
required delay range for our 44 subarray (1.06s).
Figure 27.5.4 shows the analog front-end. The transimpedance amplifier (TIA)
provides five gain levels using a programmable R network. The TIA output is taken
against a replica to facilitate supply noise cancellation as the succeeding lowpass
filter (LPF) performs single-ended to differential conversion. Both the TIA and LPF
are designed using 1.5V thick oxide devices (for large DR), while all other circuits
use core devices (1V supply). The VGA uses a Pad approximation to provide fine
linear-in-dB gain tuning. The 1b M (see Fig. 27.5.5) uses a 3rd-order
architecture with an OSR of 48 to provide 60dB peak SNR in a 10MHz BW. The
employed inverter-based SC integrator is similar to [6]. It uses three gain stages
to achieve the required gain with minimum L, and it is designed to slew for the
456 2017 IEEE International Solid-State Circuits Conference
most of the clock period. The large swing at the 3rd stage input during slewing
leads to small devices and a compact layout. The input bias of the 3rd stage is
established using diode replicas and stored on Cb. In comparison to [6], this
obviates the need for special high VT devices and resistors. As illustrated in Fig.
27.5.5, the designed ADC is the smallest published among designs with similar
BW and SNDR.
Our chip is fabricated in a 28nm UTBB FD-SOI CMOS process. The 16 RX pixels
occupy 1mm2 and consume 358mW, while the synthesized digital block occupies
0.4mm2 and consumes 173mW. The M occupies 1/4th of the pixel area and
consumes 6.65mW. The M was measured in isolation (test pixel), showing
SNRpeak = 59.9dB and SNDRpeak = 58.9dB for a 2MHz input. To evaluate the entire
RX, a diced 44 2D CMUT array is flip-chip bonded onto the 28nm chip. The
receiver is tested within a photoacoustic imaging setup, where the acoustic signals
are induced by light absorbing wire targets (see Fig. 27.5.6). The cross-sectional
view from the y-z plane shows three parallel wires at different depths, while the
view from the x-z plane captures their diagonal placement.
Figure 27.5.7 shows the top view of the chip stack and the RX chip, along with a
comparison to the state of the art (focusing on BF performance). Relative to the
hybrid analog/digital BF approach of [4], our work has comparable delay
resolution and power dissipation, while achieving 7.4 smaller area and 7dB
improvement in single-channel SNR. Our maximum delay range is lower due to
the different requirements imposed by our 44 array, but it is straightforward to
extend it through a longer FIFO. A direct comparison to analog BF ICs [2-3] is
more difficult to make, due to the significantly different performance parameters.
If we relax the SNR to 40dB and reduce the delay range to 200ns, we estimate an
8 and 5 power reduction for our M and BF, respectively. This would yield a
view the demonstration of in-pixel A/D conversion and efficient BF as the most
important aspects of this work. We believe that the presented approach offers a
viable path toward larger arrays with pitch-matched electronics, high-fidelity
readout and digital subarray BF.
Acknowledgement:
Silicon fabrication was provided by STMicroelectronics through CMP. We thank
Romain Feuillette, Christophe Bernicot (ST) and Jean-Francois Paillotin (CMP)
for design support, Astrid Tomada (SLAC), PacTech, and Hai Nguyen (Silitronics)
for chip assembly, Prof. Khuri-Yakub, Anshuman Bhuyan, Byung-Chul Lee, and
Ji-Hoon Jang for discussion and preparation of CMUT. This work was funded in
part by Stanfords Initiative on Rethinking Analog Design (RAD) and the C2S2
Focus Center, one of six research centers funded under the Focus Center Research
Program (FCRP), an SRC subsidiary.
References:
[1] A. Bhuyan, et al., 3D Volumetric Ultrasound Imaging with a 32x32 CMUT
Array Integrated with Front-End ICs Using Flip-Chip Bonding Technology, ISSCC,
pp. 396-397, Feb. 2013.
[2] C. Chen, et al., A Front-end ASIC with Receive Sub-Array Beamforming
Integrated with a 32x32 PZT Matrix Transducer for 3-D Transesophageal
Echocardiography, IEEE Symp. VLSI Circuits, pp. 38-39, June 2016.
[3] G. Gurun, et al., An Analog Integrated Circuit Beamformer for High-Frequency
Medical Ultrasound Imaging, IEEE TBioCAS, vol. 6, no. 5, pp. 454-467, Oct. 2012.
[4] J.-Y. Um, et al., An Analog-Digital-Hybrid Single-Chip RX Beamformer with
Non-Uniform Sampling for 2D-CMUT Ultrasound Imaging to Achieve Wide
Dynamic Range of Delay and Small Chip Area, ISSCC, pp. 426-427, Feb. 2014.
[5] C.-I. C. Nilson, et al., Distortion-Free Delta-Sigma Beamforming, IEEE Trans.
Ultrason., Ferroelect., Freq. Control, vol. 55, no. 8, pp. 1719-1728, 2008.
[6] Y. Lim, et al., A 100MS/s 10.5b 2.46mW Comparator-less Pipeline ADC Using
Self-Biased Ring Amplifiers, ISSCC, pp. 202-203, Feb. 2014.
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 ISSCC 2017 / February 8, 2017 / 3:45 PM

Figure 27.5.1: Block diagram of the implemented RX and pixel layout. Figure 27.5.2: Comparison of beamformer architectures.

Figure 27.5.3: Comparison of two beamforming options. Figure 27.5.4: RX front-end (contained in each pixel).

27

Figure 27.5.5: Block diagram of M (contained in each pixel) and SC

integrator half circuit. Figure 27.5.6: Photoacoustic imaging setup and results.

DIGEST OF TECHNICAL PAPERS 457

 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.5.7: Photo of chip assembly and RX die, along with a comparison to
the state of the art.

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.6
27.6 Single-Chip 3072ch 2D Array IC with RX Analog and
All-Digital TX Beamformer for 3D Ultrasound Imaging
Yusaku Katsube1, Shinya Kajiyama2, Takuma Nishimoto1,
Tatsuo Nakagawa2, Yasuyuki Okuma3, Yohei Nakamura2,
Takahide Terada2, Yutaka Igarashi1, Taizo Yamawaki2,
Toru Yazaki1, Yoshihiro Hayashi2, Kazuhiro Amino2,
Takuya Kaneko2, Hiroki Tanaka2
1
Hitachi, Yokohama, Japan
2
Hitachi, Kokubunji, Japan
3
Hitachi, Hatoyama, Japan
A diagnostic ultrasound (US) system transmits acoustic waves at several to tens
of MHz into the human body for clinical purposes and detects the reflected waves
to observe the internal organs without having a medical operation or radiation
exposure. The system is composed of a main unit and probe connected via coaxial
cables. The probe is very small because medical technicians laboriously grab and
manipulate it for a long time. To avoid image obscurity depending on medical
technicians, high-speed and high-resolution 3D/4D imaging is necessary. For this
reason, several thousands of lead bulk piezoelectric material transducers (TD)
need to be squeezed into the small probe. Since the number of cables is limited
to several hundreds, the probe needs to include beamforming functionality and a
2D array IC [1-6], which includes thousands of US transceivers.
Figure 27.6.1 shows a block diagram of the diagnostic US system and the
proposed 2D array IC, which includes 3,072 US transceivers. Since a TD pillar is
300300m2, each US transceiver size needs to be the same pitch. The TD is
connected to an IC via a low-temperature co-fired ceramic (LTCC) interposer to
alleviate fabrication difficulties. On the other side of the pillars, there is an acoustic
impedance matching layer and a lens. The 2D array IC bilaterally interfaces from
the 3,072-ch TD to the 128-ch coaxial cables. The 24 TD and US transceivers are
grouped to coherently execute transmitter and receiver US signal processing. The
main unit digitizes the signal to perform beamforming and image rendering.
The subarray block diagram is shown in Fig. 27.6.2. The transmitter is an all-
digital architecture, and is composed of a digital beamformer, a
switched-capacitor delayer (SCD), and a tunable amplitude 3-level pulser (TA3LP).
Therefore, it is free from waveform distortion and timing error caused by cable
propagation between the main unit and the probe. The pulser power consumption
is generally far less than that of linear amplifiers, but the pulsers constant
amplitude leads to limited image quality. TA3LP in this work has a built-in
amplitude control function, and the TX and RX chain share the SCD to squeeze
all the necessary blocks in a die. The TD TRX signal I/Os include zero-power-TRX-
isolation switches (ZTRSW) to protect subsequent blocks with ordinal rating
elements. Although conventional ZTRSW uses a zener diode as a floating switch
gate bias and inherently needs a lot of power, ZTRSW in this work only consumes
10W during RX mode using MOSFET active floating-gate bias topology. The next
stage is a programmable gain-and-input-impedance low-noise amplifier
(PGZLNA). PGZLNA boosts the weak signal to a reasonable level for the next
stage. The programmable input impedance is used to achieve >85dB dynamic
range. The charge-domain adders (CDADDs) perform, in the charge domain,
correlated-signal summation of 24 SCD outputs, and the CDADDs are placed in a
subarray without signal headroom concerns. If each SCD setting is ideal, and their
correlation is ideal, RX SNR is 24 times better. It means the noise level is 24
times lower. Therefore, the next stage block, which is the low-noise cable buffer
(LNCBUF), needs to be low noise and have heavy coaxial cable drivability. Finally,
the main unit digitizes the signal to perform beamforming and image rendering.
458 2017 IEEE International Solid-State Circuits Conference
Figure 27.6.3 shows the SCD circuit, which is composed of a capacitor ring
memory (CRM), an operational amplifier (OPA), and a CDADD. Since CRM
occupies most of the area, TX and RX chain share the CRM. While the RX chain
uses CRM as an analog memory, the TX chain uses them as a 2b D-latch. During
TX mode, the OPA operates as a comparator. The switches, being carefully placed
and deployed, achieve the optimal metamorphosis to avoid signal distortions. The
CRM, which is composed of 32 capacitors, controls the time differences of write
(charge) and read timing to make the necessary delay. The write and read signals
are non-overlapped 40MHz pulse trains and cover the 25-to-750ns delay range.
During RX mode, dynamically changing the focal points leads to fast image
rendering. For this reason, duplicated write pulse or doubling the read pulse width
can increase the delay time. Adversely doubling the write pulse width or skipping
read pulse can shorten it. Figure 27.6.4 shows the TA3LP circuits, which can
launch plus, zero, and minus level signals. The output stage takes on the source
follower push-pull topology (PP). PP consumes a lot of power only during the
pulse transition durations and alleviates the previous inverter (INV) stage bias
current and transistor sizes. The INV output has grounding switches to make zero
level (RZ: return to zero circuit). PP and INV will operate within a safe operating
area to avoid device destruction. Since TA3LP does not use feedback topology,
rise and fall time adjustment is necessary. As previously noted, TA3LP has a 256
level amplitude adjustment module to compete with a linear amplifier system and
cover many diagnostic modes necessary for the US system. The amplitude
transition can settle to <4.4s.
The 2D array IC is assembled and implemented in the probe and main unit with a
real-time rendering engine that is optimized and caters for the probe. The system
can capture 3D tissue images with several arbitrary 2D cutting planes within the
angle of view (AoV) of this system. Arbitrary 2D cutting plane images are easily
extracted from the full-volume 3D dataset. The System AoV is more than 9090,
and it can look over the whole human heart during echo-cardiography. Figure
27.6.5 shows the 2D and 3D image of a phantom (white ball: agar / black ball:
agar and graphite mixture) as an example. Figure 27.6.6 shows the performance
comparisons. Our work is only a 2D array IC that includes the RX analog, all-
digital TX beamformer, and related peripheral blocks. The silicon area occupies
0.09mm2/ch and consumes 0.7mW/ch during B-mode capture. Regardless of the
138Vpp US launch capability, 0.7mW/ch power consumption is also the lowest in
the table.
A die micrograph of the 2D array IC implemented in a 0.18m HV SOI CMOS
process is shown in Fig. 27.6.7. The total area is 417mm2 including the digital
beamformer and the other control and the interface circuits.
References:
[1] H.-Y. Tang, et al., Integrated ultrasonic system for measuring body-fat
composition, ISSCC, pp. 210-211, Feb. 2015.
[2] J.-Y. Um, et al., An Analog-Digital-Hybrid Single-Chip RX Beamformer with
Non-Uniform Sampling for 2D-CMUT Ultrasound Imaging to Achieve Wide
Dynamic Range of Delay and Small Chip Area, ISSCC, pp. 426-427, Feb. 2014.
[3] A. Bhuyan, et al., 3D Volumetric Ultrasound Imaging with a 3232 CMUT
Array Integrated with Front-end ICs Using Flip-chip Bonding Technology, ISSCC,
pp. 396-397, Feb. 2013.
[4] K. Chen, et al., "A Column-Row-Parallel ASIC Architecture for 3-D Portable
Medical Ultrasonic Imaging," IEEE JSSC, vol. 51, no. 3, pp. 738-751, Mar. 2016.
[5] K. Chen, et al., "Ultrasonic Imaging Transceiver Design for CMUT: A Three-
Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a
Noise-Optimized Receiver," IEEE JSSC, vol. 48, no. 11, pp. 2734-2745, Nov. 2013.
[6] C. Chen, et al., "A Front-end ASIC with Receive Sub-Array Beamforming
Integrated with a 32 x 32 PZT Matrix Transducer for 3-D Transesophageal
Echocardiography", IEEE Symp. VLSI Circuits, pp. 38-39, June 2016.
978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 4:15 PM

Figure 27.6.1: Block diagram of diagnostic ultrasound system with 3,072-ch 2D

array IC. Figure 27.6.2: Block diagram of 2D array IC.

Figure 27.6.3: Switched-capacitor delayer circuit (top). Timing chart of fixed Figure 27.6.4: Circuit diagram of tunable amplitude 3-level pulser and its
focus (bottom left) and dynamic focus (bottom right). control block.

27

Figure 27.6.5: Evaluated 3D image (top right) and 2D cutting plain images from
the full-volume 3D dataset (bottom right). Figure 27.6.6: Comparison table of ultrasound array IC.

DIGEST OF TECHNICAL PAPERS 459

 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.6.7: Die photograph.

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.7
27.7 A 30.5mm3 Fully Packaged Implantable Device with
Duplex Ultrasonic Data and Power Links Achieving
95kb/s with <10-4 BER at 8.5cm Depth
Ting Chia Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber,
Amin Arbabian
Stanford University, Stanford, CA
The next generation of implantable medical devices focuses on minimally invasive
miniaturized solutions that operate reliably at large depths, provide duplex
communication for closed-loop therapies, and enable multi-access for a network
of implants to gather information or provide systemic interventions. Using
ultrasound (US), power and data can be efficiently transferred through the body
as its wavelength at MHz is comparable to a mm-sized receiver, resulting in
improved focusing, coupling, and acoustic-to-electrical conversion efficiency.
Furthermore, thanks to the low propagation loss (~1dB/cm/MHz) and 7.2mW/mm2
safety limit, several mW of power is obtainable at the receiver, enabling high-
power, complicated functionalities.
While initial experiments using US for power transfer to implants have been
successful [1,2], there is still a significant need to have reliable uplink data
communication at depth. Other studies have worked on RF uplink [3,4] or
backscatter [2], which have limited depth and/or multi-access capability restricting
coordinated therapies throughout the body. We demonstrate a miniaturized fully
packaged implant that receives both US power and data and also transmits US
data for uplink. Figure 27.7.1 depicts the conceptual diagram of the system as
well as the block diagram of the implant. It consists of two transducers (US power
and data receiver (RX) and data transmitter (TX)), a discrete capacitor, and a
CMOS chip in TSMC 65nm GP technology, which includes power-management,
data and clock-recovery circuits, frequency generators, finite state machine,
pseudorandom binary sequence (PRBS), and the power amplifier (PA). Both RX
and TX are made from piezoelectric materials. The operating frequency of the
receiver is chosen to be ~1MHz for low propagation loss and mm-size as the
resonance of the receiver is inversely proportional to its thickness. Using clock
recovery and frequency generation circuitry, the carrier frequency of the output
data (fout) is ~2.6 of the input frequency (fin) to avoid self and external interference
from the high-power downlink and its harmonics.
Figure 27.7.2 illustrates the timing diagram during operation. The implant is
charged until the LDO voltage is established. The implant then listens for the data
input (falling edge) from the external source to generate a NOTCH and prepare
for uplink transmission. The Recovered CLK is obtained from fin. DATA CLK
divides Recovered CLK by 10; thus, the data rate is close to 100kb/s for fin ~1MHz
with OOK modulation, sufficient for a range of applications including pressure,
temperature, or neural recording. An on-chip 210 1 PRBS is used for data
generation. The next input falling edge stops the transmission. If sufficient energy
is retained on the storage capacitors, the process can be immediately restarted,
re-enabling uplink transmission.
The power-management circuits, which are shown in Figure 27.7.3, use a two-
path architecture. The main path includes an active full-wave rectifier for AC-DC
conversion, a charge pump to boost the generated voltage, and a low-dropout
regulator (LDO) regulating supply at 1V; the low-power auxiliary path sets up the
biasing, similar to what [1] presents. PMN-PT with dimension of 0.90.90.5mm3
is chosen for RX; it has a measured impedance of 900 and resonance of
0.95MHz as desired for impedance matching and low propagation loss. Chip
efficiency, defined as load power over power into rectifier, along with measured
voltage waveforms at four nodes are also plotted.
Figure 27.7.4 shows the frequency generator and the differential class-D PA
driving the TX. The frequency generator uses an open-loop architecture to ensure
fast settling and robust fout. In the setup phase, the frequency of a free-running
current-starved RO (fRO) is resolved with a 9b asynchronous counter controlled
460 2017 IEEE International Solid-State Circuits Conference
by COUNT. Five MSBs are stored in the registers, effectively dividing fRO by 16.
During transmission, a 5b asynchronous counter counts the RO cycles, which is
compared to the stored value; if they match, a pulse is sent to a 3b Johnson
counter, dividing the frequency of the pulse train by six to generate fout. An
example calculation for an fRO of 250MHz and fin of 1MHz is shown in gray text.
This method is insensitive to process and temperature variation. In addition, a
Widlar bias is used so that fRO is stable for small perturbations of supply. fRO is
recounted in the setup phase for each transmission; and fin and fout have a stepped
relationship because of the open-loop operation, leading to a more reliable system.
Measured fout across different LDO voltages shows that it stays constant for LDO
voltages from 0.84 to 1.0V. As OOK modulation is used, the generator is disabled
when DATA = 0 and the output of the PA is cycled and pulled to GND to save
energy; for DATA = 1, the generator can start up and settle in <1s and consumes
32W during runtime.
Taking into account the loss, the transmitted output power needs to be at least
100W for successful transmission at large tissue depth. Therefore, the desired
impedance of the TX driven differentially with 1V supply should be <5k around
resonance. Using PZT4, the TX is sized 0.550.550.4mm3, giving a resonance
near 2.5MHz with impedance ~4k as shown in Fig. 27.7.5. Simulated PA
efficiency is 86%, delivering a peak power of 125W to the TX. A fully wireless
end-to-end test with external power/data transmitter and data receiver in castor
oil, commonly used as a tissue phantom with loss ~0.6dB/cm/MHz, is performed.
The carrier frequency of the received voltage is 2.45MHz for fin of 950kHz. The
received voltage waveform for an 8.5cm link after filtering out the harmonics of
fin is also plotted; the interference signals are mostly due to multipath reflections
and can be mitigated. Bit error rate (BER) is calculated by sending the on-chip
PRBS 10 times; no errors are found for both 3.5 and 8.5cm links, achieving a
BER of <10-4 for a data rate of 95kb/s. The average signal-to-interference ratio
(SIR) is computed to be 27.4 and 15.8dB respectively; SIR can be further
improved with better alignment and larger receiver gain.
Figure 27.7.6 shows the fully packaged implants and their cross-sections along
with the end-to-end blind test through 6cm of animal tissue with no precise
alignment; the spectrum of the received modulated data is shown. This confirms
the end-to-end demonstration of an implant system capable of power/data transfer
through >5cm of tissue. With access to an external beamformer, based on the
measured received voltages we achieve >10cm depth in the body. Figure 27.7.7
shows the die photo and comparison to implantable devices using various
wireless powering and communication modalities with full system measurements.
Based on the table in Fig. 27.7.7, our implant is at least 2.5 smaller and operates
2 deeper (in tissue) than comparable US-powered implants and 10 smaller and
10 deeper than inductively powered implants.
Acknowledgement:
The authors thank Prof. Khuri-Yakub for valuable discussions. The chip fabrication
was made possible by the TSMC University Shuttle Program. We also
acknowledge Mentor Graphics for the use of the Analog FastSPICE (AFS)
Platform. This material is based upon work supported by the DARPA YFA and the
NSF CAREER award ECCS-1454107.
References:
[1] J. Charthad, et al., A mm-Sized Implantable Medical Device (IMD) With
Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link, IEEE JSSC, vol.
50, no. 6, pp. 1741-1753, Aug. 2015.
[2] S. Ozeri and D. Shmilovitz, Simultaneous Backward Data Transmission and
Power Harvesting in an Ultrasonic Transcutaneous Energy Transfer Link
Employing Acoustically Dependent Electric Impedance Modulation, Ultrasonics,
vol. 54, no. 7, pp. 1929-1937, Sept. 2014.
[3] A. Mirbozorgi, et al., A Single-Chip Full-Duplex High Speed Transceiver for
Multi-Site Stimulating and Recording Neural Implants, IEEE TBioCAS, vol. 10,
no. 3, pp. 643-653, June 2016.
[4] G. Yilmaz and C. Dehollain, "An implantable system for intracranial neural
recording applications," IEEE BioCAS, pp. 408-411, Oct. 2014.
978-1-5090-3758-2/17/$31.00 2017 IEEE
 ISSCC 2017 / February 8, 2017 / 4:45 PM

Figure 27.7.1: Conceptual diagram of the wireless ultrasonic powering and

communication system and the block diagram of the implant. Figure 27.7.2: Timing diagram during operation.

Figure 27.7.4: Frequency generator and measured fout versus LDO voltage and
Figure 27.7.3: Diagram and measurement of power-management circuits. fin.

27

Figure 27.7.5: Measured impedance of the US TX and the measured received Figure 27.7.6: Demonstration of US wireless power and data communication
voltage waveform in castor oil (ultrasound tissue phantom). through 6cm animal tissue with packaged implant.

DIGEST OF TECHNICAL PAPERS 461

 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.7.7: Die photo and comparisons of implantable devices with wireless
powering and data communication.

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE

ISSCC 2017 / SESSION 27 / BIOMEDICAL CIRCUITS / 27.8
27.8 Fully Integrated Optical Spectrometer with
500-to-830nm Range in 65nm CMOS
Lingyu Hong, Kaushik Sengupta
Princeton University, Princeton, NJ
Next-generation IoT systems are expected to be enabled by compact, low-cost,
low-power, smart sensing devices that provide a wealth of information to build
new applications and capabilities. Among sensing modalities, optical spectrometry
is one of the rapidly growing areas of interest due to its wide range of applications
from environment monitoring, industrial and home applications to healthcare [1-
3]. As shown in Fig. 27.8.1, current optical spectrometers are large and bulky
with non-integrated components that limit their application potential. In this paper,
we present a fully integrated CMOS-based optical spectrometer in a 65nm bulk
process that requires no external optical components. The spectrometer achieves
nearly 10nm resolution and 1.4nm accuracy in peak prediction of continuous-
wave (CW) excitations between 500 and 830nm.
The principle of operation of a classical optical spectrometer relies on light incident
on a grating structure getting diffracted, focused and sensed by a photodetector
array, which enables us to correlate the measured voltages of the photodetectors
to the incident optical spectrum (Fig. 27.8.1). The architecture of the presented
CMOS optical spectrometer is shown in Fig. 27.8.1. The incident light is delivered
through an optical fiber into the CMOS chip through a 3m-sized opening aperture
on the 7th metal layer (M7) and is converted into a propagating mode in metal-
insulator-metal (MIM) waveguides between M4-M7 [5,6]. The propagating wave
is incident onto a concave grating structure (M4-M7) that is designed to disperse
the incident mode and create a wavelength-dependent focal plane 400m away
within the MIM waveguides. The spatial distribution is sensed by deflecting the
focused light with a metal shield into an array of photodetectors underneath (Fig.
27.8.1). The signal is then processed on-chip with low-noise circuitry and digitized
off-chip for analysis. The entire structure measures 650540m2.
The layout of the dispersive optical elements, the MIM waveguide, and the
constituent circuits is shown in Fig. 27.8.2. It shows focusing of the optical waves
of different wavelengths within the chip on the focal plane. The resolution is
determined by the numerical aperture of the grating structure and the slit aperture
size at the fiber input, and is simulated to be 5nm. Unlike free-space propagation
in a classical spectrometer, mode propagation within the copper-metal
waveguides at optical frequencies can be very complex and the interaction with
the grating structure on-chip can be dependent on the mode profiles in addition
to wavelength. To remove this extra dependence, the MIM waveguides are
designed to suppress higher-order modes, allowing only the lowest fundamental
mode to interact with the grating structure. Figure 27.8.2 shows the attenuation
of the higher-order modes by >20dB relative to the fundamental over the wave
travel distance across the spectrum.
Figure 27.8.3 shows the array architecture where the photodetector arrangement
follows the curvature of the focal plane. The array of 60 detectors is realized with
n-well/ p-sub junctions, and the signals are integrated by capacitive TIAs to
remove the dependence on the diode capacitance in this non-custom imager
process. To partially suppress the effect of dark currents, each signal is sensed
differentially with a reference diode and a differential TIA which suppresses
common-mode perturbations. It is also important to ensure that the detectors are
accommodated within the 4m spot size of the optical focus points so that the
resolution is not degraded by the photodiode layout (Fig. 27.8.3). Therefore, the
grating structure and the array architecture need to be co-designed for optimal
performance and resolution. As shown in Fig. 27.8.3, the signals are multiplexed
and finally processed through a correlated double sampling architecture to remove
offsets and low-frequency drifts and ultimately digitized by a 16b ADC off-chip
and analyzed.
462 2017 IEEE International Solid-State Circuits Conference
Stray light scattering can cause unintended errors in spectral estimation, which
are typically eliminated by elaborate optical shielding. For a chip-scale
spectrometer, such external effects can be minimized by proper packaging, while
inside the chip, the propagation of light in undesired directions can be shielded
with metal optical walls (Fig. 27.8.2). In this work, we show spectral estimation
in the unpackaged die (Fig. 27.8.7) not completely shielded from external
scattered light. The spectrometer is first characterized against CW excitations with
a wide-band source and a tunable narrow-band filter (~10nm) realized with a linear
variable filter on a motorized translational stage (Fig. 27.8.4). Over the range of
measured wavelengths, the array response creates a responsivity matrix defined
as Ropt R N M, where N is the number of diodes and M is the number of
wavelengths of characterization. When a spectrum approximated by Sinc R M 1
is incident on the chip, the array response is given by Vop = Ropt Sinc + Vn, where
Vn R N 1 is the random noise voltages of the outputs. Given Vop and measured
responsivity Ropt , we estimate the incident spectrum Sest by the minimizing the
following:
 .
The regularization parameter allows for robust estimation in presence of noise
by eliminating solutions with undesirable spikes due to the inverse estimation
process [4]. The measured responsivity matrix which is a one-time
characterization is shown in Fig. 27.8.4 by removing the average spectral
responses of the sensors. The spectral dependence of the spatial distribution of
intensity is evident from the figure. The presence of scattering of stray light creates
the non-focus profile, but the wavelength-dependent variation of the spatial
distribution still allows us to achieve spectral estimation across the range.
The chip is tested with CW excitations of light and Fig. 27.8.5 shows the spectral
estimation from the measured responses showing robust estimation with
regularization with only 40nW estimated to be entering the chip. When the chip
is excited at a wavelength between the characterization wavelengths, the
reconstruction shows two peaks near the center wavelength. The estimation of
the peak can be progressively narrowed reaching down to 1.4nm when the
estimation is averaged over five responsivity matrices with 1nm spacing. The chip
is then tested with excitation of varying spectra and the estimation reasonably
matches the measured spectra without optical packaging and external shielding
(Fig. 27.8.6). The normalized RMS error of reconstructed spectra given by:
was measured to be around 15 to 20%. The chip is powered by a 3V supply and
dissipates 30mW of total DC power. The chip-scale spectrometer shows the
feasibility of integrating complex optical systems-on-chip for various applications
in sensing by exploiting metal-optical structures in CMOS through a co-design
approach.
References:
[1] B. Redding, et al., Compact Spectrometer Based on a Disordered Photonic
Chip, Nature Photonics, vol. 7, pp. 746-751, Sept. 2013,
[2] X. Ma, et al., "CMOS-Compatible Integrated Spectrometer Based on Echelle
Diffraction Grating and MSM Photodetector Array," IEEE Photon. J., vol. 5, no. 2,
Apr. 2013.
[3] Z. Shi, et al., Dispersive Element Based on Grating and Tunable FabryPerot
Filter in Miniature Spectrometer, Appl. Opt., vol. 53, pp. 76-81, 2014.
[4] X. Wu and K. Sengupta, "A 40-to-330GHz Synthesizer-free THz Spectroscope-
on-chip Exploiting Electromagnetic Scattering," ISSCC, pp. 428-429, Feb. 2016.
[5] L. Hong, et al., A Fully Integrated CMOS Fluorescence Biosensor with On-
chip Nanophotonic Filter, IEEE Symp. VLSI Circuits, pp. C206-C207, 2015.
[6] X. Lu, et al., "An Integrated Optical Physically Unclonable Function Using
Process-Sensitive Sub-Wavelength Photonic Crystals in 65nm CMOS," ISSCC,
2017.
978-1-5090-3758-2/17/$31.00 2017 IEEE

Figure 27.8.1: (a) Traditional optical spectrometer (b) and (c) principle of
operation, light-path, the grating and detection structure in the CMOS integrated
spectrometer.
Figure 27.8.3: Architecture and circuit components. Spatial distribution of light
intensity is detected by array of 60 photodetectors whose outputs are integrated
differentially through CTIAs, and multiplexed before processing through CDS.
Measured analog output waveforms for sequential addressing of pixels during
one integration time.
Figure 27.8.5: (a) Measured spectral estimation with regularization with CW-
illuminated chip at characterization frequencies. (b) Measured spectral
estimation when illuminated at between characterization wavelengths. (c)
Progressive narrowing of peak estimation by averaging with 5 responsivity
matrices shifted by 1nm (d) Averaging narrows peak estimation accuracy to
1.4nm.
ISSCC 2017 / February 8, 2017 / 5:00 PM
Figure 27.8.2: (a) Integrated grating structure layout, MIM waveguide, and
circuitry. (b) Optical simulation: focusing of different wavelengths along focus
curvature. (c,d) EM simulations showing mode profiles of 0th and 1st order,
showing higher losses for the higher-order modes that are eliminated. (e) Loss
of the first 2 modes showing >20dB rejection of all higher-order modes
compared to the fundamental.
Figure 27.8.4: (a) Spectrometer responsivity characterization set-up with
broadband source and linear variable narrow-band filter between 500 and
830nm. (b) Measured spectral responsivity shown by pixel outputs against
wavelength by removing average response. Presence of scattering of stray light
creates non-focus profile, but wavelength-dependent variation of spatial
distribution still allows spectral estimation across range.
27
Figure 27.8.6: (a-c). Measured spectral estimation when excited with
broadband optical sources showing reasonably good agreement with incident
spectra. (d) Normalized errors in spectral estimation of the three test spectra.
DIGEST OF TECHNICAL PAPERS 463
 ISSCC 2017 PAPER CONTINUATIONS

Figure 27.8.7: Chip photo and the measurement set-up.

2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 2017 IEEE