DAC Low Layer

Analog-to-digital converter (ADC)

Low Layer use case example

Hardware : Discovery stm32f4, SoC Stm32f40vg

Reference : RM0090 reference manual (DM00031020.pdf)

Contact : Mustapha.hamdi@insat.rnu.tn
Institut national des sciences appliques et de technologie, Tunisia
ADC Low Layer

ADC functional description

Reference : RM0090 reference manual (DM00031020.pdf page 391)

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

The STM32F407VG microcontroller has several ADC modes and

inputs, please refer to STM32s ADC modes and their applications
(AN3116 Application note)

Single-channel continuous conversion mode

For our example we choose to use Adc in this mode.
The single-channel continuous conversion mode converts a single channel
continuously and indefinitely in regular channel conversion.
The continuous mode feature allows the ADC to work in the background. The
ADC converts the channels continuously without any intervention from the
CPU. Additionally, the DMA can be used in circular mode, thus reducing the
CPU load,

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

ADC registers ADCx->SR = ; // Status Register

ADCx->CR1 = ; // Control Register 1
ADCx->CR2 = ; // Control Register 2
ADCx->SMPR1 = ; // SaMPle time Register 1
ADCx->SMPR2 = ; // SaMPle time Register 2
ADCx->JOFR1 = ; // inJecter channel data OFset Register 1
ADCx->JOFR2 = ; // inJecter channel data OFset Register 2
ADCx->JOFR3 = ; // inJecter channel data OFset Register 3
ADCx->JOFR4 = ; // inJecter channel data OFset Register 4
ADCx->HTR = ; // watchdog Higher Threshold Register
ADCx->LTR = ; // watchdog Lower Threshold Register
ADCx->SQR1 = ; // regular SeQuence Register 1
ADCx->SQR2 = ; // regular SeQuence Register 2
ADCx->SQR3 = ; // regular SeQuence Register 3
ADCx->JSQR = ; // inJected SeQuence Register
ADCx->JDR1 = ; // inJected Data Register 1
ADCx->JDR2 = ; // inJected Data Register 2
ADCx->JDR3 = ; // inJected Data Register 3
ADCx->JDR4 = ; // inJected Data Register 4
ADCx->DR = ; // Data Register
ADC->CSR = ; // Common Status Register
ADC->CCR = ; // Common Control Register
ADC->CDR = ; // Common regular Data Register for dual and triple mode

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

Case Study stm32f4 ADC DAC in the loop :

NVIC_EnableIRQ(ADC_IRQn)

Analog input NVIC

output
ADC DAC
M4
42 KHz

Timer 3 if the Shannon Nyquist criterion is not

respected
APB2 Clock 84 MHz
200 ns

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer ADC registers

Clock for ADCx APB2ENR

Clock for GPIOx and Mode AHB1ENR, MODER

Regular simultaneous mode only CCR

Enable ADC Interrupt for EOC CR1

ADCx ON, use TIM3, TRG0 as SC source,

CR2
Enable external SC

use PA01 as input SQR3

DR
Pin 5, 4 pin0
GPIO A

Contact : Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

ADC1->SQ1 |= 0x01 ; for PA1, 02 for PA2, 03 for PA3

Reference : RM0090 reference manual (DM00031020.pdf Page 426

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

ADCx->CR1 |= (1<<5); //for PA1, 02 for PA2, 03 for PA3

Reference : RM0090 reference manual (DM00031020.pdf Page 419

Page 88
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ADC Low Layer

ADC->CCR |= (1<<1)+(1<<2); // MULIT : 00110: Regular simultaneous

mode only

Reference : RM0090 reference manual (DM00031020.pdf Page 419

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

ADCx->CR2 |= 0x01 ; //Converter ON

ADCx->CR2 |= (8<<24); //use TIM3, TRG0 as SC source
ADCx->CR2 |= |= (1<<28); // Enable external SC, rising edge

Reference : RM0090 reference manual (DM00031020.pdf Page 422

Mustapha.hamdi@insat.rnu.tn
ADC Low Layer

Interruption takes about 200 ns

TIM3->ARR = 2000;// ~ 42 KHz of CPU time
TIM3->ARR = 2000;// ~42 KHz

TIM3->ARR = 6000;
// ~ 14 KHz

Mustapha.hamdi@insat.rnu.tn