Professional Documents
Culture Documents
Features Description
Single or Dual Resistor Network options The MCP41XX and MCP42XX devices offer a wide
Potentiometer or Rheostat configuration options range of product offerings using an SPI interface. This
Resistor Network Resolution family of devices support 7-bit and 8-bit resistor
- 7-bit: 128 Resistors (129 Steps) networks, Non-Volatile memory configurations, and
- 8-bit: 256 Resistors (257 Steps) Potentiometer and Rheostat pinouts.
RAB Resistances options of: WiperLock Technology allows application-specific
- 5 k calibration settings to be secured in the EEPROM.
- 10 k
- 50 k
- 100 k
Package Types
Zero-Scale to Full-Scale Wiper operation MCP41X1 MCP41X2
Low Wiper Resistance: 75 (typ.) Single Potentiometer Single Rheostat
Low Tempco: CS 1 8 VDD CS 1 8 VDD
- Absolute (Rheostat): 50 ppm typical SCK 2 7 P0B SCK 2 7 SDO
(0C to 70C) SDI/SDO 3 6 P0W SDI 3 6 P0B
- Ratiometric (Potentiometer): 15 ppm typical VSS 4 5 P0A VSS 4 5 P0W
Non-volatile Memory PDIP, SOIC, MSOP, PDIP, SOIC, MSOP,
- Automatic Recall of Saved Wiper Setting 3x3 DFN 3x3 DFN
- WiperLock Technology MCP42X1 Dual Potentiometers
SPI serial interface (10 Mhz, modes 0,0 & 1,1)
- High-Speed Read/Writes to wiper registers CS 1 14 VDD
SCK 2 13 SDO
- Read/Write to Data EEPROM registers SDI 3 12 SHDN
- Serially enabled EEPROM write protect VSS 4 11 WP
- SDI/SDO multiplexing (MCP41X1 only) P1B 5 10 P0B
Resistor Network Terminal Disconnect Feature P1W 6 9 P0W
P1A 7 8 P0A
via:
- Shutdown pin (SHDN) PDIP, SOIC, TSSOP
- Terminal Control (TCON) Register
SHDN
SDO
VDD
MSOP, DFN
Device Features
Technology
Resistance (typical)
POR Wiper
WiperLock
# of Steps
# of POTs
Memory
Interface
Setting
VDD
Control
Type
Wiper Wiper
Device Operating
Configuration RAB Options (k) - RW Range (2)
()
MCP4131 (3) 1 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V
MCP4132 (3) 1 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V
MCP4141 1 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V
MCP4142 1 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V
MCP4151 (3) 1 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V
MCP4152 (3) 1 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V
MCP4161 1 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V
MCP4162 1 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V
MCP4231 (3) 2 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V
MCP4232 (3) 2 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V
MCP4241 2 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V
MCP4242 2 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V
MCP4251 (3) 2 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V
MCP4252 (3) 2 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V
MCP4261 2 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V
MCP4262 2 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V
Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
3: Please check Microchip web site for device release and availability
VIHH
VIH VIH
CS VIL
84
70 72
SCK
83
71
79 78
80
75, 76 77
74
73
VIHH
VIH VIH
82
CS VIL
84
70
SCK
83
80
71 72
75, 76 77
73
SDI
MSb IN BIT6 - - - -1 LSb IN
74
RCS (kOhms)
400 5.5V 25C ICS
150 200
ICS (A)
350 5.5V 85C
5.5V 125C 0
300
250 100 -200
200 -400
150
100 50 -600
RCS -800
50
0 0 -1000
0.00 2.00 4.00 6.00 8.00 10.00 12.00 2 3 4 5 6 7 8 9 10
fSCK (MHz) VCS (V)
FIGURE 2-1: Device Current (IDD) vs. SPI FIGURE 2-4: CS Pull-up/Pull-down
Frequency (fSCK) and Ambient Temperature Resistance (RCS) and Current (ICS) vs. CS Input
(VDD = 2.7V and 5.5V). Voltage (VCS) (VDD = 5.5V).
3.0 12
Standby Current (Istby) (A)
2.5 10
CS V PP Threshold (V)
5.5V Entry
5.5V 2.7V Entry
2.0 8
1.0 4
2.7V 2.7V Exit
0.5 2
0.0 0
-40 25 85 125 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C) Ambient Temperature (C)
FIGURE 2-2: Device Current (ISHDN) and FIGURE 2-5: CS High Input Entry/Exit
VDD. (CS = VDD) vs. Ambient Temperature. Threshold vs. Ambient Temperature and VDD.
900.0
EE Write Current (Iwrite) (A)
800.0
700.0
600.0
5.5V
500.0
400.0
300.0
-40 25 85 125
Ambient Temperature (C)
Wiper Resistance (R W)
-40C DNL 25C DNL 85C DNL 125C DNL
Wiper Resistance (R W)
260 -40C DNL 25C DNL 85C DNL 125C DNL 0.2
INL 220 INL
220 4
DNL
Error (LSb)
0.1
Error (LSb)
(ohms)
(ohms)
180 180
0
140 140 2
RW
RW -0.1
100 100
125C 0
60 85C -0.2 60 -40C
25C 25C DNL
-40C 125C 85C
20 -0.3 20 -2
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-6: 5 k Pot Mode RW (), FIGURE 2-9: 5 k Rheo Mode RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V). Ambient Temperature (VDD = 5.5V).
Wiper Resistance (R W)
100
-40C DNL 25C DNL 85C DNL 125C DNL 0.2 100
-40C DNL 25C DNL 85C DNL 125C DNL
0.75
DNL INL INL
0.1
Error (LSb)
Error (LSb)
80 80 0.25
(ohms)
(ohms)
0
60 60 -0.25
-0.1
DNL
40 -40C 25C RW -0.2 40 -40C -0.75
85C 85C 25C RW
125C 125C
20 -0.3 20 -1.25
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-7: 5 k Pot Mode RW (), FIGURE 2-10: 5 k Rheo Mode RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V). Ambient Temperature (VDD = 3.0V).
5300 6000
AB)
5250 5000
Nominal Resistance (R
2.7V 4000
RWB (Ohms)
5200
(Ohms)
3000
5150
2000 -40C
5100 25C
1000 85C
5.5V
125C
5050 0
-40 0 40 80 120 0 32 64 96 128 160 192 224 256
Ambient Temperature (C) Wiper Setting (decimal)
Wiper Resistance (R W)
-40C DNL 25C DNL 85C DNL 125C DNL 0.2 -40C DNL 25C DNL 85C DNL 125C DNL
100 100
0.5
DNL INL 0.1 INL
Error (LSb)
Error (LSb)
80 80
(ohms)
(ohms)
0 0
60 60
-0.1
DNL -0.5
40 25C -40C -0.2 40 85C 25C -40C RW
RW 125C
125C 85C
20 -0.3 20 -1
0 25 50 75 100 125 150 175 200 225 250 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-17: 10 k Pot Mode RW (), FIGURE 2-20: 10 k Rheo Mode RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V). Ambient Temperature (VDD = 5.5V).
Wiper Resistance (R W)
-40C DNL 25C DNL 85C DNL 125C DNL
Wiper Resistance (R W)
260 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 3
INL
220 INL
220
DNL 2
Error (LSb)
0.1
Error (LSb)
(ohms)
(ohms)
180 180
0 1
140 140
-0.1 0
100 RW 100
DNL RW
60 -40C -0.2 60 -40C -1
25C
125C 85C 125C 85C 25C
20 -0.3 20 -2
0 32 64 96 128 160 192 224 256 0 25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-18: 10 k Pot Mode RW (), FIGURE 2-21: 10 k Rheo Mode RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V). Ambient Temperature (VDD = 3.0V).
10250 12000
AB)
10000
10200
Nominal Resistance (R
8000
RWB (Ohms)
10150
(Ohms)
2.7V
6000
10100
4000 -40C
5.5V
25C
10050
2000 85C
125C
10000 0
-40 0 40 80 120 0 32 64 96 128 160 192 224 256
Ambient Temperature (C) Wiper Setting (decimal)
Wiper Resistance (R W)
-40C DNL 25C DNL 85C DNL 125C DNL 0.2 -40C DNL 25C DNL 85C DNL 125C DNL 0.2
100 100
INL
INL
DNL 0.1 DNL 0.1
Error (LSb)
Error (LSb)
80 80
(ohms)
(ohms)
0 0
60 60
-0.1 -0.1
40 -40C 40 -40C RW
25C RW -0.2 85C 25C -0.2
125C
125C 85C
20 -0.3 20 -0.3
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-27: 50 k Pot Mode RW (), FIGURE 2-30: 50 k Rheo Mode RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V). Ambient Temperature (VDD = 5.5V).
Wiper Resistance (R W)
-40C INL 25C INL 85C INL 125C INL 260 -40C DNL 25C DNL 85C DNL 125C DNL 0.75
Wiper Resistance (R W)
260 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 INL
0.5
220 INL 220
DNL DNL
Error (LSb)
0.1
Error (LSb)
(ohms) 0.25
(ohms)
180 180
0 0
140 140
-0.25
-0.1 RW
100 RW 100
-0.5
-0.2 -40C
60 -40C 60 -0.75
125C 85C 25C 125C 85C 25C
20 -0.3 20 -1
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-28: 50 k Pot Mode RW (), FIGURE 2-31: 50 k Rheo Mode RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V). Ambient Temperature (VDD = 3.0V).
50800 60000
AB)
50600 50000
Nominal Resistance (R
50400
40000
RWB (Ohms)
(Ohms)
50200
2.7V 30000
50000
5.5V 20000 -40C
49800
25C
49600 10000 85C
125C
49400 0
-40 0 40 80 120 0 32 64 96 128 160 192 224 256
Ambient Temperature (C) Wiper Setting (decimal)
Wiper Resistance (R W)
-40C DNL 25C DNL 85C DNL 125C DNL -40C DNL 25C DNL 85C DNL 125C DNL 0.2
100 100 INL
0.1
INL
0.1
Error (LSb)
Error (LSb)
DNL DNL
80 80
(ohms)
(ohms)
0 0
60 60
-0.1
-0.1
40 25C -40C
40 -40C RW -0.2
RW
125C 85C 25C
125C 85C
20 -0.2 20 -0.3
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-37: 100 k Pot Mode RW (), FIGURE 2-40: 100 k Rheo Mode RW
INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V). Ambient Temperature (VDD = 5.5V).
Error (LSb)
Error (LSb)
0.05 (ohms)
(ohms)
180 180
0 0
140 140
-0.05 -0.2
RW
100 RW 100
-0.1
60 -40C 60 -40C -0.4
-0.15
125C 85C 25C 125C 85C 25C
20 -0.2 20 -0.6
0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-38: 100 k Pot Mode RW (), FIGURE 2-41: 100 k Rheo Mode RW
INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V). Ambient Temperature (VDD = 3.0V).
101500 120000
AB)
100000
101000
Nominal Resistance (R
Rwb (Ohms)
80000
100500
(Ohms)
2.7V
60000
100000
40000 -40C
5.5V 25C
99500 20000 85C
125C
99000 0
-40 0 40 80 120 0 32 64 96 128 160 192 224 256
Ambient Temperature (C) Wiper Setting (decimal)
FIGURE 2-39: 100 k Nominal FIGURE 2-42: 100 k RWB () vs. Wiper
Resistance () vs. Ambient Temperature and Setting and Ambient Temperature.
VDD .
0.12
0.1
0.09 0.1
0.08
0.07 0.08 5.5V
0.06 5.5V
%
0.06
%
0.05
0.04
0.03 3.0V 0.04
0.02
0.02 3.0V
0.01
0 0
-40 0 40 80 120 -40 0 40 80 120
Temperature (C) Temperature (C)
0.04 0.05
0.03 0.04
0.02 0.03
5.5V 5.5V
0.01 0.02
%
0
%
0.01
-0.01 0 3.0V
3.0V
-0.02 -0.01
-0.03 -0.02
-0.04 -0.03
-40 0 40 80 120 -40 10 60 110
Temperature (C) Temperature (C)
2.4 0
2.2 -5
5.5V -10
2 2.7V
-15
IOH (mA)
VIH (V)
1.8 -20
5.5V
1.6 -25
-30
1.4
2.7V -35
1.2 -40
1 -45
-40 0 40 80 120 -40 0 40 80 120
Temperature (C) Temperature (C)
FIGURE 2-51: VIH (SDI, SCK, CS, WP, and FIGURE 2-53: IOH (SDO) vs. VDD and
SHDN) vs. VDD and Temperature. Temperature.
1.4 50
1.3 45
5.5V
5.5V 40
1.2
35
1.1
IOL (mA)
30
VIL (V)
1 25
0.9 20
2.7V
15
0.8 2.7V
10
0.7 5
0.6 0
-40 0 40 80 120 -40 0 40 80 120
Temperature (C) Temperature (C)
FIGURE 2-52: VIL (SDI, SCK, CS, WP, and FIGURE 2-54: IOL (SDO) vs. VDD and
SHDN) vs. VDD and Temperature. Temperature.
4.2
+5V
4.0
VIN A
3.8 W VOUT
+
tWC (ms)
3.6
B -
3.4 Offset
GND
3.2
2.5V DC
3.0
-40 0 40 80 120
Temperature (C)
FIGURE 2-55: Nominal EEPROM Write FIGURE 2-58: -3 db Gain vs. Frequency
Cycle Time vs. VDD and Temperature. Test.
1.2
1
5.5V
0.8
VDD (V)
0.6 2.7V
0.4
0.2
0
-40 0 40 80 120
Temperature (C)
15.0
14.5
5.5V
14.0
fsck (MHz)
13.5 2.7V
13.0
12.5
12.0
-40 0 40 80 120
Temperature (C)
WiperLock
Default POR
Resistance
RAB Value
Status Register
Typical
Code
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
2: These bits do not affect the wiper register values.
Note 1: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
2: These bits do not affect the wiper register values.
W
R AB
1 1 R S = -------------
- 7-bit Device
( 128 )
(1) (01h) (01h)
RS RW
0 0
(1) (00h) (00h)
RW
Analog Mux
B
Note 1: The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B,
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 k)
compared to larger resistance devices
(100.0 k).
W
SHDN (from pin)
To Pot x Hardware
RxHW Shutdown Control
(from TCON register)
B
FIGURE 5-2: Hardware Shutdown FIGURE 5-3: RxHW bit and SHDN pin
Resistor Network Configuration. Interaction.
SCK SCK
I/O (1) CS
SDO
I/O SCK
(SCK)
I/O (1) CS
Note 1: If High voltage commands are desired, some type of external circuitry needs to be
implemented.
smart pull-up
SDI/SDO
SDI
Open
drain
Control SDO
Logic
FIGURE 6-2: Serial I/O Mux Block
Diagram.
Volatile SDI, SDO 10 MHz 10 MHz When the CS pin returns to the inactive state (VIH) the
SPI module resets (including the address pointer).
Memory SDI/SDO 250 kHz (4) 10 MHz
(1) While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
Note 1: MCP41X1 devices only interface to other SPI devices using the same SDI,
2: Non-Volatile memory does not support SDO, and SCK signals.
the Increment or Decrement command. The CS pin has an internal pull-up resistor. The resistor
3: After a Write command, the internal write is disabled when the voltage on the CS pin is at the VIL
cycle must complete before the next SPI level. This means that when the CS pin is not driven,
command is received. the internal pull-up resistor will pull this signal to the VIH
4: This is the maximum clock frequency level. When the CS pin is driven low (VIL), the resis-
without an external pull-up resistor. tance becomes very large to reduce the device current
consumption.
The high voltage capability of the CS pin allows High
Voltage commands. High Voltage commands allow the
devices WiperLock Technology and write protect
features to be enabled and disabled.
VIH VIHH
CS
VIL
SCK
Write to
SSPBUF
CMDERR bit
SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Input
Sample
FIGURE 6-3: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
VIHH
VIH
CS
VIL
SCK
Write to
SSPBUF
CMDERR bit
SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Input
Sample
FIGURE 6-4: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
VIHH
VIH
CS
VIL
SCK
Write to
SSPBUF
CMDERR bit
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Input
Sample
Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven
FIGURE 6-5: 16-Bit Read Command for Devices with SDI/SDO multiplexed -
SPI Waveform (Mode 1,1).
VIHH
VIH
CS
VIL
SCK
Write to
SSPBUF
CMDERR bit
X D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Input
Sample
Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven
FIGURE 6-6: 16-Bit Read Command for Devices with SDI/SDO multiplexed -
SPI Waveform (Mode 0,0).
VIHH
VIH
CS
VIL
SCK
Write to
SSPBUF
CMDERR bit
1 = Valid Command/Address
0 = Invalid Command/Address
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Input
Sample
FIGURE 6-7: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock
Technology) - SPI Waveform with PIC MCU (Mode 1,1).
VIHH
VIH
CS VIL
SCK
Write to
SSPBUF
CMDERR bit
1 = Valid Command/Address
0 = Invalid Command/Address
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Input
Sample
FIGURE 6-8: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock
Technology) - SPI Waveform with PIC MCU (Mode 0,0).
A A A A C C D D A A A A C C D D D D D D D D D D Command
D D D D 1 0 9 8 D D D D 1 0 9 8 7 6 5 4 3 2 1 0 Bits
3 2 1 0 3 2 1 0 CC
1 0
Memory Data Memory Data 0 0 = Write Data
Address Bits Address Bits 0 1 = INCR
Command Command 1 0 = DECR
Bits Bits 1 1 = Read Data
A A A A 0 0 D D D D D D D D D D
SDI D D D D 9 8 7 6 5 4 3 2 1 0
3 2 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid Address/Command combination
SDO
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid Address/Command combination (1)
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
A A A A 0 0 D D D D D D D D D D
SDI D D D D 9 8 7 6 5 4 3 2 1 0
3 2 1 0
SDO 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1 1
A A A A 0 0 D D D D D D D D D D
D D D D 9 8 7 6 5 4 3 2 1 0
3 2 1 0
1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1 1
A A A A 0 0 D D D D D D D D D D
D D D D 9 8 7 6 5 4 3 2 1 0
3 2 1 0
1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1 1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
A A A A 1 1 X X X X X X X X X X
SDI D D D D
3 2 1 0
SDO 1 1 1 1 1 1 1 D D D D D D D D D Valid Address/Command combination
8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Non-Volatile Memory Read
during Non-Volatile Memory Write Cycle
READ DATA
FIGURE 7-4: Read Command - SDI and SDO States.
A A A A 1 1 X X X X X X X X X X
SDI D D D D
3 2 1 0
SDO 1 1 1 1 1 1 1* D D D D D D D D D
8 7 6 5 4 3 2 1 0
A A A A 1 1 X X X X X X X X X X
D D D D
3 2 1 0
1 1 1 1 1 1 1* D D D D D D D D D
8 7 6 5 4 3 2 1 0
A A A A 1 1 X X X X X X X X X X
D D D D
3 2 1 0
1 1 1 1 1 1 1* D D D D D D D D D
8 7 6 5 4 3 2 1 0
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
A A A A 1 0 X X A A A A 1 0 X X A A A A 1 0 X X
SDI D D D D D D D D D D D D
3 2 1 0 3 2 1 0 3 2 1 0
1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 Note 1, 2
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 3, 4
SDO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note 3, 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
TABLE 7-6: ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY
Memory Commands and Result
Address High Voltage Decrement Wiper High Voltage Increment Wiper
00h Wiper 0 register is incremented Wiper 0 register is incremented
01h Wiper 1 register is incremented Wiper 1 register is incremented
02h WL0 is enabled WL0 is disabled
03h WL1 is enabled WL1 is disabled
04h (1) TCON register not changed, CMDERR bit is set TCON register not changed, CMDERR bit is set
05h - 0Eh (1) Reserved Reserved
0Fh WP is enabled WP is disabled
Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.
8.1 Split Rail Applications FIGURE 8-1: Example Split Rail System
1.
All inputs that would be used to interface to a Host
Controller support High Voltage on their input pin. This
allows the MCP4XXX device to be used in split power Voltage 5V
rail applications. Regulator
An example of this is a battery application where the 3V
PIC MCU is directly powered by the battery supply PIC MCU MCP4XXX
(4.8V) and the MCP4XXX device is powered by the
3.3V regulated voltage. SDI SDI
CS CS
For SPI applications, these inputs are: SCK
SCK
CS WP WP
SCK SHDN SHDN
SDI (or SDI/SDO) SDO SDO
WP
FIGURE 8-2: Example Split Rail System
SHDN
2.
Figure 8-1 through Figure 8-2 show three example split
rail systems. In this system, the MCP4XXX interface
TABLE 8-1: VOH - VIH COMPARISONS
input signals need to be able to support the PIC MCU
(1)
output high voltage (VOH). PIC MCP4XXX (2)
Comment
In Example #1 (Figure 8-1), the MCP4XXX interface VDD VIH VOH VDD VIH VOH
input signals need to be able to support the PIC MCU 5.5 4.4 4.4 2.7 1.215 (3)
output high voltage (VOH). If the split rail voltage delta
5.0 4.0 4.0 3.0 1.35 (3)
becomes too large, then the customer may be required
to do some level shifting due to MCP4XXX VOH levels 4.5 3.6 3.6 3.3 1.485 (3)
related to Host Controller VIH levels. 3.3 2.64 2.64 4.5 2.025 (3)
In Example #2 (Figure 8-2), the MCP4XXX interface 3.0 2.4 2.4 5.0 2.25 (3)
input signals need to be able to support the lower volt- 2.7 2.16 2.16 5.5 2.475 (3)
age of the PIC MCU output high voltage level (VOH). Note 1: VOH minimum = 0.8 * VDD;
Table 8-1 shows an example PIC microcontroller I/O VOL maximum = 0.6V
voltage specifications and the MCP4XXX specifica- VIH minimum = 0.8 * VDD;
tions. So this PIC MCU operating at 3.3V will drive a VIL maximum = 0.2 * VDD;
VOH at 2.64V, and for the MCP4XXX operating at 5.5V, 2: VOH minimum (SDA only) =;
the VIH is 2.47V. Therefore, the interface signals meet VOL maximum = 0.2 * VDD
specifications. VIH minimum = 0.45 * VDD;
VIL maximum = 0.2 * VDD
3: The only MCP4XXX output pin is SDO,
which is Open-Drain (or Open-Drain with
Internal Pull-up) with High Voltage Support
Common B
Balance Bias
B CS
VSS VSS
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXXXX 4131-502
XXXXXNNN E/P e3 256
YYWW 0733
XXXXXXXX 4131502E
XXXXYYWW e3
SN^^^0733
NNN 256
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXXXXXXXXXX MCP4261
XXXXXXXXXXXXXX e3
502E/P^^
YYWWNNN 0733256
XXXXXXXXXXX MCP4261
XXXXXXXXXXX e3
502E/SL^^
YYWWNNN 0733256
XXXXXXXX 4261502E
YYWW 0733
NNN 256
XXXXX 4261
XXXXXX 502
XXXXXX e3
E/ML^^
YYWWNNN 0733256
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
8-Lead Plastic Dual Flat, No Lead Package (MF) 3x3x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D e
b
N N
L
EXPOSED PAD
E E2
NOTE 1
1 2 2 1 NOTE 1
D2
TOP VIEW BOTTOM VIEW
NOTE 2
A3 A1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Length D 3.00 BSC
Exposed Pad Width E2 0.00 1.60
Overall Width E 3.00 BSC
Exposed Pad Length D2 0.00 2.40
Contact Width b 0.25 0.30 0.35
Contact Length L 0.20 0.30 0.55
Contact-to-Exposed Pad K 0.20
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-062B
D
N
E
E1
NOTE 1
1 2
e
c
A A2
A1 L1 L
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0.80
Footprint L1 0.95 REF
Foot Angle 0 8
Lead Thickness c 0.08 0.23
Lead Width b 0.22 0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B
NOTE 1
E1
1 2 3
D
E
A A2
A1 L
c
e
b1 eB
b
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB .430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
e
N
E1
NOTE 1
1 2 3
h
b
h
c
A A2
A1 L
L1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.75
Molded Package Thickness A2 1.25
Standoff A1 0.10 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 0.50
Foot Length L 0.40 1.27
Footprint L1 1.04 REF
Foot Angle 0 8
Lead Thickness c 0.17 0.25
Lead Width b 0.31 0.51
Mold Draft Angle Top 5 15
Mold Draft Angle Bottom 5 15
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
10-Lead Plastic Dual Flat, No Lead Package (MF) 3x3x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D e
b
N N
L
K
E E2
EXPOSED
PAD
NOTE 1 NOTE 1
1 2 2 1
D2
TOP VIEW BOTTOM VIEW
A3 A1 NOTE 2
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 10
Pitch e 0.50 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Length D 3.00 BSC
Exposed Pad Length D2 2.20 2.35 2.48
Overall Width E 3.00 BSC
Exposed Pad Width E2 1.40 1.58 1.75
Contact Width b 0.18 0.25 0.30
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-063B
D
N
E1
NOTE 1
1 2
b
e
c
A A2
L
A1
L1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 10
Pitch e 0.50 BSC
Overall Height A 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0.80
Footprint L1 0.95 REF
Foot Angle 0 8
Lead Thickness c 0.08 0.23
Lead Width b 0.15 0.33
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
NOTE 1
E1
1 2 3
A A2
L c
A1
b1
b e eB
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .735 .750 .775
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB .430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
E1
NOTE 1
1 2 3
e
h
b
h
c
A A2
A1 L
L1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A 1.75
Molded Package Thickness A2 1.25
Standoff A1 0.10 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (optional) h 0.25 0.50
Foot Length L 0.40 1.27
Footprint L1 1.04 REF
Foot Angle 0 8
Lead Thickness c 0.17 0.25
Lead Width b 0.31 0.51
Mold Draft Angle Top 5 15
Mold Draft Angle Bottom 5 15
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-065B
14-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
NOTE 1
1 2
e
b
c
A A2
A1 L1 L
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 0.65 BSC
Overall Height A 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 4.90 5.00 5.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle 0 8
Lead Thickness c 0.09 0.20
Lead Width b 0.19 0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087B
16-Lead Plastic Quad Flat, No Lead Package (ML) 4x4x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D D2
EXPOSED
PAD
E E2
2 2 b
1 1
K
N N
NOTE 1 L
TOP VIEW BOTTOM VIEW
A A3
A1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 16
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Width E 4.00 BSC
Exposed Pad Width E2 2.50 2.65 2.80
Overall Length D 4.00 BSC
Exposed Pad Length D2 2.50 2.65 2.80
Contact Width b 0.25 0.30 0.35
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-127B
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
06/25/07