A

PRELIMINARY DISSERTATION
CUM SYNOPSIS
ON

Design and Implementation of 3 bit Flash ADC in 45 nm

CMOS

Submitted in partial fulfillment for the award of

Master of Technology

in
VLSI Design

Submitted By:
Enroll. No. 0905EC10MTXX

Supervisor:

Co-Supervisor

Department of Electronics & Communication Engineering

INSTITUTE OF TECHNOLOGY & MANAGEMENT
GWALIOR (M.P.)
2011-2013

1
 INDEX
S.NO Content Page no.

1. Introduction & Motivation 3-4

2. A folding reduction technique of flash ADC. 5

3. Literature Review. 6-12

4. Gaps in Present Research. 13

5. Objectives. 14

6. Research Methodology. 15

7. Simulation and Result. 16-17

8. Conclusion. 18

9. References. 19-22

2
1. Introduction & Motivation

At present high speed signal processing is to be need in various applications such as the hard
disks channels read, Gigabit Ethernet that rely on digital signal processing circuits.These circuits
that provide signal processing part require high speed and high precision ADCs to provide the
interface between the analog and digital parts of the signal processing system. A Flash ADC is
required to design because it become faster than the other types of ADCs. For example a Flash
ADCs can achieve 4GS/s with 6 bit resolution in a 0.13m standard CMOS technology.The main
and considerable drawback of Flash ADC is its power consumption.In this synopsis we will
describe different issues in designing a Flash ADC and find out how to improve its
performance.Digital Signal processing is important for system-on-chip (SOC) applications.As
the technology become advance for better perspective ,digital signal processing has achieved
importance in the various fiels such like biomedical, telecommunication ,control systems and so
on. significantly.Therefore high precision, low voltage, low power, high speed ,wide bandwidth,
highly accurate and high speed data converters such like flash ADC is needed for
design,thereby attracting immense research is required in this field.Therefore main focus of
related research is to design and analyze the highly efficient low voltage ADCs that achieve and
operate at high speed .Motivational factors describe the ADCs are interfaced with digital circuits
system on chip, where digital signal processing is required and perfomed. As technology scale
down operating voltage decreasing for digital circuits..The proposed design meets both
important criteria Low supply voltage (0.7V) and technology (45nm).
Flash ADC can be describe as parallel ADC which is the fastest one as compared with all ADCs
[2].Figure 1 shows a 3-bit Flash ADC. It includes 7 comparators, 7 reference voltages generated
by resistors ladder and one encoder block.In figure 1, the comparators compare the input signal
with the reference values.After encoder, the digital signal as binary formae are obtained.Because
the design of Flash ADC is considered as parallel therefore it needs only one clock period and it
is the fastest ADC.

3
Figure 1. Block diagram of Flash ADC

4
2.A folding reduction technique of flash ADC.
The number of comparators can be reduced by the use of folding ADC architecture.
Optimization of ADC circuit is done by reducing the size of circuit which is biggest disadvantage
of flash ADCs.Therefore folding technique is used to implement the logic circuit which require
minimum number of comparators to increase bit size of ADC The number of comparators is
required must below 2N by the employ of folding logic.Fig 2show the folding logic circuit that
consists of different resistors which is connected to voltage source of 0.7 V generated 3 bit
ouput.It employ only three comparators and reducing the size of flash ADC.Resistors value are
chosen in such a way that 3 bit output are not overlapped.Different values of resistors must
chosen as R1=10K,R2=220K,R3=56 and R4=56K.

VIN

Literature Review:

5
Mingzhen Wang et.al [1] describe a 4-b low-power, low-voltage flash analog-to-digital converter
(ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold
(T/H); 2) differential comparator; and 3) differential cascade voltage switch with pass gates
(DCVSPG) Comparator
encoder. The T/H uses a current-mode dual-array structure to reduce the aperture
Comparator
jitter for high-input signal frequency. The ADC is designed in 130-nm CMOS technology. Fast
Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input
signal frequency up to 1 GHz. It demonstrate a design technique (pipelined-flash ADC
architecture) and an encoder (DCVSPG encoder) for high-speed flash CMOS ADCs.

Sunghyun Park et.al [2] proposed a 4-bit noninterleaved flash ADC implemented in 0.18- m
digital CMOS achieves a sampling rate of 4 GS/s. A 32 m by 32 m, on-chip differential inductor
Bit C
Bit
in each comparator extends theB sampling rate without an increase in power consumption. A
combination of DAC trimming and comparator redundancy reduces the measured DNL and INL
to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-
power input is 3.84 bits and
Bit3.48
A bits, at 3 GS/s and 4 GS/s, respectively. The ADC achieves a bit
error rate of less than 10 11 at 4 GS/s.

Hairyong Yu et.al [3] demonstrate an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in
90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC
employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC
R1
full-scale voltage and enables the converter operating under a single 1-V supply; and an
improved calibration scheme based on reference pre-distortion to enhance the ADC linearity
Priority Encoder

without sacrificing its sampling speed.

Ayman Ismail et.al [4] developed aR2

new termination technique for the averaging network of the
flash analog-to-digital converter (ADC) input preamplifiers is devised. The proposed technique
eliminates the over-range voltage headroom consumed by the dummy preamplifiers and
therefore, the input capacitance and power dissipation of the ADC is reduced. This technique is
applied to the design of a 6-bit 1.6-GS/s flash ADC in 0.13- m CMOS technology. The measured
peak INL and DNL are 0.42 LSB and 0.49 LSB, respectively. The ADC achieves an effective
resolution bandwidth (ERBW) of 800 MHz and an SNDR of 30 dB at 1.45-GHz input signal
R4
I3 6 R3
 I2
frequency while consuming 180 mW. The limited supply voltage offered by future technologies
will outweigh the accuracy improvement due to its superior MOS matching properties.
Therefore, optimizing the bandwidth-accuracy tradeoff of flash ADC is essential to advance its
state of the art.

Kazuaki Deguchi et.al [5] describe a 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a
clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed
operation. An acceleration capacitor s introduced for high-speed overdrive recovery of a
I1
comparator. An averaging and interpolation network is employed in this ADC. The interpolation
factor is optimized considering random offset, active area, and systematic offset to realize low
offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies
0.15mm2. It consumes 98mWwith a 0.9-V power supply.With Nyquist input, SNDR and SFDR
at 3.5 GS/s are 31.18 dB and38.67 dB, respectively.

Young Deuk Jeon et.al [6] determine a 10-bit dual-channel pipelined flashsuccessive
approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications.
The proposed ADC consists of two channels for high operating speed, and each channel adopts a
pipelined flashSAR architecture for low power and a small area. The prototype ADC fabricated
in aR/2
45-nm CMOS
R process occupies 0.16 mm2. The differential and integral nonlinearities of the
ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-
distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at
R
230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a
1.2-V supply.

Xiangliang Jing et.al [7] explore a high-performance CMOS imager with a new analog-to-
R
digital-converter (ADC) scheme. The new ADC scheme, adopting the visual perception of
human eyes, has realized a maximal 13bit variable resolution and reduced clipped noise for
imaging. The response probability of human eyes to a flash light falls in the region of [-1+, 1-]
of a normal distribution, where is the standard deviation. In the region effective to human eyes
[-1+, 1-], there exists a point corresponding to a maximum 13bit variable resolution to
improve the image quality and to save the power consumption and the chip size of sensors. The
R

7
 R
test results show the improved image quality compared with the typical CMOS products with a
linear ADC. Test results also show 79dB SNR (@Gain=0dB) with the power consumption of
90mW@54MHz. It demonstrae a variable resolution flash ADC to reduce the clipped noise for a
wide dynamic range in CMOS sensors.

Athanasios Stefanou et.al [8] analysis and then expresses the resulting sampling distortion
power by also considering the comparators nonlinearities and thus models the signal-to-noise-
and-distortion ratio (SNDR) of the converter. In particular, it is shown that substrate noise causes
an FM modulation of the clock, and the resulting timing error is a joint effect of AM
R
FMmodulation of the input signal and the coupled noise. The derivation of the analytical
expression is also valid for any multitone ground perturbation and is validated on a high-
resolution Flash converter.

Jorge Pernillo et.al [9] proposed a 7-bit 1.5-GS/s analog-to-digital converter (ADC) incorporates
redundancy, reassignment, and digital correction to reduce the complexity of analog functions
and the required accuracy compared to traditional Flash ADCs. Deliberate and random mismatch
is used to set the desired trip points, achieving a 600-mVpp differential input signal range. The
need for a low-impedance high-precision resistor reference ladder is eliminated, and comparator
performance is decoupled from matching requirements,so that small and fast
dynamiccomparators can be used.
R

Gokce Keskin et.al [10] determine the process variations in advancedCMOS nodes limit the
benefits of scaling for analog designs. In the presence of increasing random intra-die variations,
mismatch becomes a significant design challenge for circuits such as comparators. we describe
and demonstrate the details of a statistical element selection (SES) methodology that relies on the
combinatorial growth of subsets of selectable circuit elements (e.g., input transistors in a
comparator) to provide redundancy for post-manufacturing calibration of specifications (e.g.,
offset). Over 99.5% of the comparators satisfy the given offset specification compared to 15% for
Pelgrom-type sizing.Asecond test chip in the same process consists of an 8-bit, 1.5 GS/s flash
ADC and achieves 37 db SNDR at low frequencies. The total power is 35 mW, 20 mW in the
S&H. and 15 mWin the ADC core.

3R/2
Manar EI-Chammas et.al [11] demonstrate a 12-GS/s 5-bit time-interleaved flash ADC realized
in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-
based background calibration scheme for timing skew is employed. The timing skew is detected
in the digital domain through a correlation-based algorithm and minimized by adjusting digitally
controlled delay lines. In order to minimize power consumption, we employ near minimum size
comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry.With the
timing calibration activated, the skew-related impairments are reduced by 12 dB at high input
frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW
from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input
frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

U-Fat Chio et.al [12] describe the architectural concept of an optimal subranging ADC,
obtained with the cascade of a Flash and a SAR, which is also explored through its practical
design and experimental confirmation. The solution doubles the optimal speed of operation of
the SAR ADCs at the relative low power cost of a low-resolution Flash. The digital correction
method and a capacitor-based DAC ensure nondemanding requirements for the Flash. The
effectiveness of the architecture is verified in a 90-nm CMOS chip whose active core area is 0.64
mm2. The ADC obtains a peak SNDR of 51.8 dB and SFDR of 63.4 dB at 90 MS/s consuming
13.5mWfrom a 0.9-V supply.

Skyler Weaver et .al [13]proposed a stochastic flash analog-to-digital converter (ADC) . A

standard flash uses a resistor string to set individual comparator trip points. A stochastic flash
ADC uses random comparator offset to set the trip points. Since the comparators are no longer
sized for small offset, they can be shrunk down into digital cells. Using comparators that are
implemented as digital cells produces a large variation of comparator offset. Typically, this is
considered a disadvantage, but in our case, this large standard deviation of offset is used to set
the input signal range. By designing an ADC that is made up entirely of digital cells, it is a
natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer
function described by a Gaussian cumulative distribution function, and a technique is presented

9
that reduces this nonlinearity by changing the overall transfer function of the stochastic flash
ADC.

Junjie Yo et.al [14] analysis the bulk voltage trimming offset calibration technique is presented
for flash analog-to-digital converters (ADCs). Offset calibration is achieved by digitally
adjusting the bulk voltages of the preamplifier input devices. Without introducing additional
capacitive loading in the analog path, this technique improves the accuracy of flash ADCs while
not impairing their high-speed performance. A 4-bit ADC in 90-nm CMOS with the proposed
technique achieves 3.71 effective number of bits (ENOB) at 5-GS/s sampling rate with 2.5-GHz
effective resolution bandwidth (ERBW). The calibration generally improves ENOB by
approximately 0.5 bit after calibration. The ADC consumes 86 mW at 5 GS/s with a 2.5-GHz
input achieving a 1.32-pJ/convstep figure of merit.

Denis C. Daly et.al [15] proposed a 6-bit highly digital flash ADC is implemented in a 0.18
m CMOS process. The ADC operates in the subthreshold regime down to 200 mV and employs
comparator redundancy and reconfigurability to improve linearity. The low-voltage sampling
switch employs voltage boosting, stacking and feedback to reduce leakage. Common-mode
rejection is implemented digitally via an IIR filter. The minimum FOM of the ADC is 125
fJ/conversion- step at a 0.4 V supply, where it achieves an ENOB of 5.05 at 400 kS/s. A quadratic
relationship between the amount of device stacking and the strength of an input network in the
subthreshold regime is derived, demonstrating an advantage of stacking over device width
scaling to adjust comparator thresholds.

Ybe Creten et.al [16] demonstrate the first Flash analog-to-digital converter (ADC) in
standard CMOS technology that functions from 300 K (room temperature) down to 4.2 K. It has
been designed to operate in cryogenic sensor systems as they are cooled from room temperature
to their final cryogenic operating temperature. In order to preserve the circuits performance over
this wide temperature range, even in the presence of temperature- induced transistor anomalies,
dedicated architecture and switching schemes are employed. SPICE models for adequate circuit
simulation at 4.2 K have been extracted. A first prototype of the chosen architecture, an 8-bit
ADC in a standard 0.7 m CMOS technology, achieves a differential nonlinearity (DNL) of 0.5

10
LSB at room temperature and 1 LSB at 4.2 K at a sampling frequency of 12.5 kHz. A cryogenic
flash ADC operational in the temperature range from room temperature (300 K) down to 4.2 K is
presented. The proposed ADC is designed in standard CMOS technology, which, due to impurity
freeze-out, develops anomalous transistor behavior at cryogenic temperatures such as IV-
characteristic kinks, negative transconductance and slow transient behavior.

Timmy Sundstrm et.al [17] determine an experimental study on how to take advantage of
the increasing process variations in nanoscale CMOS technologies to achieve small and low-
power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference
voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with
small-sized comparators. The native comparator offsets, resulting from the process variation-
induced mismatch, are used as the only source of reference levels, and redundancy is used to
acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to
traditional state-of-the art ADCs and dissipates 23 mW.

Chun-Ying Chen et.al [18] proposed a low power 6-bit ADC that uses reference voltage and
common-mode calibration . A method for adjusting the differential and common-mode reference
voltages used by the ADC to improve its linearity is described. Power dissipationis reduced by
using small device sizes in theADCand relying on calibration to cancel the large non-ideal
offsets due to device mismatches. The ADC occupies 0.13 mm in 65 nm CMOS and dissipates
12mWat a sample rate of 800 MS/s from a 1.2 V supply. A 6-b ADC that uses reference voltage
and common-mode calibration has been presented. This ADC uses digital calibration to both
reduce power and improve linearity allowing us to overcome the inherent power versus linearity
tradeoff in the ADC design.

Bob Verbruggen et.al [19] describe a 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding
technique is presented. The 2X folding lowers the number of comparators from 31 to 16,
simplifies encoding and reduces power consumption and area. The comparators in this converter
are implemented with built-in references and calibration to further reduce power consumption.
presented. A 1 bit folding stage samples and rectifies the input signal with passive charge sharing
using a comparator controlled chopper. This folding stage uses no amplifiers, consumes only

11
dynamic power and reduces the amount of comparators needed from 31 to 16 for 5 bit resolution.
The linearity of the folding stage has been analyzed using simulations, and its nonidealities can
be cancelled by a proper design and control of the succeeding flash converter.

Ayman Ismail et.al [20] demonstrate Efficient handling of the flash analog-to-digital converter
(ADC) bandwidthaccuracy tradeoff is essential to minimizing its figure-of-merit. In this work,
an expression that represents the bandwidthaccuracy tradeoff is devised, and the effect of
technology scaling on this tradeoff is demonstrated. Based on the derived expression, the
interpolating flash ADC is analyzed, and it is shown that the interpolating architecture attains a
superior bandwidthaccuracy product compared with the full-flash architecture, especially in
deep-submicron technologies. The gain in performance achieved when using interpolation is
formulated and verified using simulations.

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13
5. Objectives.
The major objective and specific aim of the research work will be as follows:

1. To investigate and study the various ADC architectures for implementing

high speed and highly accurate Flash type ADC.

2. Develop and implement the various ADC architectures.

3.To review different architectures and implement best and suitable high
precision and high speed flash analog-to-digital converter architecture for signal
processing system.

4. To functionally simulate the various ADC architectures for performance evaluation and
optimization.

5. To implement and design different architecture using various EDA tools.

14
6. Research Methodology

S.NO Period Research Methodology

1. To investigate and study the
various ADC architectures
for implementing high speed
and highly accurate Flash
type ADC
2. Literature Review

3. Develop and implement the

various ADC architectures
4. To review different
architectures and implement
best and suitable high
precision and high speed
flash analog-to-digital
converter architecture for
signal processing system.
5. To functionally simulate the
various ADC architectures for
performance evaluation and
optimization.

6. To implement and design

different architecture using
various EDA tools.

7.Simulation and Results

15
In this paper a desigin of 3 bit flash ADC and design one of technique to optimize the flash
ADC in 45 nm CMOS.The cadence virtuoso tool is used for estimating speed ,jitter and
power consumption, is shown in table 1.Simulation flash ADC and folding technique is given
below in figure 3 and 4

Fig 3.Waveform of 3 bit flash ADC

16
 Fig 4 Waveform of folding ADC

Table 1 .Simulation result of 3 bit flash ADC using folding technique

1. CMOS Technology 45 nm
2. Supply voltage 0.7 V
3. Power consumption 1.8 W
4. Jitter 4.02 Hz
5. Delay 14.2 s

17
8.Conclusion:

As technology scale down and supply voltage become minimized which is lowered to 0.7 V in
45 nm CMOS technology.As 7 comparators increase the overhead in flash ADC therefore folding
technique consist of three comparators and 4 resistors for reference voltage generation.We take
folding technique to reduce the size of comparators and overall reduce the size of flash ADC.The
main focus of future work presented here to analyze different configuration of ADC which
optimize the performance .as technology move down to 45 nm at lower supply voltage.

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9.References

[1] Mingzhen Wang, Student Member, IEEE, Chien-In Henry Chen, and Shailesh
Radhakrishnan, Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter
in 130-nm CMOS IEEE TRANSACTIONS ON INSTRUMENTATION AND
MEASUREMENT, VOL. 56, NO. 3,pp.1064-1073, JUNE 2007.
[2] Sunghyun Park, Member, IEEE, Yorgos Palaskas, Member, IEEE, and Michael P. Flynn,
Senior Member, IEEE, A 4-GS/s 4-bit Flash ADC in 0.18-um CMOS, IEEE JOURNAL
OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, pp.1865-1872,SEPTEMBER 2007.

[3] Hairong Yu, Student Member, IEEE, and Mau-Chung Frank Chang, Fellow, IEEE, A 1-V
1.25-GS/S 8-Bit Self-Calibrated Flash ADCin 90-nm Digital CMOS, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 55,
NO. 7,pp.668-672, JULY 2008.

[4] Ayman Ismail, Member, IEEE, and Mohamed Elmasry, Fellow, IEEE, A 6-Bit 1.6-GS/s
Low-Power Wideband Flash ADC Converter in 0.13 um CMOS Technology, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9,pp.1982-1990 SEPTEMBER
2008.

[5] Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, and Takahiro Miki, Senior
Member, IEEE, A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADCin 90-nm CMOS, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, pp.2303-2010,OCTOBER
2008.

[6] Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, Tae Moon Roh, and Jong-Kee Kwon,
Member, IEEE, A Dual-Channel Pipelined ADC With Sub-ADC Based on FlashSAR
Architecture, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS
BRIEFS.

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 [7] Xiangliang Jin, Member, IEEE, Zhibi Liu, Jun Yang, A New Flash ADC Scheme with
Maximal 13bit Variable Resolution and Reduced Clipped Noise for High Performance
Imaging Sensor,IEEE Transaction Future Issue.

[8] Athanasios Stefanou, Student Member, IEEE, and Georges Gielen, Fellow, IEEE, A
Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to
Substrate Noise Coupling, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS
II: EXPRESS BRIEFS, VOL. 58, NO. 12, pp.877-881,DECEMBER 2011.

[9] Jorge Pernillo, Student Member, IEEE, and Michael P. Flynn, Senior Member, IEEE, A
1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS,
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS,
VOL. 58, NO. 12, pp.837-841,DECEMBER 2011.

[10] Gokce Keskin, Member, IEEE, Jonathan Proesel, Member, IEEE, Jean-Olivier Plouchart,
Senior Member, IEEE, and Lawrence Pileggi, Fellow, IEEE, Exploiting Combinatorial
Redundancy for Offset Calibration in Flash ADCs, IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL. 46, NO. 8,pp.1904-1918, AUGUST 2011.

[11] Manar El-Chammas, Member, IEEE, and Boris Murmann, Senior Member, IEEE, A 12-
GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew
Calibration, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 4,pp.838-
847, APRIL 2011.

[12] U-Fat Chio, Student Member, IEEE, He-Gong Wei, Student Member, IEEE, Yan Zhu,
Student Member, IEEE, Sai-Weng Sin, Member, IEEE, Seng-Pan U, Senior Member, IEEE,
R. P. Martins, Fellow, IEEE, and Franco Maloberti, Fellow, IEEE, Design and
Experimental Verification of a Power Effective Flash-SAR Subranging ADC, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 57,
NO. 8, pp.607-611,AUGUST 2010.

20
[13] Skyler Weaver, Student Member, IEEE, Benjamin Hershberg, Student Member, IEEE,Peter
Kurahashi, Student Member, IEEE, Daniel Knierim, and Un-Ku Moon, Fellow, IEEE,
Stochastic Flash Analog-to-Digital Conversion, IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 57, NO. 11,pp.2825-2833
NOVEMBER 2010.

[14] Junjie Yao, Student Member, IEEE, Jin Liu, Senior Member, IEEE, and Hoi Lee, Senior
Member, IEEE, Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs,
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS,
VOL. 57, NO. 2, pp.110-114,FEBRUARY 2010.

[15] Denis C. Daly, Student Member, IEEE, and Anantha P. Chandrakasan, Fellow, IEEE, A 6-
bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, pp.3030-
3038,NOVEMBER 2009.

[16] Ybe Creten, Member, IEEE, Patrick Merken, Willy Sansen, Life Fellow, IEEE, Robert P.
Mertens, Fellow, IEEE,and Chris Van Hoof, Member, IEEE, An 8-Bit Flash Analog-to-
Digital Converter in Standard CMOS Technology FunctionalFrom 4.2 K to 300 K, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, pp.2019-2025,JULY 2009.

[17] Timmy Sundstrm, Student Member, IEEE, and Atila Alvandpour, Senior Member, IEEE,
Utilizing Process Variations for Reference Generation in a Flash ADC, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56,
NO. 5, pp.364-368,MAY 2009.

[18] Chun-Ying Chen, Michael Q. Le, Member, IEEE, and Kwang Young Kim, A Low Power
6-bit Flash ADC With Reference Voltage and Common-Mode Calibration, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, pp.1041-1046,APRIL 2009.

21
[19] Bob Verbruggen, Student Member, IEEE, Jan Craninckx, Senior Member, IEEE, Maarten
Kuijk, Member, IEEE,Piet Wambacq, Member, IEEE, and Geert Van der Plas, Member,
IEEE, A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, pp.874-882,MARCH 2009.

[20] Ayman Ismail, Member, IEEE, and Mohamed Elmasry, Fellow, IEEE, Analysis of the
Flash ADC BandwidthAccuracy Tradeoff in Deep-Submicron CMOS Technologies,
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS,
VOL. 55, NO. 10,pp.1001-1005, OCTOBER 2008.

22