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HCM
KHOA IEN T
BO MON VIEN THONG
TP.HCM 2007
TRNG AI HOC S PHAM KY THUAT TP.HCM
KHOA IEN T
BO MON VIEN THONG
TP.HCM 2007
LI NOI AU
Cac he thong so lap trnh ngay cang hien dien trong nhieu thiet b ien t dan dung cung nh
trong cac thiet b ieu khien cong nghiep.
u iem cua thiet b so lap trnh la lam cho mach ien ngay cang nho gon do mat o tch hp
cao, khong mat nhieu thi gian cho viec ket noi va th nghiem so vi IC ri, de thay oi yeu cau ieu
khien cua mach, chiem t dien tch khong gian, toc o hay tan so lam viec cao ap ng c cac
ng dung oi hoi ve toc o hoac x ly khoi lng d lieu ln.
Noi dung cuon sach nay c bien soan gom 4 chng nham phuc vu cho mon hoc 2 tn ch,
trong o chng 1 gii thieu ve cac thiet b so lap trnh c, chng 2 trnh bay ngon ng VHDL
dung e lap trnh cho he thong so, chng 3 trnh bay cach lap trnh cho cac mach ien to hp,
chng 4 trnh bay cach lap trnh cho cac mach ien tuan t.
Noi dung trong cuon sach nham trang b cac kien thc c ban ve ky thuat PLD va ASIC cho
sinh vien nganh ien ien t.
Trong qua trnh bien soan co tham khao nhieu tai lieu nen van con sai sot nen mong s ong
gop xay dng e bai giang c hoan thien hn xin hay gi ve tac gia theo a ch
phu_nd@yahoo.com - xin chan thanh cam n.
MUC LUC
LI NOI AU
CHNG 1. GII THIEU CAC CAU TRUC LAP TRNH C
I. GII THIEU PLD 4
1. HOAT ONG CUA SPLD C BAN LA PAL 4
2. HOAT ONG CUA SPLD C BAN LA GAL 5
3. K HIEU N GIAN CHO S O CUA PAL/GAL 5
4. S O KHOI TONG QUAT CUA PAL/GAL 7
5. MACROCELL 7
6. CAC SPLD THC TE 9
7. CAC CPLD 10
II. CPLD CUA HANG ALTERA 12
1. CPLD MAX 7000 12
2. MACROCELL 13
3. KHOI M RONG CHIA SE 13
4. KHOI M RONG SONG SONG 15
5. CPLD MAX I 16
III. CPLD CUA HANG XILINX 18
1. PLA (PROGRAMMABLE LOGIC ARRAY) 18
2. COOLRUNNER I 19
IV. LOGIC LAP TRNH FPGA 22
1. CAC KHOI LOGIC CO THE NH CAU HNH CLB 23
2. CAC MODULE LOGIC 24
3. FPGA DUNG CONG NGHE SRAM 25
4. CAC LOI CUA FPGA 26
V. FPGA CUA ALTERA 27
1. KHOI MANG LOGIC (LAB: LOGIC ARRAY BLOCK) 27
2. MODULE LOGIC THCH NGHI ALM 28
3. CAC CHC NANG TCH HP 30
VI. FPGA CUA XILINX 31
1. CAC KHOI LOGIC CO THE NH CAU HNH CLB (CONFIGURABLE LOGIC BLOCK) 31
2. CHUOI LIEN TIEP SOP 32
3. CAU TRUC FPGA TRUYEN THONG VA CAU TRUC ASMBL 35
VII. PHAN MEM LAP TRNH 37
1. CACH THIET KE 39
2. MO PHONG CHC NANG 43
3. TONG HP 44
4. LIET KE LI (NETLIST) 45
5. PHAN MEM THI HANH 46
6. MO PHONG THI GIAN 47
7. LAP TRNH CHO THIET B HAY NAP CHNG TRNH CHO THIET 47
VIII. CAU HOI ON TAP VA BAI TAP 48
V du 1-2: Hay ve s o mach cho mot PAL a lap trnh e tao ra ham co 3 bien ngo vao
nh sau: X = A BC + ABC + A B + AC
Giai: S o mach cua PAL nh hnh 1-5:
(a)
(b)
(c)
Hnh 1-7. S o mach cac Macrocell.
Hnh 1-7a trnh bay mot macrocell n gian vi mot cong OR va mot cong ao ba trang
thai. Ngo ra cua cong ao ba trang thai co the hoat ong tao ra mc HIGH, mc LOW va trang
thai tong tr cao xem nh h mach.
Hnh 1-7b trnh bay mot macrocell co the hoat ong nh ngo vao hoac ngo ra. Khi ngo vao
c dung nh ngo ra th cong ao phai trang thai tong tr cao e h mach va tn hieu t ben
ngoai a en bo em va ket noi vi mang cong AND ben trong.
Hnh 1-7c trnh bay mot macrocell co the lap trnh e co ngo ra tch cc mc HIGH hoac
mc tch cc mc LOW va cung co the s dung nh ngo vao. Mot ngo vao cua cong XOR (ex-
or) co the c lap trnh mc HIGH hoac mc LOW. Khi lap trnh ngo vao cong XOR mc
HIGH th tn hieu ngo ra cua cong OR se b ao v : 0 1 = 1 va 1 1 = 0 . Tng t khi lap trnh
Hnh 1-16. Minh hoa cho bo m rong song song t macrocell khac.
Hnh 1-16 trnh bay cach mot macrocell co the mn cac thanh phan m rong song song t
macrocell khac e tang bieu thc ngo ra SOP. Macrocell th 2 dung 3 thanh phan tch t
macrocell th 1 e tao ra bieu thc SOP gom 8 thanh phan.
5. CPLD MAX I
Cau truc cua CPLD MAX II khac vi hoc MAX 7000 va c Altera goi la CPLD Post-
macrocell. Nh a trnh bay trong s o khoi hnh 1-17, thiet b nay cha cac khoi LAB cung
vi nhieu thanh phan logic LE (Logic Elements). Mot LE la mot n v thiet ke logic c ban va
tng t nh macrocell. Ket noi ben trong co the lap trnh c sap xep theo hang va cot chay
gia cac LAB va cac phan t ngo vao/ngo ra (IOE: Input/Output Elements) c nh hng
xung quanh. Cau truc cua ho CPLD nay giong nh FPGA co the xem MAX II la FPGA co mat
o thap.
S khac nhau gia CPLD MAX II va cac CPLD thiet ke t SPLD la cach xay dng mot
ham logic. CPLD MAX II s dung cac bang tra LUT (Look-Up Tables) thay cho ma tran
AND/OR. Mot LUT ve c ban la loai bo nh co the lap trnh e tao ra cac ham SOP. Hai
phng phap nay c minh hoa nh hnh 1-18.
Ket noi ben trong dung hang/cot Ket noi theo kieu kenh
Hnh 1-19. Phan biet 2 kieu ket noi.
Hau het cac CPLD dung cong nghe x ly khong bay hi cho cac iem noi lap trnh. Tuy
nhien MAX II dung cong nghe x ly nh SRAM nen chung co the bay hi tat ca cac logic a
lap trnh se mat het khi mat ien. Bo nh c gan vao ben trong chip e lu tr d lieu chng
trnh dung cong nghe bo nh khong bay hi va se nh cau hnh lai cho CPLD khi co ien.
III. CPLD CUA HANG XILINX:
Cung giong nh Altera, Xilinx san xuat ra cac ho CPLD c sap xep theo mat o tch
hp, cong nghe x ly, ien ap nguon cung cap va toc o. Xilinx che tao ra nhieu ho CPLD nh
Cool Runner II, Cool Runner XPLA3 va XC9500. Ho XC9500 th co cau truc giong nh ho
CPLD MAX 7000 cua Altera s dung cau truc loai PAL/GAL. Trong phan nay chung ta ch
phan tch Cool Runner II.
Sau khi ket thuc phan nay ban co the: mo ta PLA va so sanh vi PAL, thao luan ve cau
truc CPLD Cool Runner II va mo ta cac khoi chc nang.
1. PLA (PROGRAMMABLE LOGIC ARRAY)
Nh a trnh bay, cau truc cua CPLD la cach ma cac thanh phan ben trong c to chc
va sap xep. Cau truc cua ho Cool Runner II cua Xilinx th da vao cau truc mang logic lap trnh
PLA (Programmable Logic Array) tot hn cau truc PAL (Programmable Array Logic). Hnh 1-
20 so sanh cau truc PAL vi cau truc PLA n gian.
Hnh 1-22. Cau truc cua mot khoi chc nang FB.
Mang cong AND co 56 cong AND va mang cong OR lap trnh co 16 cong OR. Vi cau
truc PLA th bat ky thanh phan tch nao cung co the noi ti cong OR e tao nen bieu thc SOP
cho ngo ra. Vi kha nang cc ai moi khoi chc nang co the tao ra 16 ngo ra va moi ngo ra co
bieu thc SOP cha 56 thanh phan tch.
V du 1-2: Hay lap trnh ket noi ben trong khoi FB cua hnh 1-22 e tao ra ham chc nang
SOP t macrocell th 1 la: ABCD + A BC D + ABC D va ham cho macrocell th 2 la:
ABC D + ABCD + A BCD + ABC D
Giai: ket qua nh hnh 1-23:
Hnh 1-27. Khai niem c ban cua LUT c lap trnh e tao SOP ngo ra.
V du 1-3: Hay thiet lap LUT co 3 bien c ban c lap trnh e tao ra bieu thc SOP theo
sau: A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0
a. FPGA bay hi nh lai cau hnh dung bo nh khong bay hi ben trong.
Hnh 1-30. Khai niem chc nang loi phan cng trong FPGA.
Viec thiet ke cac loi phan cng thng c xay dng bi nha che tao FPGA va chung
thuoc s hu cua nha che tao. Cac thiet ke rieng bi nha che tao c at ten la Intellectual
Property (IP) s hu tr tue. Mot cong ty thng liet cac loai s hu tr tue ma chung co hieu
lc tren cac website. Nhieu s hu tr tue la s ket hp cua loi phan cng va loi phan mem. Vi
x ly la mot v du minh hoa co vai tnh nang mem deo trong la chon va ieu chnh mot vai
thong so bi ngi dung.
Cac FPGA cha cac vi x ly tch hp mot trong hai hoac ca hai loi phan cng va loi phan
mem va nhieu chc nang khac th c at ten la Platform FPGA bi v chung co the c
dung e ieu khien mot he thong ay u ma khong can them mot thiet b ho tr nao.
V. FPGA CUA ALTERA
Altera san xuat ra nhieu ho FPGA bao gom Stratix II, Stratix , Cyclone va ACEX. Trong
phan nay chung ta ch khao sat ho Stratix II e minh hoa cho cac khai niem.
Sau khi ket thuc phan nay chung ta co the:
Thao luan ve cau truc c ban cua FPGA ho Stratix II, giai thch cach thanh phan c tao
ra trong FPGA, thao luan ve cac chc nang c tch hp.
1. KHOI MANG LOGIC (LAB LOGIC ARRAY BLOCK)
S o khoi cua FPGA tong quat a c trnh bay nh hnh 1-24; cau truc cua Stratix II
va cac ho Altera khac th giong nhau. Chung eu co cau truc loai LUT cho cac module logic
c goi la module logic thch nghi ALM (Adaptive Logic Module) c trnh bay trong thiet
b tong quat LAB. Mat o c phan loai t 2000 LAB cho en 22000 LAB tuy thuoc vao cac
ho cu the va moi LAB co 8 ALM. Kch thc vo thay oi t 314 chan en 1173 chan. Thiet b
Hnh 1-31. S o khoi cua cau truc LAB cua Stratix II va ALM
2. MODULE LOGIC THCH NGHI ALM
ALM la n v thiet ke c ban trong FPGA Stratix II. Moi ALM cha mot phan to hp
logic dung cau truc LUT va mach logic ket hp co the c lap trnh cho 2 ngo ra logic to hp
hoac hai ngo ra thanh ghi dch. Ben canh o, ALM co mach cong logic, cac flip flop va cac
mach logic khac cho phep thc hien chc nang tnh toan so hoc, chc nang em va thanh ghi
dch. S o khoi ALM cua Stratix II c trnh bay nh hnh 1-32.
Hoat ong cua ALM:
Mot ALM co the c lap trnh cho ra nhieu kieu hoat ong nh sau:
Kieu hoat ong bnh thng.
Kieu hoat ong LUT m rong.
Kieu tnh toan so hoc.
Kieu tnh toan so hoc dung chung.
Ngoai 4 kieu hoat ong th ALM co the c dung nh la 1 chuoi thanh ghi e xay dng
bo em va thanh ghi dch. Trong phan nay chung ta se khao sat kieu hoat ong bnh thng va
kieu hoat ong LUT m rong.
Hnh 1-33. Cac cau hnh co the co cua LUT trong ALM kieu bnh thng.
Hai ham SOP moi ham co 4 bien hoac t hn co the c thc hien trong mot ALM
ma khong can dung cac ngo vao chia se. V du ban co the co 2 ham 4 bien, mot ham co 4
bien va mot ham 3 bien hoac hai ham 3 bien. Bang cach chia se cac ngo vao, ban co the co
bat ky to hp nao cua 8 ngo vao len en toi a 6 ngo vao cho moi LUT. Trong kieu hoat ong
bnh thng th ban b gii han la cac ham SOP ch co toi a la 6 bien.
Ky thuat PLD va ASIC 29
Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
b. Kieu hoat ong LUT m rong
Cho phep m rong ham len en 7 bien c minh hoa hnh 1-34. Mach ien AND OR
vi ngo vao ao la mot v du n gian cua mach don kenh. Mach don kenh la mot phan cua
mach logic dung rieng trong ALM.
Hnh 1-34. M rong ALM e tao ra ham SOP 7 bien trong kieu LUT m rong.
V du 1-4: Mot ALM trong FPGA Stratix II c nh cau hnh hoat ong kieu LUT m
rong c trnh bay hnh 1-35. Hay xac nh bieu thc ngo ra SOP.
A5 A4 A3 A2 A1 A0 + A5 A4 A3 A2 A1 A0 + A5 A4 A3 A2 A1 A0 + A6 A5 A4 A3 A2 A0 + A6 A5 A4 A3 A2 A0 + A6 A5 A4 A3 A2 A0
Hnh 1-37. Minh hoa cac cap logic nh cau hnh t te bao logic cho en CLB.
2. CHUOI LIEN TIEP SOP
Slice n gian (hai te bao logic LC) vi logic chuoi lien tiep c trnh bay hnh 1-38.
Co mach a hp (MUX) danh rieng nam trong mach logic ket hp cua moi LC c dung
trong chuoi lien tiep va mot cong OR danh rieng nam trong slice.
(a)
(b)
(c)
Hnh 1-38. V du cach dung chuoi noi tiep e m rong bieu thc SOP.
V du 1-5: Hay trnh bay cach cong AND co 16 ngo vao co the tao ra bieu thc trong CLB.
Giai: Hai slice c nh cau hnh c trnh bay hnh 1-39 la ket qua cua cong AND co
16 ngo vao.
(c) FPGA co nhieu bo nh, them loi DSP va loi vi x ly se yeu cau kch thc ln hn.
Hnh 1-40. Tch hp nhieu chc nang IP ket qua lam giam CLB va/hoac phai tang kch
thc chip.
Logic cau hnh trong FPGA cang phc tap th cang dung nhieu IO. Moi lien he rang buoc
gia logic va IO se dan en tang kch thc chip va tang gia thanh. Ngoai ra mot van e khac
vi FPGA platform la khi them cac chc nang loi IP tch hp ben trong neu co yeu cau th phai
thiet ke lai thanh phan chnh hoac thiet ke lai mot phan trong cach bo tr chip (layout) co the
c yeu cau se lam tang them gia thanh.
a. Cau truc ASMBL
Xilinx a xay dng mot phng phap mem deo cho FPGA platform chip Virtex II Pro X
e khac phuc mot vai han che xuat hien trong cau truc truyen thong. Cau truc ASMBL la cau
truc s dung cot thay v dung cau truc hang/cot. Cac IO c at rai rac khap ni tot hn la at
xung quanh, dan en so lng IO cua no tang ma khong can lam tang kch thc chip. Moi cot
ve c ban la mot dai logic co the c thay the bang dai logic khac ma khong can thiet ke lai
cach bo tr chip. Cac v du ve cac loai cua cac dai logic la cac khoi logic nh cau hnh CLB,
khoi IO, bo nh va cac loi phan cng va phan mem nh DSP va vi x ly.
So lng khac nhau cua moi loai dai logic co the c tron lai e tng thch vi cac yeu
cau ng dung rieng biet. V du, trong cau hnh n gian nhat th co the pha tron cac dai CLB va
cac dai khoi IO c minh hoa nh hnh 1-41a. Nhieu hoac t hn cua ca 2 cung co the c s
dung tuy thuoc vao cac yeu cau.
(a) (b)
(c) (d)
Hnh 1-41. Minh hoa cau truc ASMBL cua FPGA platform.
Hnh 1-42. S o dong thiet ke tong quat e lap trnh cho SPLD, CPLD hoac FPGA.
Phai co 4 thiet b e co the lap trnh cho thiet b la: may tnh, phan mem lap trnh, thiet b
logic lap trnh (SPLD, CPLD hoac FPGA) va thiet b ket noi may tnh vi thiet b lap trnh (cap
hoac mach nap). Tat ca cac thanh phan nay c minh hoa nh hnh 1-43.
Hnh 1-43. Cac thiet b c ban e lap trnh cho SPLD, CPLD hoac FPGA.
1. CACH THIET KE
Gia s rang chung ta co mot thiet ke mach ien logic muon ieu khien bang thiet b lap
trnh th chung ta co the thiet ke tren may tnh bang mot trong hai cach c ban: thiet ke dung s
o nguyen ly (schematic entry) va cach dung ngon ng (text entry).
e dung cach thiet ke bang ngon ng th phai lam quen vi ngon ng HDL nh VHDL,
Verilog, ABEL hoac AHDL. Hau het cac nha che tao thiet b lap trnh cung cap cac goi phan
mem ho tr ngon ng VHDL va Verilog bi v chung la ngon ng HDL chuan. Nhieu nha che
tao con cung cap them ngon ng ABEL, AHDL.
Kieu thiet ke dung s o mach cho phep chung ta at cac k hieu cua cac cong logic va
cac chc nang logic khac t th vien len man hnh va ket noi chung theo yeu cau cua thiet ke.
Vi kieu thiet ke nay th can biet cac ngon ng HDL. Hnh 1-44 minh hoa cho ca 2 kieu thiet ke
cho mot mach ien logic AND-OR n gian.
Hnh 1-47. Man hnh soan thao dang song tong quat .
Bc tiep theo chung ta xay dng dang song cho moi ngo vao bang cach nhap vao 1 hoac
0 cho moi khoang thi gian. Hnh 1-48 trnh bay cac dang song ngo vao.
(a). Mach ien thiet ke (b). Mach toi u sau khi tong hp
Hnh 1-50. Minh hoa cho chc nang tong hp.
Phan mem tong hp tao ra danh sach liet ke li. e minh hoa cho khai niem tao ra danh
sach li th hnh 1-51a se trnh bay cach gan ten cho li, gan ten cho instance va gan ten cho
IO. Danh sach liet ke li c trnh bay hnh 1-51b khong can thiet phai giong bat ky danh
sach liet ke nao ve cu phap va khuon kho. Danh sach liet ke nham xac nh cac loai thong tin
can e mo ta mach ien. Mot khuon kho c dung cho bang liet ke cac li la EDIF
(Electronic Design Interchange Format).
(a) (b)
Hnh 1-51. S o mach va danh sach liet ke.
5. PHAN MEM THI HANH
Sau khi thiet ke a c tong hp th trnh bien dch thi hanh thiet ke ve c ban cong
viec nay chnh la sap xep thiet ke e no co the tng thch vi thiet b lap trnh a chon bang
cach da vao cau truc va cau hnh chan.
Qua trnh x ly nay goi la lam cho tng thch (fitting). e ket thuc cong oan thi hanh
cua dong thiet ke th phan mem phai biet thiet b ro rang va co ay u cac thong tin chi tiet ve
chan. D lieu ay u cho tat ca cac thiet b thng c lu trong th vien cua bo nh va ngi
thiet ke ch can chon ung thiet b lap trnh.
6. MO PHONG THI GIAN
Phan nay nam trong dong thiet ke c thc hien sau khi phan mem thi hanh bien dch va
trc khi nap chng trnh vao thiet b. Mo phong theo thi gian e kiem tra mach ien hoat
ong tai tan so thiet ke va khong co thi gian tre hoac cac van e ve thi gian khac lam anh
hng en hoat ong cua mach.
Phan mem thiet ke dung cac thong tin cua thiet b lap trnh nh thi gian tr hoan cua cac
cong e thc hien mo phong theo thi gian cua thiet ke.
Khi mo phong chc nang a c thc hien th mach ien se hoat ong ung theo quan
iem logic. Khi mo phong chc nang th cac thong so ch nh ve thiet b ch la khong can thiet
nhng khi mo phong ve thi gian th phai la chon thiet b ch. Phan mem soan thao dang song
co the c dung e xem ket qua mo phong cung nh mo phong chc nang c minh hoa nh
hnh 1-52.
end
package typedef IS
package SUBTYPE byte IS bit_vector (7 downto 0);
END ;
Use clause USE work.typedef.all
e tm hieu chng trnh th chung ta can nh ngha mot so thuat ng c s dung trong
ngon ng VHDL.
Entity (thc the) tat ca cac thiet ke eu c bieu dien dang cac thuat ng thc the (entity).
Mot thc the la mot khoi xay dng c ban nhat trong thiet ke. Mc cao nhat cua thc the la mc
nh. Neu thiet ke co th bac th mo ta mc cao nhat se cha cac mo ta mc thap hn nam ben
trong. Nhng mo ta mc thap hn nay se cha cac thc the mc thap hn na. Trong VHDL th
thc the dung e khai bao cac cong input_output cua cac thanh phan va ten cua no.
Architecture (kien truc) tat ca cac thc the co the c mo phong eu co mot mo ta kien truc.
Kien truc mo ta hanh vi cua thc the. Mot thc the n co the co nhieu kien truc. Mot kien truc co
the mo ta hanh vi (behavioral description) trong khi o mot kien truc khac co the mo ta cau truc
(structural description).
Configuration (cau hnh) phat bieu cau hnh c s dung e rang buoc mot the hien
(instance) thanh phan vi mot cap thc the - kien truc. Mot cau hnh co the c khao sat giong
nh mot danh sach cac thanh phan cua mot thiet ke. Danh sach cac thanh phan mo ta hanh vi e
s dung cho moi thc the, giong nh danh sach liet ke cac phan mo ta s dung cho moi thanh phan
trong thiet ke.
Package (goi) mot goi la mot tap hp cac loai d lieu c dung pho bien va cac chng
trnh con (subprogram) c s dung trong thiet ke. Xem package nh la mot hop cong cu cha
nhieu cong cu c dung e xay dng cac thiet ke.
Driver (nguon kch) la nguon kch cua mot tn hieu. Neu mot tn hieu c kch bi hai
nguon, th ca hai nguon eu mc tch cc, khi o ta xem tn hieu co 2 driver.
Bus (nhom tn hieu) thuat ng bus xem mot nhom cac tn hieu hoac mot phng phap
truyen thong ac biet c s dung trong thiet ke phan cng. Trong VHDL, bus la loai tn hieu ac
biet co nhieu nguon kch trang thai tat.
Attribute (thuoc tnh) la d lieu c gan cho cac oi tng VHDL hoac d lieu a nh
ngha trc lien quan en cac oi tng VHDL. V du la kha nang kch dong cua mot mach em
hoac nhiet o hoat ong cc ai cua linh kien.
Generic la thuat ng cua VHDL dung cho mot thong so, thong so nay chuyen thong tin en
mot thc the. Th du, neu mot thc the la mot mo hnh cong co tr hoan canh len va tr hoan canh
xuong, cac gia tr cua cac tr hoan len va xuong co the c chuyen vao trong thc the bang cac
dung generic.
Process (qua trnh) qua trnh la mot n v thc thi c ban trong VHDL. Tat ca cac hoat ong
c thc hien trong mo phong cua mot mo ta VHDL th c chia ra thanh mot hoac nhieu
qua trnh x ly.
III. MO TA PHAN CNG TRONG VHDL
Cac mo ta VHDL cha nhieu n v thiet ke s cap va nhieu n v thiet ke th cap.
n v thiet ke s cap la thc the (Entity) va goi (Package).
n v thiet ke th cap la cau hnh (Configuration) va than goi (Package Body).
Cac n v thiet ke th cap th luon co moi lien he vi n v thiet ke s cap. Cac th vien
cha nhieu cac n v thiet ke s cap va th cap.
1. ENTITY (THC THE )
Entity dung e khai bao ten cua thc the, cac port cua thc the va cac thong tin lien quan en
thc the. Tat ca cac thiet ke c xay dng dung mot hoac nhieu thc the.
V du 2_1: Khai bao n gian ve thc the:
ENTITY mux IS
PORT (a, b, c, d: IN BIT;
s0, s1: IN BIT;
x: OUT BIT);
END mux;
T khoa ENTITY bao cho biet bat au mot phat bieu thc the.
Trong cac mo ta c trnh bay trong toan bo tai lieu, cac t khoa cua ngon ng va cac loai
d lieu c cung cap cho goi chuan (STANDARD) th c trnh bay dang ch hoa. V du:
trong v du a trnh bay th cac t khoa la ENTITY, IS, PORT, IN, INOUT, Loai d lieu chuan
la BIT. Ten cua cac oi tng do ngi dung nh ngha v du nh mux trong v du tren la dang
ch thng.
Ten cua thc the la mux. Thc the co 7 port trong cau lenh khai bao PORT 6 port cho kieu
IN va 1 port cho kieu OUT. 4 port d lieu ngo vao (a, b, c, d) la dang BIT. Hai ngo vao la chon
mach a hp (s0, s1) cung thuoc kieu d lieu BIT. Ngo ra cung la BIT.
Thc the mo ta giao tiep vi the gii ben ngoai. Thc the ch nh ro bao nhieu port, hng
tn hieu cua port va loai d lieu cua port.
2. ARCHITECTURE (KIEN TRUC)
Thc the mo ta giao tiep vi mo hnh VHDL.
Kien truc mo ta chc nang c ban cua thc the va cha nhieu phat bieu mo phong hanh vi
cua thc the. Kien truc luon luon co lien quan en thc the va cac mo ta hanh vi cua thc the.
Mot kien truc cua bo a hp tren co dang nh sau:
ARCHITECTURE dataflow OF mux IS
SIGNAL select: INTEGER;
BEGIN
Select <= 0 WHEN s0 = 0 AND s1= 0 ELSE
1 WHEN s0 = 1 AND s1= 0 ELSE
2 WHEN s0 = 0 AND s1= 1 ELSE
3;
x <= a AFTER 0.5 NS WHEN select = 0 ELSE
b AFTER 0.5 NS WHEN select = 1 ELSE
c AFTER 0.5 NS WHEN select = 2 ELSE
d AFTER 0.5 NS ;
END dataflow;
T khoa ARCHITECTURE cho biet phat bieu nay mo ta kien truc cho mot thc the. Ten
cua kien truc la dataflow. Kien truc cua thc the ang c mo ta c goi la mux.
Ly do cho ket noi gia thc the va kien truc la mot thc the co the co nhieu kien truc mo ta
hanh vi cua thc the. V du mot kien truc co the la mot mo ta hanh vi va mot kien truc khac co the
la mo ta cau truc.
Vung ky t nam gia t khoa ARCHITECURE va t khoa BEGIN la ni khai bao cac phan
t va cac tn hieu logic cuc bo e sau nay dung. Trong v du tren bien tn hieu select c khai bao
la tn hieu cuc bo.
Vung cha cac phat bieu cua kien truc bat au vi t khoa BEGIN. Tat ca cac phat bieu
nam gia cac cau lenh BEGIN va END c goi la cac phat bieu ong thi bi v tat ca cac phat
bieu c thc hien cung mot luc.
a. Gan Cac Tn Hieu ong Thi
Trong ngon ng lap trnh thong thng nh C hoac C++ th moi phat bieu gan thc hien mot
lan sau mot phat bieu gan khac va theo mot th t c ch nh. Th t thc hien c xac nh
bi th t cua cac phat bieu trong file chng trnh nguon.
Trong kien truc VHDL th khong co th t ch nh nao cho cac phat bieu gan. Th t thc
hien c ch nh ro bi s kien xay ra tren tn hieu ma phat bieu gan hng en.
Khao sat phat bieu gan au tien c trnh bay nh sau:
Hai phat bieu gan tn hieu trong kien truc behave hnh thanh mo hnh hanh vi (behavioral
model), hoac kien truc cho thc the mux.
Kien truc dataflow th khong co cau truc.
3. CAC THIET KE CO CAU TRUC (STRUCTURAL DESIGNS)
Mot cach khac e viet thiet ke mux la xay dng cac thanh phan phu ma chung thc hien cac
hoat ong nho hn cua mo hnh ay u. Vi mo hnh n gian nhat cua mach a hp 4 ngo vao
nh chung ta a dung la mo ta cap o cong n gian.
Kien truc c trnh bay sau ay la mo ta cau truc cua thc the mux.
ARCHITECTURE netlist OF mux IS
COMPONENT andgate
PORT(a, b, c: IN BIT; x: OUT BIT);
END COMPONENT;
COMPONENT inverter
PORT(in1: IN BIT; x: OUT BIT);
END COMPONENT;
COMPONENT orgate
PORT(a, b, c, d: IN BIT; x: OUT BIT);
END COMPONENT;
SIGNAL s0_inv, s1_inv, x1, x2, x3, x4: BIT;
BEGIN
U1: inverter (s0, s0_inv);
U2: inverter (s1, s1_inv);
U3: andgate (a, s0_inv, s1_inv, x1);
U4: andgate (b, s0, s1_inv, x2);
U5: andgate (c, s0_inv, s1, x3);
U6: andgate (d, s0, s1, x4);
U7: orgate (x2 => b, x1 => a, x4 => d, x3 => c, x => x);
END netlist;
Mo ta nay s dung mot so cac thanh phan mc thap hn e mo hnh hoa hanh vi cua thiet b
mux. Co mot thanh phan cong ao inverter, mot thanh phan cong andgate, va mot thanh phan
orgate. Mot trong cac thanh phan nay c khai bao trong phan khai bao kien truc nam gia cau
lenh kien truc va BEGIN.
Mot so cac tn hieu c dung e ket noi mot trong cac thanh phan e thanh lap mo ta kien
truc. Cac loai tn hieu nay c khai bao dung khai bao SIGNAL.
Vung cha phat bieu kien truc c thiet lap tai v tr ngay sau t khoa BEGIN. Trong v du
nay co mot so phat bieu cua cac thanh phan. Cac thanh phan nay c at ten la U1U7.
Phat bieu U1 la phat bieu cho cong ao. Phat bieu nay noi port s0 vi port ngo vao cua thanh
phan cong ao va tn hieu s0_inv vi port ngo ra cua thanh phan cong ao.
Ket qua la port in1 cua cong ao th c noi ti port s0 cua thc the mux va port x cua cong
ao c noi ti tn hieu cuc bo s0_inv. Trong phat bieu nay th cac port c noi ti theo th t
ma chung xuat hien trong phat bieu.
Chu y phat bieu thanh phan U7 phat bieu nay dung cac k hieu nh sau:
U7: orgate (x2 => b, x1 => a, x4 => d, x3 => c, x => x);
Phat bieu nay ket hp cac ten e tng thch vi cac port. V du port x2 cua cong orgate th
c noi ti port b cua thc the cua phat bieu ket hp au tien. S ket hp va th t co the khong
theo th t nhng khong nen thc hien.
4. HOAT ONG TUAN T (SEQUENTIAL BEHAVIOR)
Co mot cach khac e mo ta chc nang cua thiet b mux trong ngon ng VHDL. Thc ra ngon
ng VHDL co nhieu cach trnh bay cho chc nang vi ket qua tng t. Cach th 3 e mo ta chc
nang cua mux la s dung phat bieu qua trnh (process) e mo ta chc nang trnh bay theo thuat
toan. Cach nay c dung cho kien truc sequential nh sau:
ARCHITECTURE sequential OF mux IS
PROCESS (a, b, c, d, s0, s1)
VARIABLE sel: INTEGER;
BEGIN
IF s0 = 0 and s1 = 0 THEN sel:= 0 ;
ELSIF s0 = 1 and s1 = 0 THEN sel:= 1 ;
ELSIF s0 = 0 and s1 = 1 THEN sel:= 2 ;
ELSE sel:= 3 ;
END IF;
CASE sel IS
WHEN 0 => x <= a ;
WHEN 1 => x <= b ;
WHEN 2 => x <= c ;
WHEN OTHERS => x <= d ;
END CASE;
END PROCESS;
END sequential;
Kien truc nay ch cha 1 phat bieu duy nhat c goi la phat bieu qua trnh (process). c
bat au vi hang co t khoa PROCESS va ket thuc vi hang co t khoa END PROCESS. Tat ca
cac phat bieu nam gia hai hang tren c xem thanh phan cua phat bieu qua trnh.
a. Cac phat bieu qua trnh
Phat bieu qua trnh cha nhieu thanh phan.
Thanh phan th nhat c goi la danh sach cac phan t nhay.
Thanh phan th hai c goi la thanh phan khai bao qua trnh.
Thanh phan th 3 la cac phat bieu.
Trong v du tren th danh sach liet ke cac tn hieu nam trong dau ngoac sau t khoa
PROCESS c goi la danh sach nhay. Danh sach nay liet ke chnh xac nhng tn hieu lam cho
phat bieu qua trnh c thc hien. Trong v du nay th danh sach cha cac tn hieu la a, b, c, d, s0
va s1. Ch co nhng s kien xay ra tren cac tn hieu nay lam cho phat bieu qua trnh c thc
hien.
Cach e la chon gia 2 phng phap nay co the lam nay sinh mot cau khoi ve kieu lap
trnh. Ngi xay dng mo hnh thch viet chng trnh VHDL theo kieu ong thi hay theo kieu
trnh t?
Neu ngi xay dng mo hnh muon viet ma VHDL kieu ong thi th phai chon kieu kien
truc dataflow, ngc lai th chon kieu kien truc sequential. Thng th ngi xay dng mo hnh
quen vi kieu lap trnh tuan t nhng kieu ong thi la nhng cong cu manh e viet cho cac mo
hnh nho hieu suat cao.
6. CAC PHAT BIEU CAU HNH
Mot thc the co the co nhieu hn mot kien truc nhng lam the nao e ngi xay dng mo
hnh chon kien truc nao e s dung trong mo phong a cho. Phat bieu cau hnh sap xep cac thuyet
minh thanh phan cho thc the. Vi kha nang manh cua cau hnh ngi xay dng mo hnh co the
c la chon dung xay dng mo hnh cho thc the tai moi cap o trong thiet ke.
Chung ta se xem xet phat bieu cau hnh dung kien truc liet ke cua thc the mux.
V du 2-2: Phat bieu hnh nh sau:
CONFIGURATION muxcon1 OF mux IS
FOR netlist
FOR U1, U2: Inverter USE ENTITY WORK.myinv (version1);
END FOR;
FOR U3, U4, U5, U6: andgate USE ENTITY WORK.myand (version1);
END FOR;
END muxcon1;
Chc nang cua phat bieu cau hnh la dien ta chnh xac kien truc nao dung cho moi thanh
phan trong mo hnh. ieu nay xay ra kieu he thong co cap bac. Thc the co cap bac cao nhat
trong thiet ke can co kien truc e s dung cho cac ch nh cung nh bat ky thanh phan nao can
c thuyet minh trong thiet ke.
Bat au phat bieu cau hnh la ten cua cau hnh muxcon1 cho thc the mux. S dung kien
truc netlist nh la kien truc cho thc the cap cao nhat o la mux.
oi vi 2 thanh phan U1 va U2 cua cong ao inverter c thuyet minh cho kien truc
netlist, s dung thc the myinv, kien truc version1 t th vien c goi la WORK.
oi vi cac thanh phan U3 U6 cua and andgate, dung thc the myand, kien truc version1
t th vien WORK.
oi vi thanh phan U7 cua cong orgate s dung thc the myor, kien truc version1 t th
vien WORK.
Tat ca cac thc the bay gi eu co cac kien truc c ch nh cho chung. Thc the mux co
kien truc netlist va cac thanh phan khac co kien truc c at ten ch nh version1.
SC MANH CUA CAU HNH
Khi bien dch cac thc the, cac kien truc va cau hnh a ch nh trc th co the xay dng mo
hnh co the mo phong. Nhng ieu g se xay ra neu khong muon mo phong cap o cong? Va neu
muon dung kien truc BEHAVE thay the. Sc manh cua cau hnh cho phep ban khong can bien
dch lai toan bo thiet ke ma ch can bien dch lai cau hnh mi.
V du 2-3: Cho cau hnh nh sau:
CONFIGURATION muxcon2 OF mux IS
FOR dataflow
END FOR;
END muxcon2;
Cau hnh nay co ten la muxcon2 cho thc the mux. S dung kien truc dataflow cho thc the
cap cao nhat la mux. Khi bien dch cau hnh nay th kien truc dataflow c la chon cho thc the
mux trong mo phong.
Cau hnh nay khong can thiet trong VHDL chuan nhng cung cap cho ngi thiet ke s t do
e ch nh chnh xac kien truc nao se c dung cho thc the. Kien truc mac nhien c dung cho
thc the la kien truc sau cung c bien dch cho vao th viec lam viec.
7. TOM TAT
Trong phan nay a gii thieu c ban ve VHDL va cach s dung ngon ng e xay dng mo
hnh hanh vi cua thiet b va thiet ke. V du th nhat a trnh bay cach xay dng mo hnh dataflow
n gian trong VHDL c ch ro. V du th 2 trnh bay cach mot thiet ke ln co the c thc
hien t nhng thiet ke nho hn trong trng hp nay bo a hp 4 ngo vao a c xay dng
dung cac cong AND, OR, va INVERTER. V du nay cung cap tong quan cau truc cua VHDL.
IV. GII THIEU VE MO HNH HANH VI
Phat bieu gan tn hieu la dang c ban nhat cua mo hnh hanh vi trong VHDL.
V du 2-4: Phat bieu gan tn hieu nh sau:
a <= b;
Phat bieu nay c oc nh sau: a co gia tr cua b. Ket qua cua phat bieu gan nay la gia tr
hien tai cua b c gan cho tn hieu a. Phat bieu gan nay c thc hien bat ky luc nao tn hieu b
thay oi gia tr. Tn hieu b nam trong danh sach nhay cua cau lenh nay. Bat ky tn hieu nao trong
danh sach nhay cua phat bieu gan tn hieu thay oi gia tr th phat bieu gan tn hieu c thc
hien.
Neu ket qua thc hien co gia tr mi khac vi gia tr trc o th sau mot thi gian tre th tn
hieu se xuat hien tai tn hieu ch.
Neu ket qua thc hien co cung gia tr th se khong co thi gian tre tn hieu nhng s chuyen
trang thai van c tao ra. S chuyen trang thai luon c tao ra khi mo hnh c anh gia nhng
ch nhng tn hieu co gia tr thay oi mi co s kien tre.
Phat bieu sau se gii thieu ve phat bieu gan tn hieu sau mot thi gian tre:
a <= b AFTER 10 ns;
Phat bieu nay c oc la a co gia tr cua b sau thi gian tre 10 ns
Ca hai phat bieu eu la cac phat bieu gan tn hieu ong thi, va nhay vi s thay oi gia tr
cua tn hieu b. Khi b thay oi gia tr th cac phat bieu gan thc hien va gia tr mi c gan cho gia
tr cua tn hieu a.
V du 2-5: Phat bieu gan tn hieu ong thi cho mo hnh cong AND nh sau:
ENTITY and2 IS
PORT (a, b: IN BIT;
c: OUT BIT);
END and2;
ARCHITECTURE and2_behav OF and2 IS
BEGIN
c <= a AND b AFTER 5 ns;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux4 IS
PORT (I0, I1, I2, I3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux4;
Ky thuat PLD va ASIC 61
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
B A Q
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Hnh 2-3. Bang trang thai cua mux co 4 ngo vao.
Bieu thc (gia tr sel trong v du nay) c anh gia va phat bieu ma no tng thch vi gia
tr cua bieu thc c gan gia tr cho tn hieu ch. Tat ca cac gia tr co the co cua bieu thc phai
co s la chon tng thch trong cach gan tn hieu a la chon.
Moi mot tn hieu ngo vao co the c gan cho ngo ra q tuy thuoc vao cac gia tr cua 2 ngo
vao a va b. Neu cac gia tr cua a va b khong xac nh th gia tr sau cung X (khong xac nh)
c gan cho ngo ra q. Trong v du nay, khi cac ngo vao la chon gia tr khong xac nh th ngo
ra c gan cho gia tr khong xac nh.
Phat bieu th hai nhay vi cac tn hieu a va b. Bat ky luc nao khi a hoac b thay oi gia tr,
phat bieu gan th hai c thc hien va tn hieu sel c cap nhat. Phat bieu th 1 nhay vi tn
hieu sel. Khi tn hieu sel thay oi gia tr th gan tn hieu tn hieu th nhat c thc hien.
Neu v du nay c x ly bi cong cu tong hp, th ket qua cau truc cong c xay dng
giong nh mot bo a hp 4 ng sang 1 ng. Neu th vien tong hp cha bo a hp 4 ng
sang 1 ng th bo a hp nay co the c cap phat da vao s phc tap cua cong cu tong hp va
at vao trong thiet ke.
1. DELAY QUAN TNH VA DELAY TRUYEN
Trong VHDL co 2 loai delay co the dung cho mo hnh hanh vi. Delay quan tnh th c s
dung pho bien, trong khi delay truyen c s dung nhng ni ma mo hnh delay day dan c
yeu cau.
a. Delay quan tnh:
Delay quan tnh la mac nhien trong VHDL. Neu khong co kieu delay c ch nh th delay
quan tnh c s dung. Delay quan tnh la delay mac nhien bi v trong hau het cac trng hp th
no thc hien giong nh thiet b thc.
Gia tr cua delay quan tnh bang vi delay trong thiet b.
Neu bat ky xung tn hieu co chu ky vi thi gian cua tn hieu ngan hn thi gian delay cua
thiet b th gia tr tn hieu ngo ra khong thay oi.
Neu thi gian cua tn hieu c duy tr mot gia tr ac biet dai hn thi gian delay cua thiet
b th delay quan tnh se c khac phuc va thiet b se thay oi sang trang thai mi.
Hnh 2-4 la mot v du ve k hieu bo em rat n gian co 1 ngo vao A va mot ngo ra B, dang
song c trnh bay cho tn hieu ngo vao A va ngo ra B.
Tn hieu A thay oi t 0 sang 1 tai moc thi gian 10ns va t 1 sang 0 tai moc thi gian
20ns. Vi cac khoang thi gian nay cho phep xay dng mot xung hoac xung nhon co thi gian nho
hn 10ns. Cho bo em co thi gian tre la 20ns.
Chuyen trang thai t 0 sang 1 tren tn hieu A lam cho mo hnh bo em c thc hien va
theo d kien th gia tr 1 xuat hien ngo ra B tai moc thi gian 30ns.
moc thi gian 20ns, s kien tiep theo tren tn hieu A xay ra (tn hieu a xuong mc 0) th
mo hnh bo em d kien mot s kien mi se xay ra tren ngo ra B co gia tr 0 tai moc thi gian
40ns. Trong khi o s kien a d kien ngo ra B cho moc thi gian 30ns van cha xay ra. S kien
mi c d oan bi mo hnh bo em xung ot vi s kien trc va trnh mo phong u tien cho s
kien co moc thi gian 30ns.
Ket qua cua viec u tien la xung b nuot (mat). Ly do xung b nuot la tuy thuoc vao mo hnh
delay quan tnh, s kien th nhat tai moc thi gian 30ns cha co u thi gian e hoan thanh delay
quan tnh cua tn hieu ngo ra.
Mo hnh thi gian delay quan tnh thng c s dung trong tat ca cac trnh mo phong.
Trong hau het cac trng hp mo hnh delay quan tnh u chnh xac cho cac yeu cau cua ngi
thiet ke. Mot trong nhng ly do cho viec m rong s dung thi gian delay quan tnh la no ngan
chan thi gian tr hoan cua xung xuyen qua thiet b.
ENTITY buf IS
PORT (a: IN STD_LOGIC;
b: OUT STD_LOGIC);
END buf;
ENTITY delay_line IS
PORT (a: IN STD_LOGIC;
b: OUT STD_LOGIC);
END delay_line;
Mach ien gom co mot cong ao, mot cong NAND va mot cong AND thuc ngo vao ong ho
cua thanh phan flip flop. Cong NAND va cong AND c dung e gac ngo vao xung clock en flip
flop.
Chung ta se khao sat hoat ong cua mach dung c cau delay delta va c cau khac. Bang cach
kiem tra 2 c cau delay chung ta se hieu ro hn cach delay delta sap xep cac s kien.
Time Delta
10 ns (1) A <= 0
Evaluate inverter
(2) B <= 1
Evaluate AND
Evaluate NAND
(3) D <= 1
C <= 0
Evaluate AND
(4) D <= 0
11 ns
Hnh 2-8. C cau anh gia delay delta.
iem thi gian delta au tien cua 10ns, tn hieu A nhan gia tr 0. Gia tr nay lam cho cong
ao c anh gia lai vi gia tr mi. Tn hieu ngo ra cong ao B co gia tr la 1. Gia tr nay
khong truyen ngay lap tc ma ch cho en iem thi gian delta th 2.
Sau o trnh mo phong bat au thc hien iem thi gian delta th 2. Tn hieu B c cap nhat
gia tr la 1 va cong AND va cong NAND c anh gia lai. Ca hai cong AND va NAND phai
ch cac gia tr mi iem thi gian delta th 3.
Khi iem thi gian delta th 3 xay ra, tn hieu D nhan gia tr la 1 va tn hieu C nhan gia tr
la 0. Do tn hieu C cung thuc cong AND, cong AND c anh gia lai va ch ket qua ngo ra
iem thi gian delta th 4. Cuoi cung ngo ra D bang 0.
Tom lai mo phong delta la lng thi gian vo cung nho c dung nh mot c cau ong bo
khi cac s kien delay zero xuat hien. Delay delta c dung khi delay zero c ch nh va trnh
bay nh sau:
Ky thuat PLD va ASIC 67
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
Phat bieu th hai tao ra mot driver cha gia tr cua tn hieu c c tr hoan 10 ns.
Nhng ngi thiet ke s dung VHDL khong muon tuy y them vao cac rang buoc ngon ng
oi vi hanh vi cua tn hieu. Khi tong hp v du tren se noi tat b va c vi nhau.
b. Mo hnh nhieu driver xau:
Ta hay khao sat mot mo hnh thoat nhn co ve ung nhng lai khong thc hien chc nang nh
ngi s dung d nh. Mo hnh nay s dung mot mach a hp 4 ng sang 1 ng a thao luan:
USE IEEE.std_logic_1164.ALL;
ENTITY mux4 IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux4;
Generic la mot c cau tong quat c dung e chuyen thong tin en thc the. Thong tin c
chuyen en thc the la mot trong cac kieu c VHDL cho phep.
Generic cung co the c dung e chuyen cac kieu d lieu bat ky do ngi thiet ke nh
ngha bao gom cac thong tin nh ien dung tai, ien tr, Cac thong so tong hp nh o rong
ng d lieu, o rong tn hieu, co the chuyen c di dang cac generic.
Tat ca d lieu c chuyen en mot thc the la cac thong tin ro rang. Cac gia tr d lieu co
lien quan en instance ang c truyen d lieu. phng phap nay, ngi thiet ke co the truyen
cac gia tr khac nhau en cac instance khac nhau trong thiet ke.
D lieu c truyen en instance la d lieu tnh. Sau khi mo hnh c cho them chi tiet (lien
ket vi trnh mo phong), d lieu se khong thay oi trong thi gian mo phong. Cac generic khong
the c gan thong tin cho cac thanh phan chay chng trnh mo phong. Thong tin cha trong cac
generic c chuyen en instance thanh phan hoac mot khoi co the c s dung e thay oi cac
ket qua trong mo phong, nhng cac ket qua khong the sa oi cac generic.
V du 2-8: thc the cong AND co 3 generic ket hp:
ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal BIT;
BEGIN
internal <= a AND b;
c <= Internal AFTER (rise + (load*2 ns)) Internal = 1 ELSE Internal
AFTER (rise + (load*3 ns));
END load_dependent;
Kien truc nay khai bao mot tn hieu cuc bo goi la internal e lu gia tr cua bieu thc a va b.
Cac gia tr tnh toan trc dung cho nhieu instance la mot phng phap rat hieu qua cho viec xay
dng mo hnh.
Cac generic rise, fall va load cha cac gia tr a c chuyen vao bi phat bieu cua instance
thanh phan. Ta hay khao sat mot phan cua mo hnh ma no the hien cac thanh phan loai AND2
trong mot cau truc khac:
ENTITY test IS
GENERIC (rise, fall: TIME; load: INTEGER);
PORT (ina, inb, inc, ind: IN STD_LOGIC;
Out1, out2: OUT STD_LOGIC);
END test;
Tiep theo, than cua phat bieu kien truc cha hai phat bieu the hien thanh phan cua cac thanh
phan U1 va U2. Port a cua thanh phan U1 c anh xa en tn hieu ina, port b c anh xa en tn
hieu inb va port c c anh xa en tn hieu out1. Cung phong phap nh vay thanh phan U2 c
anh xa en cac tn hieu inc, ind va out2.
Generic rise cua the hien U1 c anh xa en 10ns, generic fall c anh xa en 12ns va
generic load c anh xa en 3. Cac generic cua thanh phan U2 c anh xa en cac gia tr 9 ns,
11ns va gia tr 5.
Cac generic cung co the co gia tr mac nh, cac gia tr nay c ghi e neu cac gia tr thc
te c anh xa en cac generic. V du tiep theo trnh bay hai the hien thanh phan loai AND2.
Trong thanh phan U1, gia tr thc te c anh xa en generic va cac gia tr nay c dung e
ieu khien hanh vi mo phong neu c ch nh ro, ngc lai se phat sinh loi.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY test IS
GENERIC (rise, fall: TIME; load: INTEGER);
PORT (ina, inb, inc, ind: IN STD_LOGIC;
Out1, out2: OUT STD_LOGIC);
END test;
package bit32 IS
TYPE tw32 IS ARRAY ( 31 downto 0 ) OF std_logic;
END bit32;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.bit32.ALL;
ENTITY cpu IS
PORT (clk, interrupt: IN STD_LOGIC;
addr: OUT tw32;
data: INOUT tw32;);
END cpu;
REG8: BLOCK
SIGNAL zbus: tw32;
BEGIN
REG1: BLOCK
SIGNAL qbus: tw32;
BEGIN
-- REG1 behavior stataments
END BLOCK REG1;
-- more REG8 stataments
cac khoi co cap mc o cao hn th khong the truy xuat en cac tn hieu cuc bo cua khoi cap thap
hn.
Tn hieu qbus c khai bao trong phan khai bao khoi cua khoi ALU. Tn hieu nay la tn hieu
cuc bo cho khoi ALU va cac khoi ben ngoai khong the truy xuat. Tat ca cac phat bieu nam ben
trong khoi ALU co the truy xuat qbus, nhng cac phat bieu ben ngoai khoi ALU th khong the
dung qbus.
Tng t, tn hieu zbus cho khoi REG8. Khoi REG1 nam ben trong khoi REG8 co the truy
xuat tn hieu zbus va tat ca cac phat bieu khac trong khoi REG8 cung co the truy xuat tn hieu
zbus.
Trong phan khai bao cua khoi REG1 con khai bao mot tn hieu khac goi la qbus. Tn hieu
nay co cung ten vi tn hieu qbus c khai bao trong khoi ALU ieu nay co gay ra xung ot g
khong ? oi vi chng trnh chng trnh bien dch th hai tn hieu nay la oc lap. Hai tn hieu nay
c khai bao trong hai vung khac nhau va ch co hieu lc cho vung o.
Mot trng hp khac long vao nhau nh sau:
BLK1: BLOCK
SIGNAL qbus: tw32;
BEGIN
BLK2: BLOCK
SIGNAL qbus: tw32;
BEGIN
-- blk2 stataments
END BLOCK BLK2;
-- blk1 stataments
END BLOCK BLK1;
Trong v du nay, tn hieu qbus c khai bao trong 2 khoi. Cau truc long vao nhau trong mo
hnh nay la mot khoi co cha mot khoi khac.
Khoi BLK2 truy xuat 2 tn hieu c goi la qbus: tn hieu qbus th nhat khai bao trong BLK2
va tn hieu qbus th 2 khai bao trong BLK1. Khoi BLK1 la cha cua khoi BLK2. Tuy nhien, khoi
BLK2 xem tn hieu qbus nam trong chnh no, nhng tn hieu qbus cua khoi BLK1 se b ghi e bi
khai bao cung ten cua tn hieu khoi BLK2.
Tn hieu qbus t BLK1 co the c nhn thay ben trong khoi BLK2, neu ten cua tn hieu
qbus c bo sung them bang ten cua khoi. Cu the cho v du tren, e truy xuat tn hieu qbus t
khoi BLK1 th dung BLK1.qbus.
Nh a e cap tren, cac khoi cha cac vung cua mo hnh ben trong no. Nhng cac khoi la
duy nhat bi v mot khoi co the cha cac port va cac generic. ieu nay cho phep ngi thiet ke
anh xa lai cac tn hieu va cac generic ben ngoai en cac tn hieu va generic nam ben trong khoi.
Nhng tai sao ngi thiet ke muon lam ieu nay.
Dung lng cua cac port va cac generic trong mot khoi cho phep ngi thiet ke dung lai cac
khoi a viet cho muc ch khac trong thiet ke mi.
Gia s ta muon cai tien thiet ke CPU va can m rong them chc nang cho khoi ALU, va ta
gia s rang mot ngi thiet ke khac co khoi ALU mi co the thc hien c cac chc nang ma ta
can th van e ch con la hieu chnh lai ten cua cac port va cac generic cho tng thch vi khoi
mi la xong. Phai anh xa cac ten cua tn hieu va cac thong so generic trong thiet ke ang cai tien
vi cac port va cac generic a xay dng cua khoi ALU mi.
V du 2-10: minh hoa cho s cai tien:
package math IS
TYPE tw32 IS ARRAY ( 31 downto 0 ) OF std_logic;
FUNCTIOB tw_add(a,b; tw32) RETURN tw32;
FUNCTIOB tw_sub(a,b; tw32) RETURN tw32;
END math;
USE WORK.math.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cpu IS
PORT (clk, interrupt: IN STD_LOGIC;
addr: OUT tw32;
cont : IN INTEGER;
data: INOUT tw32);
END cpu;
Anh xa co ngha la ket noi gia port va tn hieu ben ngoai chang han nh khi co mot s thay
oi gia tr tren mot tn hieu noi en 1 port th port se thay oi sang gia tr mi. Neu s thay oi xay
ra trong tn hieu ibus th gia tr mi cua ibus c truyen vao khoi ALU va port abus se co gia tr
mi. Tng t cho tat ca cac port.
Cac khoi co bao ve
Cac phat bieu khoi co khoi hanh vi long vao ben trong c xem nh nhng khoi co bao ve.
Mot khoi co bao ve cha mot bieu thc bao ve co the cho phep va khong cho phep cac driver
ben trong khoi.
Bieu thc bao ve la bieu thc ai so boolean: neu bang true th cac driver ben trong khoi
c phep va neu bang false th cac driver b cam.
Chung ta se khao sat v du 2-11:
V du 2-11: co khoi bao ve
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY latch IS
PORT (d, clk: IN STD_LOGIC;
q, qb: OUT STD_LOGIC);
END latch;
Khi port clk cua thc the co gia tr la 1 th bieu thc bao ve co gia tr la true va khi gia tr
cua ngo vao d se xuat hien ngo ra q sau khoang thi gian tre 7ns.
Khi port clk co gia tr la 0 hoac bat ky gia tr nao khac hp le cua kieu d lieu th ngo ra q
va qb chuyen sang tat va gia tr ngo ra cua tn hieu c xac nh bi gia tr c gan cho mot gia
tr mac nh bi ham phan giai. Khi clk khong bang 1 th cac driver c xay dng cho cac lenh
gan tn hieu q va qb trong kien truc se chuyen sang tat. Cac driver khong tham gia vao gia tr tong
the cua tn hieu.
Gan tn hieu co the c bao ve bang cach dung t khoa GUARDED. Tn hieu mi c
khai bao hoan toan trong khoi khi khoi co bieu thc bao ve. Tn hieu nay c goi la GUARD.
Gia tr cua no la gia tr cua bieu thc bao ve. Tn hieu nay co the c dung e cac x ly khac xay
ra.
Cac khoi rat tien li e chia nho thiet ke thanh cac khoi nho hn, cac n v de quan ly hn.
Chung cho phep ngi thiet ke s mem deo e xay dng nhng thiet ke ln t nhng khoi nho hn
va cung cap phng phap thuan tien cho ieu khien cac driver oi vi tn hieu.
6. TOM TAT
Cach gan tn hieu la dang c ban nhat cua mo hnh hanh vi.
Phat bieu gan tn hieu co the c la chon tuy vao ieu kien.
Phat bieu gan tn hieu co the cha thi gian tre.
VHDL cha tr hoan tre quan tnh va tr hoan truyen.
Cac iem thi gian mo phong delta dung e cac s kien hoat ong ung thi gian.
Cac driver cho mot tn hieu c xay dng bi cac phat bieu gan tn hieu.
Generic c dung e truyen d lieu cho thc the.
Cac phat bieu khoi cho phep xay dng nhom trong cung mot thc the.
Cac phat bieu khoi bao ve cho phep kha nang tat cac driver trong mot khoi.
V. X LY TUAN T
phan trc chung ta a khao sat mo hnh hanh vi dung cac phat bieu ong thi. Chung ta
a thao luan cac phat bieu gan ong thi cung nh cac phat bieu khoi va the hien thanh phan.
Trong phan nay chung ta tap trung cho phat bieu tuan t. Cac phat bieu tuan t la cac phat
bieu thc hien noi tiep nhau.
1. PHAT BIEU
Trong mot kien truc cua mot thc the, tat ca cac phat bieu la ong thi. Vay th cac phat bieu
tuan t ton tai au trong VHDL ?
Co mot phat bieu c goi la phat bieu qua trnh ch cha cac phat bieu tuan t. Phat bieu
qua trnh cung chnh la phat bieu ong thi. Phat bieu qua trnh co the ton tai trong kien truc va
nhng vung xac nh trong kien truc ni cha cac lenh tuan t.
Phat bieu qua trnh co phan khai bao va phan phat bieu. Trong phan khai bao th cac kieu,
cac bien, cac hang so, cac chng trnh con, , co the c khai bao. Phan phat bieu ch cha cac
phat bieu tuan t. Cac phat bieu tuan t cha cac phat bieu CASE, phat bieu IF THEN ELSE,
phat bieu LOOP,
ENTITY nand2 IS
PORT (a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END nand2;
B A Q
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Hnh 2-9. K hieu mach a hp va bang trang thai.
Mo hnh th nhat la mo hnh khong ung va mo hnh th hai la mo hnh ung.
a. V du mo hnh mach a hp khong ung
Mo hnh khong ung cua bo a hp co thieu sot lam cho mo hnh hoat ong khong ung. Mo
hnh nay c trnh bay nh sau:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux;
CASE muxval IS
WHEN 0 => q <= I0 AFTER 10 ns;
WHEN 1 => q <= I1 AFTER 10 ns;
WHEN 2 => q <= I2 AFTER 10 ns;
WHEN 3 => q <= I3 AFTER 10 ns;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END wrong;
Khi co 1 trong cac tn hieu ngo vao nam trong danh sach nhay thay oi gia tr th cac phat
bieu tuan t c thc hien.
Phat bieu qua trnh trong v du nay cha 4 phat bieu tuan t.
Phat bieu th nhat khi tao tn hieu cuc bo muxval vi gia tr 0. Cac phat bieu tuan t con
cong gia tr cho tn hieu tuy thuoc vao cua cac tn hieu vao a va b.
Phat bieu case cuoi cung la chon mot ngo vao e truyen en ngo ra tuy thuoc vao gia tr
cua tn hieu muxval. Mo hnh nay co mot thieu sot nghiem trong vi phat bieu: muxval <=0; lam
cho gia tr 0 c sap xep nh mot s kien oi vi tn hieu muxval. Thc te th gia tr 0 c sap
xep trong mot s kien cho thi gian tre delta e mo phong bi v khong co thi gian tr hoan.
Khi phat bieu th 2:
IF (a = 1 ) THEN muxval <= muxval + 1;
END IF;
c thc hien, gia tr cua tn hieu muxval la gia tr c truyen lan cuoi cung. Gia tr mi
a sap xep t phat bieu th nhat cha c truyen en. Trong thc te th khi nhieu phep gan cho
tn hieu xay ra trong cung phat bieu qua trnh th gia tr gan sau cung la gia tr c truyen.
Tn hieu muxval co gia tr vo ngha (khong xac nh) khi bat au qua trnh. Gia tr cua
muxval khong thay oi cho en khi cac phat bieu nam trong qua trnh c thc hien xong. Neu
tn hieu b co gia tr la 1 th sau o gia tr vo ngha c cong them vi 2.
V du tiep theo se chat che hn. S khac nhau gia 2 mo hnh cua 2 v du la khai bao muxval
va phep gan cho mulval. Trong mo hnh v du trc, muxval la tn hieu va phat bieu gan tn hieu
c dung e gan gia tr cho muxval. Trong mo hnh v du nay th muxval la bien va phep gan
bien c dung e gan gia tr cho muxval.
b. V du mo hnh mach a hp ung
Trong v du nay th mo hnh khong ung tren c viet lai e cho thay cach giai quyet van
e cua mo hnh khong ung:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux;
CASE muxval IS
WHEN 0 => q <= I0 AFTER 10 ns;
WHEN 1 => q <= I1 AFTER 10 ns;
WHEN 2 => q <= I2 AFTER 10 ns;
WHEN 3 => q <= I3 AFTER 10 ns;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END better;
Khi phat bieu th nhat muxval:=0; c thc hien th gia tr 0 c at vao cho bien muxval
ngay lap tc. Gia tr khong c sap xep v muxval trong v du nay la bien, khong phai la tn hieu.
Cac bien tng trng cho o nh lu tr cuc bo khac vi tn hieu tng trng cho ket noi mach
ien ben trong. O nh lu tr cuc bo c cap nhat ngay lap tc va gia tr mi co the c dung
sau o trong mo hnh cho cac tnh toan sau o.
Do bien muxval c khi tao gia tr 0 ngay lap tc nen hai phat bieu gan trong qua trnh
dung gia tr 0 nh gia tr khi tao va cong vi cac con so thch hp tuy thuoc vao tuy thuoc vao gia
tr cua tn hieu a va b. Cac phat bieu gan nay cung c thc hien ngay lap tc va do o khi phat
bieu case c thc hien th bien muxval a cha gia tr ung. T gia tr nay tn hieu ngo vao
ung co the c truyen en ngo ra.
3. CAC PHAT BIEU TUAN T
Cac phat bieu tuan t nam ben trong phat bieu qua trnh va nam trong cac chng trnh con.
Trong phan nay chung ta se khao sat cac phat bieu tuan t nam ben trong phat bieu qua trnh.
Cac phat bieu tuan t se c trnh bay la: IF, CASE, LOOP, EXIT, ASSERT, WAIT.
4. PHAT BIEU IF
Phat bieu IF cho phep chon mot trong cac cau lenh e thc hien. Ket qua tra ve cua menh e
ieu kien la gia tr kieu BOOLEAN. Da vao ket qua tra ve cua menh e ieu kien e cho phep
mot lenh co c thc thi hay khong.
Cu phap cua phat bieu IF nh sau
if condition then sequential statements;
[elsif condition then sequential statements;]
[else sequential statements;]
end if;
V du 2-13: cho phat bieu IF
IF (x < 10 ) THEN a:= b;
END IF;
Phat bieu c bat au bang t khoa IF. Theo sau t khoa IF la menh e ieu kien (x < 10).
ieu kien tra ve true khi x nho hn 10, ngc lai th co gia tr false. Khi ieu kien la true th phat
bieu gia THEN va END IF c thc hien. Trong v du nay th lenh phat bieu gan (a:=b) c
thc hien bat ky luc nao x nho hn 10.
V du 2-14: cho phat bieu IF THEN ELSE:
IF (day = sunday ) THEN weekend := true;
ELSIF (day = saturday ) THEN weekend := true;
ELSE weekday := true;
END IF;
Trong v du nay co hai bien weekend va weekday c thiet lap gia tr tuy thuoc vao
gia tr cua tn hieu day. Bien weekend c thiet lap la true khi day bang Saturday hoac Sunday.
Ngc lai bien weekday c thiet lap la true.
Thc hien phat bieu IF bat au kiem tra xem bien day co bang vi Sunday hay khong.
Neu ket qua la true th phat bieu ke c thc hien va ieu khien c chuyen ti phat bieu
nam sau t khoa END IF.
Ngc lai ieu khien c chuyen ti phan phat bieu ELSIF va kiem tra day co phai la
Saturday hay khong. Neu bien day la Saturday th phat bieu ke c thc hien va ieu khien
c chuyen ti phat bieu nam sau t khoa END IF.
Cuoi cung neu day khong bang Sunday va Saturday th phan phat bieu ELSE c thc
hien. Phat bieu IF co the co nhieu phan phat bieu ELSIF nhng ch co duy nhat mot lan phat bieu
ELSE.
5. PHAT BIEU CASE
Phat bieu CASE c s dung khi gia tr cua bieu thc duy nhat co the c dung e la
chon mot trong so hoat ong. Cu phap cho phat bieu CASE nh sau:
case expression is
when choices => sequential statements;
when choices => sequential statements;
-- branches are allowed
[ when others => sequential statements ];
end case;
Ket qua bieu thc la so nguyen, hoac kieu liet ke cua mang mot chieu chang han nh
bit_vector. Phat bieu case anh gia bieu thc va so sanh gia tr cua bieu thc vi moi gia tr cua
cac la chon. Menh e when tng ng vi la chon trung hp se c thc hien. Cac nguyen tac
sau phai nh:
Khong co 2 la chon trung lap (la chon nay bao phu la chon kia).
Neu phat bieu la chon when others khong hien dien th tat ca gia tr co the co cua
bieu thc phai bao phu het bi cac la chon.
Phat bieu CASE cha t khoa CASE theo sau la bieu thc va t khoa IS. Bieu thc co gia tr
tng thch vi CHOICES nam trong phat bieu WHEN hoac tng thch vi phat bieu WHEN
OTHERS.
Neu bieu thc tng thch vi phan CHOICES cua cac phat bieu WHEN choices => th
sequence_of_statement theo sau se c thc hien. Sau khi cac phat bieu nay c thc hien
xong th ieu khien chuyen ti phat bieu nam sau t khoa END CASE.
V du 2-15: phat bieu case :
CASE instruction IS
WHEN load_accum => accum <= data;
WHEN store_accum => data_out <= accum;
WHEN load|store => process_IO (addr) ;
WHEN OTHERS => process_error (instruction);
END CASE;
Phat bieu CASE thc hien phat bieu tng ng tuy thuoc vao gia tr cua bieu thc ngo vao.
Neu gia tr cua bieu thc la mot gia tr nam trong cac gia tr c liet ke trong cac menh e
WHEN th sau o phat bieu theo sau menh e WHEN c thc hien. Ngc lai th phat bieu theo
sau menh e OTHERS c thc hien.
Trong v du nay khi gia tr cua bieu thc la load_accum th phat bieu gan au tien c thc
hien. Neu gia tr cua bieu thc la load hoac store th thu tuc process_IO c goi.
Neu gia tr cua bieu thc nam ngoai day la chon a cho th sau o menh e OTHERS tng
thch vi bieu thc va phat bieu theo sau menh e OTHERS c thc hien. Se phat sinh loi neu
khong co menh e OTHERS va cac la chon a cho khong bao trum gia tr co the co cua bieu
thc.
V du 2-16 vi bieu thc co ket qua tra ve phc tap hn. Phat bieu CASE dung kieu d lieu
nay e la chon mot trong cac phat bieu.
V du 2-16:
TYPE vectype IS ARRAY (0 TO 1) OF BIT;
VARIABLE bit_vector: vectype;
CASE bit_vector IS
WHEN 00 => RETURN 0;
WHEN 01 => RETURN 1;
WHEN 10 => RETURN 2;
WHEN 11 => RETURN 3;
END CASE;
V du nay trnh bay mot phng phap chuyen oi mot mang bit thanh mot so nguyen.
Khi hai bit cua bien bit_vec co gia tr 0 th la chon 00 tng thch va gia tr tra ve la 0.
Khi hai bit cua bien bit_vec co gia tr 1 th la chon 11 tng thch va gia tr tra ve la 3.
Phat bieu CASE khong can menh e OTHERS v tat ca cac gia tr cua bien bit_vec c liet
ke bi cac la chon.
6. PHAT BIEU LOOP
Phat bieu LOOP c s dung e lap lai chuoi cac lenh tuan t. Cu phap cho phat bieu
LOOP nh sau:
[ loop_label :]iteration_scheme loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [loop_label];
Phat bieu next va exit la cac phat bieu tuan t ch co the c s dung ben trong vong lap.
Phat bieu next cham dt phan con lai cua vong lap hien tai va sau o se lap lai vong
lap ke.
Phat bieu exit bo qua phan con lai cua phat bieu, cham dt hoan toan vong lap va
tiep tuc vi phat bieu ke sau vong lap v thoat.
Co 3 loai vong lap:
Vong lap loop c ban
Vong lap while loop
Vong lap for loop
a. Phat bieu vong lap LOOP c ban
Vong lap thc hien lien tuc cho en khi bat gap phat bieu exit hoac next. Cu phap nh sau:
[ loop_label :] loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [ loop_label];
Vong lap c ban phai co t nhat mot phat bieu wait. V du mot bo em 5 bit em t 0 en 31.
Khi bo em at gia tr 31 th bo em bat au tran ve 0. Phat bieu wait co cha trong chng trnh
e cho vong lap se thc hien moi khi xung clock thay oi t 0 sang 1.
V du 2-17: s dung vong lap c ban cho mach em t 0 en 31.
ENTITY count31 IS
PORT (CLK: IN STD_LOGIC;
Count: OUT INTEGER);
END count31;
ieu kien lap c kiem tra trc moi lan lap ke ca lan lap au tien. Neu ieu kien la false
th vong lap cham dt.
c. Phat bieu vong lap FOR LOOP:
Vong lap for loop dung gian o lap so nguyen e xac nh so lan lap. Cu phap nh sau:
[ loop_label :] for identifier in range loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
Ch so lap c khai bao t ong bi chnh vong lap do o khong can khai bao rieng le. Gia
tr cua ch so ch co the c oc ben trong vong lap va khong co hieu lc ngoai vong lap.
Khong the gan hoac thay oi gia tr cua ch so lap. Ch so lap nay oi ngc vi vong lap while
loop khi ieu kien cua vong lap while-loop co cha bien va c hieu chnh ben trong vong lap.
Day so cua vong lap phai la mot day so nguyen co the tnh toan c mot trong cac dang
sau, trong moi dang th integer_expression phai la mot so nguyen:
o integer_expression to integer_expression
o integer_expression downto integer_expression
d. Phat bieu Next va Exit:
Phat bieu next bo qua viec thc hien e en thc hien vong lap ke cua phat bieu vong lap.
Cu phap nh sau:
next [label] [when condition];
T khoa when la tuy chon va se c thc hien phat bieu ke khi ieu kien anh gia la true.
Phat bieu exit bo qua phan con lai cua phat bieu, cham dt hoan toan vong lap va tiep tuc
vi phat bieu ke sau khi vong lap b thoat. Cu phap nh sau:
exit [label] [when condition];
T khoa when la tuy chon va se c thc hien phat bieu ke khi ieu kien anh gia la true.
Chu y: s khac nhau gia phat bieu next va exit la phat bieu exit cham dt vong lap.
V du 2-18: Minh hoa cho vong lap next
PROCESS (A, B)
CONSTANT max_limit: INTEGER :=255;
BEGIN
FOR i IN 0 TO max_limit
LOOP
IF (done(i) = true ) THEN next;
ELSE done(i) = true;
END IF;
q(i) <= a(i) and b(i);
END LOOP;
END PROCESS;
Phat bieu qua trnh cha mot phat bieu vong lap LOOP. Phat bieu LOOP la and cac bit cua
mang a va mang b va at ket qua vao mang q. Mo ta hanh vi tiep tuc cho en khi nao c trong
mang done la false.
Neu gia tr cua c done la true vi ch so i th phat bieu next c thc hien. Viec thc hien
tiep tuc vi phat bieu au tien cua vong lap va ch so i bay gi co gia tr la i + 1.
Neu gia tr cua c done la false th phat bieu next khong c thc hien va viec thc hien
tiep tuc vi phat bieu cha trong menh e ELSE cho phat bieu IF.
Phat bieu next cho phep ngi thiet ke kha nang ngng viec thc hien cac lenh cua vong lap
va tiep tuc vi vong lap tiep theo. Co mot so trng hp khac th can thoat khoi vong lap th kha
nang nay c thc hien bi phat bieu EXIT.
Trong thi gian thc thi mot phat bieu LOOP, co the ta can nhay ra khoi vong lap. ieu nay
co the xay ra do mot loi quan trong xuat hien trong thi gian thc thi mo hnh hoac toan bo viec x
ly ket thuc sm.
Phat bieu EXIT cua VHDL cho phep ngi thiet ke thoat hoac nhay ra khoi mot phat bieu
LOOP hien ang thc thi. Phat bieu EXIT lam cho viec thc thi dng v tr cua phat bieu nay.
Viec thc thi se tiep tuc phat bieu theo sau phat bieu LOOP.
V du 2-19: Minh hoa cho vong lap exit
PROCESS (A)
CONSTANT int_a: INTEGER;
BEGIN
Int_a := a;
FOR i IN 0 TO max_limit
LOOP
IF (int_a <0 ) THEN exit;
ELSE (int_a := int_a - 1);
q(i) <= 3.14 / REAL (int_a* i); -- signal assign
END IF;
END LOOP;
y <= q;
END PROCESS;
Ben trong phat bieu cua qua trnh nay, gia tr cua int_a luon luon c gia nh la gia tr
dng ln hn 0. Neu gia tr cua int_a am hoac bang 0 th sinh ra loi va viec tnh toan se khong
c hoan tat. Neu gia tr cua int_a nho hn hoac bang 0 th phat bieu IF la ung va phat bieu
EXIT se c thc thi. Vong lap ket thuc ngay lap tc va phat bieu ke tiep c thc thi chnh la
phat bieu gan cho y sau phat bieu LOOP.
Phat bieu EXIT co 3 loai c ban. Loai th nhat yeu cau phat bieu EXIT khong co nhan vong
lap hoac WHEN condition. Neu cac ieu kien nay ung, phat bieu EXIT se hoat ong nh sau:
phat bieu EXIT ch thoat khoi phat bieu LOOP hien tai. Neu phat bieu EXIT ben trong mot phat
bieu LOOP va phat bieu LOOP nay c long trong mot phat bieu LOOP khac, phat bieu EXIT
ch thoat khoi phat bieu LOOP ben trong. Viec thc thi van duy tr trong phat bieu LOOP ben
ngoai. Phat bieu EXIT ch thoat khoi phat bieu LOOP gan nhat.
V du 2-20: Minh hoa
PROCESS (a)
BEGIN
First_loop: FOR i IN 0 TO 100 LOOP
second_loop: FOR j IN 0 TO 10 LOOP
.
Exit second_loop; -- exit the second loop only
.
Exit first_loop; -- exit the first loop and second loop
END LOOP;
86 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
END LOOP;
END PROCESS;
Neu phat bieu co them ieu kien WHEN th phat bieu EXIT ch thoat khoi vong lap khi ieu
kien la TRUE. Phat bieu ke c thc hien tuy thuoc vao ieu kien cua phat bieu EXIT co nhan
ch nh hay khong.
Neu nhan cua vong lap c ch nh th phat bieu ke c thc hien th cha trong phat bieu
LOOP ch nh bi nhan vong lap.
Neu khong co nhan th phat bieu ke c thc hien th nam vong lap ke ben ngoai.
V du 2-21: cho phat bieu EXIT vi ieu kien WHEN
Exit first_loop WHEN (i < 10);
Phat bieu nay ket thuc viec thc hien cua vong lap co nhan la first_loop khi bieu thc i <
10.
Phat bieu EXIT cung cap mot phng phap de dang va nhanh chong e thoat khoi phat bieu
LOOP khi toan bo cong viec x ly ket thuc hoac mot loi hay canh bao xay ra.
7. PHAT BIEU ASSERT
Phat bieu ASSERT la phat bieu rat hu ch e bao cao chuoi van ban en ngi thiet ke.
Phat bieu ASSERT kiem tra gia tr cua mot bieu thc logic xem ung hay sai. Neu gia tr la ung,
phat bieu nay khong lam g ca. Neu gia tr la sai, phat bieu ASSERT xuat mot chuoi dang van ban
c ch nh bi ngi s dung en ngo ra chuan cua thiet b au cuoi.
Ngi thiet ke cung co the ch ra mc o nghiem trong e xuat chuoi dang van ban. Theo
trnh t tang dan cua mc o nghiem trong ta co 4 mc: chu y, canh bao, loi va that bai. Mc o
nghiem trong cung cap cho ngi thiet ke kha nang phan loai thong iep thanh cac loai thch hp.
Phat bieu ASSERT c s dung chu yeu e quan ly khi viet mo hnh, khong co phan cng
nao c xay dng.
Cu phap:
assert_statement ::=
ASSERT condition
[REPORT expression];
T khoa ASSERT c theo bi mot bieu thc co gia tr logic c goi la mot ieu kien
(condition). ieu kien nay xac nh bieu thc dang van ban c phep xuat ra hay khong bi phat
bieu REPORT. Neu sai, bieu thc dang van ban c xuat, con neu ung, bieu thc dang van ban
khong c xuat.
Chung ta khao sat v du thc te cho phat bieu ASSERT, v du nay thc hien viec kiem tra
thiet lap d lieu gia hai tn hieu ieu khien flip flop D. Hau het cac flip flop yeu cau d lieu ngo
vao din phai gia tr on nh vi mot khoang thi gian xac nh trc khi co canh xung clock xuat
hien. Thi gian nay c goi la thi gian thiet lap va am bao rang d lieu vao din se c chot
vao ben trong flip flop. V du 2-22 ve phat bieu ASSERT tao ra thong bao loi cho ngi thiet ke
biet neu thi gian thiet lap khong u hay b vi pham.
V du 2-22:
PROCESS (clk, din)
Ky thuat PLD va ASIC 87
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
Phat bieu WAIT cung co the c s dung e ieu khien cac tn hieu cua qua trnh hay
chng trnh con nhay vi bat ky iem nao trong khi thc hien chng trnh.
V du 2-23:
PROCESS
BEGIN
WAIT ON a;
WAIT ON b;
END PROCESS;
V du 2-27:
WAIT ON nmi, interrupt UNTIL ((nmi = true) or (interrupt = true) ) FOR 5 usec;
Phat bieu nay i mot s kien tren cac tn hieu nmi va interrupt va ch tiep tuc neu interrupt
hoac nmi la true hoac cho en het thi gian 5s. Ch khi mot hoac nhieu ieu kien tren la true th
qua trnh thc hien mi tiep tuc. Hay xem v du 2-28:
V du 2-28:
WAIT UNTIL (interrupt = true ) OR (old_clk = 1);
Phai chac chan co t nhat mot gia tr trong bieu thc cha tn hieu ieu nay la can thiet e
am bao phat bieu WAIT khong phai ch i mai.
Neu ca hai interrupt va old_clk eu la bien th phai bieu WAIT khong phai anh gia lai khi
hai bien nay thay oi gia tr. Ch can 1 tn hieu thay oi se lam cho phat bieu WAIT hoac cac phat
bieu gan tn hieu ong thi anh gia lai.
VI. CAC KIEU OI TNG TRONG VHDL
Cac oi tng cua VHDL cha mot trong cac kieu sau:
Signal: tng trng cho cac day dan ket noi ben trong dung e ket noi cac port cua
cac thanh phan vi nhau.
Variable: c dung nh mot o nh cuc bo e lu d lieu tam thi ch nhn thay c
ben trong qua trnh.
Constant: la khai bao hang so.
1. KHAI BAO TN HIEU (SIGNAL):
Kieu tn hieu c s dung e ket noi cac thc the lai vi nhau e tao ra mot module. Signal
la phng thc truyen cac tn hieu ong gia cac thc the vi nhau.
Kieu signal c khai bao nh sau
SIGNAL signal_name: signal_type[:=initial_value];
Theo sau t khoa SIGNAL la mot hoac nhieu ten tn hieu. Vi moi ten tn hieu se tao ra mot
signal mi. Phan biet ten vi loai tn hieu bang dau :. Loai tn hieu ch nh loai d lieu cua
thong tin cha trong tn hieu. Cuoi cung th tn hieu co the cha mot gia tr bat au (gia tr khi
gan) e cho gia tr tn hieu co the c khi ong.
Cac tn hieu co the c khai bao trong phan khai bao cua thc the, trong kien truc va trong
khai bao goi. Cac tn hieu trong khai bao goi c xem nh cac tn hieu toan cuc.
V du 2-29: ve khai bao tn hieu nh sau:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux;
PACKAGE sigdecl IS
TYPE bus_type IS ARRAY (0 to 7) OF std_logic;
ENTITY and5 IS
PORT (a, b, c, d, e: IN std_logic;
q: OUT std_logic);
END and5;
Khi bat ky tn hieu a, b, c, d, hoac e thay oi th qua trnh thc hien. Bien state c gan cho
ham AND cua tat ca cac ngo vao. Bc tiep theo th da vao gia tr cua bien state ma bien delay
c gan gia tr thi gian tre. Da vao gia tr thi gian a c gan cho bien delay, tn hieu ngo ra
q se co gia tr cua bien state.
3. KHAI BAO HANG SO :
Hang so gi mot gia tr khong oi trong qua trnh thiet ke. Hang so c khai bao nh sau
CONSTANT constant_name :type_name[:=value];
Cac ten hang cach nhau bang dau ;. Cac gia tr cua hang la tuy y, kieu hang co quy nh
giong kieu tn hieu.
Hang co the s dung trong toan thc the neu hang c khai bao trong khoi khai bao cua
thc the, hoac co the c s dung trong toan package neu no c khai bao trong oan khai bao
cua package.
V du 2-31:
CONSTANT PI : REAL := 3.1414;
END test;
Hai phat bieu th 1 va 2 la cac phep gan so nguyen. Phat bieu th 3 la phep cho bien so
nguyen la mot so khong phai so nguyen, khi bien dch th phat bieu nay co the sinh ra loi. Bat ky
con so nao co dau cham c xem la so thc.
b. Kieu d lieu a nh ngha
VHDL cha nhieu loai d lieu a c nh ngha, ac biet la cac chuan IEEE 1076 va IEEE
1164. ac biet hn na chang han nh nh ngha cac loai d lieu co the c tm thay trong th
vien va trong goi.
Goi chuan standard (package standard) cua th vien std: xac nh cac kieu d lieu
BIT, BOOLEAN, INTEGER va REAL.
Goi std_logic_1164 cua th vien IEEE: nh ngha cac kieu d lieu STD_LOGIC va
STD_ULOGIC.
Goi std_logic_arith cua th vien IEEE: nh ngha cac kieu d lieu SIGNED va
STD_ULOGIC, cung vi nhieu ham chuyen oi d lieu nh conv_integer (p),
conv_unsigned(p,b), conv_signed(p,b) va conv_std_vector(p,b).
Goi std_logic_signed va std_logic_unsigned cua th vien IEEE: cha cac ham cho
phep hoat ong vi cac d lieu STD_LOGIC_VECTOR c thc hien khi d lieu
loai SIGNED hoac UNSIGNED.
Tat ca cac d lieu a nh ngha (nam trong cac goi hoac th vien tren) c mo ta nh
sau:
BIT (and BIT_VECTOR): co 2 mc logic la 0 va 1.
V du 2-33: khai bao cac tn hieu dang BIT va BIT_VECTOR
SIGNAL x: BIT; -- x c khai bao la mot tn hieu bit
SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y la mot vector 4 bit vi bit ben trai la MSB.
SIGNAL w: BIT_VECTOR (0 TO 7); -- w la mot vector 8 bit vi bit ben phai la MSB.
Da vao cac tn hieu tren th cac phat bieu gan sau la hp le:
x <= 1; -- x c gan vi gia tr la 1.
Chu y k hieu dau nhay n ch c dung cho 1 bit n.
y <= 0111; -- y c gan tn hieu 4 bit co gia tr la 0111 vi bit MSB la bit 0.
Chu y k hieu dau nhay kep c dung cho vector.
w <= 01110001; -- w c gan tn hieu 8 bit co gia tr la 01110001 vi bit MSB la bit
1.
STD_LOGIC va STD_LOGIC_VECTOR: co 8 gia tr logic c gii thieu trong chuan
IEEE 1164 chuan:
X co ngha la cha xac nh
0 co ngha la mc thap
1 co ngha la mc cao
Z trang thai tong tr cao
W yeu cha xac nh
L yeu thap
H yeu cao
- bat chap
V du 2-34: khai bao cac tn hieu dang STD_LOGIC va STD_LOGIC_VECTOR
SIGNAL x: STD_LOGIC -- x c khai bao la tn hieu bit kieu STD_LOGIC.
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0):= 0001;
-- y c khai bao la mot vector 4 bit vi bit ben trai la MSB va gia tr khi tao la 0001.
Chu y k hieu toan t := c dung e thiet lap gia tr khi gan.
STD_ULOGIC va STD_ULOGIC_VECTOR: co 9 gia tr logic c gii thieu trong chuan
IEEE 1164 chuan la (U, X, 0, 1, Z, W, L, H, -). K hieu U tng trng cho
unresolve khong quyet oan.
Kieu BOOLEAN: co 2 gia tr la TRUE va FALSE.
Kieu so nguyen INTEGER: la so nguyen 32 bit t -2,147,483,657 en +2,147, 483,
647.
Kieu so nguyen dng NATURAL: t 0 en +2,147, 483, 647.
Kieu so thc REAL: t -1.0E38 en +1.0E38. Khong c tong hp.
Kieu cac con so vat ly: c dung cho cac ai lng vat ly nh thi gian, ien ap,
dung cho mo phong. Khong c tong hp.
Kieu SIGNED va UNSIGNED: kieu d lieu a nh ngha trong goi std_logic_arith
cua th vien IEEE.
V du 2-35: ve cac lenh gan bit, vector, cac kieu he thong so:
x0 <= 0; -- co the xem x la bit, std_logic hoac std_ulogic co gia tr la 0.
x1 <= 00011111; -- co the xem la bit_vector, std_logic_vector, std_ulogic, signed hoac
unsigned.
x2 <= 0001_1111; -- dau gach cho phep e de nhn.
x3 <= 101111; -- tng trng cho so nh phan co gia tr thap phan la 47.
x4 <= B101111; -- tng trng cho so nh phan co gia tr thap phan la 47.
x5 <= O57; -- tng trng cho bat phan co gia tr thap phan la 47.
x6 <= X2F; -- tng trng cho so thap luc phan co gia tr thap phan la 47.
n<= 1200; -- so nguyen.
m<= 1_200; -- so nguyen cho phep tach ra e de nhn.
IF ready THEN -- ready kieu boolean c thc hien neu ready bang true.
y <= 1.2E-5; -- so thc, nhng khong tong hp.
q <= d AFTER 10 ns; -- vat ly nhng khong tong hp.
V du 2-36: ve cac khai bao hp le va khong hp le vi cac loai d lieu khac nhau:
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR (7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
a <= b(5); -- phep gan bit th 5 cua b cho a la hp le v cung d lieu BIT.
b(0) <= a; -- phep gan a cho bit th 0 cua b la hp le v cung d lieu BIT.
c <= d(5); -- phep gan bit th 5 cua d cho c la hp le v cung d lieu
STD_LOGIC.
d(0) <= c; -- phep gan nay la hp le v cung kieu d lieu STD_LOGIC.
a <= c; -- phep gan nay khong hp le v khac kieu d lieu BIT va
STD_LOGIC.
b <= d; -- khong hp le v khac kieu BIT_VECTOR va
STD_LOGIC_VECTOR.
e <= b; -- khong hp le v khac kieu INTEGER va BIT_VECTOR.
e <= d; -- khong hp le v khac kieu INTEGER va STD_LOGIC_VECTOR.
y(1) (7 downto 3) <= x(4 downto 0); -- hp le v cung kieu va kch thc d lieu.
v(1) (7 downto 3) <= v(2) ( 4 downto 0); -- hp le v cung kieu va kch thc d lieu.
w(1, 5 downto 1) <= v(2) ( 4 downto 0); -- khong hp le v khong cung kieu.
giong nh cac mang vector. Do kieu khai bao TYPE khong c phep khai bao trong thc the
entity nen giai phap e khai bao cac kieu d lieu do ngi dung nh ngha trong PACKAGE, sau
o co the dung cho toan thiet ke.
V du 2-41:
-- khai bao goi package--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE my_data_type IS
TYPE vector_array IS ARRAY ( NATURAL RANGE <>) OF std_logic_vector (7
downto 0);
END my_data_type;
-- khai bao d lieu dung cho chng trnh --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.my_data_type.ALL; -- goi do ngi dung nh ngha
ENTITY mux IS
PORT (inp: IN vector_array (0 to 3);
: );
END mux;
SIGNAL a: REAL;
BEGIN
a <= 1.0; -- ok 1
a <= 1; -- error 2
a <= -1.0E10; -- ok 3
a <= 1.5E-20; -- ok 4
a <= 5.3 ns; -- error 5
END test;
Hang 1 trnh bay cach gan so thc cho tn hieu loai REAL. Tat ca cac con so thc eu co dau
cham e phan biet vi so nguyen.
Hang th 2 se phat sinh loi v gan so nguyen cho bien kieu so thc.
Hang th 3 gan mot so thc rat ln va hang th 4 gan mot so thc rat nho.
Hang th 5 se phat sinh loi v khong the gan thi gian cho tn hieu so thc.
j. Kieu liet ke
Kieu liet ke la mot cong cu ho tr ac lc cho qua trnh thiet ke bang ngon ng VHDL.
Ngi thiet ke co the dung cac loai d lieu liet ke ai dien chnh xac cho cac gia tr chnh
xac c yeu cau cho phep toan ch nh. Tat ca cac gia tr cua kieu d lieu liet ke do ngi dung
nh ngha. Cac gia tr nay co the la ten hoac cac hang so ac tnh n, v du cho ten la x, abc,
hang so ac tnh n la X, 1 va 0.
Loai d lieu liet ke cho he thong co 4 gia tr mo phong nh sau:
TYPE fourval IS (X, 0, 1, Z);
Mot ng dung co dung kieu liet ke la minh hoa cho tat ca cac lenh cua vi x ly. V du 2-48
kieu liet ke cho mot vi x ly n gian nh sau:
V du 2-48:
TYPE instruction IS (add, sub, lda, ldb, sta, stb, outa, xfr);
Va mo hnh cho he thong vi x ly:
PACKAGE instr IS
TYPE instruction IS (add, sub, lda, ldb, sta, stb, outa, xfr);
END instr;
USE work.instr.ALL;
ENTITY mp IS
PORT (instr: IN instruction;
addr: IN INTEGER;
data: INOUT INTEGER);
END mp;
ARCHITECTURE mp OF mp IS
BEGIN
PROCESS (instr)
TYPE regtype IS ARRAY (0 to 255 ) OF INTEGER;
VARIABLE a, b: INTEGER;
VARIABLE reg: regtype;
BEGIN
102 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
CASE instr IS
WHEN lda => a:= data; -- load a accumulator
WHEN ldb => b:= data; -- load b accumulator
WHEN add => a:= a + b; -- add accumulator
WHEN sub => a:= a - b; -- subtract accumulator
WHEN sta => reg(addr) := b; -- put b accu in reg array
WHEN out => data<= a ; -- output a accumulator
WHEN xfr => a:= b ; -- transfer b to a
END CASE;
END PROCESS ;
END mp;
Mo hnh nhan mot chuoi lenh (instr), mot a ch (addr) va mot chuoi d lieu (data). Da
vao gia tr cua instr c liet ke ma lenh tng ng c thc hien. Phat bieu CASE c dung
e la chon lenh e thc hien. Phat bieu c thc hien va sau o qua trnh se i cho en lenh
ke.
2. KIEU VAT LY:
Kieu vat ly c s dung e mo ta cac ai lng vat ly nh: khoang cach, dong ien, thi
gian V du 2-49 ve kieu d lieu vat ly ve dong ien nh sau:
V du 2-49:
TYPE current IS RANGE 0 TO 1000000000;
UNITS
na; -- nano amps
ua = 1000 na; -- micro amps
ma = 1000 ua; -- mili amps
a = 1000 ma; -- amps
END UNITS;
Viec xac nh kieu d lieu c bat au vi cau lenh khai bao ten kieu va vung cua kieu (0
to 1000000000), cac khai bao c thc hien trong oan UNITS. Trong v du tren n v chnh cua
UNITS la na. Sau khi n v chnh cua UNITS c khai bao cac n the khac se c xac nh.
Kieu vat ly a c nh ngha: trong VHDL co kieu vat ly a c nh ngha la thi gian
nh sau:
TYPE TIME IS <implementation defined>;
UNITS
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 ns; -- milisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour
END UNITS;
3. CAC THUOC TNH:
VHDL ho tr 5 loai thuoc tnh. Cac thuoc tnh a nh ngha luon c ap dung tiep au ng
nh ten cua tn hieu, ten cua bien hoac kieu. Cac thuoc tnh c dung e tra ve nhieu loai thong
tin khac nhau nh tn hieu, bien hoac kieu. Cac thong tin cha dau phay () theo sau la ten cua
thuoc tnh.
a. Thuoc tnh tn hieu
Bang sau ay liet ke cac thuoc tnh cua tn hieu:
Thuoc tnh Chc nang
signal_nameevent Tra ve gia tr Boolean la True neu co s kien tren tn hieu
xay ra, ngc lai th tra ve gia tr false.
signal_nameactive Tra ve gia tr Boolean la True neu co tch cc (gan) tren tn
hieu xay ra, ngc lai th tra ve gia tr false.
signal_nametransaction Tra ve tn hieu kieu bit lat trang thai (0 sang 1 hoac 1 sang
0) moi lan co chuyen trang thai tren tn hieu.
signal_namelast_event Tra ve gia tr khoang thi gian t khi xay ra s kien sau cung
tren tn hieu.
signal_namelast_active Tra ve gia tr khoang thi gian t khi xay ra mc tch cc
tren tn hieu.
signal_namelast_value Cung cap gia tr cua tn hieu trc khi s kien sau cung xay
ra tren tn hieu.
signal_namedelayed(T) Cung cap tn hieu tre i T lan so vi tn hieu goc. T la tuy
chon, mac nhien T = 0.
signal_namestable(T) Tra ve gia tr Boolean, la true neu khong co s kien xay ra
tren tn hieu trong khoang thi gian T, ngc lai th tra ve
gia tr false. T la tuy chon, mac nhien T = 0.
signal_namequiet(T) Tra ve gia tr Boolean, la true neu khong co s thay oi xay
ra tren tn hieu trong khoang thi gian T, ngc lai la false. T
la tuy chon va mac nhien T = 0.
Bang 2-1. Thuoc tnh tn hieu.
V du 2-50: ve cac thuoc tnh:
if (CLOCKevent and CLOCK= 1) then
Bieu thc nay kiem tra s xuat hien cua xung clock canh len. e tm khoang thi gian t khi
co xung clock canh len sau cung th dung thuoc tnh sau:
CLOCKlast_event
scalar_typelow Tra ve gia tr thap nhat cua kieu d lieu scalar trong kieu
a nh ngha.
scalar_typehigh Tra ve gia tr cao nhat cua kieu d lieu scalar trong kieu
a nh ngha
scalar_typeascending La true neu T la day tang ngc lai th false.
scalar_typevalue(s) Tra ve gia tr cua T c tng trng bi s (string value).
Bang 2-2. Thuoc tnh d lieu scalar.
V du 2-51: ve cac thuoc tnh:
Type conductance is range 1E-6 to 1E3
Units mho;
End units conductance;
Type my_index is range 3 to 15;
Type my_levels is (low, high, dontcare, highZ);
MYARR8x4left(1) 8
MYARR8x4left(2) 0
MYARR8x4right(2) 3
MYARR8x4high(1) 8
MYARR8x4low(1) 1
MYARR8x4ascending(1) False
Th t Loai
1 Toan logic and or nand nor xor xnor
2 Toan t quan he = /= < <= > >=
3 Toan t dch sll srl sla sra rol ror
4 Toan t so hoc + = &
5 Toan t khong xac nh + -
6 Toan t nhan chia * / mod rem
7 Toan t hon hp ** abs not
Bang 2-4. Tat ca cac toan t.
Th t u tien cao nhat cho toan t th 7, tiep theo la th 6 va thap nhat la toan t th 1. Tr
trng hp dau ngoac c s dung th toan t co th t u tien cao nhat se c thc hien trc.
Neu cac toan t cung th t u tien th cac toan t se c thc hien t trai sang phai cua bieu
thc.
V du 2-53: Cho cac d lieu nh sau: X (=010), Y(=10), and Z (=10101) eu thuoc
kieu std_ulogic_vectors.
not X & Y xor Z rol 1
th se tng ng vi ((not X) & Y) xor (Z rol 1) = ((101) & 10) xor (01011) =(10110) xor
(01011) = 11101.
1. CAC TOAN T LOGIC:
Toan t logic (And, Or, Nand, Nor, Xor va Xnor) c dung cho cac loai d lieu bit,
boolean, std_logic, std_ulogic va cac vector. Cac toan t nay c dung e xac nh bieu
thc logic Boolean hoac thc hien cac phep toan bit vi bit tren mot mang bit. Ket qua cung kieu
d lieu nh cac tac to (Bit hoac Boolean). Cac toan t nay co the c ap dung cho cac tn hieu,
cac bien va cac hang so.
Chu y: cac toan t nand va nor khong the ket hp. Phai s dung dau ngoac e chia cac toan
t nand va nor e khong phat sinh loi khi bien dch:
X nand Y nand Z se phat sinh loi va phai viet nh sau (X nand Y) nand Z.
2. CAC TOAN T QUAN HE:
Toan t quan he kiem tra cac gia tr quan he cua 2 loai d lieu scalar va cho ket qua la kieu
Boolean true hoac false.
Toan t nam ben trai toan t va so lan dch nam ben phai toan t xem v du 2-57:
V du 2-57: Cho variable NUM1 :bit_vector := 10010110;
Thc hien NUM1 srl 2;
Ket qua NUM1 = 00100101.
Khi so lan dch la so am th hoat ong dch xay ra theo chieu ngc lai, dch trai se tr thanh
dch phai.
Toan t Mo ta D lieu ben trai D lieu ben phai D lieu ket qua
** Ham mu So nguyen So nguyen Giong d lieu ben trai
Dau cham So nguyen Giong d lieu ben trai
abs Ham tr tuyet oi Kieu so Cung kieu
not Ham phu nh Kieu bit hoac Boolean Cung kieu
Bang 2-10. Cac toan t hon hp.
a. Ham - FUNCTION:
V du 2-60 la mot ham, ham nay nhan vao mot mang co kieu STD_LOGIC va tra ve mot gia
tr so nguyen. Gia tr so nguyen nay bieu dien gia tr so hoc cua tat ca cac bit c x ly di dang
so nh phan:
V du 2-60: cach viet ham
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE num_type IS
TYPE log8 IS ARRAY (0 TO 7) OF std_logic; -- line 1
END num_type;
USE work.num_type.ALL;
ENTITY convert IS
PORT (I1: IN log8; -- line 2
O1: OUT INTEGER); -- line 3
END convert;
BEGIN
O1 <= vector_to_int (I1);
END behave;
Dong 1 khai bao kieu mang c s dung cho toan bo chng trnh.
Cac dong 2 va 3 khai bao cac port ngo vao, ngo ra cua thc the convert va cac kieu d lieu.
Cac dong t 4 en 11 mo ta mot ham c khai bao trong mien khai bao cua kien truc
behave. Bang cach khai bao ham trong mien khai bao cua kien truc, ham nay se c s dung bat
ky mien nao cua kien truc.
Cac dong 4 va 5 khai bao ten cua ham, cac oi so cua ham va kieu ma ham tra ve.
dong 6 mot bien cuc bo cua ham c khai bao. Cac ham co cac mien khai bao rat giong
vi cac phat bieu qua trnh. Cac bien, cac hang va cac kieu co the c khai bao nhng tn hieu th
khong.
Cac dong t 7 en 10 khai bao mot phat bieu vong lap cho moi gia tr trong mang. Giai thuat
c ban cua ham nay la dch va cong vi moi v tr bit trong mang. au tien ket qua c dch (tc
la nhan 2) va tiep theo la v tr bit la 1 th gia tr 1 c cong vao ket qua.
cuoi phat bieu vong lap, bien result se cha gia tr nguyen cua mang c chuyen vao. Gia
tr cua ham c chuyen ngc ve thong qua phat bieu RETURN. Trong v du tren th phat bieu
RETURN c trnh bay dong 11.
Cuoi cung, dong 12 trnh bay cach thc mot ham c goi. Ten cua ham c theo sau bi
cac oi so cua ham trong hai ngoac n. Ham se luon luon tra ve mot gia tr, do vay qua trnh
goi, phat bieu ong thi, phai co mot v tr e ham co the tra ve gia tr nay. Trong v du nay, ngo
ra cua ham c gan cho mot port ngo ra.
Cac thong so cua ham la d lieu nhap. Khong co phep gan nao c thc hien cho bat ky
thong so nao cua ham. Trong v du tren cac thong so thuoc loai hang so do khong co loai ro rang
c ch nh va mac nh la hang. Cac oi so c x ly nh the chung la cac hang c khai bao
trong mien khai bao cua ham.
Loai thong so cua ham co the la thong so tn hieu. Vi mot thong so tn hieu, cac thuoc tnh
cua tn hieu c chuyen vao trong ham va san sang c s dung. Ngoai le oi vi phat bieu
thuoc tnh STABLE, QUIET, TRANSACTION, va DELAYED se tao ra cac tn hieu ac biet.
Mot v du 2-61 cho thay mot ham cha cac thong so tn hieu nh sau:
V du 2-61:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT (d, clk: IN std_logic;
q: OUT std_logic);
FUNCTION resing_edge (SINGAL S : std_logic) -- line 1
RETURN BOOLEAN IS -- line 2
BEGIN
IF (SEVENT) AND (S=1) AND -- line 3
(SLAST_VALUE = 0) THEN -- line 4
RETURN TRUE; -- line 5
ELSE RETURN FALSE; -- line 6
END IF;
END resing_edge;
END dff;
BEGIN
PROCESS (CLK)
BEGIN
IF rising_edge(clk) THEN -- line 7
q <= d; -- line 8
END IF;
END PROCESS;
END behave;
V du nay cung cap phng phap phat hien canh len cho mo hnh flip flop D. Ham khai bao
trong phan khai bao thc the va do vay co the s dung cho bat ky kien truc nao cua thc the nay.
Cac dong 1 va 2 cho thay khai bao ham. Ch co mot thong so (S) cho ham va thong so nay
thuoc loai tn hieu.
Cac dong 3 va 4 la mot phat bieu IF, phat bieu nay xac nh co phai tn hieu va thay oi hay
khong, co phai gia tr hien tai la 1 hay khong va co phai gia tr trc o la 0 hay khong. Neu tat
ca cac ieu kien nay la ung, phat bieu IF se tra ve gia tr ung (true), co ngha la mot canh tang
a c phat hien tren tn hieu. Neu mot ieu kien nao o trong cac ieu kien nay khong ung,
gia tr c tra ve se la sai (false), nh c trnh bay dong 6.
Dong 7 goi ham s dung tn hieu c tao ra bi port clk cua thc the dff. Neu co mot canh
tang tren tn hieu clk, gia tr cua d c chuyen en ngo ra q.
Cong dung pho bien nhat cua ham la tra ve mot gia tr trong mot bieu thc, tuy nhien con co
hai cong dung na co san trong VHDL. Cong dung au tien la ham chuyen oi (conversion
function) va cong dung th hai la ham phan tch (resolution function). Cac ham chuyen oi c s
dung e chuyen oi t kieu nay sang kieu khac. Cac ham phan tch c s dung e phan tch viec
tranh chap bus tren mot tn hieu co nhieu nguon kch (multiply-driven signal).
b. Ham chuyen oi:
Cac ham chuyen oi c s dung e chuyen oi mot oi tng co kieu nay thanh oi tng
co kieu khac. Cac ham chuyen oi c s dung trong cac phat bieu the hien thanh phan e cho
phep viec anh xa cac tn hieu va port co cac kieu khac nhau. Loai tnh huong nay thng phat sinh
khi mot ngi thiet ke muon s dung mot thc the t mot thiet ke khac.
Gia nh rang ngi thiet ke A ang s dung kieu d lieu co 4 gia tr nh sau:
TYPE fourval IS (X, L, H, Z);
Ngi thiet ke B ang s dung kieu d lieu cung cha 4 gia tr nhng cac nh danh gia tr lai
khac, nh c trnh bay sau ay
TYPE fourvalue IS (X, 0, 1, Z);
Ca hai kieu nay eu co the c s dung e bieu dien cac trang thai cua mot he thong gia tr
4-trang thai cho mot mo hnh cua VHDL. Neu ngi thiet ke A muon s dung mot mo hnh t
ngi thiet ke B, nhng ngi thiet ke B a s dung cac gia tr t kieu fuorvalue lam cac port giao
dien cua mo hnh, ngi thiet ke A khong the s dung mo hnh nay ma khong chuyen oi kieu cua
cac port thanh cac gia tr c s dung bi ngi thiet ke B. Van e nay co the giai quyet c
thong qua viec s dung cac ham chuyen oi.
Trc tien ta hay viet ham chuyen oi gia tr gia hai he thong.
Cac gia tr t he thong th nhat bieu dien cac trang thai phan biet:
X gia tr cha biet.
L gia tr logic 0.
H gia tr logic 1.
PACKAGE my_std IS
TYPE fourval IS (X, L, H, Z) ;
TYPE fourvalue IS (X, L, H, Z) ;
TYPE fvector4 IS ARRAY (0 TO 3) OF fourval;
END my_std;
USE WORK.my_std.ALL;
ENTITY reg IS
PORT (a IN fvector4;
clr: IN fourval;
clk: IN fourval;
q: OUT fvector4);
BEGIN
U1: dff PORT MAP ( convert4val(a(0)),
convert4val(clk),
convert4val(clr),
convert4value(q) => q(0));
END structure;
V du nay la mot thanh ghi 4 bit c xay dng bang cac flip flop. Kieu c s dung trong
khai bao thc the cho thanh ghi la mot vector kieu fourval. Tuy nhien cac flip flop c the hien co
cac port co kieu fourvalue. Mot loi khong tng thch kieu se c tao ra neu cac port cua thc the
thanh ghi c anh xa trc tiep en cac port thanh phan. Do vay mot ham chuyen oi c can
en e chuyen oi hai he thong gia tr.
Neu cac port eu che o IN th ch mot chuyen oi c can en e anh xa t kieu cua
thc the cha en kieu cua thc the c cha. Trong v du nay, neu cac port eu che o ngo
vao th ch co ham convert4value c yeu cau.
Neu thanh phan cung co cac port ngo ra, cac gia tr ngo ra cua thc the c cha can c
chuyen oi tra ve kieu cua thc the cha. Trong v du nay port q cua thanh phan dff la mot port
ngo ra. Kieu cua cac gia tr ngo ra. Kieu cua cac gia tr ngo ra se la fourvalue. Cac gia tr nay
khong the c anh xa en cac port kieu fourval. Ham convert4value se chuyen oi t kieu
fourvalue thanh kieu fourval. Ap dung ham nay tren cac port ngo ra se cho phep anh xa port xay
ra.
Co 4 the hien thanh phan s dung cac ham chuyen oi nay: cac thanh phan t U1 en U4.
Lu y rang cac port ngo vao s dung ham chuyen oi convert4val trong khi cac port ngo ra s dung
ham chuyen oi convert4value.
Dung dang ket hp at nay cua anh xa cho the hien thanh phan U1 nh sau:
U1: dff PORT MAP ( d => convert4val(a(0)),
clk => convert4val(clk),
clr => convert4val(clk),
convert4value(p) => p(0));
Cac ham chuyen oi giai phong ngi thiet ke khoi viec tao ra nhieu tn hieu hoac bien tam
thi e the hien viec chuyen oi. V du 2-64 trnh bay mot phng phap khac e thc hien cac
ham chuyen oi:
V du 2-64:
Temp1 <= convert4val(a(0));
Temp2 <= convert4val(clk));
Temp3 <= convert4val(clr);
Phng phap nay dai dong, yeu cau mot bien tam trung gian cho moi port cua thanh phan
c anh xa. Phng phap t c la chon.
Neu mot port che o INOUT, cac ham chuyen oi khong the thc hien c vi ky hieu v
tr. Cac port phai s dung ket hp at ten do hai ham chuyen oi phai c ket hp vi port
INOUT. Mot ham chuyen oi se c s dung cho phan ngo vao cua port INOUT va mot ham
khac se c s dung cho phan ngo ra cua port nhap/xuat.
Trong v du sau ay, linh kien truyen hai chieu c cha trong thc the co ten la trans2:
V du 2-64:
PACKAGE my_pack IS
TYPE nineval IS (Z0, Z1, ZX, R0, R1, RX, F0, F1, FX) ;
TYPE nvector2 IS ARRAY (0 TO 1) OF (nineval) ;
TYPE fourstate IS (X, L, H, Z);
USE WORK.my_pack.ALL;
ENTITY trans2 IS
PORT ( a, b: INOUT nvector2;
enable: IN nineval);
END trans2;
BEGIN
U1: trans PORT MAP ( convert4state(x1) => convert9val(a(0)) ,
( convert4state(x2) => convert9val(b(0)) ,
en => convert9val(enable));
Ta hay khao sat mot ham phan tch oi vi kieu fourval a c s dung trong cac v du ham
chuyen oi. Khai bao kieu cho fourval nh sau:
TYPE fourval IS (X, L, H, Z);
4 gia tr phan biet c khai bao bieu dien tat ca cac gia tr co the co ma tn hieu co the
cha. Gia tr L bieu dien logic 0, gia tr H logic 1, gia tr Z bieu dien ieu kien tong tr cao, gia tr
X bieu dien ieu kien cha biet, trong o gia tr co the bieu dien logic 0 hoac logic 1 (ngha la tuy
nh) nhng ta khong chac la gia tr nao. Cac ieu kien nay co the xay ra khi hai driver ang kch
mot tn hieu mot driver kch vi logic H va driver kia kch vi logic L.
Liet ke vao theo th t o manh, vi yeu nhat tren cung, cac gia tr nay nh sau.
Z yeu nhat H, L va X co the ghi e.
H, L trung bnh ch co X co the ghi e.
X manh nhat khong b ghi e.
Bang cach s dung thong tin nay, mot bang gia tr co hai ngo vao co the c phat trien nh
c trnh bay bang di.
Bang 2-11 cho gia tr ngo ra co 2 ngo vao
Z L H X
Z Z L H X
L L L X X
H H X H X
X X X X X
Bang 2-11.
Bang gia tr nay dung cho cac gia tr hai ngo vao, ta co the m rong nhieu ngo vao hn bang
cach ap dung lien tiep bang nay cho hai gia tr mot thi iem. ieu nay co the thc hien c do
bang nay co tnh giao hoan va ket hp.
Mot L va mot Z hoac mot Z va mot L se cung cho ket qua.
Mot (L, Z) vi H se cho ket qua giong nh mot (H, Z) vi mot L.
Cac nguyen tac nay rat quan trong do th t cac gia tr cua driver ben trong oi so ngo vao
cua ham phan tch la khong nh trc theo quan iem cua ngi thiet ke. Bat ky phu thuoc nao
tren th t eu co the gay ra ket qua khong nh trc t ham phan tch.
Bang cach s dung tat ca cac thong tin nay, mot ngi thiet ke co the viet mot ham phan tch
cho kieu nay. Ham phan tch se duy tr o manh cao nhat trong chng mc thay c va so sanh
gia tr nay vi gia tr mi, mot phan t duy nhat mot thi iem cho en khi tat ca cac gia tr eu
a c s dung het. Giai thuat nay se tra ve gia tr co o manh cao nhat. Di ay la mot v du
cho mot ham phan tch nh vay.
V du 2-65:
PACKAGE fourpack IS
TYPE fourval IS (X, L, H, Z) ;
TYPE fourval_vector IS ARRAY (nineval RANGE <>) OF fourval;
FUNCTION resolve (s : fourval_vector) RETURN fourval;
END fourpack;
BEGIN
FOR i IN sRANGE LOOP
CASE result IS
WHEN Z =>
CASE s(i) IS
WHEN H => result := H;
WHEN L => result := L;
WHEN X => result := X;
WHEN OTHERS => NULL;
END CASE ;
WHEN L =>
CASE s(i) IS
WHEN H => result := X;
WHEN X => result := X;
WHEN OTHERS => NULL;
END CASE ;
WHEN H =>
CASE s(i) IS
WHEN L => result := X;
WHEN X => result := X;
WHEN OTHERS => NULL;
END CASE ;
END resolve ;
END fourpack ;
oi so ngo vao la mot mang khong rang buoc co kieu nen cua driver la fourval. Ham phan
tch se khao sat tat ca cac gia tr cua cac driver c chuyen vao oi so s, mot gia tr mot thi
iem, roi tra ve gia tr duy nhat co kieu fourval e c nh thi nh la gia tr cua tn hieu.
Bien result c khi ong bang gia tr Z cho trng hp khong co driver nao oi vi tn
hieu. Trong trng hp nay vong lap se khong bao gi c thc thi va gia tr cua result c tra
ve se la gia tr khi ong. ay cung la mot y hay neu ta khi ong gia tr cua result bang gia tr
yeu nhat cua he thong gia tr e cho phep ghi e bi cac gia tr manh hn.
Neu co mot driver c tien hanh, vong lap se c thc thi mot lan cho moi gia tr cua
driver c chuyen vao oi so s. Moi gia tr cua driver c so sanh vi gia tr hien tai c lu
trong bien result. Neu gia tr mi manh hn theo qui luat a c neu tren, gia tr cua result se
c cap nhat bang gia tr mi.
d. Thu tuc :
120 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
Thu tuc co the co nhieu thong so ngo vao, ra va vao-ra. Goi thu tuc c xem nh mot phat
bieu rieng, ham thng ton tai nh mot phan cua bieu thc. Trong hau het cac trng hp s dung
thu tuc ch khi co nhieu hn 1 gia tr c tra ve.
Thu tuc co nhng quy nh ve cu phap giong nh ham. Phan khai bao thu tuc bat au vi t
khoa PROCEDURE, tiep theo la ten cua thu tuc va sau o la danh sach cac oi so. S khac nhau
gia ham va thu tuc la danh sach cac oi so cua thu tuc giong nh co hng ket hp vi moi thong
so, con danh sach cua ham th khong co. Trong thu tuc, co nhieu oi so co the kieu IN, OUT
hoac INOUT, trong ham th tat ca cac oi so kieu IN.
V du 2-66 ve cach s dung thu tuc:
V du 2-66:
USE LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PROCEDURE vector_to_int (z : IN std_logic_vector;
x_flag: OUT BOOLEAN, q : INOUT INTEGER) IS
BEGIN
Q := 0;
X_flag := false;
FOR I IN zRANGE LOOP
Q := q * 2;
IF z(i) = 1 THEN q := q + 1;
ELSIF z(i) /= F0 THEN x_flag := true;
END IF;
END LOOP ;
END vector_to_int ;
Hanh vi cua thu tuc la chuyen oi oi so ngo vao z t mang kieu so nguyen. Tuy nhien neu
mang ngo vao co gia tr cha xac nh th gia tr so nguyen khong the c tao ra t mang. Khi
ieu kien nay xay ra th oi so x_flag c thiet lap gia tr true e xac nh gia tr so nguyen ngo
ra la khong xac nh. Thu tuc c yeu cau e ieu khien hanh vi nay bi v co nhieu ket qua tra
ve. Chung ta hay kiem tra ket qua t thu tuc vi mang gia tr ngo vao nh sau:
0 0 1 1
Bc th nhat thu tuc se khi ong cac gia tr ngo ra vi cac ieu kien a biet, trong trng
hp oi so ngo vao dai bang 0 c truyen vao. oi so ngo ra x_flag c khi tao trang thai
false va tiep tuc trang thai false cho en khi chng minh trang thai ngc lai.
Phat bieu vong lap xuyen qua vector ngo vao z va tiep tuc cong moi gia tr cua vector cho
en khi tat ca cac gia tr a c cong.
Neu gia tr la 1 th sau o no c cong vao ket qua. Neu gia tr la 0 th khong cong.
Neu bat ky gia tr nao c tm thay trong vector th ket qua x_flag c thiet lap la true xac
nh rang ieu kien cha biet a c tm thay mot trong cac ngo vao. (Chu y thong so q a
c nh ngha nh thong so vao-ra, ieu nay la can thiet bi v gia tr c oc trong thu tuc).
Thu tuc khong co thong so
V du 2-67 trnh bay mot thu tuc co 1 oi so vao-ra thuoc dang ban ghi. Ban ghi cha mot
mang 8 so nguyen cung vi trng so c dung e lu gia tr trung bnh cua tat ca cac so nguyen.
Thu tuc tnh toan gia tr trung bnh cua cac gia tr so nguyen, ghi gia tr trung bnh trong vung
trng trung bnh cua ban ghi va tr ve vi ban ghi a cap nhat:
V du 2-67:
PACKAGE intpack IS
TYPE bus_stat_vec IS ARRAY (0 TO 7) OF INTEGER;
TYPE bus_stat_t IS
RECORD
bus_val: bus_stat_vec;
average_val: INTEGER;
END RECORD;
PROCESS (mem_update)
VARIABLE bus_statistics : bus_stat_t;
BEGIN
bus_statistics.bus_val := (50, 40, 30, 35, 45, 55, 65, 85);
bus_average(bus_statistics);
average <= bus_statistics.average_val;
END PROCESS ;
Phat bieu au tien la gan bien. Phat bieu th hai la goi thu tuc bus_average e thc hien tnh
toan gia tr trung bnh. e bat au, oi so cho thu tuc bus_average la mot gia tr ngo vao nhng sau
khi thu tuc thc hien xong th oi so tr thanh gia tr ngo ra co the c s dung ben trong cho
viec goi x ly. Gia tr ngo ra t thu tuc c gan cho tn hieu ngo ra nam hang cuoi cung cua qua
trnh.
2. GOI:
Muc ch quan c ban cua goi la goi gon cac phan t co the dung chung, bao gom hai hay
nhieu n v thiet ke. Goi la mien lu tr chung c s dung e lu tr d lieu dung chung gia
mot so thc the. Viec khai bao d lieu ben trong mot goi cho phep d lieu c tham chieu bi cac
thc the khac.
Mot goi gom co hai phan: phan khai bao goi va phan than cua goi. Khai bao goi nh ngha
giao dien cho goi vi cung phng phap ma mot thc the nh ngha giao dien cho mot mo hnh.
Than cua goi ch ra hanh vi thc s cua goi theo cung phng phap ma phat bieu kien truc thc
hien oi vi mot mo hnh.
a. Khai bao goi:
Phan khai bao goi co the cha cac khai bao sau:
Khai bao chng trnh con.
Khai bao kieu, kieu con.
Khai bao chng trnh con cho resolve_cluster ch nh ten cua chng trnh con, cac oi so
bat ky cua chng trnh con, cac kieu va cac loai cua cac oi so va tra ve kieu neu chng trnh
con la mot ham. Khai bao nay co the c s dung e bien dch bat ky mo hnh nao d nh s
dung chng trnh con ma cha co than chng trnh con thc s c ch nh. Than chng trnh
con phai hien hu trc khi trnh mo phong c xay dng.
Than cua goi: Muc ch chnh cua than cua goi la nh ngha cac gia tr cho cac hang tr hoan
va ch nh cac than chng trnh con cho bat ky khai bao chng trnh con nao t khai bao goi.
Tuy nhien than goi cung co the cha cac khai bao sau:
Khai bao chng trnh con.
Than chng trnh con.
Khai bao kieu, kieu con.
Khai bao hang, khai bao nay ien vao gia tr cua hang tr hoan.
Khai bao tap tin.
Khai bao b danh.
Menh e USE.
Tat ca cac khai bao trong than cua goi ngoai tr khai bao hang ma chung ch nh gia tr
cua hang tr hoan va khai bao than chng trnh con la cuc bo oi vi than cua goi. Chung ta hay
khao sat than cua goi cho khai bao goi a c e cap phan trc.
V du 2-70:
PACKAGE BODY cluspack IS
CONSTANT undriven: t_wclus:=
(ZX, ZX, ZX, ZX,
ZX, ZX, ZX, ZX,
ZX, ZX, ZX, ZX,
ZX, ZX, ZX, ZX,);
Phat bieu than cua goi tng t nh khai bao goi ngoai tr t khoa BODY theo sau
PACKAGE. Tuy nhien cac noi dung cua hai n v thiet ke nay rat khac nhau. Than goi cho v du
nay ch cha hai muc: gia tr hang tr hoan cua hang tr hoan undriven va than chng trnh con
cua chng trnh con resolve_cluster. Ta hay lu y en cach thc ma ac ta gia tr hang tr hoan
tng thch vi khai bao hang tr hoan trong khai bao goi va than chng trnh con tng thch vi
khai bao chng trnh con trong khai bao goi. Than chng trnh con phai tng thch chnh xac vi
khai bao chng trnh con ve so thong so, kieu cua cac thong so va kieu tra ve.
Than cua goi cung co the cha cac khai bao cuc bo ch c s dung ben trong than cua goi
e xay dng cac than chng trnh con khac hoac cac gia tr hang tr hoan. Cac khai bao nay
khong c nhn thay t ben ngoai than cua goi nhng co the rat co ch ben trong than goi. V du
2-71 ve mot goi hoan chnh s dung tnh chat nay nh sau:
V du 2-71:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE math IS
TYPE st16 IS ARRAY (0 TO 15) OF std_logic;
FUNCTION add(a, b : IN st16) RETURN st16;
FUNCTION sub(a, b : IN st16) RETURN st16;
END math;
RETURN result;
END vect_to_int ;
BEGIN
Result := vect_to_int(a) + vect_to_int(b) ;
RETURN int_to_st16 (result);
END add;
FUNCTION sub (a,b : IN st16) RETURN st16 IS
VARIABLE result : INTEGER;
BEGIN
Result := vect_to_int(a) - vect_to_int(b) ;
RETURN int_to_st16 (result);
END sub;
END math;
Khai bao goi tren la mot khai bao kieu st16 va hai ham add va sub hoat ong theo kieu neu
tren. Than goi co cha than cac ham cho cac khai bao ham add va sub va cung cha hai ham ch
c s dung trong than cua goi o la cac ham nay la int_to_st16 va vec_to_int. Cac ham nay
khong c thay t ben ngoai than cua goi. e lam cho cac ham nay co the nhn thay c, mot
khai bao ham can phai them vao phan khai bao goi cho moi ham.
Cac ham vec_to_int va int_to_st16 phai c khai bao trc ham add e dch chng trnh
cho ung. Tat ca cac ham phai c khai bao trc khi chung c s dung.
end
GII THIEU
THIET KE MACH GIAI MA MACH MA HOA
THIET KE MACH GIAI MA
THIET KE MACH MA HOA
THIET KE MACH GIAI MA LED 7 OAN LOAI ANODE CHUNG
THIET KE MACH A HP MACH GIAI A HP
THIET KE MACH A HP
THIET KE MACH GIAI A HP
CAU HOI ON TAP VA BAI TAP
Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
CAC HNH VE
Hnh 3-1. S o khoi mach GM 2 - 4.
Hnh 3-2. S o khoi mach GM 3 - 8.
Hnh 3-3. S o khoi mach MH 4 - 2.
Hnh 3-4. S o khoi mach GM led 7 oan loai anode chung.
Hnh 3-5. S o khoi mach H 4 vao.
Hnh 3-6. S o khoi mach GH 4 ra.
CAC BANG
Bang 3-1. BTT mach GM 2 - 4.
Bang 3-2. BTT mach GM 3 - 8.
Bang 3-3. BTT mach MH 4 - 2.
Bang 3-4. BTT mach GM led 7 oan anode chung.
Bang 3-5. BTT mach a hp 4 ngo vao.
Bang 3-6. BTT mach GH 4 ra.
I. GII THIEU:
Trong phan nay se thiet ke cac mach logic to hp dung ngon ng VHDL va s dung thiet
b lap trnh.
Cac mach logic to hp bao gom mach giai ma n ng sang m ng, mach ma hoa m
ng sang n ng, mach don kenh va mach phan kenh, mach giai ma led 7 oan loai anode
chung va cathode chung.
Cac thiet b lap trnh co the dung CPLD XC9572, XC 95144, Coolrunner XC2C256.
II. THIET KE MACH GIAI MA MACH MA HOA
1. THIET KE MACH GIAI MA:
Bai 3-1: Thiet ke mach giai ma 2 ng sang 4 ng vi ngo ra tch cc mc cao:
Bc 1: Ve s o khoi cua mach:
DECODE
I0 Q0
Q1
Q2
I1
Q3
2 to 4
I0 Q0
Q1
Q2
I1
Q3
I2 Q4
Q5
E Q6
Q7
3 to 8
end
Ky thuat PLD va ASIC 137
Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
GII THIEU
THIET KE CAC LOAI FLIP FLOP
THIET KE FLIP FLOP JK
THIET KE FLIP FLOP D CO ENABLE
THIET KE THANH GHI DCH
THIET KE THANH GHI DCH 4 BIT
THIET KE THANH GHI DCH 8 BIT
THIET KE MACH EM JOHNSON 8 BIT
THIET KE MACH EM VONG 8 BIT
THIET KE MACH IEU KHIEN 8 LED SANG DAN TAT DAN
THIET KE MACH EM
THIET KE MACH EM NH PHAN 4 BIT EM LEN
THIET KE MACH BCD EM LEN
THIET KE MACH EM BCD VA GIAI MA HIEN TH LED 7 OAN
THIET KE MACH EM BCD T 00 EN 59 HIEN TH TREN 2 LED 7 OAN
THIET KE MACH EM BCD T 000 EN 999 HIEN TH TREN 3 LED 7 OAN
CAU HOI ON TAP VA BAI TAP
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Hnh 4-1. S o khoi FLIP FLIP JK.
Hnh 4-2. S o khoi FLIP FLIP D co enable.
Hnh 4-3. S o khoi thanh ghi 4 bit.
Hnh 4-4. S o khoi thanh ghi 4 bit, nap song song.
Hnh 4-5. S o khoi thanh ghi 8 bit.
Hnh 4-6. S o khoi mach em vong Johnson 8 bit.
Hnh 4-7. S o khoi mach em vong 8 bit.
Hnh 4-8. S o khoi mach ieu khien 8 led sang tat dan.
Hnh 4-9. S o khoi mach em nh phan 4 bit.
Hnh 4-10. S o khoi mach em BCD.
Hnh 4-11. S o khoi mach em BCD co giai ma 7 oan anode chung.
Hnh 4-12. S o khoi mach em t 00 en 59 co hien th.
Hnh 4-13. S o khoi mach em t 000 en 999.
I. GII THIEU:
Trong phan nay se thiet ke cac mach flip flop, thanh ghi va mach em dung ngon ng VHDL
va s dung thiet b lap trnh.
Cac mach flip flop bao gom flip flop JK, flip flop T, flip flop D.
Thanh ghi dch bao gom thanh ghi dch noi tiep sang noi tiep, noi tiep sang song song, mach
em vong, mach em JohnSon.
Mach em nh phan, mach em len em xuong, mach em BCD, mach em at trc so
em, mach em co giai ma sang led 7 oan, mach em giay, em phut giay,
Cac thiet b lap trnh co the dung CPLD XC9572, XC 95144, Coolrunner XC2C256.
II. THIET KE CAC LOAI FLIP FLOP
1. THIET KE FLIP FLOP JK:
Bai 4-1: Thiet ke flip flop JK gom co cac ngo vao J, K, CLK, PRE, CLR va cac ngo ra gom Q
va Q :
Hnh 4-4. S o khoi thanh ghi 4 bit, nap song song, noi tiep.
Bc 2: Lap bang trang thai:
NGO VAO NGO RA Ghi chu
CLR CLK D PL P3 P2 P1 P0 Q3 Q2 Q1 Q0
0 x x x x x x x 0 0 0 0 Reset
1 x x 0 P3 P2 P1 P0 P3 P2 P1 P0 Load
1 0 x 1 x x x x Q30 Q20 Q10 Q00 Khong co xung clk
1 d 1 x x x X Q20 Q10 Q00 d Dch d lieu vao
Bang 4-4. BTT mach thanh ghi dch 4 bit, nap song song, noi tiep.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tghi4b_ntss is
Port ( D : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
D Q0
Q1
CLK
Q2
CLR Q3
Q4
Q5
Q6
Q7
Q0
Q1
CLK Q2
CLR Q3
Q4
Q5
D Q6
Q7
Chu y: Chng trnh sau s dung bien thay v tn hieu nh cac chng trnh tren:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ringcounter8 is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end ringcounter8;
architecture Behavioral of ringcounter8 is
begin
PROCESS (CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR (7 downto 0);
BEGIN
IF CLR = '0' THEN QT:="00000001";
ELSIF CLK='0' AND CLK'EVENT THEN
QT := QT(6 DOWNTO 0) & QT(7);
END IF;
Q <= QT;
Hnh 4-8. S o khoi mach ieu khien 8 led sang tat dan.
Bc 2: Lap bang trang thai:
NGO VAO NGO RA
clr clk Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 THAP PHAN
0 X 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1
1 0 0 0 0 0 0 1 1 2
1 0 0 0 0 0 1 1 1 3
1 0 0 0 0 1 1 1 1 4
1 0 0 0 1 1 1 1 1 5
1 0 0 1 1 1 1 1 1 6
1 0 1 1 1 1 1 1 1 7
1 1 1 1 1 1 1 1 1 8
1 1 1 1 1 1 1 1 0 9
1 1 1 1 1 1 1 0 0 10
1 1 1 1 1 1 0 0 0 11
1 1 1 1 1 0 0 0 0 12
1 1 1 1 0 0 0 0 0 13
1 1 1 0 0 0 0 0 0 14
1 1 0 0 0 0 0 0 0 15
1 0 0 0 0 0 0 0 0 16
1 1 0 0 0 0 0 0 0 17
1 1 1 0 0 0 0 0 0 18
1 1 1 1 0 0 0 0 0 19
1 1 1 1 1 0 0 0 0 20
1 1 1 1 1 1 0 0 0 21
1 1 1 1 1 1 1 0 0 22
1 1 1 1 1 1 1 1 0 23
1 1 1 1 1 1 1 1 1 24
1 0 1 1 1 1 1 1 1 25
1 0 0 1 1 1 1 1 1 26
Q0 I0 a
b
Q1 I1 c
CLK d
CLR Q2 I2 e
f
Q3 I3 g
OSC anod0
1,8432MHz CLK anod1
a
b
c
CLR d
e
f
g
g
d
d
c
c
b
e
a
a
f
end