Amplifiers

MEL 607 ( CMOS Analog
Integrated circuit design )
A Mahesh Kumar
mahesh.kumar@ieee.org
(MANIPAL) MEL 607 1

Syllabus
Introduction and Background: MOS Device Basics, MOS Device
Models, RC Circuits, Passive Devices, Layout, Design Rules. (3 hours)
Single Stage Amplifiers: Common Source Amplifiers, Source
Follower Common Gate, Cascode Structures and Folded Cascode
Structures.
(3 hours)
Differential Amplifier: Introduction to Differential Pair Amplifier,
Quantitative Analysis to Differential Pair Amplifier, Common Mode
Response, Differential Amplifiers with Different Loads, Effects of
Mismatches. (4 hours)
Current Mirrors/Sources: Simple Current Mirrors/Sources, Cascode
Current Mirrors/Sources, Differential Pair with Current Mirror Load.
(4 hours)
Output Stages:
Operational Amplifiers: Op Amps Low Frequency Analysis,
Telescopic Op Amps, Folded Cascode Op Amps, Two Stage Op Amps,
Common Mode Feedback. (4 hours)
(MANIPAL) MEL 607 2

Syllabus
Frequency Response: Frequency Response of Common Source
Amplifiers, Source Follower Common Gate, Cascode Structures and
Folded Cascode Structures, Differential Amplifiers, Single Ended
Differential Pair. (4 hours)
Feedback: Voltage-Voltage, Current -Voltage, Voltage-Current &
Current-Current Feedback, Loading. (3 hours)
Frequency Compensation & Stability: Frequency Compensation
Techniques in Telescopic Op Amps, Folded Cascode Op Amps, Two
Stage Op Amps.(4 hours)
Operational Amplifier Applications: Filters, Applications, A/D's &
D/A's, Pipeline A/D with Open Loop Op Amp Wireless Circuits, RF
Frontend and Review. (3 hours)
(MANIPAL) MEL 607 3

Introduction to
Analog-VLSI Design
(MANIPAL) MEL 607 4

Contents
Title: Introduction to analog-VLSI design
1) What is CMOS?
2) Design flow (with examples)
(MANIPAL) MEL 607 5

What is CMOS
CMOS is a silicon-based integrated circuit fabrication
technology with complementary FETs
1) Conformance with very high integration with

very low power consumption.
2) Complicated analog-digital circuits are allowed
to be mixed together
3) Fabrication process is well matured.
(MANIPAL) MEL 607 6

What is CMOS
4) Easy to be destructed by static discharge.

5) Difficult to implement large capacitors and high
resistors.
6) Allowable power-rail voltage is relatively low.
7) Absolute value for elements is very poor, while
matching is excellent.
(MANIPAL) MEL 607 7

Design Flow
1) Making-up Specs
2) Functional description
3) Transistor-based description+verification
4) Layout design +verification
5) Silicon Process ( front-end, back-end)
(MANIPAL) MEL 607 8

Functional description
1) To design any circuit example opamp we need to

study its application to meet its functionality.
2) Do required analysis in design to meet functionality.
3) Write test bench to check functionality through
simulation.
4) Once Functionality is meet we need to twig design
to meet specifications
(MANIPAL) MEL 607 9

Functional description
Ex: Comparator Should provide non-inverting output and
should meet timing.
(a) (b)
(a) Functional Failure
(b) Functionality is achieved but circuits

doesn't meet specification.
(c) Circuit meet Functionality and

Specification.
(c) (MANIPAL) MEL 607 10
Transistor-based circuit design
W/O large capacitors, and high resistors

DC, AC, Transient, & Noise analysis for circuit
blocks, signal chains, and finally entire chip.
Analysis with SKEW(FAST, TYPICAL, SLOW)
parameter is a mandatory part .
Temperature dependence, power-rail dependence,
and/or bias current sensitivities should be checked out
as a part of final confirmation.
(MANIPAL) MEL 607 11

LAYOUT Design
LAYOUT design is a step to draw mask geometries
for a photo-lithography
Examples (amplifier, Resistance circuit, and etc)
1) DRC
2) LVS
3) Extraction

Silicon Process and Assembly

Mixed signal issues in CMOS
technologies
Mixed signal designs have both analogue and digital
subsections combined. Overall operation of the system relies
on both functionality of each section, and interoperation
between the analogue/digital subsections.

technologies
Backend Aspects
It is very difficult to simulate non-intentional

interactions between analogue and digital sections,
Guard ringing (if appropriate) can give a degree of
noise isolation between analogue and digital sections.
However, this is not the whole story.

technologies
Things to do
Keep analogue/digital supplies separate.

Keep analogue circuitry differential where possible.
Design analogue circuits to rely on device matching
rather than absolute parameters.
Analyse guardrings wrt process and use if applicable.
Simulate in as much detail as possible.

technologies
Things to avoid
Large current switching i/os close to analogue

circuitry.
Routing high speed digital lines close to analogue
reference signals.
Differential ground noise.
Matching small or well separated devices.

CMOS Basics

CMOS Device
Cross section of CMOS n-well technology
Note that the MOS device is a four-terminal
device. The forth terminal is called body or
bulk.
MOS Symbols

Operation of MOSFET
A MOSFET driven by a gate voltage Formation of depletion region
Onset of inversion Formation of inversion layer

I/V Characteristics Triode Region
Condition: VDS VGS - VTH l Derivation
I D = Qd ( x ) v = WC ox [VGS V ( x ) VTH ] v
Equal source and drain voltage dV ( x )
= WC ox [VGS V ( x ) VTH ] n
dx
L VDS
x=0
I D dx =
V =0
WCox n [VGS V ( x ) VTH ]dx
VDS
where V ( x) = x
L
Thus,
W 1 2
I D = n Cox
Unequal source and drain voltage L (VGS VTH )V DS
2
VDS

and
Q d = WCox (VGS VTH ), Cox : F / m 2
1 W
I D ,max = n Cox (VGS VTH ) 2
2 L
Qd ( x ) = WCox [VGS V ( x ) VTH(MANIPAL)

] MEL 607 21
I/V Characteristics Triode Region
Drain current versus drain-source voltage
Linear operation in deep triode

region
With the condition VDS << 2(VGS VTH),

-- deep triode region
1
Ron =
W
n Cox (VGS VTH )
L

I/V Charaeristics Saturation Region
l Pinch-off behavior
Condition: VDS > VGS VTH
1 W
ID = n Cox (VGS VTH ) 2
2 L
Saturated MOSFETs operating

as current sources
1 W
ID = n Cox (VGS VTH ) 2
2 L'
I/V Characteristics Summary
Region NMOS PMOS
VGS<VTHN VGS>VTHP
Cut-off
ID=0 ID=0
VGS>VTHN VGS<VTHP
Triode VDS<VGS-VTHN VDS>VGS-VTHP
(Linear)
ID=0.5nCOX(W/L)[2(VGS- ID=0.5PCOX(W/L)[2(VGS-
VTHN)VDS-VDS2] VTHP)VDS-VDS2]
VGS>VTHN VGS<VTHP
Saturatio VDS>VGS-VTHN VDS<VGS-VTHP
n
ID=0.5nCOX(W/L)(VGS-VTHN) 2 ID=0.5pCOX(W/L)(VGS-VTHP)2

Transconductance
For amplification purposes, the transconductance
of the device is calculated
I D W
gm = = n Cox (VGS VTH )
VGS V DS = constant
L
W 2I D
= 2 n Cox ID =
L VGS VTH
MOS transconductance as functions of:

Second-Order Effects
VTH = VTH 0 + ( 2 F VSB 2 F )

Body effect
where = 2 q Si N sub / Cox denotes the body effect
coefficient.
No body effect Body effect

Example: Source follower with (b) no body effect
and (c) body effect
Ignoring body effect:
As Vin varies, Vout closely follows the input because the drain current remains
equal to I1. It can be written by
nCox (Vin Vout VTH )

1 W
I1 =
2
2 L
Channel-length modulation
I D 1 W
slope = nCox (VGS VTH ) 2
VDS 2 L
L' is a function of VDS .

1 W
L ID n C ox (VGS VTH ) 2 (1 + VDS )
1 (1 + ) 2 L
Let L' = L L, i.e., L
L' L : the channel-length modulation coefficient
L
and assume = VDS .
L

Subthreshold conduction, VGS < VTH
VGS
I D = I 0 exp
VT
where > 1 is a nonideality factor and VT = kT/q.
If W increases while ID remains constant, then VGS

VTH and the device enters the subthreshold
region. As a result, the transconductance is
calculated to gm = ID / (VT),

Voltage-Limitations
JUNCTION BREAKDOWN :-- drain-substrate PN

junction
PUNCH THROUGH:--depletion region touching
HOT CARRIER:--vertical horizontal fields
OXIDE BREAKDOWN:--excess gate voltages
IMPACT IONIZATION:-- substrate current flow

Vds Voltage Impact
Impact of Vds voltage on Short Channel devices
impact as follows.
Channel Length Modulation
DIBL
Impact Ionization

Example
a) Transistor with fixed Vgs and

Vbs with variable Vds
b) Total drain current Id vs Vds
c) Output Conductance with domain

effects marked

MOS Device Capacitances
(1) Oxide capacitance between the gate and the channel, C1 = WLCox.
(2) Depletion capacitance between the channel and the substrate, C2
(3) Capacitance due to the overlap of the gate poly with the source and drain areas, C3 and
C4.The overlap capacitance per unit width is denoted by Cov.
(4) Junction capacitance between the source/drain areas and the substrate.
a. bottom-plate capacitance associated with the bottom of the junction, Cj=Cj0
/[1+VR/(2F)]m.
b. sidewall capacitance due to the perimeter of the junction, CjSW.(note Cj : F/m2,
CjSW : F/m)

Cd : depletion capacitance
COX : cap/unit area
COV : cap/unit length
CDB , CSB : junction capacitance, function of VSB, VDB
CGB ~ 0 when device is on because the inversion layer is

shield between the gate and the bulk.
Region CGB CGD CGS

OFF WLCOX||Cd WCOV WCOV
Linear ~0 WCOV+WLCOX/2 WCOV+WLCOX/2
Saturation ~0 WCOV WCOV+2WLCOX/3

Variation of CGS and CGD versus VGS
Example:

MOS Small-Signal Model
Basic MOS small-signal model
Channel-length modulation represented

by a depend current source
Channel-length modulation represented

by a resistor
VDS 1 1 1
ro = = =
I D I D / VDS 1 C W (V V )2 I D
n ox GS TH
2 L
Body effect represented by a dependent current
source
In the saturation region, g mb can be expressed as
I D
g mb = = n C ox
W
(VGS VTH ) VTH
V BS L V BS
VTH V
We also have = TH = (2 F + V SB )1 / 2
V BS V SB 2
l Example:
Thus,
I D
g mb = = gm = g m
V BS 2 2 F + V SB
where = g mb /g m

Complete MOS small-signal model and frequency
dependent parameters

Complete MOS model
Complete MOS model including small-signal
frequency dependent parameters and Large signal
equivalent circuit.

SPICE MODELS

SPICE
Spice Transistor Model

SPICE
MOS SPICE MODELS

SPICE
Spice Resistor Model
Syntax: Rname n1 n2 <value> <Mname>
<L=Length> <W=Width>
Example: Rload A B RMODEL L=10u W=1u
Spice Capacitor Model

Syntax: Cname n1 n2 <value> <Mname>
<L=Length> <W=Width>
Example: Cfilter A B CMODEL L=10u W=1u

SPICE

SPICE
Solution of DC Equation with Non-Linear Model

SPICE

SPICE

AMPLIFIERS

Principle of Amplification

Amplifiers
Amplifier is a device which increases, the amplitude

of a signal. The "signal" is usually voltage or current.
Amplifiers are divided into two categories
Single Ended Amplifiers
Differential Amplifiers

Low Frequency Parameters

Single Ended Amplifier is defined as one that is

measured with respect to a fixed potential usually
ground.
Single Ended Amplifier are divided into:

Common Source stage
Common drain stage
Common gate stage


Common Source with Resistive Load
MOS device acts as Voltage Controlled current
source (VCCS).
( is neglected)

Common Source with Resistive Load
Small Signal Model for CS Amplifier with Resistive
load
Av = g m (RD || rO )
Rin =
Rout = RD || rO

Diode connected load
Very inefficient to implement a large resistance in
CMOS technology.
CS with resistive load is never implemented on CMOS.
Diode connected transistor can act as resistance.
NMOS or PMOS diode connected load can be used.

Diode connected load
Diode connected load with body bias effect.
Impedance seen at source of M1 is lower when body

effect is included.

CS with diode connected load
Nmos and Pmos diode connected loads.
1
Av = g m1 || rO 2 || rO1
gm2
1
Rout = || rO 2 || rO1
gm2

CS with current source load
Small Signal Model for CS Amplifier with current

source load
Av = g m1 (rO1 || rO 2 )
Rout = rO1 || rO 2

CS stage with Degeneration
RD
If = 0 : Av =
1
+ RS
gm

(a) CS without degeneration (b) CS with degeneration

Degeneration boosts the output impedance:

CS Amplifier Example
Vi
VB

Common drain (source follower)
Common drain amplifier and its input/output
characteristics.
(Output voltage)
(Gain)

Common drain (source follower)
Small signal model of Common drain amplifier.
Voltage gain of source follower with input signal

CD with nmos current source
Av = gm1 ( ro1 || ro2 || 1/gm1)
Body effect is neglected
Rout = 1/(gm + gmb)

Common Gate Amplifier




CD Vs CG Amplifier
Common Drain Common Gate

Summary of Single Stage Amplifiers
Input
Output
Impedance Gain (Av)
Impedance (Rout)
(Rin)
CS Amplifier INF ro1 || ro2 -gm (ro1 || ro2)
CD Amplifier INF 1/(gm + gmb) gm1Rs / [1+(gm2+gmb2)Rs]
{[1+(gm+gmb)ro]Rs
[(gm+gmb)ro+1]RD /
CG Amplifier 1/(gm + gmb) +ro} || RD
ro+(gm+gmb)roRs+Rs+RD

Cascade Circuit

Cascode circuit

Folded Cascode circuit

Differential Amplifiers

Single-Ended & Differential Operation
Single-ended signal is one that is measured with

respect to a fixed potential usually the ground.
Differential signal is one that is measured between
two nodes that have equal and opposite signal around
a fixed potential.

Advantages of Differential Operation
Higher Immunity to Environmental Noise.

Rejects power supply noise

Reduction of coupled noise due to differential

operation.

Advantages
Differential input
Good bias stability
Robust to supply noise
High Common-mode noise rejection
Higher voltage swing
Used in all major blocks of Analog design

Basic Differential pair

Modified Differential pair

Operation with a Differential Input Voltage
The MOS differential pair

with a differential input signal
vid applied.
With vid positive: vGS1 >
vGS2, iD1 > iD2, and vD1 < vD2;
thus (vD2 - vD1) will be
positive.
With vid negative: vGS1 <
vGS2, iD1 < iD2, and vD1 > vD2;
thus (vD2 - vD1) will be
negative.
Large Signal operation



Nonlinear curves.
Maximum value of input differential voltage.
When vid = 0, two drain currents are equal to I/2.
Linear segment.
Linearity can be increased by increasing overdrive
voltage (see next slide).

The linear range of operation of the MOS differential pair can be extended by
operating the transistor at a higher value of VOV.

Differential amplifier parameters
The diff amplifier topology contains two inputs, two
two loads ( variable ), along with a dc current source
We will define the

differential mode of the input vi,dm = v1 v2
common mode of the input as vi,cm= (v1+v2)
Using these definitions, the inputs v1 and v2 can be written as
linear combinations of the differential and common modes
v1 = vi,cm + vi,dm
v2 = vi,cm vi,dm
These definitions can also be applied to the output voltages

Differential mode vo,dm = vo1 vo2
Common mode vo,cm = (vo1 + vo2)
Alternately, these can be written as

vo1 = vo,cm + vo,dm
vo2 = vo,cm vo,dm


Small-Signal Operation of MOS
Differential Pair
Differential gain
Common-mode gain
Common-mode rejection ratio (CMRR)
Mismatch on CMRR

Differential Gain
Half Circuit Method

Differential Gain
Differential gain
Output taken single-ended
vo1 vo 2 1
Ad 1 = = 12 g m RD Ad 2 = = 2 g m RD
vid vid
Output taken differentially
vo
Ad = = g m RD
v id
Advantages of output signal taken differentially
Reject common-mode signal
Increase in gain by a factor of 2
Differential Gain
Differential gain

vo1
Ad 1 = = 12 g m ( RD // ro )
vid
vo 2 1
Ad 2 = = 2 g m ( RD // ro )
vid
vo
Ad = = g m ( RD // ro )
vid
Operation with common mode input
voltage

Common mode Gain
Common Mode circuit Analysis

Common mode Gain
Common-mode gain

vo1 vo 2 RD / 2 RD g m
Acm1 = Acm 2 = = =
vicm vicm 1
+ Rss 1 + 2 g m Rss
2 * gm

vo 2 vo1
Acm = =0
vicm

CMRR
Common-mode rejection ratio (CMRR)
Ad 1 Ad 2
CMRR = = g m Rss
Acm1 Acm 2
CMRR =
This is true only when the circuit is perfectly
matched.
Mismatch on CMRR
Effect of RD mismatch on CMRR

RD
vo = vo 2 vo1 = vicm
2 Rss
RD
CMRR = (2 g m Rss ) ( )
RD
Effect of gm mismatch on CMRR

g m
CMRR = (2 g m Rss ) ( )
gm

Differential Amplifier with MOS
Loads

Current Mirror
Unity gain (Iin=Iout)

Parameters of Current Mirror
Small signal output resistance Ro
Systematic Gain error - (E)
Input voltage Vin (minimum low-voltage app.)
Output voltage- Vout (minimum-high swing)

SimpleMOS current mirror

Cascode current mirror

Max-Swing

Sooch-Current Mirror

High Swing Two Branches

Wilson Current Mirror

Differential Amplifier with current
mirror load
Large Signal Operation

mirror load
Small Signal Operation

mirror load

Output Stages
Functions of output stage

Lower output resistance
Efficient delivery of needed power
However, the DC bias current should be low to
avoid Static power dissipation
Follower circuit
Unity voltage gain
Low output resistance
Efficiency?
Class A (Source follower)
Transistors conducting for a full cycle.

Typical Follower circuit.
vi VDD + VT
Rout 1
gm
vo = vi vGS

Voltage Characteristics

Efficiency for a Class A output stage :

Efficiency: Power delivered to the load divided by
power supplied by amplifier.
PL
=
PS
Sinusoidal input
Uses full output range
Maximum output voltage

Neglecting VGS1 voltage drop
Output is
vo VDD sin (t + o )
Average power supplied is
0
1 T VDD sin (t + o )
PS = 0 I SS (VSS + VDD ) + VDD dt
T RL
Current flowing
between supplies Current flowing
through load
PS = 2 I SSVDD
Average power through load
2
VDD
2
PL =
2 VDD
=
RL 2 RL
Efficiency
2 2
VDD VDD
2 RL 2 RL 1
= = = or = 25%
2
2 I SSVDD VDD 4
2
RL
Push-pull stage (Class B)
Both M1 and M2 transistors acts as source

follower or voltage buffer driving low output
resistance

Push-pull stage (Class B)
Input and Output waveforms of Class B circuit.
Problem
Dead Zone

Class B efficiency
Load approximately power 2
VDD
PL =
RL
Power supplied
1 T2 VDD 2 2V 2
PS = 2g 0 VDD sin t dt = DD
T RL T RL
Efficiency
2
VDD
2 RL
= 2
= or = 78.5%
2VDD 4
RL
Class AB output stage
Problem with class B: distortion
Solution
Reduce dead zone by having a small current
flow through transistor when off



Summary
Output stages
Class A
Always conducting, Inefficient
Class B
Conduct only half the cycle, Distortion
Class AB
Small conduction during half cycle when Class
B would be off
Eliminates distortion

Operational Amplifier

Operational amplifier
Operational amplifier is High-gain differential
Amplifier
Operational amplifier, or simply OpAmp refers to an

integrated circuit that is employed in wide variety of
applications.
Noninverting input
v o = Ad ( v i 1 v i 2 )
v i1 vi 2 Inverting input

Operational amplifier
What makes an ideal OpAmp
infinite input impedance
Infinite open-loop gain for differential signal
zero gain for common-mode signal
zero output impedance
Infinite bandwidth
Some useful amplifier circuits
Inverting amplifier
R2
R1 A v = v out / v in = R 2 / R1
Z in = R1
v out Rl Z out = 0
v in
Noninverting amplifier
R2
R1 A v = v out / v in = 1 + R 2 / R1
Z in =
v in v out Rl Z out = 0

Performance parameters of opamp
Gain.
Small Signal Bandwidth.
Output Swing.
Linearity.
Noise and offset.
Supply Rejection.
Parameters of interest-small signal
bandwidth

Parameters of interest-Slew Rate

Parameters of interest

Opamp Topologies
Basic one stage Opamp
Telescopic Opamp
Folded Cascode Opamp
Two Stage Opamp
Common mode feedback Circuit

One-stage opamp
Low Frequency Gain (Av)

One-stage opamp with unity gain
configuration

Telescopic Opamp
Low Frequency Voltage Gain (Av) & Small Signal Output resistance



Low Frequency Voltage Gain (Av) & Small Signal Output resistance

One-Stage Op Amp
Single stage opamp is divided in to two groups
Bias stage
Gain/Bandwidth stage

Two-Stage Op Amp
In single stage there are tradeoff between output

swing, gain and bandwidth.
First stage providing High gain and second stage

providing large swings.

Two-Stage Op Amp

Two-Stage Op Amp

Two-Stage Op Amp
Basic two stage opamp is divided in to three groups
Bias stage
Gain/Bandwidth stage
Output stage.

Op Amp design constraints
DC gain
Gain-bandwidth
Phase Margin
ICMR
Load Capacitance.
Slew Rate
Output Swing
Power Budget.

Comparison of Opamp topologies

Common Mode Feedback
CMFB Operation: Sensing the output CM level,

Comparison with a reference, and returning the error
to the amplifiers bias network.
Frequency Response

Poles and Zeros

Poles and Zeros significance

Impact of Pole

Gain and Phase response due to pole

Impact of Zero

Gain and Phase response due to zero

Millers Theorem

Limitation of Miller Theorem

Association of Poles with Nodes

Common Source Stage

Common Source Stage
This results are not valid when Rs value is large.

Common Source Stage

Source Follower

Source Follower
Interesting Points :
Zero at left hand plane.

If you assume two poles are far from each other,
then dominant pole will be

Output Impedance

Input Impedance

Source Follower

Common Gate
Wout= 1/[(CDG+CDB)*RD]

Cascode Stage
Here we have three poles & one zero.

Feedback

Feedback General Consideration


It is instructive to find four elements in the feedback
system.
Feed forward Amplifier
Sensing the output
Feedback Network
Generating the feedback error

Properties of Feedback Circuits
Gain Desensitization
Terminal Impedance modification
Bandwidth Modification
Nonlinearity Reduction

Feedback Topologies

Voltage Voltage Feedback
Voltage voltage or series shunt Feedback.
Gain Calculation

Rin Calculation
V e = I X R in
V F = A 0 I X R in
V e = V X V F = V X A 0 IX R in
IX R in = V X A 0 IX R in
V X / I X = R in (1 + A 0 )

Rout Calculation
IX = [VX VeA0]
IX = [VX ( A0VX )] / Rout
VX / IX = Rout /(1 + A0)

Voltage - Current Feedback
voltage current or shunt shunt Feedback.
Gain Calculation
IF = [ gmFVout]
Ie = Iin IF
Vout = RoIe = Ro(Iin gmFVout)
Vout / Iin = Ro /(1 + gmFRo)

Rin Calculation
IF = IX VX / Rin
(VX / Rin ) gmFR 0 = IF
VX / IX = Rin /(1 + gmFR 0)

Rout Calculation
IF = VX ( gmF )
Ie = IF
VM = R 0 gmFVX
IX = (VX VM ) / Rout
IX = (VX + R 0 gmFVX ) / Rout
VX / IX = Rout /(1 + gmFR 0)

Current Current Feedback
current current or shunt series Feedback.
Gain Calculation
Iout / Iin = AI /(1 + AI )

Current Current Feedback
Rin Calculation
V X / IX = R in /(1 + A I )
Rout Calculation
V X / I X = R out (1 + A I )

Current Voltage Feedback
current voltage or series series Feedback.
Gain Calculation
VF = RFIout
Ve = Vin VF
Ve = Vin RFIout
Iout = Gm (Vin RFIout )
Iout / Vin = Gm /(1 + GmRF )

Rin Calculation
IX R in G m = Iout
V e = V X G m R F IX R in
V X / IX = R in (1 + G m R F )

Rout Calculation
VF = RFIX
RFIXGm = IX VX / Rout
VX / IX = Rout (1 + GmRF )

Stability & Compensation

Stability General Considerations

Multi pole system

Phase Margin

Frequency Compensation

Two Stage Opamp

2 Pole System Response

Negative Feedback System

Pole Splitting

Two Stage Opamp Circuit

High Frequency Equivalent Circuit

High Frequency Response

Zero cancellation using nulling resistor

Analog Layout

Analog Layout
Geometrically or Mask representation of circuits
represents Analog Layout.
Example

Goals of Analog Layout
Minimum Parasitics
Low Cross Talks
Minimum Noise
Device Matching
Antenna Effect
Latch up

Minimum Parasitics
Mos device capacitances

Minimum Parasitics
Example

Minimum Parasitics
Minimum Interconnect resistance

Low Cross Talks
Cross Talk is because of
Parallel Plate capacitance
Fringe Capacitance (Side Wall Capacitance)
Avoid Cross Talk

Avoid Long Parallel runs of signals
Greater spacing between sensitive lines
Shielding Sensitive signals

Minimum Noise
Two Major sources of the noise
Substrate Noise ( Coupled into the circuit )
Digital Noise ( Via Power supply )
Techniques to reduce noise

Power supply routing
Placement
Epitaxial Layer
Guard Rings
Dual well process
Device Matching

Device Matching
Orientation

Device Matching
Symmetric

Device Matching
Interdigitized Matching
Interdigitation distributes transistors uniformly

Device Matching
Common centroid Matching
Common centroid configuration eliminates the
first order gradient effects of parameters
along both the axes

Device Matching
Dummy gates for outside transistors

Antenna Effect

Latch Up

Latch Up

Failure Mechanisms
Failure mechanisms which are entirely prevented by
layout Precautions
Electrical over stress

Contamination
Surface effects

Thank You

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MEL 607 ( CMOS Analog

Integrated circuit design )

(MANIPAL) MEL 607 1

(MANIPAL) MEL 607 2

(MANIPAL) MEL 607 3

(MANIPAL) MEL 607 4

Title: Introduction to analog-VLSI design

2) Design flow (with examples)

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1) Conformance with very high integration with

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4) Easy to be destructed by static discharge.

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4) Layout design +verification

5) Silicon Process ( front-end, back-end)

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1) To design any circuit example opamp we need to

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(a) Functional Failure

(b) Functionality is achieved but circuits

(c) Circuit meet Functionality and

W/O large capacitors, and high resistors

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It is very difficult to simulate non-intentional

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Keep analogue/digital supplies separate.

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Large current switching i/os close to analogue

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Onset of inversion Formation of inversion layer

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Qd ( x ) = WCox [VGS V ( x ) VTH(MANIPAL)

Linear operation in deep triode

With the condition VDS << 2(VGS VTH),

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Saturated MOSFETs operating

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MOS transconductance as functions of:

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VTH = VTH 0 + ( 2 F VSB 2 F )

No body effect Body effect

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Ignoring body effect:

equal to I1. It can be written by

nCox (Vin Vout VTH )

L' is a function of VDS .

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where > 1 is a nonideality factor and VT = kT/q.

If W increases while ID remains constant, then VGS

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JUNCTION BREAKDOWN :-- drain-substrate PN

PUNCH THROUGH:--depletion region touching

HOT CARRIER:--vertical horizontal fields

OXIDE BREAKDOWN:--excess gate voltages

IMPACT IONIZATION:-- substrate current flow

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a) Transistor with fixed Vgs and

b) Total drain current Id vs Vds