Optimized 40-character title for schematic document sections

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2010-07-22
SCHEMATIC MBA , MLB D

D
08/28/10
(.csa) Date (.csa) Date
Page Contents Sync Page Contents Sync

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
1 57 07/07/2010
1 Table of Contents 46 WELLSPRING 1 K16_MLB
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2 12/11/2009 61 07/07/2010
2 System Block Diagram K6_MLB 47 SPI ROM K16_MLB
3 12/11/2009 66 02/09/2010
3 Power Block Diagram K6_MLB 48 AUDI0: SPEAKER AMP AUDIO

4 12/11/2009 69 11/09/2009
4 K99 BOM Variants K6_MLB 49 DC-In & Battery Connectors K84_MLB
5 07/20/2009 70 11/09/2009
5 BOM Configuration K24_MLB 50 PBus Supply & Battery Charger K6_MLB
6 01/19/2009 72 07/07/2010
6 Revision History K24_MLB 51 5V / 3.3V Power Supply K16_MLB
7 12/11/2009 73 07/07/2010
7 FUNCTIONAL TEST K6_MLB 52 1.5V/1.35V LVDDR3 Supply K16_MLB
8 12/11/2009 74 07/13/2005
8 Power Aliases K6_MLB 53 IMVP6 CPU VCore Regulator POWER
9 12/11/2009 75 12/11/2009
9 SIGNAL ALIAS K6_MLB 54 MCP VCore Regulator K6_MLB
10 07/07/2010 76 07/07/2010
10 CPU FSB K16_MLB 55 CPUVTT (1.05V) Power Supply K16_MLB
11 07/07/2010 77 07/07/2010
11 CPU Power & Ground K16_MLB 56 Misc Power Supplies K16_MLB
12 03/24/2010 78 07/07/2010
12 CPU Decoupling & VID K16_MLB 57 Power Sequencing K16_MLB
13 07/07/2010 79 07/07/2010
13 eXtended Debug Port (Micro-XDP) 58 Power FETs
C TABLE_TABLEOFCONTENTS_ITEM
14
14
MCP CPU Interface
K16_MLB
K16_MLB
07/07/2010
TABLE_TABLEOFCONTENTS_ITEM
59
90
Internal DisplayPort Connector
K16_MLB
K16_MLB
07/07/2010 C
15 07/07/2010 93 07/07/2010
15 MCP Memory Interface K16_MLB 60 External DisplayPort Support K16_MLB

16 07/07/2010 94 07/07/2010
16 MCP PCIe Interfaces K16_MLB 61 DisplayPort Connector K16_MLB
17 07/07/2010 97 03/31/2010
17 MCP Graphics K16_MLB 62 LCD Backlight Driver K16_MLB
18 07/07/2010 98 07/07/2010
18 MCP SATA, USB & Ethernet K16_MLB 63 LCD Backlight Support K16_MLB
19 07/07/2010 99 07/07/2010
19 MCP HDA, LPC & MISC K16_MLB 64 Additional CPU/GPU Decoupling K16_MLB
20 07/07/2010 100 07/07/2010
20 MCP Power & Ground K16_MLB 65 CPU/FSB Constraints K16_MLB

23 07/07/2010 101 07/07/2010
21 MCP89 Memory Rail Gating K16_MLB 66 Memory Constraints K16_MLB

24 07/07/2010 102 07/07/2010
22 MCP89 GFX Core Rail Gating K16_MLB 67 MCP Constraints 1 K16_MLB

25 07/07/2010 103 07/07/2010
23 MCP Standard Decoupling K16_MLB 68 MCP Constraints 2 K16_MLB

26 07/07/2010 104 07/07/2010

24 MCP Graphics Support K16_MLB 69 Ethernet Constraints K16_MLB
28 12/11/2009 106 07/07/2010

25 SB Misc K6_MLB 70 SMC Constraints K16_MLB
31 07/07/2010 108 07/07/2010

26 DDR3 DRAM Channel A (0-31) K16_MLB 71 K16/K99 Specific Constraints K16_MLB
32 07/07/2010 109 07/07/2010

27 DDR3 DRAM Channel A (32-63) K16_MLB 72 K99 RULE DEFINITIONS K16_MLB
33 07/07/2010 110 07/07/2010

28 DDR3 DRAM Channel B (0-31) K16_MLB 73 Acoustic Cap BOM Config Tables K16_MLB
34 07/07/2010
29 DDR3 DRAM Channel B (32-63) K16_MLB
35 07/07/2010
30 DDR BYPASSING 1 K16_MLB
B TABLE_TABLEOFCONTENTS_ITEM
31
36
37
DDR BYPASSING 2 K16_MLB
07/07/2010
07/07/2010
B
32 Memory Active Termination K16_MLB
39 07/07/2010
33 FSB/DDR3 Vref Margining K16_MLB
40 07/07/2010
34 X21 WIRELESS CONNECTOR K16_MLB
45 07/07/2010
35 SATA CONNECTOR K16_MLB
46 07/07/2010
36 External USB Connectors K16_MLB
47 N/A
37 LIO CONNECTORS N/A
49 07/07/2010
38 SMC K16_MLB
50 07/07/2010
39 SMC Support K16_MLB
51 07/07/2010
40 LPC+SPI Debug Connector K16_MLB

52 07/07/2010
41 K16/K99 SMus Connections K16_MLB
53 07/07/2010
42 Voltage & Current Sensing K16_MLB
54 07/07/2010
43 Current Sensing K16_MLB
55 07/07/2010
44 Thermal Sensors K16_MLB
56 07/07/2010
45 Fan K16_MLB
A A
DRAWING TITLE
SCHEM,MLB,K99
DRAWING NUMBER SIZE
Apple Inc. 051-8379 D

REVISION
R
4.4.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 110
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1000
INTEL CPU J1300
1.6 GHZ XDP CONN

PG 13
PENRYN
1GB
PG 10
D
FSB
64-BIT
800MHZ
BASE FREQ.=200MHZ
U3100,U3200
MEMORY
D
128MX8
DDR3-1066/1333MHZ
PG 14 J6950,U7000
A PG 26,27
64-BIT 1GB
CHARGER,BATT CONN POWER SUPPLY
PG 50,51 PG 52-57
MAIN
GPIO FSB INTERFACE MEMORY
U5515.U5535
U3300,3400
PG 19 PG 15 MEMORY CPU/MCP TEMP SENSOR
DDR3-1066/1333MHZ 128MX8 PG 44
B
64-BIT
PG 28,29
Y2815
RTC XTAL VOLTAGE/CURRENT SENSOR

32.768KHZ
PG 42,43
PG 25
MISC
J5600
U6100
Y2810 PG 19 SPI
SPI FAN CONN
MCP BOOTROM PG 45
25MHZ PG 19
PG 48
PG 25 U5920
SATA SMS
PG 47
SUPPORT GEN3,6.0GB/S
NVIDIA
UP TO 2 PORTS
J4501 U4900
SSD MCP89U-A01 J5100

SMB_BSA SMB_B/0 ADC FAN0 SMS
SATA SATA 2.0 3GBIT/S

SATA_A0 LPC
C CONN 24.5X24.5MM
0.6MM PITCH PG 19
LPC+SPI
CONN
PG 40
SERIAL
PORT SMC
PG 38
C
PG 35 PM_SLP
FCPBGA S3/S4
LID SYS_LED SMB_A
1244P
PG 18
FLAT
PANEL
PWR
CTRL J6955
LVDS OUT
RGB OUT HALL EFFECT
HDMI OUT CONN
DVI OUT PG 19
TMDS OUT
J9000 PG 50
INTERNAL
DISPLAY X2 DP LINK
DP1[1:0]
J5700
CONN USB 2.0 TRACKPAD
PG 60
(IPD)
CONN
X4 DP LINK DP0[3:0] PG 46
J9400
EXTERNAL USB_2
DISPLAY PG 17
PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES
PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES
CONN PCI-E USB_6
(UP TO 8 DEVICES)
PG 62
USB_0
J4600
USB_7 RIGHT
EXT USB
CONN
B USB_5
PG 36
B
PG 18 USB_4
J4001 LAN
PCIE GEN1 SMB HDA
AIRPORT+ PE1_0 RGMII J6903
BLUETOOTH PG 16 PG 18 PG 19 PG 19
CONN SIL+
U6610
SPEAKER
PG 34 SPEAKER CONN
AMPS
PG 50
PG 49
J4700 I2C HDA USB USB SPK

MIKEY CAMERA EXT
LIO FLEX CONN I2C

LIO
PG 37
J4702 J4610 U6201
CAMERA+ LEFT
ALS EXT USB
CONN CONN
PG 5 PG 6
AUDIO CODEC
PG 6
A SYNC_MASTER=K6_MLB SYNC_DATE=12/11/2009 A
PAGE TITLE
U6620
System Block Diagram
LIO BOARD SPEAKER
AMPS
LINE IN
FILTER
HEADPHONE
FILTER DRAWING NUMBER SIZE
PG 9 PG 11 PG 8
REVISION
R
4.4.0
J6702 J6700 NOTICE OF PROPRIETARY PROPERTY: BRANCH
LEFT HEADPHONE/ THE INFORMATION CONTAINED HEREIN IS THE
SPEAKER LINE IN PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
CONN JACK THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PG 10 PG 10 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP18V5_DCIN_CONN
POWER SYSTEM ARCHITECTURE
Q7080
02
PPDCIN_G3H_OR_PBUS ENABLE
3.425V G3HOT 03 SMC PWRGD 04
PP3V42_G3H_REG
Q7085 PBUS_VSENSE LT3470 RN5VD30A-F
VOUT
U6990 U5010
8A FUSE V Q5315
D
D PPVBAT_G3H_CHGR_REG PPBUS_G3H PBUS_G3H_VSENSE
01 F7040
02
VIN
CPUVTTS0_EN PP1V05_S0
CHGR_EN EN_PSV VOUT
(S5) (S0)
F6905 CPUVTT (8A MAX CURRENT)
6A FUSE ENABLES (1.05V)
AC DCIN(16.5V) MCP89 06-1
ADAPTER
IN
A VIN
VOUT
ISL95870
U7600 PWRBTN*
R7050
R7020 SMC_BATT_ISENSE 31
PBUS SUPPLY/ PGOOD
SMC_DCIN_ISENSE
BATTERY CHARGER A CPUVTTS0_PGOOD
PLTRST* LPC_RESET_L
RSMRST*
ISL6259 MCP_PS_PWRGD
U7000 01 V SMC_CPU_VSENSE
29
PWRGD
CPUPWRGD(GPIO49)
CPU_PWRGD
CPU VCORE PPVCORE_S0_CPU
02 26 30
VOUT
VIN (44A MAX CURRENT)
J6950 SMC_CPU_ISENSE U2850 CPU_RESET#
FSB_CPURST_L
ISL6261A
U1400
IMVP_VR_ON_R
VR_ON
3S2P Q7055 28
PPVBAT_G3H_CONN PPVBAT_G3H_CHGR_R 25 PGOOD VR_PWRGOOD_DELAY
(9 TO 12.6V)
U7400
C CPU C
CHGR_BGATE
PPBUS_G3H 4.5V AUDIO PWRGOOD
VIN MAX8840
U6200 PP4V5_AUDIO_ANALOG
EN VOUT RESET*
U1000
32
MCP89 11 11-1
P3V3S3_EN
PM_SLP_S4_L Q7940
SMC 02 PP5V_S0_FET
P16
15
VIN
PM_SLP_S3_L P5VS3_EN_L PP5V_S3_REG
11-3
U4900 04 5V VOUT1 17
EN1 P5VS0_EN
(RT) (13A MAX CURRENT)
RC
DDRREG_EN SMC_PM_G2_EN
U1400 P60 05
DELAY (S5) PP3V3_S5_REG
VOUT2
P3V3S5_EN_L (5.5A MAX CURRENT) 07
EN2 3.3V
Q7910
U7840 TPS51980
02 PP3V3_S3_FET
11-2 U7201 13
RC
P5VS3_EN_L PGOOD1,2 VREG3 Q4050
DELAY VIN
P3V3S3_EN P3V3_S3_WLAN
MC34845 P5V3V3_PGOOD
U9700 PPVOUT_SW_LCDBKLT
BKLT_EN
ENA VOUT PM_WLAN_EN_L
24 SMC 10
B Q7930 ALL_SYS_PWRGD
RSMRST_OUT(P15) PM_RSMRST_L B
PWRGD(P12) 99ms DLY
18 IMVP_VR_ON_R
PP3V3_S0_FET IMVP_VR_ON(P16) 25
09 RSMRST_PWRGD
VIN RSMRST_IN(P13)
Q7890 PP0V9_S5_REG
AP_PWR_EN EN VOUT PLT_RST*
SMC_ONOFF_L
PM_WLAN_EN_L 1.8V PWR_BUTTON(P90)
16 ISL8009B P3V3S0_EN TPS62202
PP1V8_S0_REG PM_PWRBTN_L
P17(BTN_OUT)
U7750 U7760
05
SMC_RESET_L
RST*
P1V5S0_PGOOD
1.5V
PP1V5_S0_REG
ISL8009B P5V3V3_PGOOD
SLP_S5_L
Q7890,Q7891 U7710 SLP_S5_L(P95)
MCPCORES0_PGOOD SLP_S4_L
PM_SLP_S3_L SLP_S4_L(P94)
CPUVTTS0_PGOOD
SLP_S3_L
SMC_ADAPTER_EN 04-1 1.05V SLP_S3_L(P93)
Q2300 MCPPLLDO_PGOOD
TPS74701
PP1V5R1V35_SW_MCP S0PGOOD_RST_L U4900
U7740
21
02 PP1V05_S0_MCP_PLL_REG
1.2V
VIN ST1S12G12R PP1V2_ENET_REG
=DDRREG_EN 1.5V MCPMEM_GATE PP1V5_S3_REG U7720
S5 VOUT1
(12A MAX CURRENT) RST*
PM_SLP_S3_L =DDTVTT_EN 14
S3 0.75V PP3V3_S0 V1
VOUT2 PP0V75_S0_REG
PP1V5_S0
(1A MAX CURRENT) V2
P1V8S0_EN
A RC
DELAY
16-3
PBUSVSENSE_EN
16-1 TPS51116
U7300
PP1V05_S0
V3
ISL88042 SYNC_MASTER=K6_MLB SYNC_DATE=12/11/2009 A
(S0) 20 PAGE TITLE
U7870
RC P1V5S0_EN 16-1 MCP_CORE
PPMCPCORE_S0_R R7525 PPMCPCORE_S0_REG Power Block Diagram
16-4 P5VS0_EN VOUT DRAWING NUMBER SIZE
DELAY MCPCORES0_EN
(S0)
EN (25A MAX CURRENT)
REVISION
R
RC CPUVTTS0_EN
16-6
RC
P3V3S0_EN
16-2 4.4.0
DELAY DELAY NOTICE OF PROPRIETARY PROPERTY: BRANCH
DDRVTT_EN
VIN THE POSESSOR AGREES TO THE FOLLOWING: PAGE
RC MCPCORES0_EN
DELAY
16-5
02
ISL9563B I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
3 OF 110
U7500 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants Bar Code Labels / EEE #s
DRAM CFG CHART

TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM
639-0651 PCBA,MLB,HY 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DX7,DDR3:HYNIX_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DX7] CRITICAL EEE:DX7
TABLE_BOMGROUP_ITEM
639-1055 PCBA,MLB,HY 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD15,DDR3:HYNIX_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0L] CRITICAL EEE:DD0L VENDOR CFG 1 CFG 0
TABLE_BOMGROUP_ITEM
639-1048 PCBA,MLB,HY 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0X,DDR3:HYNIX_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0M] CRITICAL EEE:DD0M
TABLE_BOMGROUP_ITEM
HYNIX 0 0
639-1043 PCBA,MLB,HY 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Q,DDR3:HYNIX_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0N] CRITICAL EEE:DD0N
TABLE_BOMGROUP_ITEM
639-1044 PCBA,MLB,HY 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0R,DDR3:HYNIX_4GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0P] CRITICAL EEE:DD0P SAMSUNG
TABLE_BOMGROUP_ITEM
1 0
639-1039 PCBA,MLB,HY 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0L,DDR3:HYNIX_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0Q] CRITICAL EEE:DD0Q
TABLE_BOMGROUP_ITEM
MICRON 0 1
D 639-1045 PCBA,MLB,SA 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0T,DDR3:SAMSUNG_2GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0R] CRITICAL EEE:DD0R
D
639-1054 PCBA,MLB,SA 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD14,DDR3:SAMSUNG_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0T] CRITICAL EEE:DD0T ELPIDA 1 1
TABLE_BOMGROUP_ITEM
639-1049 PCBA,MLB,SA 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Y,DDR3:SAMSUNG_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0V] CRITICAL EEE:DD0V
TABLE_BOMGROUP_ITEM
SIZE CFG 2 DIE REV CFG 3

639-1052 PCBA,MLB,SA 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD12,DDR3:SAMSUNG_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0W] CRITICAL EEE:DD0W
TABLE_BOMGROUP_ITEM
639-1046 PCBA,MLB,SA 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0V,DDR3:SAMSUNG_4GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0X] CRITICAL EEE:DD0X
TABLE_BOMGROUP_ITEM
2GB 0 A 0
639-1040 PCBA,MLB,SA 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0M,DDR3:SAMSUNG_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD0Y] CRITICAL EEE:DD0Y
TABLE_BOMGROUP_ITEM
4GB B 1
639-1042 PCBA,MLB,MI 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0P,DDR3:MICRON_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD10] CRITICAL EEE:DD10 1
TABLE_BOMGROUP_ITEM
639-1053 PCBA,MLB,MI 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD13,DDR3:MICRON_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD11] CRITICAL EEE:DD11
TABLE_BOMGROUP_ITEM
639-1047 PCBA,MLB,MI 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0W,DDR3:MICRON_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD12] CRITICAL EEE:DD12
TABLE_BOMGROUP_ITEM
639-1051 PCBA,MLB,MI 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD11,DDR3:MICRON_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD13] CRITICAL EEE:DD13
TABLE_BOMGROUP_ITEM
639-1041 PCBA,MLB,MI 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD0N,DDR3:MICRON_4GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD14] CRITICAL EEE:DD14
TABLE_BOMGROUP_ITEM
639-1050 PCBA,MLB,MI 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DD10,DDR3:MICRON_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DD15] CRITICAL EEE:DD15
TABLE_BOMGROUP_ITEM
639-1446 PCBA,MLB,1.6GHZ,EL 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4Q,DDR3:ELPIDA_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF82] CRITICAL EEE:DF82
TABLE_BOMGROUP_ITEM
639-1438 PCBA,MLB,1.6GHZ,EL 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4G,DDR3:ELPIDA_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF83] CRITICAL EEE:DF83
TABLE_BOMGROUP_ITEM
639-1444 PCBA,MLB,1.6GHZ,EL 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4N,DDR3:ELPIDA_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF84] CRITICAL EEE:DF84
TABLE_BOMGROUP_ITEM
639-1449 PCBA,MLB,1.6GHZ,EL 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4V,DDR3:ELPIDA_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF85] CRITICAL EEE:DF85
TABLE_BOMGROUP_ITEM
639-1448 PCBA,MLB,1.6GHZ,EL 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4T,DDR3:ELPIDA_4GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF86] CRITICAL EEE:DF86
TABLE_BOMGROUP_ITEM
639-1445 PCBA,MLB,1.6GHZ,EL 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.6GHZ,EEE:DG4P,DDR3:ELPIDA_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF87] CRITICAL EEE:DF87
C 607-6999 CMN PTS,PCBA,MLB,K99 K99_COMMON

TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
825-7557 1 LABEL,MLB,K16/K99 [EEE_DF88] CRITICAL EEE:DF88 C
085-1121 K99 MLB DEVELOPMENT BOM K99_DEVEL:ENG 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF89] CRITICAL EEE:DF89
TABLE_BOMGROUP_ITEM
639-1355 PCBA,MLB,1.4GHZ,HY 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8L,DDR3:HYNIX_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8C] CRITICAL EEE:DF8C
TABLE_BOMGROUP_ITEM
639-1341 PCBA,MLB,1.4GHZ,HY 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF83,DDR3:HYNIX_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8D] CRITICAL EEE:DF8D
TABLE_BOMGROUP_ITEM
639-1353 PCBA,MLB,1.4GHZ,HY 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8J,DDR3:HYNIX_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8F] CRITICAL EEE:DF8F
TABLE_BOMGROUP_ITEM
639-1350 PCBA,MLB,1.4GHZ,HY 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8F,DDR3:HYNIX_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8G] CRITICAL EEE:DF8G
TABLE_BOMGROUP_ITEM
639-1356 PCBA,MLB,1.4GHZ,HY 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8M,DDR3:HYNIX_4GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8H] CRITICAL EEE:DF8H
TABLE_BOMGROUP_ITEM
639-1348 PCBA,MLB,1.4GHZ,HY 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8C,DDR3:HYNIX_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8J] CRITICAL EEE:DF8J
TABLE_BOMGROUP_ITEM
639-1349 PCBA,MLB,1.4GHZ,SA 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8D,DDR3:SAMSUNG_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8K] CRITICAL EEE:DF8K
TABLE_BOMGROUP_ITEM
639-1351 PCBA,MLB,1.4GHZ,SA 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8G,DDR3:SAMSUNG_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8L] CRITICAL EEE:DF8L
TABLE_BOMGROUP_ITEM
639-1357 PCBA,MLB,1.4GHZ,SA 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8N,DDR3:SAMSUNG_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8M] CRITICAL EEE:DF8M
TABLE_BOMGROUP_ITEM
639-1344 PCBA,MLB,1.4GHZ,SA 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF86,DDR3:SAMSUNG_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DF8N] CRITICAL EEE:DF8N
TABLE_BOMGROUP_ITEM
639-1352 PCBA,MLB,1.4GHZ,SA 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8H,DDR3:SAMSUNG_4GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4G] CRITICAL EEE:DG4G
TABLE_BOMGROUP_ITEM
639-1354 PCBA,MLB,1.4GHZ,SA 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF8K,DDR3:SAMSUNG_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4H] CRITICAL EEE:DG4H
TABLE_BOMGROUP_ITEM
639-1342 PCBA,MLB,1.4GHZ,MI 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF84,DDR3:MICRON_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4J] CRITICAL EEE:DG4J
TABLE_BOMGROUP_ITEM
639-1346 PCBA,MLB,1.4GHZ,MI 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF88,DDR3:MICRON_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4K] CRITICAL EEE:DG4K
TABLE_BOMGROUP_ITEM
639-1343 PCBA,MLB,1.4GHZ,MI 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF85,DDR3:MICRON_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4M] CRITICAL EEE:DG4M
TABLE_BOMGROUP_ITEM
639-1347 PCBA,MLB,1.4GHZ,MI 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF89,DDR3:MICRON_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4N] CRITICAL EEE:DG4N
B 639-1345 PCBA,MLB,1.4GHZ,MI 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF87,DDR3:MICRON_4GB,CAPS:MU
TABLE_BOMGROUP_ITEM
825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4P] CRITICAL EEE:DG4P

B
TABLE_BOMGROUP_ITEM
639-1340 PCBA,MLB,1.4GHZ,MI 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DF82,DDR3:MICRON_4GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4Q] CRITICAL EEE:DG4Q
TABLE_BOMGROUP_ITEM
639-1442 PCBA,MLB,1.4GHZ,EL 2GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4L,DDR3:ELPIDA_2GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4R] CRITICAL EEE:DG4R
TABLE_BOMGROUP_ITEM
639-1443 PCBA,MLB,1.4GHZ,EL 2GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4M,DDR3:ELPIDA_2GB,CAPS:MU 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4L] CRITICAL EEE:DG4L
TABLE_BOMGROUP_ITEM
639-1447 PCBA,MLB,1.4GHZ,EL 2GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4R,DDR3:ELPIDA_2GB,CAPS:TY 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4T] CRITICAL EEE:DG4T
TABLE_BOMGROUP_ITEM
639-1441 PCBA,MLB,1.4GHZ,EL 4GB,SS CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4K,DDR3:ELPIDA_4GB,CAPS:SS 825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4V] CRITICAL EEE:DG4V
TABLE_BOMGROUP_ITEM
639-1439 PCBA,MLB,1.4GHZ,EL 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4H,DDR3:ELPIDA_4GB,CAPS:MU

TABLE_BOMGROUP_ITEM
639-1440 PCBA,MLB,1.4GHZ,EL 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4J,DDR3:ELPIDA_4GB,CAPS:TY
Sub-BOMs
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
A 085-1121 1 K99 MLB DEVELOPMENT BOM DEVEL CRITICAL DEVEL_BOM SYNC_MASTER=K6_MLB SYNC_DATE=12/11/2009 A
PAGE TITLE
607-6999 1 CMN PTS,PCBA,MLB,K99 CMNPTS CRITICAL K99_CMNPTS
K99 BOM Variants
DRAWING NUMBER SIZE

REVISION
R
4.4.0
4 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Module Parts
Programmable Parts
338S0563 1 IC,SMC,HS8/2117,9X9MM,TLP,HF U4900 CRITICAL SMC:BLANK
337S3792 1 CDC,QKWH,QS,1,2,10W,800,R0,1M,BGA U1000 CRITICAL CPU:1.2GHZ
341T0261 1 IC ASSY,SMC EXTERNAL,K99 U4900 CRITICAL SMC:PROG
337S3947 1 PDC,SLGFN,PRQ,1,6,10W,R0,3M,BGA U1000 CRITICAL CPU:1.6GHZ
335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM:BLANK
337S3954 1 PDC,SLGAK,PRQ,1,4,10W,R0,3M,BGA U1000 CRITICAL CPU:1.4GHZ
341T0262 1 IC ASSY,EFI UNLOCKED,K99 U6100 CRITICAL BOOTROM:UNLOCKED
337S3820 1 IC,MCP89U-A01,24.5MMX24.5MM,1244FCBGA U1400 CRITICAL MCP89U:A01
341T0263 1 IC ASSY,EFI,LOCKED,K99 U6100 CRITICAL BOOTROM:LOCKED
D Alternate Parts
TABLE_ALT_HEAD
D
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 333S0552 4 HYNIX,LVDDR3,1GBIT,7.5X11.0 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_2GB
PART NUMBER
TABLE_ALT_ITEM
138S0681 138S0638 ALL TAIYO YUDEN AS ALTERNATE

333S0552 4 HYNIX,LVDDR3,1GBIT,7.5X11.0 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_2GB
TABLE_ALT_ITEM
152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE

TABLE_ALT_ITEM

TABLE_ALT_ITEM
353S2987 353S2988 HVDDLDO:FIXED ALL TPS71725DCK AS ALTERNATE FOR U2590

333S0553 4 SAMSUNG,LVDDR3,1GBIT,7.5X11.0 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:SAMSUNG_2GB
TABLE_ALT_ITEM
104S0023 104S0018 ALL CYNTEC/DALE AS ALTERNATES

TABLE_ALT_ITEM
107S0139 107S0075 ALL CYNCTEC AS ALTERNATE

TABLE_ALT_ITEM
138S0671 138S0673 ALL TAIYO AS ALTERNATE

TABLE_ALT_ITEM
155S0578 155S0367 ALL TAIYO AS ALTERNATE

333S0554 4 MICRON,LVDDR3,1GBIT,8X11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:MICRON_2GB
TABLE_ALT_ITEM
376S0926 376S0610 ALL FAIRCHILD AS ALTERNATE

TABLE_ALT_ITEM

TABLE_ALT_ITEM
377S0107 377S0066 ALL ONSEMI AS ALTERNATE

333S0565 4 ELPIDA,LVDDR3,1GBIT,7.5X10.6 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:ELPIDA_2GB
333S0555 4 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_4GB

C 333S0555 4
HYNIX,LVDDR3,2GBIT,9X11.1
HYNIX,LVDDR3,2GBIT,9X11.1 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_4GB

C
333S0555 4 HYNIX,LVDDR3,2GBIT,9X11.1 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:HYNIX_4GB
333S0555 4 HYNIX,LVDDR3,2GBIT,9X11.1 U3400,U3410,U3420,U3430 CRITICAL DRAM_TYPE:HYNIX_4GB
BOM Groups 333S0557 4 MICRON,LVDDR3,2GBIT,9X11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:MICRON_4GB

TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS 333S0557 4 MICRON,LVDDR3,2GBIT,9X11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:MICRON_4GB

TABLE_BOMGROUP_ITEM
K99_COMMON COMMON,ALTERNATE,PROJ:K99,K99_MISC,MCP89U:A03,K99_DEBUG:ENG,K99_PROGPARTS,SPI:41MHZ,LVDDR3:YES,WLAN_PCTL:HW,IPD_5V:S5_INT,IPD_3V3:S5
TABLE_BOMGROUP_ITEM
K99_MISC DP_ESD,DP_PWR:SMC,VFRQ:SLPS3,HVDDLDO:FIXED,MCPHVDD:P2V5,MCPPLL_R:REG,S0PGOOD_BJT,ISL6259_SCREENED:YES,DPI2C:SMC
333S0566 4 ELPIDA,LVDDR3,2GBIT,9X11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:ELPIDA_4GB
TABLE_BOMGROUP_ITEM
K99_PROGPARTS BOOTROM:UNLOCKED,SMC:PROG 333S0566 4 ELPIDA,LVDDR3,2GBIT,9X11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:ELPIDA_4GB

TABLE_BOMGROUP_ITEM
K99_DEVEL:ENG BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LED 333S0566 4 ELPIDA,LVDDR3,2GBIT,9X11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:ELPIDA_4GB

TABLE_BOMGROUP_ITEM
K99_DEVEL:PVT LPCPLUS 333S0566 4 ELPIDA,LVDDR3,2GBIT,9X11.5 U3400,U3410,U3420,U3430 CRITICAL DRAM_TYPE:ELPIDA_4GB

TABLE_BOMGROUP_ITEM
K99_DEBUG:ENG DEVEL_BOM,SMC_DEBUG:YES,XDP 353S2392 1 IC,ISL6259,BATCHARGER,4X4MM,QFN28 U7000 CRITICAL ISL6259_SCREENED:NO

TABLE_BOMGROUP_ITEM
K99_DEBUG:PVT DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO 353S2929 1 IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28 U7000 CRITICAL ISL6259_SCREENED:YES

TABLE_BOMGROUP_ITEM
B K99_DEBUG:PROD BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
TABLE_BOMGROUP_ITEM
607-6811 1 ASSEMBLY,SUBASSY,PCBA HALL EFFECT, K99 J6955 CRITICAL B
DDR3:HYNIX_2GB DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB
TABLE_BOMGROUP_ITEM
DDR3:SAMSUNG_2GB DRAM_CFG0:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB
TABLE_BOMGROUP_ITEM
DDR3:MICRON_2GB DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB
TABLE_BOMGROUP_ITEM
DDR3:ELPIDA_2GB DRAM_CFG0:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_2GB
TABLE_BOMGROUP_ITEM
DDR3:HYNIX_4GB DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB
TABLE_BOMGROUP_ITEM
DDR3:SAMSUNG_4GB DRAM_CFG0:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB
TABLE_BOMGROUP_ITEM
DDR3:MICRON_4GB DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:MICRON_4GB
TABLE_BOMGROUP_ITEM
DDR3:ELPIDA_4GB DRAM_CFG0:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB
TABLE_BOMGROUP_ITEM
CAPS:SS SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF,SS_CAP_22UF
TABLE_BOMGROUP_ITEM
CAPS:MU MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF,MU_CAP_22UF
TABLE_BOMGROUP_ITEM
CAPS:TY TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF,TY_CAP_22UF
PAGE TITLE
BOM Configuration
DRAWING NUMBER SIZE

REVISION
R
4.4.0
5 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Revision History NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping. 07/07/2010: Release 4.2.0 (MAJOR)-
<rdar://problem/7993210> K99 MLB: Cosmetic updates
- Moved BOM group table on page 4 to page 5 for space limitations
03/05/2010: RELEASE 0.41.0 (MAJOR)- 03/30/2010: Release 1.5.0 (MAJOR)- <rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout <rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400
- PAGE 9: ADDED Z0920 (OMIT) APN 998-3068 METAL TAB SYMBOL FOR MDP - Page 4: Deleted SMS:NO BOM option as SMS has been removed - Page 4: Updated SU9400 BOMs with correct EEEEs (Elpidas still pending)
CONNECTOR - Page 4: Deleted 376S0895 alternate part entry to avoid mixing of vendors - Page 50: Deleted BOM option SMS:NO from R5093 - Page 4: Updated Label table with correct EEEEs for SU9400 configs
- PAGE 19: ADDED 10K R1954 APN 117S0007 PD ON MLB_RAM_CFG0 AS THERE IS NO between high & low side FETs, per Dayu - Page 52: Deleted Accelerometer block from the SMBUS page
INTERNAL PD ON GPIO 48 - Page 4: Deleted DPI2C:SMC BOM OPTION as eDP I2C Bus wont be routed on <rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory
- PAGE 72: RENAMED =P5VS3_EN_L TO =P5VS3_EN AND =P3V3S5_EN_L TO =P3V3S5_EN Proto 1 <rdar://problem/8007333> K99 MLB: Stuff R7872 to enable output connection of ISL power - Page 4: Added 12 new BOMs corresponding to Elpida 2GB and 4GB configs
- PAGE 78: MOVED P3V3S5_EN_L NET FROM PIN 4 TO PIN 3 (NON-INVERTING) AND - Page 4: Changed BOM OPTION SPI:25MHz to 62MHz monitor to ALL_SYS_PWRGD - Page 5: Added DDR3:ELPIDA_4GB BOM group
RENAMED IT TO P3V3S5_EN AS IT IS ACTIVE HIGH SIGNAL. LEFT PIN 4 - Page 9: Changed BOM OPTION attribute of ZS0904 to OMIT_TABLE - Page 78: Added BOM option S0PGOOD_ISL to R7872 - Page 5: Added DRAM_TYPE:ELPIDA_4GB BOM option to the Module Parts table
NC - Page 10-11: Changed BOM OPTION attribute of U1000 to OMIT_TABLE (2Gb APN is not ready yet- using 2Gb Micron APN as a placeholder)
- PAGE 78: NO STUFF C7801 - Page 14-20: Changed BOM OPTION attribute of U1400 to OMIT_TABLE <rdar://problem/7993210> K99 MLB: Cosmetic updates
- PAGE 78: ALIASED =P0V9S5_EN TO CONNECT TO =PP3V3_S5_P0V0S5 - Page 25: Changed BOM OPTION attribute of C2600 to OMIT_TABLE - Page 8: Added =PP3V3_S3_DBGLEDS alias to =PP3V3_S3_FET for debug LEDS (like K16) <rdar://problem/8168390> K99 MLB BOM: Swap 155S0556-> 155S0578, fix 0402
- PAGE 78: DELETED Q7891 (PINS 3,4,5) SYMBOL AS P5VS3_EN_L IS ACTIVE HIGH - Page 31-34: Changed BOM OPTION attribute of U3100-U3430 to OMIT_TABLE - Page 57: Changed PP3V3_S5_TPAD_CONN to PP3V3_TPAD_CONN pad with 0603
SIGNAL (SO NO NEED TO INVERT) AND RENAMED IT TO P5VS3_EN. ALSO, - Page 35-36: Changed BOM OPTION attribute of all caps to OMIT_TABLE - Page 69: Renamed PP3V3_S3 going to debug LEDs to =PP3V3_S3_DBGLEDS - Page 5: Changed 155S0556 to 155S0578 to address the 0603 0402 mismatch
CONNECTED IT TO PM_SLP_S4_L VIA RC NETWORK - R7813 & C7813 - Page 49: Changed BOM OPTION attribute of U4900 to OMIT_TABLE alternate parts
- PAGE 78: REPLACED R7813 WITH 0 OHMS APN 117S0002 FOR NOW - Page 52: Changed R5290 & R5291 to 2K APN 118S0174 per RADAR# 7810865 <rdar://problem/8007524> K99 MLB: Stuff C9799 to provide better phase margin
- Page 61: Changed BOM OPTION attribute of U6100 to OMIT_TABLE - Page 97: Stuff C9799 <rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps
- Page 69: Changed R6905 to 10 Ohms APN 101S0089 & C6990 to 2.2uF APN - Page 12: Changed BOM option attribute of C1200,C1201,C1202,C1203,C1204,
03/05/2010: RELEASE 0.42.0 (MAJOR)- 138S0672 to improve noise immunity & reduce inrush stress, per <rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements C1205,C1206,C1207,C1208,C1209,C1211,C1212,C1213,C1215,C1216,
- PAGE 4: ADDED DRAM_CFG0:L TO RAM TABLES NOT CALLING OUT DRAM_CFG0:H, AND Dayu - Page 8: Changed min neck width of PP3V3_S3 to 0.1mm C1219, C1220,C1221,C1222,C1224,C1225,C1228,C1229,C1231 from
D REMOVED DRAM_CFG1:H AS IT IS NO LONGER NEEDED
- PAGE 4: DELETED MODULE TABLE ENTRY FOR ZS0907 AS POR SYMBOL IS READY
- PAGE 4: ADDED MODULE TABLE ENTRY FOR Z0920 MLB STIFFENER: 806-1176
- Page 69: Changed BOM OPTION attribute of U6955 to OMIT_TABLE
- Page 69: Changed BOM OPTION attribute of C6999 to OMIT_TABLE
- Page 70: Changed BOM OPTION attribute of U7000 to OMIT_TABLE
- Page 8: Changed min neck width of PP5V3_S3 to 0.2mm
- Page 74: Deleted IMVP6_CS_P/N & IMVP6_CS_R_P/N nets from the constraints set as the
bottom of the page
OMIT_TABLE to NOSTUFF
***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16***
D
- PAGE 9: REPLACED ZS0907 WITH POR APN 870-1938 AND DELETED OMIT ATTRIBUTE - Page 72: Replaced Q7220 & Q7225 with APN 376S0895 (RJK03E0) per Dayu - Page 97: Changed min neck width of PPBUS_SW_BKL to 0.25mm
- PAGE 9: REPLACED POGO PIN ZS0906 WITH APN 870-1938 PER PD - Page 72: Changed R7220 to 41.2K APN 118S0360 to boost 5V, per Dayu <rdar://problem/8118512> K99 MLB BOM: Swap 155S0423 -> 155S0559, Supply
- PAGE 19: REMOVED R1955 PULL-UP ON MLB_RAM_CFG1 (INTERNAL PULL-UP) - Page 73: Replaced Q7330 with APN 376S0749 (SIS426) per Dayu 05/19/2010: Release 3.3.0 (Major)- Constraint (TDK)
- PAGE 19: CHANGED R1956 PULL-DOWN TO 470 OHMS (STRONGER PD VS 8.5K PU) - Page 76: Replaced Q7630 & Q7635 with APN 376S0895 (RJK03E0) per Dayu <rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 90: Changed FL9000, FL9001 from 155S0423 to 155S0559
APN 117S0103 - Page 77: Changed R7751 to 2.55K APN 118S0234 & R7752 to 20K APN - Page 69: Fixed netname =PP3V3_S3_DBGLEDs (= sign was missing) - Page 94: Changed FL9400-FL9403 from 155S0423 to 155S0559
- PAGE 19: REPLACED R1957 WITH 10K APN 117S0007 TO BE CONSISTENT 118S0175 to improve noise immunity & reduce inrush stress, per
- PAGE 78: ADDED BYPASS PROPERTIES TO C7895 AND C7896 Dayu <rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps
- PAGE 78: CHANGED BASE NET FOR PM_SLP_S4_DLY_L PER WILL 05/21/2010: Release 3.4.0 (Major)- - Page 110: Removed caps listed above on page 12 from the BOM table as
03/31/2010 - Proto 1 Agile Release 2.0.0 (FAB) <rdar://problem/7993210> K99 MLB: Cosmetic updates these would get NOSTUFFed
- Proto 1 Ok2FAB Agile Release!!! - Page 2: Updated CPU block to reflect 1.6GHz
03/05/2010: RELEASE 0.43.0 (MAJOR)-
- PAGE 2: REPLACED THIS PAGE WITH QUANTAS UPDATED ONE <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD 7/12/2010: Release 4.3.0 (MAJOR)-
- PAGE 4: SWITCHED BOM TABLE TO USE SCREENED ISL6259 PART 3/31/2010: Proto 1+ Release 2.1.0 (MAJOR) - Page 4: Changed IPD_PWR:S5 to IPD_5V:S5_INT BOM option to use internal LDO of 5V/3.3V
- PAGE 4: ADDED APN 376S0895 UNDER MODULE PART TABLE FOR Q7220 & Q7225 PER switcher for IPD 5V supply <rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory
DAYU FOR PART SUPPLY ISSUE - Page 4: Activated PROJ:K99 BOMOPTION to select proper APN for U9701 - Page 4: Updated BOM options table with correct EEEEs for Elpida configs
- PAGE 4: MOVED SMS_YES BOM OPTION FROM K99_MISC TO DEVEL_BOM - Page 97: Changed BOM OPTION attribute of C9797 to OMIT_TABLE after <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 4: Added label table with correct EEEEs for Elpida configs
- PAGE 4: UPDATED MICRON 2GB APN 333S0557 IN THE BOM TABLE syncing from K16 - Page 4: Added IPD_3V3:S5 BOM option under K99_COMMON to select 3.3V S5 power supply - Page 5: Updated Elpida 2Gb configs with correct APN 333S0566
- PAGE 9: FIXED MCPCOREISNS SIGNALS ALIASES PER WILLS CHANGES ON K16 - Page 7: Renamed =PP3V3_S3_TPAD to PP3V3_TPAD_CONN and =PP5V_S3_TPAD TO PP5V_TPAD_FILT
- PAGE 39: REMOVED CRITICAL ATTRIBUTE FROM THE BOM TABLE AS IT IS NOT ***Synced from K16*** - Page 8: Added =PP3V3_SMC_PME alias to PP3V3_S5 <rdar://problem/8180364> K99 MLB BOM: Remove 806-1176 stiffener
NEEDED - Page 9: Deleted CRITICAL attribute from MT0900 and NOSTUFFed it
- PAGE 70: NO STUFF Q7080, D7005,Q7055 AND F7040 FOR NON-FUNCTIONAL BOARD -Page 90: Added Q9090 isolation FET to support LCD panel power-down per <rdar://problem/8009884> K99 MLB: Add new CPU APN for U1000
- PAGE 72: ADDED OMIT BOM OPTION TO Q7220 & Q7225 AS SYMBOL IS NOT READY radar 7761747 - Page 4: Added SU9600 CPU APN 337S3947 1.6GHz to the module part table. And, updated
- PAGE 72: CHANGED R7246 AND R7247 TO 1.69K, 1% APN 118S0134 PER VENDOR -Page 97: Reversed previous change, U9701 back to 353S2896, handled via a BOM variant table to call out this new APN 7/22/2010: Release 4.4.0 (MAJOR)-
- PAGE 72: CHANGED R7216 AND R7256 TO 4.02K, 1% APN 118S0354 PER VENDOR table now to support/clarify different values for K16/K99
- PAGE 72: CHANGED C7237 AND C7239 TO 1000PF, 10% APN 132S0122 PER VENDOR -Page 108: Added constraints for new nets on page90, I2C_TCON_SCL/SDA_CONN <rdar://problem/8011930> K99 MLB: Remove SIL BOM option as SIL is not POR <rdar://problem/8175202> K99 MLB: Move MCP Temp Sensor to SMC B SMBUS
- PAGE 76: CHANGED OCP TEXT NOTE PAR VENDOR per radar 7761747 - Page 4: Removed SIL BOM option from the development BOM - Page 52: Move MCP TEMP I2C connections to SMC B Bus
- PAGE 76: CHANGED R7641 AND R7642 TO 1.78K, 1% APN 118S0144 PER VENDOR - Page 52: NOSTUFFed R5250 & R5251
- PAGE 78: ADDED NC SYMBOL TO PIN 5 OF U7896 3/31/2010: Proto 1+ Release 2.2.0 (MAJOR) <rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements - Page 52: Changed MCP TEMP I2C address note to reflect 0XD8/0XD9
- Page 97: Swapped pins of R9700 to match original orientation before - Page 8: Changed min neck width of PP3V3_S3 to 0.1mm - Page 55: Changed R5536 to 15K APN 118S0105 to set ADDR = 0XD8/0XD9.
syncing with K16 - Page 40: Deleted line/neck width attributes from =PP3V3_S3_WLAN as duplicates Updated schematic note too for address
03/07/2010: PROTO1 NON-FUNCTIONAL AGILE RELEASE 1.0.0 (FAB)- - Page 97: Deleted OMIT_TABLE BOM option attribute from C9797 and replaced
- NON-FUNCTIONAL PROTO 1 OK2FAB RELEASE!!! it with actual POR APN 138S0673 symbol. Also, deleted it from <rdar://problem/7825507> K99 MLB BOM: Change label P/N <rdar://problem/8141673> K99 MLB: Change eDP connector J9000 pinout
BOM table as it is no longer required - Fixed typo in APN (first column) - Page 90: Changed pine 2 to NC and connected pin 4 to PPVOUT_SW_LCDBKLT
<rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO Flex
3/19/2010: RELEASE 1.1.0 (MAJOR)- 5/12/2010: Proto 1+ Agile Release 3.0.0 (FAB) - Page 47: Connected pin 38 to GND
- Proto 1+ OK2FAB Agile Release!!! <rdar://problem/8224515> K99 MLB: Remove Q9090 isolation FET
- PAGE 4: REMOVED SMS_YES BOM OPTION FROM K99_DEVEL:ENG BOM GROUP. INSTEAD, <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V - Page 90: Removed Q9090 FET and directly connected TCON I2C bus J9000
ADDED SMS:NO TO K99_MISC [ALSO SEE BELOW CHANGES FOR PAGES 50,59] - Page 4: Added APN 353S2988 (MICREL) as an alternate for 353S2986 - Page 90: Deleted =I2C_TCON_SCL/SDA_CONN net names and kept
- PAGE 50: ADDED BOM OPTION ATTRIBUTE SMS:NO TO R5093 PU ON SMS_INT_L. 5/17/2010: Release 3.1.0 (Major)- - Page 4: Added APN 353S2987 (TI) as an alternate for 353S2986 =I2C_TCON_SCL/SDA
IDEA IS TO PULL THIS NET TO S5 RAIL WHEN SMS IN NOT STUFFED, - Page 4: Deleted APN 353S3047 entry from the alternate table
ELSE PU TO S3 RAIL (PAGE 59) PER RADAR 7765442 <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V - Page 25: Reverted U2590 back to the 2.5 LDO APN 353S2988 <rdar://problem/8224857> K99 MLB: Replace APN 155S0559 with 155S0423
- PAGE 52: CONNECTED SMC 0 SMBUS INTERFACE TO THE TCON-A CHIP IN THE - Page 4: Added APNs 353S2987 & 353S2988 as alternates for 353S2986 - Page 25: Replaced APN 353S3048 with 353S2986 in the BOM table for U2590 as primary (incompatible pad sizes)
INTERNAL DISPLAY. ALSO, PROVIDED 0 OHMS STUFFING OPTIONS TO BE for HVDDLDO:FIXED - Page 90: Changed FL9000 and FL9001 back to the original APN 155S0423
DRIVEN FROM MCP89 0 SMBUS [R5240-R5243 APN 117S0002] PER <rdar://problem/7964678> K99 MLB BOM: Change MCP APN to A03 version - Page 94: Changed FL9400-FL9403back to the original APN 155S0423
RADAR 7749046 - Page 4: Added MCP89U:A03 BOM table. Changed K99_Common to call out A03 ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***
- PAGE 59: REPLACED BOM OPTION SMS_YES WITH SMS:YES ** Didnt sync page 52 as K16 need to sync it first from K99 to remove accelerometer** <rdar://problem/8224921> K99 MLB: Change R9714 (BKLT_ISET) resistor to
- PAGE 59: ADDED 10K R5924 PU ON SMS_INT_L TO =PP3V3_S3_SMS WITH BOM <rdar://problem/7861271> K99 MLB: Set SPI operating frequency to 42MHz ** Didnt sync page 25 as K16 need to sync it first from K99 to revert to 2.5 LDO** 18.2K 1% APN 118S0155
OPTION ATTRIBUTE SMS:YES PER RADAR 7765442 <rdar://problem/7851979> K16/K99: Set SPI operating frequency to 42Mhz ** Didnt sync page 40 as K16 needs to sync it first from K99 for above change** - Page 97: Change R9714 to 18.2K 1% APN 118S0155
- PAGE 70: STUFF BACK Q7080, D7005,Q7055 AND F7040 - Page 4: Changed SPI:62Mhz to SPI:41MHZ BOM option
C - PAGE 75: REPLACED L7560 WITH 10X10X3MM APN 152S1236 PER RADAR 7769386
- PAGE 90: ROUTED NEWLY ADDED =I2C_TCON_SDA/SCL TO PINS 1 & 30 OF J9000
RESPECTIVELY PER RADAR 7749046
- PAGE 93: ADDED 3300PF APN 132S0241 C9302 CAP ON DP_CA_DET TO GND PER
<rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change
- Page 4: Added WLAN_PCTL:HW to K99_Common
<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements
- Page 24: Changed PPVCORE_SW_MCP_GFX min neck width to 0.12mm for routing
<rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- Page 97: Fixed schematic note - I_LED=369/Riset C
RADAR 7742010 <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD - Page 77: Changed IPD_PWR:S5 to IPD_5V:S5_EXT BOM option
- PAGE 108: ADDED SMBUS_SMC_0_S0_SCL/SDA_R CONSTRAINTS SET <rdar://problem/7953783> K99 IPD power regulator new design - Page 77: Changed IPD_PWR:S3 to IPD_5V:S3 BOM option
- Page 4: Added IPD_PWR:S5 to K99_Common - Page 77: Added R7761 0 ohm bypass option to use internal LDO of 5V/3.3V switcher for
- Page 8: Aliased =PPBUS_5V_S5 to PPBUS_G3H signal IPD 5V supply. Added BOM option IPD_5V:S5_INT to R7761
03/24/2010: Release 1.2.0 (MAJOR)- - Page 77: Added place near J5700.10:1.5mm to R7761 to avoid long stub
- Text sizes have been fixed - safe to sync <rdar://problem/7825507> K99 MLB BOM: Change label P/N
- Page 8: Renamed PP3V3_S5_LCD to PP3V3_S0_LCD - Page 4: Replaced label APN 826-4393 with 825-7557 <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
- Page 8: Moved PP3V3_S0_LCD & PP3V3_S5_DP_PORT_PWR to S5 rail - Page 49: Changed port P92 from SMC_BS_ALRT_L to SMC_PME_S4_L
- Page 7: Added =I2_TCON_SCL/SDA FCTs under INT DP FUNC_TEST group <rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector - Page 50: Changed R5076 to a PU to =PP3V3_SMC_PME. And, renamed SMC_BS_ALERT_L to
- Page 12: After syncing from K16, deleted C1273 as it NA to K99 - Page 7: Renamed PP3V3_LCDVDD_SW_F to PP3V3_SW_LCD to match page 90, making it SMC_PME_S4_L
- Page 90: After syncing, renamed PP3V3_S5_LCD to PP3V3_S0_LCD convention compliant power net - Page 57: Changed IPD_PWR:S5 to IPD_3V3:S5 BOM option
- Page 57: Changed IPD_PWR:S3 to IPD_3V3:S3 BOM option
***Synced ALL but pages 1-9,28,47,69,70,74,75 and 97 from K16*** <rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state - Page 57: Removed U5750, R5751,R5750 and C5750 USB_IPD Debug Mux as it is not needed
*Please NOTE that some of the below changes were already part of 1.1 - Page 7: Renamed PP3V3_S0_DPPWR to PP3V3_SW_DPPWR to match page 94 changes, making it - Page 57: Renamed pins 5 & 6 to USB_TPAD_CONN_P/N as before
release. Below list depicts all the changes since 3/1 K16 release * convention compliant power net - Page 57: Renamed pin 10 to PP5V_TPAD_FILT
- Page 78: Removed =USB_TPAD_MUX_EN alias to DDREG_EN as MUX has been removed
- Page 12: Fixed invisible pins on CPU bypass caps. Also changed all OMITs <rdar://problem/7993210> K99 MLB: Cosmetic updates
to OMIT_TABLEs and performed other cleanup - Page 7: Removed SYS_LED_ANODE_R <rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state
- Page 14: Swapped BCLK_IN_N/P after library symbol refresh - Page 8: Removed =PP3V3_S5_PWRCTL alias - Page 19: Added alias for PM_SLP_S4_L to PM_SLP_S5_L
- Page 17: Added CKPLUS_WAIVE properties to VDD_IFPx pins that are legally - Page 49: Changed port P94 from SMC_DP_HPD_L to PM_SLP_S4_L
grounded on K16 <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 49: Changed port P95 from PM_SLP_S4_L to PM_SLP_S5_L
- Page 19: Removed PM_SLP_S5_L alias. Other cleanup to make all CRefs - Page 8: Added =PP3V3_S5_TPAD to PP3V3_S5 net - Page 49: Changed port PB6 from SMC_PB6 to SMC_DP_HPD_L
visible - Page 50: Removed R5095 PU resistor on SMC_PB6
- Page 19: Removed pull-up on MLB_RAM_CFG1 (internal pull-up), changed <rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout
pull-down to 470 ohms. Added pull-down on MLB_RAM_CFG0, made - Page 59: Deleted csa page as SMS is no longer POR
both pull-up and pull-down 10K
- Page 25: Added MCPHVDD LDO, SC-70 version. Added 1uF 0201 input cap and <rdar://problem/7795028> K99 MLB: 5V/3V3 power supply BOM changes per characterization
10K pull-up resistor, BOMOPTIONed same as LDO. L2590 retained - Page 74: Changed C7451/C7452 to same APN 131S0287 as C7237/C7239 for BOM consolidation
with MCPHVDD:P3V3 BOMOPTION
- Page 25: Added voltage divider for HVDD LDO. OMIT_TABLEd U2590, added <rdar://problem/7993241> K99 MLB: Cleanup of CheckPlus warnings/errors 05/26/2010: Release 3.5.0 (Major)-
tables for fixed (2.5V Intersil) and adjustable (TI) regulators - Page 4: Deleted ZS0904 entry from the module parts table as symbol is ready
- Page 39: Removed CRITICAL flag from 0-ohm resistor table - Page 9: Renamed stiffener Z0920 to MT0900, similar to K16 ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***
- Page 49: PB3 changed from SMC_DRAM_S3_PWRDN to SMC_SLPS5_L. P74 changed - Page 9: Tagged POGOS and MT0900 as CRITICAL ** Didnt sync page 52 as K16 need to sync it first from K99 to remove accelerometer**
from PM_SLP_S4_L to SMC_DP_HPD_L. P75 changed from PM_SLP_S5_L - Page 9: Replaced ZS0904 with actual symbol for APN 870-1940 and deleted OMIT_TABLE ** Didnt sync page 40 as K16 needs to sync it first from K99 to remove neck width
to PM_SLP_S4_L - Page 9: Cleaned-up TP/NC _P/_N errors from PP3V3_S3_WLAN**
- Page 49: C4902 changed from 0805 to 0603 to free up some layout space for - Page 74: Renamed VSNS nets to VSEN to match page 100 constraints and deleted these
MCP VCore regulator nets from constraints table on the same page <rdar://problem/8033353> K99 MLB: Change to dual USB port power switch
- Page 50: Added SMS:NO BOMOPTION to SMS_INT_L pull-up. Other cleanup - Page 79: Changed OMIT associated with C7980 to OMIT_TABLE - Page 46: Changed USB port power switch U4690 back to dual port TPS2052B APN 353S2298
including deleting unused alias for SMC_PB3 - Page 99: Changed OMIT associated with all caps to OMIT_TABLE
- Page 50: Added 2 resistors to control DP_PWR and one to connect <rdar://problem/7744955> K99 Proto0 Task: Characterize Voltage/Current/Temperature
DP_EXT_HPD_L to SMC. Updated netname on R5090 and added <rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request Sensors
BOMOPTION of DP_PWR:S0 - Page 75: Added Critical attribute to R7560 _ Page 53: For IZDM, change U5360 to INA210 (APN : 353S2073)
- Page 52: Added TCON I2C block and Rs to connect to SMC 0 and MCP 0 - Page 97: Added Critical attribute to R9700 - Page 54: For IN1C, change R5412 to 118 Ohms, APN : 114S0127
- Page 53: Removed PP prefix from non-power nets. Added OMIT_TABLE to
buses. Other cosmetic cleanup including grid compliance ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16*** <rdar://problem/8033256> K99 MLB: Implement 3V3 S5 bleed resistor to satisfy IPD Cumulus
C5310 for vendor control ** Didnt sync pages 79 & 99 as K16 need to sync it first from K99 to fix OMIT_TABLE power sequencing on shutdown
- Page 59: Synced with K99 (adds R5924, S3 pull-up on SMS_INT_L), plus attribute as mentioned above** - Page 78: Added R7899 0ohm 0603 (will change later) pull-up to =PP3V3_S5_REG and
lots of cleanup including removing PP prefix from signal net, connected R7899 to pin 3 of Q7890; Q7890.5 gate tied to P3V3S5_EN_L; Q7890.4
correcting BYPASS & PLACE_NEAR properties, correcting offpages, etc <rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector to GND and, U7840.4 output to P3V3S5_EN_L
B - Page 72: Changed Q7220 & Q7225 to 376S0895 per Dayus request. Fixed
netnames on switcher enables, removing _L suffixes since they
are active-high
- Page 52: Added notes about I2C addresses on panel, may not be 100% accurate yet
<rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements
- Page 108: Changed Therm, Sense, Audio line-to-line spacing to 1:1 instead of 2:1
B
- Page 72: Value changes to C7237/C7239/R7216/R7246/R7247/R7256 per Dayu. - Page 13: Changed XDP SMBus nets to =I2C_XDP_* for new aliases on page52
Changed C7288 to match C7218. Removed alias that was serving no - Page 52: Added XDP to MCP_0 SMBus diagram
purpose and was incorrect since it lacked a MAKE_BASE anyhow - Page 76: Cleaned-up page, including correcting application of two PLACE_NEAR 05/28/2010: Release 3.6.0 (Major)-
- Page 76: Value changes to R7641/R7642 and OCP note correction per Dayu properties and changing an OMIT to OMIT_TABLE
- Page 78: Removed RAM power-down circuit, reconnecting =DDRREG_EN to <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR)
original net <rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state -Page 4: Removed MIC5366 from alternate BOM table as it is primary now and replaced
- Page 78: Disconnected half of Q7891 from 5V S3 power sequencing, gate - Page 50: Added PLACE_NEAR property on R5022 to ensure no stub in fallback case. 353S2986 with 353S2988, making TI its alternate
left indicated as unused. Removed inverter from P5VS3_EN and - Page 4: Deleted 138S0635 from alternate table as its been replaced per GSM(see below)
reconnected P3V3S5_EN to be non-inverted. R7813 changed from <rdar://problem/7794868> K99 MLB: Change to single USB port power switch <rdar://problem/8036605> K99 MLB BOM: Implement MCP VCORE characterization changes
pull-up to series R (0-ohms). P0V9S5_EN changed to alias to - Page 46: Corrected Refdes from Q4690 to U4690 - Page 75: Changed C7580 to 560pF APN 132S4001 per Intersil FAE
3.3V S5 rail. Cleaned up page including fixing grid issues.
Added BYPASS properties to C7895 and C7896. Changed base net <rdar://problem/7993278> K99 MLB: Schematic sync with K16 MLB ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below***
for PM_SLP_S4_DLY_L - Page 26: Synced with K16, OMIT changed to OMIT_TABLE
- Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up - Page 73: Synced with K16, OMITs changed to OMIT_TABLE and cosmetic clean-up <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR)
page, adding offpages, fixed grid issues, made power nets - Page 25: Changed BOM table from ISL 353S2986 to MIC5366 353S2988, as Intersil is NOT
convention-compliant and added note about DP_CA_DET pull-up / <rdar://problem/7994057> K99 MLB: Need to add Need_TP=True property to CPU POR
FET Vgs reqirements - Page 10: Added Need_TP=True attribute to pin E37 & D40
- Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up <rdar://problem/8027047> K99 MLB BOM: Swap 132s0247 w/132s0257, 138s0621 w/138s0653, 138s0635 w/138s0654
page, adding offpages, fixed grid issues, made power nets <rdar://problem/7871167> K99 MLB: Change RC on CPUVCORE PMON output - Page 25,26: Swapped 138s0621 w/138s0653 as per GSM
convention-compliant and added note about DP_CA_DET pull-up / - Page 54: Changed R5471 from 4.53K to 15k for higher PMON pin sink capability - Page 31-34,37,49: Swapped 132s0247 w/132s0257 as per GSM
FET Vgs reqirements - Page 54: Changed C5470 from 0.22UF to 68nF 10%. Only one in the library - Page 49,73: Swapped 138s0635 w/138s0654 as per GSM
- Page 93: Added CKPLUS_WAIVE properties to _P nets connecting to FET DRAIN
pins <rdar://problem/7934374> K99 MLB BOM: Replace 376S0868 with 376S0912 <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- Page 94: Renamed DP_PWR nets to indicate SW state instead of S0. - Page 23: Changed Q2300 from 376S0868 to 376S0912 - Page 77: Fixed BOM table attribute to attach BOM option value to TBL_BOMOPTION
Switch input changed from PM_SLP_S3_L to =DP_PWR_EN. HPD_L
netname changed, offpage added and pull-up changed to DP_PWR. <rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change
Other cleanup including removing PLACE_NEARs that should be - Page 78: Swapped unused gate to Q7890 and SMC_Adapter_En fet to Q7891. 6/4/2010: EVT Agile Release 4.0.0 (FAB)-
handled via constraints, OMIT_TABLEs for caps, CRITICAL flags on - Page 78: Added BOM Options WLAN_PCTL:HW to Q7891 both halves
common-mode chokes and cosmetic changes - Page 78: Added R7891 0 ohm 5% *** EVT OK2FAB Agile Release ***
- Page 108: Added net constraints for diffpairs reported by diffpNoPhysNet - Page 78: Added Bom option WLAN_PCTL:SW to R7891 - No changes since last release 3.6.0
report (except for 4 false errors). Other cleanup including - This release matches Quantas official BOM for EVT build
removing some unnecessary net properties <rdar://problem/7871918> K99 MLB: Investigate larger replacement for LCD backlight fuse
- Page 98: Changed F9800 to 0603 package APN 740S0115 - Upcoming changes (Acoustic, Alternates) will be reflected in 4.1 major release, which
will match Quantas deviations for EVT
03/25/2010: Release 1.3.0 (MAJOR)- <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD
- Page 4: Fixed DRAM CFG table - swapped CFG 1 and 0 columns <rdar://problem/7953783> K99 IPD power regulator new design 06/06/2010: Release 4.1.0 (MAJOR)-
- Page 4: Updated EEE numbers - Page 57: L5720.2 now connects to PP5V_S5_LDO
- Page 4: Pulled new 607-XXXX APN and added K99_CMNPTS BOM option - Page 77: Added U7760 and surrounding circuits. BOM table need to replace later <rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400
corresponding to this new sub-BOM consisting of common parts - Page 77: Added R7760 for switching capability - Page 4: Added 18 new 639-XXXX BOMS corresponding to 1.4GHz SU9400 CPU
between 18 BOMs - Page 77: Added min line and neck width properties to PP5V_S5_LDO - Page 4: Added 18 new EEEs corresponding to new BOMs
- Page 4: Replaced K99_COMMON with K99_CMNPTS in the BOM variant table - Page 78: Aliased =P5V_S5_EN to =P5V3V3_REG_EN - Page 5: Added SU9400 1.4GHz APN 337S33954 to the BOM module parts table
- Page 4: Replaced K99_SS/MU/TY_CAP BOM option with better nomenclature - - Page 78: Added R7846 and C7846 0ohm 0.47F (NO STUFF) stuffing options
CAPS:SS/MU/TY <rdar://problem/8065431> K99 MLB: Add new Elpida 1Gb memory APN - 333S0565
- Page 4: Removed K99_ prefix from K99_DDR3_ BOM Group <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 4: Added DDR3:ELPIDA_2GB BOM group and set appropriate CFG bits
- Page 4: Deleted 376S0895 APN module parts table entry as it is already - Page 57: Added R5730 & R5731 for power switch on PP3V3_TPAD - Page 4: Added Elpida DRAM to the CFG table
duplicated on page 72 - Page 57: Added U5750 USB Mux - Page 5: Added Elpida 1Gb APN 333S0565 to the BOM module parts table with DRAM_TYPE:
- Page 4: Deleted module table entry for 806-1176 as actual symbol has been - Page 57: Added R5751 (NO STUFF) to bypass U5750 MUX ELPIDA_2GB BOM option
added - Page 78: Added =USB_TPAD_MUX_EN to DDRREG_EN
A - Page 9: Replaced Z0920 with POR stiffener symbol for APN 806-1176 and
deleted OMIT
- Page 46: Replaced Q4690 with single port switch APN 353S1930 (Higher DCR)
to fix USB short issue
<rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request
- Page 39: Added Critical attribute to U3920, U3940
- Page 54: Added Critical attribute to Q5401,U5413
<rdar://problem/8066033> K99 MLB BOM: Change CPU VCORE 0603 bypass caps for acoustics
- Page 4: Added SS_CAP_22uF, MU_CAP_22uF and TY_CAP_22uF BOM options for corresponding
vendor BOM group
- Page 49: Added OMIT_TABLE BOM option to C4902
SYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009 A
- Page 46: Changed BOM attribute OMIT to OMIT_TABLE for C4690 & C4695 - Page 77: Removed Critical from C7710, C7715 - Page 73: Added OMIT_TABLE BOM option to C7360 & C7361 PAGE TITLE
- Page 54: Changed R5418 to 4.53K 0201 APN 118S0384
- Page 54: Changed R5471 to 4.53K 0402 APN 114S0281
- Page 72: Changed R7246, R7247 to 1.87K, 1% APN 118S0159 per Dayu
- Page 98: Added Critical attribute toF9800
5/19/2010: Release 3.2.0 (Major)-
- Page 94: Added OMIT_TABLE BOM option to C9480
- page 110: Added BOM config table for 22uF caps for three vendors - Samsung (138S0635),
Murata (138S0676) and Taiyo (138S0688). Also assigned C1200-C1231, C4902,
Revision History
- Page 72: Changed R7216, R7256 to 3.16K, 1% APN 118S0289 per Dayu C7360, C7361 and C9480 to these groups DRAWING NUMBER SIZE
- Page 72: Changed C7236, C7238 to 0.01uF, 10% APN 132S0097 per Dayu <rdar://problem/8006037> K99 MLB: Change RC Filter Values on AMON, and BMON - Page 110: Removed C1200-C1231 from 10uF caps BOM config table
- Page 72: Changed C7237, C7239 to 100pF, 10% APN 131S0287 per Dayu
- Page 97: Replaced U9701 with new improved E00 version APN 353S2967
- Page 54: Changed R5481 to 150K APN 118S0106 and C5487 to 0.0068uF APN 132S0009
- Page 54: Changed R5401 to 300K APN 118S0276 and C5490 to 0.0033uF APN 132S0049 <rdar://problem/7993210> K99 MLB: Cosmetic updates Apple Inc. 051-8379 D
- Page 97: Changed R9704 to 33 ohms APN 117S0080 per Kiran - Page 5: Deleted revision history and replaced it with BOM module parts, Programmable REVISION
- Page 97: Stuffed C9704 per Kiran <rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO parts and Alternate parts tables as space was limited R
3/26/2010: Release 1.4.0 (MAJOR)-

Flex
- Page 47: Replaced J4700 with new POR connector APN 516S0862 <rdar://problem/8065428> K99 MLB: Add alternates per GSM
4.4.0
- Page 4: Added 376S0895 as an alternate for 376S0749 per Dayu - Page 5: Added APN 104S0023 as an alternate for APN 104S0018 per GSM/CE NOTICE OF PROPRIETARY PROPERTY: BRANCH
- Page 4: Added 138S0681 as an alternate for 138S0638 per GSM <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V - Page 5: Added APN 107S0139 as an alternate for APN 104S0075 per GSM/CE
- Page 4: Added 138S0676 as an alternate for 138S0635 per GSM - Page 4: Deleted APN 353S2988 entry from the alternate table - Page 5: Added APN 138S0671 as an alternate for APN 138S0673 per GSM/CE THE INFORMATION CONTAINED HEREIN IS THE
- Page 4: Removed alternates that were NA to K99 - Page 4: Replaced APN 353S2987 entry with APN 353S3047 (TI) as an alternate - Page 5: Added APN 155S0556 as an alternate for APN 155S0367 per GSM/CE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
- Page 72: Deleted OMIT_TABLE attribute from Q7220 & Q7225. Also deleted - Page 25: Replaced U2590 with 2.85V LDO APN 353S3048 (MICREL) - Page 5: Added APN 376S0926 as an alternate for APN 376S0610 per GSM/CE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
the BOM table. Plan is to use 376S0895 as alternate instead - Page 25: Replaced APN 353S2986 with 353S3048 in the BOM table too for HVDDLDO:FIXED - Page 5: Added APN 155S0457 as an alternate for APN 155S0329 per GSM/CE
<rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep
- Page 5: Added APN 377S0107 as an alternate for APN 377S0066 per GSM/CE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
6 OF 110
- Page 57: Connected a new PME signal SMC_PME_S4_L to pin 2 <rdar://problem/8064296> K99 MLB: Change pull-up values for SMC 0 SMBus for TCON I2C III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
- Page 52: Changed R5250 & R5251 with 2K APN 117S0052 to reduce rise time
<rdar://problem/8004981> K99 MLB: Connect eDP SMBUS interface to SMC SMBUS 0
- Page 4: Added BOM option DPI2C:SMC to stuff R5242 & R5243
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Functional Test Points
LCP + SPI CONN

Fan Connectors LIO CONNECTOR DEBUG VOLTAGE
PP5V_S0 TRUE =PP3V3_S0_AUDIO 37

8 TRUE =PP3V3_S5_LPCPLUS 8 40
TRUE 7 8 57 (NEED 2 TP) PPVCORE_S0_CPU
D
I12
I15 TRUE FAN_RT_PWM 45

TRUE =PP3V42_G3H_ONEWIRE
SMC_BC_ACOK
8 37 TRUE =PP5V_S0_LPCPLUS
LPC_AD<3..0>
8 40
TRUE
TRUE PPVCORE_S0_MCP
8 42
8 42
D
I16
TRUE FAN_RT_TACH 45
TRUE 9 37 38 39 TRUE 19 38 40 68
TRUE PP1V05_S0 8 57
TRUE SYS_ONEWIRE 37 38 TRUE SPI_ALT_MOSI 40 68
(NEED TO ADD 1 GND TP) TRUE PP1V5_S0 8 57 71
TRUE =USB_PWR_EN 36 37 57 TRUE SPI_ALT_MISO 40 68
TRUE PP3V3_S0 8 57 71
TRUE USB_EXTD_OC_L 18 37 TRUE LPC_FRAME_L 19 38 40 68
TRUE PP5V_S0 7 8 57
TRUE USB_CAMERA_P 18 37 68 TRUE PM_CLKRUN_L 19 38 40
TRUE PP3V3_S3 8
TRUE USB_CAMERA_N 18 37 68 TRUE SMC_TMS 38 39 40
TRUE PP5V_S3 8
TRUE USB_EXTD_P 18 37 68 TRUE LPCPLUS_RESET_L 25 40
TRUE PP0V9_S5 8
TRUE USB_EXTD_N 18 37 68 TRUE SMC_TDO 38 39 40
TRUE PP3V3_S5 8 57 71
TRUE =PP1V8R1V5_S0_AUDIO 8 37 TRUE SMC_TRST_L 38 40
TRUE PP3V42_G3H 8
SPEAKER FUNC_TEST TRUE =I2C_LIO_SDA 37 41 TRUE SMC_MD1 38 40
TRUE PPBUS_G3H 8 42 49
TRUE SPKRAMP_R_N_OUT TRUE =I2C_LIO_SCL 37 41 TRUE SMC_TX_L 36 38 39 40
I228
48 49
TRUE PP3V3_WLAN_F 7 34 39
TRUE SPKRAMP_R_P_OUT TRUE AUD_GPIO_3 37 48 TRUE LPC_CLK33M_LPCPLUS 25 40 68
I230
48 49
AUD_I2C_INT_L TRUE PP3V3_S0_HDD_R 7 35
TRUE 19 37 TRUE SPIROM_USE_MLB 19 40 47
TRUE PPDCIN_S5_S5 8
TRUE =I2C_MIKEY_SDA 37 41 TRUE SPI_ALT_CLK 40 68
PPVOUT_SW_LCDBKLT
TRUE 7 42 59 62
TRUE =I2C_MIKEY_SCL 37 41 TRUE SPI_ALT_CS_L 40 68
TRUE PP3V3_SW_LCD 7 59
TRUE AUD_IP_PERIPHERAL_DET 17 37 TRUE LPC_SERIRQ 19 38 40
TRUE PP1V5R1V35_S3 8 71
TRUE SPKRAMP_INR_P 37 48 71 TRUE LPC_PWRDWN_L 19 38 40
TRUE SMC_PM_G2_EN 38 57
TRUE SPKRAMP_INR_N 37 48 71 TRUE SMC_TDI 38 39 40
TRUE PM_SLP_S4_L 19 38 57
TRUE HDA_SDIN0 19 37 68 TRUE SMC_TCK 38 39 40
TRUE PM_SLP_S3_L 19 38 39 57
TRUE HDA_SDOUT 19 37 68 TRUE SMC_RESET_L 38 39 40 50
TRUE HDA_BIT_CLK 19 37 68 TRUE SMC_NMI 38 40 TRUE PP0V9_ENET 8
TRUE HDA_SYNC 19 37 68 TRUE SMC_RX_L 36 38 39 40 TRUE PP1V05_S0_MCP_PLL_UF 8

INT DP FUNC_TEST TRUE HDA_RST_L 19 37 68 TRUE LPCPLUS_GPIO 19 40 TRUE PP3V3_ENET 8
TRUE AUD_IPHS_SWITCH_EN 19 37
(NEED TO ADD 6 GND TP) TRUE PP3V3_SW_DPPWR 61
TRUE PP3V3_SW_LCD 7 59
(NEED 2 TP)
(NEED TO ADD 5 GND TP) PP5V_S3_RTUSB_A_F
I259 TRUE 36
TRUE PPBUS_G3H_ISNS
C I260
TRUE
TRUE
PPVOUT_SW_LCDBKLT
DP_INT_ML_F_N<0>
7 42 59 (NEED 2 TP)
62
59 71
8
C
I261
I256
TRUE DP_INT_ML_F_P<0> 59 71
I257
TRUE DP_INT_ML_F_N<1> 59 71
I255
TRUE DP_INT_ML_F_P<1> 59 71 (NEED TO ADD 27 GND TP)
I252 TRUE DP_INT_AUX_CH_C_N 59 71

DC POWER CONN
I253
TRUE DP_INT_AUX_CH_C_P 59 71
(NEED 6 TP)
I254 TRUE DP_INT_HPD_CONN 59 TRUE =PP18V5_DCIN_CONN 8 49
TRUE LED_RETURN_1 59 62 TRUE =PP5V_S3_LIO_CONN 8 49

I251
AIRPORT / BT
I313
TRUE LED_RETURN_2 59 62 (NEED TO ADD 6 GND TP)
TRUE LED_RETURN_3 59 62
TRUE PCIE_AP_R2D_P 34 67
I246
TRUE PCIE_AP_R2D_N 34 67
I247
TRUE PCIE_AP_D2R_P 16 34 67
I248
TRUE PCIE_AP_D2R_N 16 34 67
I249
TRUE =I2C_TCON_SCL 41 59
TRUE PCIE_CLK100M_AP_P 16 34 67
I488
TRUE =I2C_TCON_SDA 41 59
TRUE PCIE_CLK100M_AP_N 16 34 67
I489
(NEED TO ADD 5 GND TP)
TRUE USB_BT_P 18 34 68
TRUE USB_BT_N 18 34 68
TRUE WIFI_EVENT_L 34 38 39
HALL EFFECT CONN (PLACEHOLDER) TRUE =PP3V3_S3_BT 8 34
TRUE PP3V3_WLAN_F (NEED 6 TP) 7 34 39

I479 TRUE SMC_LID_R 49 TRUE PCIE_WAKE_L 16 34
=PP3V42_G3H_HALL TRUE AP_RESET_CONN_L 34

TRUE 8 49
I480
TRUE AP_CLKREQ_Q_L 34
B FSB SIGNALS WITH NOTEST

B
NO_TEST=TRUE FSB_A_L<35..3> 10 14 65
NO_TEST=TRUE FSB_ADS_L 10 14 65
NO_TEST=TRUE FSB_ADSTB_L<1..0> 10 14 65
NO_TEST=TRUE FSB_D_L<63..0> 10 14 65
SATA HDD NO_TEST=TRUE FSB_DINV_L<3..0> 10 14 65
(NEED 5 TP)
NO_TEST=TRUE FSB_DSTB_L_N<3..0> 10 14 65
I319
TRUE PP3V3_S0_HDD_R 7 35 NO_TEST=TRUE FSB_DSTB_L_P<3..0> 10 14 65
I314
TRUE SATA_HDD_R2D_P 35 67 NO_TEST=TRUE FSB_HIT_L 10 14 65
I315
TRUE SATA_HDD_R2D_N 35 67 NO_TEST=TRUE FSB_HITM_L 10 14 65
IPD_FLEX_CONN
I318
TRUE SATA_HDD_D2R_C_P 35 67 NO_TEST=TRUE FSB_LOCK_L 10 14 65
I317
TRUE SATA_HDD_D2R_C_N 35 67 TRUE SMC_TPAD_RST_L 39 46 NO_TEST=TRUE FSB_REQ_L<4..0> 10 14 65
I455
TRUE SMC_HDD_OOB_TEMP 35 38 TRUE SMC_LID 38 39 46 49
I456
TRUE SMC_HDD_TEMP_CTL 35 38
TRUE SMC_ONOFF_L 38 39 46
TRUE =I2C_TPAD_SCL 41 46
TRUE =I2C_TPAD_SDA 41 46
TRUE =PP3V42_G3H_TPAD 8 46
TRUE PP3V3_TPAD_CONN 46
TRUE PP5V_TPAD_FILT 46
BATT POWER CONN TRUE USB_TPAD_CONN_N 46 71
TRUE USB_TPAD_CONN_P 46 71
I322
TRUE SMBUS_SMC_BSA_SCL 41 70
I321
TRUE SMBUS_SMC_BSA_SDA 41 70
I320
TRUE SYS_DETECT_L 49
A I305
TRUE PPVBAT_G3H_CONN 49
50
(NEED TO ADD 4 GND TP NEAR J6950 AND 1 FOR SHIELD)

(NEED 4 TP)
PAGE TITLE
FUNCTIONAL TEST
DRAWING NUMBER SIZE

REVISION
R
4.4.0
7 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"S0,S0M" RAILS "S3" RAILS "G3H" RAILS

LVDDR (1.5V/1.35V) Rails
49 =PP3V42_G3H_REG PP3V42_G3H 7
53 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 7 42 58 =PP5V_S0_FET PP5V_S0 7 57 52 =PPDDR_S3_REG PP1V5R1V35_S3 7 71 MIN_LINE_WIDTH=0.6 MM
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 mm 0.064 MIN_NECK_WIDTH=0.2 MM
18 A MIN_NECK_WIDTH=0.25 MM 0.100 A MIN_NECK_WIDTH=0.2 MM 11.30 A MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V
VOLTAGE=1.25V VOLTAGE=5V VOLTAGE=1.5V MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE (OR 1.35V)
=PPVIN_S5_SMCVREF 39
=PPVCORE_S0_CPU 11 12 64 =PP5V_S0_LPCPLUS 7 40 =PPLVDDR_S3_MEM_A 26 27 30
=PP3V42_G3H_SMBUS_SMC_BSA 41
=PP5V_S0_FAN 45 =PPLVDDR_S3_MEM_B 28 29 31
=PP3V42_G3H_PWRCTL 57
D
=PP5V_S0_CPU_IMVP
=PP5VR3V3_S0_DPCADET
53
61
0 mA
4250 mA
=PP1V5R1V35_S3_MCP_MEM
=PP1V5R1V35_S0_MCPDDRFET
15
21
=PP3V42_G3H_CHGR 50 57 D
=PP3V42_G3H_SMCUSBMUX 36
=PP5V_S0_CPUVTTS0 55 =PPVIN_S0_DDRREG_LDO 52
55 =PPCPUVTT_S0_REG PP1V05_S0 7 57 =PP3V42_G3H_TPAD 7 46
MIN_LINE_WIDTH=0.6 mm =PP5V_S0_BKL 62
9.40 A MIN_NECK_WIDTH=0.2 mm =PP3V42_G3H_HALL 7 49
VOLTAGE=1.05V =PP5V_S0_MCPREG 54
MAKE_BASE=TRUE =PP3V3_S5_SMC 38 39
=PP5V_S0_MCPFSBFET 22
=PP1V05_S0_CPU 10 11 12 =PP3V3_S5_LPCPLUS 7 40
=PP1V05_S0_MCP_FSB 14 20 23 =PP3V42_G3H_BMON_ISNS 43
=PP1V05_S0_MCP_AVDD_UF 23 58 =PP3V3_S3_FET PP3V3_S3 7 =PP3V42_G3H_ONEWIRE 7 37

MIN_LINE_WIDTH=0.5 mm
=PP1V05_S0_MCP_SATA_DVDD 20 23 1.274 A MIN_NECK_WIDTH=0.1 mm PP3V3_G3_RTC 19 20 23
VOLTAGE=3.3V
=PP1V05_S0_MCP_PLL_UF_R 56 MAKE_BASE=TRUE
=PP1V05_SW_MCP_FSB 20 23 =PP3V3_S3_SMBUS_SMC_A_S3 41
58 =PP3V3_S0_FET PP3V3_S0 7 57 71
=PP1V05_S0_MCP_PE_DVDD 20 23 MIN_LINE_WIDTH=0.6 mm =PP3V3_S3_PDCISENS 52
3.30 A MIN_NECK_WIDTH=0.2 mm
=PP1V05_S0_MCP_M2CLK_DLL 15 23 VOLTAGE=3.3V =PP3V3_S3_VREFMRGN 33
MAKE_BASE=TRUE 49 7 =PP18V5_DCIN_CONN PPDCIN_S5_S5 7
=PP3V3_S3_MCP_GPIO 19 MIN_LINE_WIDTH=1mm
=PP3V3_S0_XDP 13 MIN_NECK_WIDTH=0.20mm
=PP1V05_S0_MCP_DP0_VDD 17 24 =PP3V3_S3_SMS VOLTAGE=18.5V
=PP3V3_S0_MCP 20 23 MAKE_BASE=TRUE
=PP1V05_S0_XDP 13 =PP3V3_S3_1V5S3ISNS 42
=PP3V3_S0_P1V5S0 56 =PPDCIN_S5_CHGR 50
=PP3V3_S3_WLANISNS 42
=PP3V3_S0_DEBUGROM 40
=PP3V3_S3_DBGLEDS 49
=PP3V3_S0_SMBUS_SMC_0_S0 41
=PP3V3_S0_SMBUS_SMC_B_S0 41 50 =PPBUS_G3H PPBUS_G3H 7 42 49

=PP3V3_S3_BT 7 34 MIN_LINE_WIDTH=0.4 mm
54 =PPMCPCORE_S0_REG PPVCORE_S0_MCP 7 42 =PP3V3_S0_SMBUS_MCP_0 41 MIN_NECK_WIDTH=0.25 mm
(MCP VCORE AFTER SENSE RES) MIN_LINE_WIDTH=0.6 MM =PP3V3_S3_WLAN 34 VOLTAGE=8.4V
23.8 A MIN_NECK_WIDTH=0.2 MM =PP3V3_S0_FAN 45 MAKE_BASE=TRUE
VOLTAGE=1.05V =PP3V3_S3_TPAD 46
MAKE_BASE=TRUE =PP3V3_S0_AUDIO 7 37 =PPBUS_S0_LCDBKLT 63
=PPVCORE_S0_MCP 20 23 =PP3V3_S0_IMVP 53
=PPVIN_S5_P5VP3V3 51
=PPVCORE_S0_MCPGFXFET 22 =PP3V3_S0_MCP_GPIO 17 18 19
=PP3V3_S0_MCP_PLL_UF =PPBUS_G3H_R_IN 43
LVDDR VRef/VTT (0.75V/0.675V) Rails 23
=PP3V3_S0_MCP_HVDD =PPBUS_5V_S5 56
20 23
C 52 =PPVTT_S0_DDR_LDO
1.20 A
PPDDRVTT_S0
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
39
44
51 =PP5V_S3_REG
5.40 A
PP5V_S3
7 C
VOLTAGE=0.75V VOLTAGE=5V
MAKE_BASE=TRUE =PP3V3_S0_CPUTHMSNS 44 MAKE_BASE=TRUE
43 =PPBUS_G3H_R_OUT PPBUS_G3H_ISNS 7
=PP3V3_S0_PWRCTL 57 =PP5V_S3_MCPDDRFET 21 MIN_LINE_WIDTH=0.6 mm
=PPDDRVTT_S0_MEM_A 32 MIN_NECK_WIDTH=0.25 MM
=PP3V3_S0_SMBUS_MCP_1 41 =PP5V_S3_SYSLED 39 VOLTAGE=8.4V
=PPDDRVTT_S0_MEM_B 32 MAKE_BASE=TRUE
=PP3V3_S0_HDD 35 =PP5V_S3_TPAD 56
=PPVIN_S0_CPUVTTS0 55
=PP3V3_S0_MCP_PLL_VLDO 56 =PP5V_S3_DDRREG 52
=PPVIN_S5_CPU_IMVP 53
=PP3V3_S0_MCPCOREISNS 43 =PP5V_S3_AUDIO_AMP 48
=PPVIN_S0_MCPCORE 54
52 33 =PPVTT_S3_DDR_BUF PPDDRVREF_S3 =PP3V3_S0_MCPDDRISNS 43 =PP5V_S3_P5VS0FET 58
=PPVIN_S3_DDRREG
MIN_LINE_WIDTH=0.3 mm 52
MIN_NECK_WIDTH=0.2 mm =PP3V3_S0_BKLTISNS 42 =PP5V_S3_RTUSB 36
VOLTAGE=0.75V
MAKE_BASE=TRUE =PP3V3_S0_CSREGISNS 43 =PP5V_S3_LIO_CONN 7 49
=PP3V3_S0_BKL_VDDIO 62
=PP3V3_S0_DPCONN 61
=PP3V3_S0_HDDISNS 42
56 =PP1V5_S0_REG PP1V5_S0 7 57 71
.210 A MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_CPU 11 12
=PP1V5_S0_MCP_PLL_VLDO 56
=PP1V8R1V5_S0_AUDIO 7 37
=PP3V3R1V5_S0_MCP_HDA 19 23
B "ENET" RAILS B
"S5" RAILS
9 =PP3V3_ENET_FET_R PP3V3_ENET 7
400mA MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 57 51 =PP3V3_S5_REG PP3V3_S5 7 57 71
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm
1.07 A + S3 + S0 MIN_NECK_WIDTH=0.2 mm
=PP3V3_ENET_MCP_RMGT 18 20 23 VOLTAGE=3.3V
56 =PP1V05_S0_MCP_PLL_OR PP1V05_S0_MCP_PLL_UF 7 300mA MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM =PP3V3_ENET_MCP_PLL_MAC 23
MIN_NECK_WIDTH=0.2 mm =PP3V3_S5_MCP_GPIO 18 19
VOLTAGE=1.05V ~100mA
MAKE_BASE=TRUE =PP3V3_S5_ROM 47
=PP1V05_S0_MCP_PLL_UF 23 =PP3V3_S5_MCP 20 23
=PP3V3_S5_MCPPWRGD 25
58 =PP0V9_ENET_FET PP0V9_ENET 7 =PP3V3_S5_P3V3S3FET 58

MIN_NECK_WIDTH=0.2 mm =PP3V3_S5_P3V3S0FET 58
VOLTAGE=0.9V
MAKE_BASE=TRUE =PP3V3_S5_P3V3ENETFET 58
=PP0V9_ENET_MCP_RMGT 20 23 =PP3V3_S5_P0V9S5 56 57
=PP3V3_S5_VMON 57
=PP3V3_S5_SMBUS_SMC_MGMT 41
=PP3V3_S5_P0V9ENETFET 58
=PP3V3_S5_TPAD 46
=PP3V3_S5_DP_PORT_PWR 61
=PP3V3_S0_LCD 59
=PP3V3_SMC_PME 39
A 56 =PP0V9_S5_REG
0.290 A
PP0V9_S5
7
VOLTAGE=0.9V PAGE TITLE
105 mA/241 mA
MAKE_BASE=TRUE
=PP0V9_S5_MCP_VDD_AUXC 20 23
Power Aliases
DRAWING NUMBER SIZE
=PP0V9_ENET_P0V9ENETFET 58

REVISION
R
4.4.0
8 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HEAT SINK MOUNTING BOSSES CPU ALIASES
PCI-E ALIASES LVDS ALIASES
UNUSED GPU LANES 65 10 CPU_BSEL<0:2> =MCP_BSEL<0:2> BSEL<2..0> 14
Z0906 Z0907 Z0908 =PEG_D2R_N<5:4> NC_PEG_D2RN<5:4> =MCP_IFPA_TXC_P NC_LVDS_IG_A_CLKP NO_TEST=TRUE
MAKE_BASE=TRUE
FSB MHZ
STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM 16

NO_TEST=TRUE MAKE_BASE=TRUE
17
MAKE_BASE=TRUE 14 CPU_PECI_MCP TP_CPU_PECI_MCP 0 0 0 266
17 =MCP_IFPA_TXC_N NC_LVDS_IG_A_CLKN NO_TEST=TRUE MAKE_BASE=TRUE 0 0 1 133
1 1 1 16 =PEG_D2R_P<5:4> NC_PEG_D2RP<5:4> MAKE_BASE=TRUE 0 1 0 200
NO_TEST=TRUE MAKE_BASE=TRUE 17 =MCP_IFPA_TXD_P<0..3> NC_LVDS_IG_A_DATAP<0..3> NO_TEST=TRUE 0 1 1 (166)
16 =PEG_R2D_C_N<5:4> NC_PEG_R2DCN<5:4> 17 =MCP_IFPA_TXD_N<0..3> NC_LVDS_IG_A_DATAN<0..3>MAKE_BASE=TRUE

NO_TEST=TRUE
1
1
0
0
0
1
333
100
NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 1 1 0 (400)
MCP89 ALIASES
Z0909 Z0910 Z0911 16 =PEG_R2D_C_P<5:4> NC_PEG_R2DCP<5:4>
1 1 1 (RSVD)
STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.8H-SM 67 16 PEG_CLK100M_P NC_PEG_CLK100MP
1 1 NO_TEST=TRUE MAKE_BASE=TRUE 17 =MCP_IFPB_TXC_P NC_LVDS_IG_B_CLKP NO_TEST=TRUE 17 TP_MCP_RGB_DAC_VREF NC_MCP_RGB_DAC_VREF NO_TEST=TRUE
1 MAKE_BASE=TRUE MAKE_BASE=TRUE
67 16 PEG_CLK100M_N NC_PEG_CLK100MN 17 =MCP_IFPB_TXC_N NC_LVDS_IG_B_CLKN NO_TEST=TRUE
D 16 PEG_CLKREQ_L
NO_TEST=TRUE
NC_PEG_CLKREQ_L
MAKE_BASE=TRUE
17 =MCP_IFPB_TXD_P<0..3> NC_LVDS_IG_B_DATAP<0..3> MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
66 15 MEM_A_CLK_P<1> TP_MEM_A_CLKP<1> MAKE_BASE=TRUE
D
NO_TEST=TRUE MAKE_BASE=TRUE 17 =MCP_IFPB_TXD_N<0..3> NC_LVDS_IG_B_DATAN<0..3> NO_TEST=TRUE 66 15 MEM_A_CLK_N<1> TP_MEM_A_CLKN<1>
Z0912 Z0913 ENET_CLKREQ_L NC_ENET_CLKREQ_L MAKE_BASE=TRUE
MEM_B_CLK_P<1> TP_MEM_B_CLKP<1> MAKE_BASE=TRUE
MAKE_BASE=TRUE
STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM 16
66 15
1 1 66 15 MEM_B_CLK_N<1> TP_MEM_B_CLKN<1> MAKE_BASE=TRUE

USB ALIASES
17 LCD_IG_BKLT_PWM LCD_BKLT_PWM 62
UNUSED USB PORTS MAKE_BASE=TRUE 66 15 MEM_A_A<15> TP_MEM_A_A<15> MAKE_BASE=TRUE
59 17 9 LCD_IG_PWR_EN LCD_IG_PWR_EN 9 17 59
68 18 USB_SDCARD_P NC_USB_SDCARDP NO_TEST=TRUE MAKE_BASE=TRUE 66 15 MEM_B_A<15> TP_MEM_B_A<15> MAKE_BASE=TRUE
MAKE_BASE=TRUE 17 LCD_IG_BKLT_EN LCD_BKLT_EN 63
68 18 USB_SDCARD_N NC_USB_SDCARDN NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
68 18 USB_MINI_P NC_USB_MINIP NO_TEST=TRUE
MAKE_BASE=TRUE 17 =MCP_IFPAB_DDC_CLK TP_LVDS_DDC_CLK
68 18 USB_MINI_N NC_USB_MININ NO_TEST=TRUE MAKE_BASE=TRUE 19 MCP_MEM_VDD_SEL_1V5 TP_MEM_VDD_SEL_1V5 MAKE_BASE=TRUE
MAKE_BASE=TRUE 17 =MCP_IFPAB_DDC_DATA TP_LVDS_DDC_DATA
68 18 USB_EXTC_P NC_USB_EXTCP NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
68 18 USB_EXTC_N NC_USB_EXTCN NO_TEST=TRUE
MAKE_BASE=TRUE
FAN BOSS SSD BOSS X16 BOSS

Z0915 Z0914 ETHERNET ALIASES
Z0905 STDOFF-4.5OD1.9H-SM STDOFF-4.5OD1.9H-SM
STDOFF-4.5OD1.8H-SM PLACE_NEAR=U7980.A1:5MM
1 1
1 R0911
0 DISPLAY PORT ALIASES
PP3V3_ENET_FET 1 2 =PP3V3_ENET_FET_ROUT 8
MIN_NECK_WIDTH=0.2 MM 5%
VOLTAGE=3.3V 1/16W DP_IG_ML0_P<0..3> DP_EXT_ML_P<0..3>
MAKE_BASE=TRUE MF-LF 67 17 61 71
MAKE_BASE=TRUE
402 DP_IG_ML0_N<0..3> DP_EXT_ML_N<0..3>
58 =PP3V3_ENET_FET 67 17 61 71
MAKE_BASE=TRUE
17 DP_IG_HPD0 DP_EXT_HPD 61
67 17 DP_IG_AUX_CH0_P DP_EXT_AUX_CH_P MAKE_BASE=TRUE

60
67 17 DP_IG_AUX_CH0_N DP_EXT_AUX_CH_N MAKE_BASE=TRUE

60
MAKE_BASE=TRUE
DP_AUX_CH_C_N DP_EXT_AUX_CH_C_N
C MDP CONN METAL TAB
ENET_RXD_PD
MAKE_BASE=TRUE
ENET_RXD<0>
ENET_RXD<1>
OUT
OUT
18 69
18 69
60
60 DP_AUX_CH_C_P DP_EXT_AUX_CH_C_P
61 71
MAKE_BASE=TRUE
61 71
MAKE_BASE=TRUE
C
ENET_RXD<2> 18 69
60 DP_CA_DET DP_EXT_CA_DET 61
OUT MAKE_BASE=TRUE
NOSTUFF ENET_RXD<3> OUT 18 69
MT0900 DP_IG_ML1_P<1:0> DP_INT_ML_P<1:0>
STIFFENER-K16-K99 ENET_RXCLK_PD ENET_CLK125M_RXCLK OUT 18 69
67 17 59 71
SM-SP MAKE_BASE=TRUE 67 17 DP_IG_ML1_N<1:0> DP_INT_ML_N<1:0> MAKE_BASE=TRUE

59 71
ENET_RX_CTRL MAKE_BASE=TRUE
1 OUT 18 69
67 17 DP_IG_AUX_CH1_P DP_INT_AUX_CH_P 59 71
ENET_MDIO 18 69
67 17 DP_IG_AUX_CH1_N DP_INT_AUX_CH_N MAKE_BASE=TRUE
59 71
BI MAKE_BASE=TRUE
MCP_RGMII_VREF OUT 18
17 DP_IG_HPD1 DP_INT_HPD 59
MAKE_BASE=TRUE
ENET_ENERGY_DET 17 DP_IG_ML1_P<3:2> TP_DP_INT_MLP<3:2>
R09801 1
R0981 R09841 OUT 18
17 DP_IG_ML1_N<3:2> MAKE_BASE=TRUE
TP_DP_INT_MLN<3:2>
MAKE_BASE=TRUE
10K 10K 10K CHARGER SIGNAL
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 2 2 201 201 2 50 IN =CHGR_ACOK SMC_BC_ACOK OUT 7 37 38 39
SATA ALIASES MAKE_BASE=TRUE
1
R0985 UNUSED SATA ODD SIGNALS
R09821 1
R0983 10K
5%
10K 10K 1/20W
5% 5% MF
1/20W 1/20W 2 201 67 18 SATA_ODD_R2D_C_P NC_SATA_ODD_R2DCP NO_TEST=TRUE MCPCOREISNS SIGNAL
MF MF MAKE_BASE=TRUE
201 2 2 201 67 18 SATA_ODD_R2D_C_N NC_SATA_ODD_R2DCN NO_TEST=TRUE
MAKE_BASE=TRUE 54 MCPCORES0_VO =MCPCOREISNS_N 43
67 SATA_ODD_R2D_P NC_SATA_ODD_R2DP NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
67 SATA_ODD_R2D_N NC_SATA_ODD_R2DN NO_TEST=TRUE
MAKE_BASE=TRUE MCPCORES0_ISP_R =MCPCOREISNS_P
67 18 SATA_ODD_D2R_P NC_SATA_ODD_D2RP NO_TEST=TRUE 54 43
MAKE_BASE=TRUE MAKE_BASE=TRUE
67 18 SATA_ODD_D2R_N NC_SATA_ODD_D2RN NO_TEST=TRUE
MAKE_BASE=TRUE
B B
EMI IO POGO PINS

CRITICAL
CRITICAL CRITICAL
ZS0904 ZS0905 ZS0906
1.4DIA-SHORT-SILVER-K99 POGO-2.0OD-3.6H-K86-K87
POGO-2.0OD-2.95H-K86-K87 SM SM
SM
1 1
1
CRITICAL
ZS0907
POGO-2.0OD-3.6H-K86-K87
SM
1
PAGE TITLE
SIGNAL ALIAS
DRAWING NUMBER SIZE
GND 051-8379 D
VOLTAGE=0V Apple Inc. REVISION
MIN_LINE_WIDTH=0.50MM R
MIN_NECK_WIDTH=0.20MM 4.4.0
9 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
65 14 7 BI FSB_A_L<3> P2 A3* U1000 ADS* M4 FSB_ADS_L BI 7 14 65
65 14 7 BI FSB_A_L<4> V4 A4* BGA BNR* J5 FSB_BNR_L BI 14 65
65 14 7 BI FSB_A_L<5> W1 A5* (1 OF 8) BPRI* L5 FSB_BPRI_L BI 14 65

=PP1V05_S0_CPU 8 11 12
FSB_A_L<6>
CDC-QKWH-QS-1.2-10W-800-R0-1M
PENRYN-SFF
65 14 7 BI T4 A6*
65 14 7 BI FSB_A_L<7> AA1 A7* DEFER* N5 FSB_DEFER_L BI 14 65
65 14 7 BI FSB_A_L<8> AB4 A8* DRDY* F38 FSB_DRDY_L BI 14 65
65 14 7 BI FSB_A_L<9> T2 A9* DBSY* J1 FSB_DBSY_L BI 14 65

R10001
54.9
65 14 7 BI FSB_A_L<10> AC5 A10* 1%
1/20W
65 14 7 BI FSB_A_L<11> AD2 A11* BR0* M2 FSB_BREQ0_L BI 14 65 MF
201 2
65 14 7 BI FSB_A_L<12> AD4 A12*
D 65 14 7
65 14 7
BI
BI
FSB_A_L<13>
FSB_A_L<14>
AA5
AE5
A13*
A14*
IERR*
INIT*
B40
D8
65 CPU_IERR_L
CPU_INIT_L IN 14 65
D
65 14 7 BI FSB_A_L<15> AB2 A15*
65 14 7 BI FSB_A_L<16> AC1 A16* LOCK* N1 FSB_LOCK_L BI 7 14 65
65 14 7 BI FSB_ADSTB_L<0> Y4 ADSTB0*
ADDR GROUP0
RESET* G5 FSB_CPURST_L IN 13 14 65
65 14 7 FSB_REQ_L<0> R1 REQ0* RS0* K2 FSB_RS_L<0> 14 65
CONTROL
BI IN
65 14 7 BI FSB_REQ_L<1> R5 REQ1* RS1* H4 FSB_RS_L<1> IN 14 65
65 14 7 BI FSB_REQ_L<2> U1 REQ2* RS2* K4 FSB_RS_L<2> IN 14 65
65 14 7 BI FSB_REQ_L<3> P4 REQ3* TRDY* L1 FSB_TRDY_L IN 14 65
65 14 7 BI FSB_REQ_L<4> W5 REQ4*
HIT* H2 FSB_HIT_L BI 7 14 65
FSB_A_L<17> AN1 F2 FSB_HITM_L OMIT_TABLE

65 14 7 BI A17* HITM* BI 7 14 65
65 14 7 BI FSB_A_L<18> AK4 A18* 65 14 7 BI FSB_D_L<0> F40 D0* U1000 D32* AP44 FSB_D_L<32> BI 7 14 65
65 14 7 BI FSB_A_L<19> AG1 A19* BPM0* AY8 XDP_BPM_L<0> BI 13 65 65 14 7 BI FSB_D_L<1> G43 D1* BGA D33* AR43 FSB_D_L<33> BI 7 14 65
XDP/ITP SIGNALS
65 14 7 BI FSB_A_L<20> AT4 A20* BPM1* BA7 XDP_BPM_L<1> BI 13 65
R10011 65 14 7 BI FSB_D_L<2> E43 D2* (2 OF 8) D34* AH40 FSB_D_L<34> BI 7 14 65
54.9
PENRYN-SFF
FSB_A_L<21> AK2 A21* BPM2* BA5 XDP_BPM_L<2> 1% FSB_D_L<3> J43 D3* D35* AF40 FSB_D_L<35>
ADDR GROUP1
65 14 7 BI BI 13 65 65 14 7 BI BI 7 14 65
1/20W
65 14 7 BI FSB_A_L<22> AT2 A22* BPM3* AY2 XDP_BPM_L<3> BI 13 65 MF 65 14 7 BI FSB_D_L<4> H40 D4* D36* AJ43 FSB_D_L<36> BI 7 14 65
201 2
65 14 7 BI FSB_A_L<23> AH2 A23* PRDY* AV10 XDP_BPM_L<4> BI 13 65 65 14 7 BI FSB_D_L<5> H44 D5* D37* AG41 FSB_D_L<37> BI 7 14 65
65 14 7 BI FSB_A_L<24> AF4 A24* PREQ* AV2 XDP_BPM_L<5> BI 13 65 65 14 7 BI FSB_D_L<6> G39 D6* D38* AF44 FSB_D_L<38> BI 7 14 65
65 14 7 BI FSB_A_L<25> AJ5 A25* TCK AV4 XDP_TCK IN 10 13 65 65 14 7 BI FSB_D_L<7> E41 D7* D39* AH44 FSB_D_L<39> BI 7 14 65
65 14 7 BI FSB_A_L<26> AH4 A26* TDI AW7 XDP_TDI IN 10 13 65 65 14 7 BI FSB_D_L<8> L41 D8* D40* AM44 FSB_D_L<40> BI 7 14 65
65 14 7 BI FSB_A_L<27> AM4 A27* TDO AU1 XDP_TDO OUT 10 13 65 65 14 7 BI FSB_D_L<9> K44 D9* D41* AN43 FSB_D_L<41> BI 7 14 65
65 14 7 BI FSB_A_L<28> AP4 A28* TMS AW5 XDP_TMS IN 10 13 65 65 14 7 BI FSB_D_L<10> N41 D10* D42* AM40 FSB_D_L<42> BI 7 14 65
65 14 7 BI FSB_A_L<29> AR5 A29* TRST* AV8 XDP_TRST_L IN 10 13 65 65 14 7 BI FSB_D_L<11> T40 D11* D43* AK40 FSB_D_L<43> BI 7 14 65
65 14 7 BI FSB_A_L<30> AJ1 A30* 65 14 7 BI FSB_D_L<12> M40 D12* D44* AG43 FSB_D_L<44> BI 7 14 65
C 65 14 7 BI FSB_A_L<31> AL1 A31* R10021 65 14 7 BI FSB_D_L<13> G41 D13* D45* AP40 FSB_D_L<45> BI 7 14 65 C
68
65 14 7 BI FSB_A_L<32> AM2 A32* THERMAL 5% 65 14 7 BI FSB_D_L<14> M44 D14* D46* AN41 FSB_D_L<46> BI 7 14 65
DATA GRP 0
DATA GRP 2
1/20W
65 14 7 BI FSB_A_L<33> AU5 A33* MF 65 14 7 BI FSB_D_L<15> L43 D15* D47* AL41 FSB_D_L<47> BI 7 14 65
201 2
65 14 7 BI FSB_A_L<34> AP2 A34* 65 14 7 BI FSB_DSTB_L_N<0> K40 DSTBN0* DSTBN2* AK44 FSB_DSTB_L_N<2> BI 7 14 65
65 14 7 BI FSB_A_L<35> AR1 A35* PROCHOT* D38 CPU_PROCHOT_L OUT 14 39 65 65 14 7 BI FSB_DSTB_L_P<0> J41 DSTBP0* DSTBP2* AL43 FSB_DSTB_L_P<2> BI 7 14 65
65 14 7 BI FSB_ADSTB_L<1> AN5 ADSTB1* THRMDA BB34 CPU_THERMD_P OUT 44 71 65 14 7 BI FSB_DINV_L<0> P40 DINV0* DINV2* AJ41 FSB_DINV_L<2> BI 7 14 65
THRMDC BD34 CPU_THERMD_N OUT 44 71
65 14 IN CPU_A20M_L C7 A20M*
DATA GRP 3
CPU_FERR_L D4 FERR* THERMTRIP* B10 PM_THRMTRIP_L FSB_D_L<16> P44 D16* D48* AV38 FSB_D_L<48>
DATA GRP1
65 14 OUT OUT 14 39 65 65 14 7 BI BI 7 14 65
65 14 IN CPU_IGNNE_L F10 IGNNE* 65 14 7 BI FSB_D_L<17> V40 D17* D49* AT44 FSB_D_L<49> BI 7 14 65
ICH 65 14 7 BI FSB_D_L<18> V44 D18* D50* AV40 FSB_D_L<50> BI 7 14 65
65 14 CPU_STPCLK_L F8 STPCLK* H CLK 65 14 7 FSB_D_L<19> AB44 D19* D51* AU41 FSB_D_L<51> 7 14 65

IN BI BI
65 14 IN CPU_INTR C9 LINT0 65 14 7 BI FSB_D_L<20> R41 D20* D52* AW41 FSB_D_L<52> BI 7 14 65
65 14 IN CPU_NMI C5 LINT1 BCLK0 A35 FSB_CLK_CPU_P IN 14 65 65 14 7 BI FSB_D_L<21> W41 D21* D53* AR41 FSB_D_L<53> BI 7 14 65
65 14 IN CPU_SMI_L E5 SMI* BCLK1 C35 FSB_CLK_CPU_N IN 14 65 65 14 7 BI FSB_D_L<22> N43 D22* D54* BA37 FSB_D_L<54> BI 7 14 65
65 14 7 BI FSB_D_L<23> U41 D23* D55* BB38 FSB_D_L<55> BI 7 14 65
65 14 7 BI FSB_D_L<24> AA41 D24* D56* AY36 FSB_D_L<56> BI 7 14 65
65 14 7 BI FSB_D_L<25> AB40 D25* D57* AT40 FSB_D_L<57> BI 7 14 65

25 13 OUT XDP_DBRESET_L J7 DBR*
65 14 7 BI FSB_D_L<26> AD40 D26* D58* BC35 FSB_D_L<58> BI 7 14 65
RSVD7 J9 TP_CPU_RSVD_J9
65 14 7 BI FSB_D_L<27> AC41 D27* D59* BC39 FSB_D_L<59> BI 7 14 65
10 CPU_TEST1 E37 TEST1 RSVD9 F4 TP_CPU_RSVD_F4
NEED_TP=TRUE 65 14 7 BI FSB_D_L<28> AA43 D28* D60* BA41 FSB_D_L<60> BI 7 14 65
10 CPU_TEST2 D40 TEST2 RSVD10 H8 TP_CPU_RSVD_H8
NEED_TP=TRUE 65 14 7 BI FSB_D_L<29> Y40 D29* D61* BB40 FSB_D_L<61> BI 7 14 65
TP_CPU_TEST3 C43 TEST3 RSVD11 V2 TP_CPU_RSVD_V2
65 14 7 BI FSB_D_L<30> Y44 D30* D62* BA35 FSB_D_L<62> BI 7 14 65
10 CPU_TEST4 AE41 TEST4 RSVD12 Y2 TP_CPU_RSVD_Y2
65 14 7 BI FSB_D_L<31> T44 D31* D63* AU43 FSB_D_L<63> BI 7 14 65
TP_CPU_TEST5 AY10 TEST5 RSVD13 AG5 TP_CPU_RSVD_AG5 1
R1005 65 14 7 BI FSB_DSTB_L_N<1> U43 DSTBN1* DSTBN3* AY40 FSB_DSTB_L_N<3> BI 7 14 65
TP_CPU_TEST6 AC43 TEST6 RSVD14 AL5 TP_CPU_RSVD_AL5 1K
1% PLACE_NEARs: 65 14 7 BI FSB_DSTB_L_P<1> W43 DSTBP1* DSTBP3* AY38 FSB_DSTB_L_P<3> BI 7 14 65
1/20W
B CPU JTAG Support R1090 2
MF
201 R1005.2: U1000.AW43:12.7 mm
R1006.1: U1000.AW43:12.7 mm
65 14 7 BI FSB_DINV_L<1> R43 DINV1* DINV3* BC37 FSB_DINV_L<3> BI 7 14 65
B
XDP_TMS 1
54.9 2 C1014.1: U1000.AE41:12.7 mm
CPU_GTLREF CPU_COMP<0>
65 13 10 65 33 AW43 GTLREF COMP0 AE43 65
1% CPU_TEST1 10
MISC COMP1 AD44 65 CPU_COMP<1>
R1091 1/20W
MF 1
R1006 CPU_TEST2 10 COMP2 AE1 65 CPU_COMP<2>
XDP_TDI 54.9 2 201
CPU_COMP<3>
65 13 10 1 2K COMP3 AF2 65
1%
1% 1/20W CPU_TEST4 10
1/20W
MF R1092 MF
2 201 NO STUFF DPRSTP* G7 CPU_DPRSTP_L IN 14 53 65 R10231 R10211
201 54.9 2
65 13 10 XDP_TDO 1 C1014 1 DPSLP* B8 CPU_DPSLP_L IN 14 65 54.9
1%
54.9
1%
PLACE_NEAR=J1300.52:12.7 mm 1% NO STUFF 0.1UF DPWR* C41 FSB_DPWR_L IN 14 65 1/20W 1/20W
1/20W 10% MF MF
6.3V 2 CPU_BSEL<0> CPU_PWRGD
MF
201 R1010 X5R
201
65 9 OUT A37 BSEL0 PWRGOOD E7 IN 13 14 65 201 2 201 2
0 65 9 OUT CPU_BSEL<1> C37 BSEL1 SLP* D10 FSB_CPUSLP_L IN 14 65
1 2
65 9 OUT CPU_BSEL<2> B38 BSEL2 PSI* BD10 TP_CPU_PSI_L 1 1
NO STUFF 5%
1/20W
NO STUFF R1022 R1020
R1093 R10111 MF
201
1
R1012 27.4
1% 1%
27.4
54.9 2 1K 1K 1/20W 1/20W
65 13 10 XDP_TCK 1 5% 5% MF MF
1/20W 1/20W 2 201 2 201
1% MF MF
R1094 1/20W
MF
201 2 2 201
54.9 2 201
65 13 10 XDP_TRST_L 1 PLACE_NEARs:
1%
1/20W R1020.1: U1000.AE43:12.7 mm
MF R1021.1: U1000.AD44:12.7 mm
201 R1022.1: U1000.AE1:12.7 mm
R1023.1: U1000.AF2:12.7 mm
PAGE TITLE
CPU FSB
DRAWING NUMBER SIZE

REVISION
R
4.4.0
10 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(CPU CORE POWER)
=PPVCORE_S0_CPU 8 11 12 64 =PP1V05_S0_CPU 8 10 11 12
OMIT_TABLE OMIT_TABLE
18 A (CULV Design Target) OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
17.6 A (CULV ICC_Max)
BD30 K20 H32 AD28 AE37 R13 B42 AP34 E21 AE17 Y6 AJ3
BB28 U1000 M16 G33 U1000 AD30 AP38 U1000 P12 H42 U1000 AM34 E23
U1000 AE19 Y8
U1000 AG3
BB30 BGA M18 F32 BGA AB28 AN37 BGA P14 F42 BGA AV36 E25 BGA AR17 AK6 BGA AE3
B24 (7 OF 8) K16 N33 (3 OF 8) AB30 AL37 (8 OF 8) AB10 D42 (4 OF 8) AT36 N21 (5 OF 8) AR19 AK8 (6 OF 8) AR3
PENRYN-SFF
PENRYN-SFF
PENRYN-SFF
PENRYN-SFF
PENRYN-SFF
PENRYN-SFF
B22 K18 M32 Y28 C33 AD14 D44 AY34 N23 AN17 AH6 AN3
H22 V20 L33 Y30 B32 AC11 F44 AW33 N25 AN19 AH8 AL3
H24 T20 K32 AK26 H36 AC13 M42 AW35 L21 AL17 AF6 AW3
D F22 P20 J33 AH26 F36 AB12 K42 AV34 L23 AL19 AF8 AU3 D
F24 V16 W33 AF26 G35 AB14 V42 AU35 L25 AW17 AP6 BD4
D24 V18 V32 AK28 F34 AA11 T42 BD36 J21 AW19 AP8 BC3
D22 T16 U33 AK30 E33 AA13 P42 BB36 J23 AU17 AM6 BB2
M22 T18 T32 AH28 E35 Y14 AD42 BC33 J25 AU19 AM8 BA3
M24 P16 R33 AH30 D32 AK10 AB42 BA33 W21 BC17 AY6 G1
K22 P18 P32 AF28 K36 AF10 Y42 C31 W23 BC19 AW9 E1
K24 AD20 AD32 AF30 N35 AK12 AK42 C29 W25 BA17 AU7 AW1
V22 AB20 AC33 AP26 L35 AK14 AH42 C27 U21 BA19 AV6 BA1
V24 Y20 AB32 VCC AM26 J35 AJ11 AF42 G31 U23 C15 AU9 A39
T22 AD16 AA33 AP28 W35 AJ13 AP42 E31 U25 C11 AT6 VSS VSS A41
T24 AD18 Y32 AP30 V36 AH14 AM42 G27 R21 H10 AT8 A31
P22 AB16 AK32 AM28 P36 AG11 AY42 G29 R23 G15 BD6 A27
P24 AB18 AJ33 AM30 U35 AG13 AV42 E27 R25 E15 BC9 A29
AD22 Y16 AH32 AY26 R35 AF12 AT42 E29 AC21 M10 BB6 A21
AD24 Y18 AG33 AV26 AB36 AF14 AV44 N31 AC23 N15 BA9 A23
AB22 AK20 AF32 AT26 AC35 AE11 AY44 L31 AC25 L15 C3 A25
AB24 AK16 AE33 AY28 AA35 AE13 BB42 J31 AA21 J15 B4 A17
Y22 AK18 AR33 AY30 AK36 AP10 BA43 N27 AA23 M12 G3 A19
Y24 AH20 AP32 AV28 AF36 AR11 C39 N29 AA25 T10 E3 A15
AK22 AF20 AN33 AV30 AJ35 AR13 H38 L27 AJ21 W15 D2 A11
AK24 AH16 AM32 AT28 AG35 AP12 G37 L29 AJ23 U15 N3 A9
AH22 VCC VCC AH18 AL33 AT30 AE35 AN11 E39 J27 AJ25 R15 L3 A5
AH24 AF16 AY32 BD26 AP36 VCCP VCCP AN13 N39 J29 AG21 T12 J3 A7
AF22 AF18 AV32 BB26 AN35 AL11 M38 W31 AG23 AD10 W3
VCC
AF24 AP20 AU33 BD28 (CPU IO POWER 1.05V) AL35 AL13 L39 W27 AG25 Y10 U3
=PP1V05_S0_CPU
C AP22
AP24
AM20
AP16
AT32
AT34 N37
8 10 11 12
4500 mA (before VCC stable)

C13
B14
AU11
AU13
J39
W39
W29
U31
AE21
AE23
AC15
AA15
R3
AC3
C
AM22 AP18 BD32 L37 B12 N7 U39 R31 AE25 AD12 AA3
AM24 AM16 BB32 K38
2500 mA (after VCC stable) H12 N9 T38 U27 AR21 Y12
AY22 AM18 B26 J37 H14 L7 R39 U29 AR23 AH10
AY24 AY20 B30 W37 G11 L9 AD38 R27 AR25 AJ15
AV22 AV20 B28 V38 G13 W7 AC39 R29 AN21 AG15
AV24 AT20 H26 U37 F12 W9 AA39 AC31 AN23 VSS VSS AE15
VSS VSS
AT22 AY16 F26 VCCP R37 F14 U7 Y38 AA31 AN25 AH12
AT24 AY18 D26 P38 E11 U9 AJ39 AC27 AL21 AM10
BD22 AV16 H28 AC37 E13 R7 AH38 AC29 AL23 AR15
BD24 AV18 H30 AB38 D14 R9 AG39 AA27 AL25 AN15
BB22 AT16 F28 AA37 D12 AC7 AE39 AA29 AW21 AL15
BB24 AT18 F30 AK38 K10 AC9 AR37 AJ31 AW23 AM12
B20 BD20 D30 AJ37 N11 AA7 AR39 AG31 AW25 AT10
B18 BB20 D28 AG37 N13 AA9 AN39 AE31 AU21 AW15
B16 BD16 M26 AF38 M14 AJ7 AM38 AJ27 AU23 AU15
H20 BD18 K26 (CPU INTERNAL PLL POWER 1.5V) L11 AJ9 AL39 AJ29 AU25 AY12
F20 BB16 M28 B34 =PP1V5_S0_CPU 8 12 L13 AG7 AW37 AG27 BC21 AW11
D20 BB18 M30 VCCA D34 K12 AG9 AW39 AG29 BC23 AW13
H16 AP14 K28
130 mA K14 AE7 AU37 AE27 BC25 AV12
H18 AM14 K30 BD8 CPU_VID<0> OUT 12 53 65 J11 AE9 AU39 AE29 BA21 AT12
F16 AY14 V26 BC7 CPU_VID<1> OUT 12 53 65 J13 AR7 AT38 AR31 BA23 BC15
=PPVCORE_S0_CPU 8 11 12 64
F18 AV14 T26 BB10 CPU_VID<2> OUT 12 53 65 V10 AR9 BD38 AR27 BA25 BA15
D18 AT14 P26 VID BB8 CPU_VID<3> OUT 12 53 65
1 P10 AN7 BD40 AR29 C19 BC11
D16 BD14 V28 BC5 CPU_VID<4> OUT 12 53 65
R1100 W11 AN9 BC41 AN31 C17
CPU_VID<5> 100
M20 BB14 V30 BB4 12 53 65 1% W13 AL7 BA39 AL31 G17 BB12
B T28 AY4 CPU_VID<6>
OUT
OUT 12 53 65
1/20W
MF
2 201
V12 AL9 B36 AN27 G19 BA11 B
T30 V14 A33 D36 AN29 E17 BA13
PLACE_NEAR=U1000.BD12:25.4 mm
P28 VCCSENSE BD12 CPU_VCCSENSE_P OUT 53 65 U11 A13 H34 AL27 E19 B6
P30 U13 M36 AL29 N17 H6
AD26 VSSSENSE BC13 CPU_VCCSENSE_N OUT 53 65 T14 M34 AW31 N19 G9
AB26 PLACE_NEAR=U1000.BC13:25.4 mm R11 K34 AU31 L17 F6
1
Y26 R1101 T36 AW27 L19 E9
100 V34 AW29 J17 D6
1%
1/20W T34 AU27 J19 M6
MF
2 201 P34 AU29 W17 M8
AD36 BC31 W19 K6
Y36 BA31 U17 K8
AD34 BC27 U19 U5
AB34 BC29 R17 V6
Y34 BA27 R19 V8
AK34 BA29 AC17 T6
AH36 C25 AC19 T8
AH34 C23 AA17 P6
AF34 C21 AA19 P8
AR35 G21 AJ17 AD6
AM36 G23 AJ19 AD8
G25 AG17 AB6
AG19 AB8
PAGE TITLE
CPU Power & Ground

DRAWING NUMBER SIZE

REVISION
R
4.4.0
11 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PPVCORE_S0_CPU
CPU VCORE HF AND BULK DECOUPLING
64 11 8
4x 270uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402
LAYOUT NOTE: CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU 1
NOSTUFF
C1200 1
NOSTUFF
C1201 1
NOSTUFF
C1202 1
NOSTUFF
C1203 1
NOSTUFF
C1204 1
NOSTUFF
C1205 1
NOSTUFF
C1206 1
NOSTUFF
C1207 1
NOSTUFF
C1208 1
NOSTUFF
C1209 CPU VCORE VID CONNECTIONS
D 10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
D
6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 65 53 11 IN CPU_VID<0..6> IMVP6_VID<0..6> OUT 65
603 603 603 603 603 603 603 603 603 603 MAKE_BASE=TRUE
OMIT_TABLE NOSTUFF NOSTUFF NOSTUFF OMIT_TABLE NOSTUFF NOSTUFF OMIT_TABLE OMIT_TABLE NOSTUFF
PLACE ON OPPOSITE SIDE OF CPU 1 C1210 1 C1211 1 C1212 1 C1213 1 C1214 1 C1215 1 C1216 1 C1217 1 C1218 1 C1219
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603
NOSTUFF NOSTUFF NOSTUFF OMIT_TABLE NOSTUFF NOSTUFF OMIT_TABLE OMIT_TABLE NOSTUFF NOSTUFF
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603
VCCA (CPU AVdd) DECOUPLING

=PP1V5_S0_CPU 1x 10uF, 1x 0.01uF C
C LAYOUT NOTE: CRITICAL CRITICAL
11 8
OMIT_TABLE NOSTUFF OMIT_TABLE

PLACE ON OPPOSITE SIDE OF CPU 1 C1230 1 C1231 C1280 1 1 C1281 LAYOUT NOTE:
10UF 10UF 10uF 0.01UF
20% 20% 20% 10%
6.3V
2 X5R 6.3V
2 X5R 6.3V 2 2 10V
X5R X5R
603 603 603 201 PLACE C1281 NEAR PIN B34 OF U1000
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
VCCP (CPU I/O) DECOUPLING

11 10 8 =PP1V05_S0_CPU 1x 270uF, 12x 2.2uF
LAYOUT NOTE: CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
PLACE ON OPPOSITE SIDE OF CPU
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE 1 C1283 1 C1284 1 C1285 1 C1286 1 C1287 1 C1288
1 C1250 1 C1251 1 C1252 1 C1253 1 C1254 1 C1255 1 C1256 1 C1257 1 C1258 1 C1259 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
B 20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF B
LAYOUT NOTE: CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE CRITICAL OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
PLACE ON OPPOSITE SIDE OF CPU 1 C1260 1 C1261 1 C1262 1 C1263 1 C1264 1 C1265 1 C1266 1 C1267 C1290 1 1 C1291 1 C1292 1 C1293 1 C1294 1 C1295 1 C1296
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 270UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
TANT 2 2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
2 CERM
402-LF
CASE-B4-SM
LAYOUT NOTE:
PLACE C1290 CLOSE TO CPU
PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS
PLACE C1291-C1296 CLOSE TO FSB DATA PINS
LAYOUT NOTE:
CRITICAL CRITICAL CRITICAL
1 1 1
PLACE ON SAME SIDE AS CPU C1270 C1271 C1272
270UF 270UF 270UF
20% 20% 20%
2V
2 TANT 2V
2 TANT 2V
2 TANT
CASE-B4-SM CASE-B4-SM CASE-B4-SM
PAGE TITLE
CPU Decoupling & VID

DRAWING NUMBER SIZE

REVISION
R
4.4.0
12 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Micro2-XDP Connector
NOTE: This is not the standard XDP pinout.
D Use with 920-0782 Adapter Flex to support chipset debug. D
8 =PP3V3_S0_XDP
8 =PP1V05_S0_XDP
XDP XDP_CONN
R13151 CRITICAL
54.9 J1300
1%
1/20W DF40C-60DS-0.4V
MF F-ST-SM-HF
201 2
1 2
65 10 XDP_BPM_L<5> OBSFN_A0 3 4 OBSFN_C0 JTAG_MCP_TDO 19
BI IN
65 10 XDP_BPM_L<4> OBSFN_A1 5 6 OBSFN_C1 JTAG_MCP_TRST_L 19
BI
7 8
65 10 XDP_BPM_L<3> OBSDATA_A0 9 10 OBSDATA_C0 TP_XDP_OBSDATA_C0
BI
IN
13 14
IN
IN
19 20
C TP_XDP_OBSFN_B0 OBSFN_B0 21 22 OBSFN_D0 JTAG_MCP_TDI 19
C
TP_XDP_OBSFN_B1 OBSFN_B1 23 24 OBSFN_D1 JTAG_MCP_TMS 19
25 26
TP_XDP_OBSDATA_B0 OBSDATA_B0 27 28 OBSDATA_D0 TP_XDP_OBSDATA_D0
31 32
XDP TP_XDP_OBSDATA_B3 35 36 TP_XDP_OBSDATA_D3
OBSDATA_B3 OBSDATA_D3
R1399 37 38
1K 39 40
65 14 10 IN CPU_PWRGD 1 2 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 FSB_CLK_ITP_P IN 14 65
XDP_OBS20 41 42 FSB_CLK_ITP_N XDP
5%
1/20W
HOOK1 ITPCLK#/HOOK5 IN 14 65
MF VCC_OBS_AB 43 44 VCC_OBS_CD R1303
201
45 46 1K
19 IN PM_LATRIGGER_L HOOK2 RESET#/HOOK6 65 XDP_CPURST_L 1 2 FSB_CPURST_L IN 10 14 65
19 JTAG_MCP_TCK HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.
OUT 10 25 1/20W
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF
51 52 201
41 BI =I2C_XDP_SDA SDA TDO XDP_TDO IN 10 65
41 =I2C_XDP_SCL SCL 53 54 TRSTn XDP_TRST_L
BI OUT 10 65
TCK1 55 56 TDI XDP_TDI
NC OUT 10 65
65 10 XDP_TCK TCK0 57 58 TMS XDP_TMS
OUT OUT 10 65
59 60 XDP_PRESENT#
XDP XDP
C1300 1 518S0774
1 C1301
0.1UF 0.1UF
10% 10%
6.3V 2 6.3V
2 X5R
X5R
201 201
B B
Direction of XDP adapter flex

Please place J1300 within 1" of
board edge with odd-numbered pins
facing edge. Avoid any tall
components between J1300 and edge.
PAGE TITLE
eXtended Debug Port (Micro-XDP)

DRAWING NUMBER SIZE

REVISION
R
4.4.0
13 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U1400
MCP89U-A01
BGA
SYMBOL 1 OF 11
65 10 7 FSB_DSTB_L_P<0> J38 CPU_DSTBP0* CPU_D0* M37 FSB_D_L<0> 7 10 65
BI BI
65 10 7 BI FSB_DSTB_L_N<0> J39 CPU_DSTBN0* CPU_D1* M39 FSB_D_L<1> BI 7 10 65
65 10 7 FSB_DINV_L<0> F39 CPU_DBI0* CPU_D2* P39 FSB_D_L<2> 7 10 65

BI BI
CPU_D3* L38 FSB_D_L<3>
FSB_DSTB_L_P<1> R34 CPU_DSTBP1* BI 7 10 65
65 10 7 BI
FSB_DSTB_L_N<1> R35 CPU_DSTBN1* BI 7 10 65
65 10 7 BI
FSB_DINV_L<1> U36 CPU_DBI1* BI 7 10 65
65 10 7 BI
CPU_D6* M40 FSB_D_L<6> 7 10 65
D 65 10 7 BI FSB_DSTB_L_P<2> J37
J36
CPU_DSTBP2* CPU_D7* P40
H40
FSB_D_L<7>
BI
BI 7 10 65 D
65 10 7 BI FSB_DSTB_L_N<2> CPU_DSTBN2* CPU_D8* FSB_D_L<8> BI 7 10 65
65 10 7 FSB_DINV_L<2> L35 CPU_DBI2* CPU_D9* L37 FSB_D_L<9> 7 10 65

BI BI
CPU_D10* F38 FSB_D_L<10>
FSB_DSTB_L_P<3> C37 CPU_DSTBP3*
BI 7 10 65
65 10 7 BI
FSB_DSTB_L_N<3> C38 CPU_DSTBN3* BI 7 10 65
65 10 7 BI
CPU_D12* H38 FSB_D_L<12>
FSB_DINV_L<3> B35 CPU_DBI3* BI 7 10 65
65 10 7 BI
CPU_D13* M38 FSB_D_L<13> 7 10 65
BI
FSB_A_L<3> U38 CPU_A3* BI 7 10 65
65 10 7 BI
CPU_D15* J40 FSB_D_L<15>
FSB_A_L<4> V37 CPU_A4* BI 7 10 65
65 10 7 BI
CPU_D16* U35 FSB_D_L<16>
FSB_A_L<5> Y36 CPU_A5* BI 7 10 65
65 10 7 BI
CPU_D17* R36 FSB_D_L<17>
FSB_A_L<6> V40 CPU_A6* BI 7 10 65
65 10 7 BI
FSB_A_L<7> Y39 CPU_A7* BI 7 10 65
65 10 7 BI
CPU_D19* P35 FSB_D_L<19>
FSB_A_L<8> Y40 CPU_A8* BI 7 10 65
65 10 7 BI
FSB_A_L<9> V39 CPU_A9* BI 7 10 65
65 10 7 BI
FSB_A_L<10> AA39 CPU_A10* BI 7 10 65
65 10 7 BI
CPU_D22* U34 FSB_D_L<22>
FSB_A_L<11> AA36 CPU_A11*
BI 7 10 65
65 10 7 BI
BI 7 10 65
65 10 7 BI
FSB_A_L<13> Y38 CPU_A13*
BI 7 10 65
65 10 7 BI
FSB_A_L<14> AC36 CPU_A14*
BI 7 10 65
65 10 7 BI
BI 7 10 65
65 10 7 BI
AA38
FSB
BI 7 10 65
65 10 7 BI FSB_A_L<16> CPU_A16* P33
AF39 CPU_D28* FSB_D_L<28> BI 7 10 65
65 10 7 BI FSB_A_L<17> CPU_A17* P32
AD38 CPU_D29* FSB_D_L<29> BI 7 10 65
65 10 7 BI FSB_A_L<18> CPU_A18* R32
AC38 CPU_D30* FSB_D_L<30> BI 7 10 65
65 10 7 BI FSB_A_L<19> CPU_A19* R39
AJ38 CPU_D31* FSB_D_L<31> BI 7 10 65
65 10 7 BI FSB_A_L<20> CPU_A20* H36
AD37 CPU_D32* FSB_D_L<32> BI 7 10 65
65 10 7 BI FSB_A_L<21> CPU_A21* F36 FSB_D_L<33>
C 65 10 7 BI FSB_A_L<22>
FSB_A_L<23>
AJ39
AC40
CPU_A22*
CPU_A23*
CPU_D33*
BI
BI
7 10 65
7 10 65
C
65 10 7 BI
CPU_D35* M35 FSB_D_L<35>
FSB_A_L<24> AC37 CPU_A24*
BI 7 10 65
65 10 7 BI
FSB_A_L<25> AD40 CPU_A25*
BI 7 10 65
65 10 7 BI
FSB_A_L<26> AC39 CPU_A26* BI 7 10 65
65 10 7 BI
FSB_A_L<27> AF36 CPU_A27* BI 7 10 65
65 10 7 BI
FSB_A_L<28> AF40 CPU_A28* BI 7 10 65
65 10 7 BI
CPU_D40* J34 FSB_D_L<40>
FSB_A_L<29> AG39 CPU_A29* BI 7 10 65
65 10 7 BI
FSB_A_L<30> AD39 CPU_A30* BI 7 10 65
65 10 7 BI
FSB_A_L<31> AD36 CPU_A31*
BI 7 10 65
65 10 7 BI
FSB_A_L<32> AF37 CPU_A32*
BI 7 10 65
65 10 7 BI
FSB_A_L<33> AJ40 CPU_A33*
BI 7 10 65
65 10 7 BI
FSB_A_L<34> AG40 CPU_A34*
BI 7 10 65
65 10 7 BI
FSB_A_L<35> AG38 CPU_A35*
BI 7 10 65
65 10 7 BI
CPU_D47* J35 FSB_D_L<47> BI 7 10 65
65 10 7 FSB_ADSTB_L<0> Y37 CPU_ADSTB0* CPU_D48* D39 FSB_D_L<48> 7 10 65

BI BI
65 10 7 FSB_ADSTB_L<1> AF38 CPU_ADSTB1* CPU_D49* E36 FSB_D_L<49> 7 10 65
BI BI
CPU_D50* D40 FSB_D_L<50> 7 10 65
BI
65 10 7 FSB_REQ_L<0> U40 CPU_REQ0* CPU_D51* E40 FSB_D_L<51> 7 10 65
BI BI
65 10 7 BI FSB_REQ_L<1> U39 CPU_REQ1* CPU_D52* C39 FSB_D_L<52> BI 7 10 65
65 10 7 BI FSB_REQ_L<2> V38 CPU_REQ2* CPU_D53* E38 FSB_D_L<53> BI 7 10 65
65 10 7 BI FSB_REQ_L<3> U37 CPU_REQ3* CPU_D54* A37 FSB_D_L<54> BI 7 10 65
65 10 7 FSB_REQ_L<4> V36 CPU_REQ4* CPU_D55* C36 FSB_D_L<55> 7 10 65

BI BI
CPU_D56* B38 FSB_D_L<56> 7 10 65
BI
65 10 7 FSB_ADS_L AG33 CPU_ADS* CPU_D57* E37 FSB_D_L<57> 7 10 65
IN BI
65 10 IN FSB_BNR_L AD35 CPU_BNR* CPU_D58* C35 FSB_D_L<58> BI 7 10 65
65 10 FSB_BREQ0_L AG34 CPU_BR0* CPU_D59* A35 FSB_D_L<59> 7 10 65
B 65 10
IN
IN FSB_DBSY_L AF35
U32
CPU_DBSY* CPU_D60* B37
D36
FSB_D_L<60>
BI
BI 7 10 65 B
65 10 IN FSB_DRDY_L CPU_DRDY* CPU_D61* FSB_D_L<61> BI 7 10 65
23 20 14 8 =PP1V05_S0_MCP_FSB AD34 A36
65 10 7 IN FSB_HIT_L CPU_HIT* CPU_D62* FSB_D_L<62> BI 7 10 65
65 10 7 FSB_HITM_L AD32 CPU_HITM* CPU_D63* D38 FSB_D_L<63> 7 10 65

IN BI
65 10 7 FSB_LOCK_L AG37 CPU_LOCK*
1 1 IN
R1410 R1415 65 10 BI FSB_TRDY_L AG32 CPU_TRDY* CPU_BPRI* AF32 FSB_BPRI_L OUT 10 65
54.9 62 AG35 FSB_DEFER_L
1% 5% CPU_DEFER* OUT 10 65
1/20W 1/20W AG36
MF MF 9 OUT CPU_PECI_MCP CPU_PECI
201 2 2 201 V32
65 39 10 OUT CPU_PROCHOT_L CPU_PROCHOT* AJ37
V35 BCLK_OUT_CPU_P FSB_CLK_CPU_P OUT 10 65
65 39 10 IN PM_THRMTRIP_L CPU_THERMTRIP* AJ36
AC33 BCLK_OUT_CPU_N FSB_CLK_CPU_N OUT 10 65
65 10 IN CPU_FERR_L CPU_FERR*
BCLK_OUT_ITP_P AK32 FSB_CLK_ITP_P 13 65
OUT
9 =MCP_BSEL<2> D35 CPU_BSEL2 BCLK_OUT_ITP_N AK33 FSB_CLK_ITP_N 13 65
IN OUT
=MCP_BSEL<1> E35 CPU_BSEL1
9 IN
BCLK_OUT_NB_P AJ35 65 FSB_CLK_MCP_P
=MCP_BSEL<0> F35 CPU_BSEL0
9 IN
BCLK_OUT_NB_N AJ34 65 FSB_CLK_MCP_N
65 10 FSB_RS_L<0> AF33 CPU_RS0* Loop-back clock for delay matching.
OUT
65 10 OUT FSB_RS_L<1> AD33 CPU_RS1* BCLK_IN_N AJ32
R14301 1
R1435 65 10 OUT FSB_RS_L<2> AF34 CPU_RS2* BCLK_IN_P AJ33
49.9 49.9
1% 1%
1/20W 1/20W
MF MF AA33 =PP1V05_S0_MCP_FSB 8 14 20 23
201 2 2 201 CPU_A20M* CPU_A20M_L OUT 10 65
V33 CPU_IGNNE_L NO STUFF
AK39 CPU_IGNNE* OUT 10 65
65 MCP_BCLK_VML_COMP_VDD BCLK_VML_COMP_VDD Y33
1
R1440
AK40 CPU_INIT* CPU_INIT_L OUT 10 65
65 MCP_BCLK_VML_COMP_GND BCLK_VML_COMP_GND Y35 150
CPU_INTR CPU_INTR OUT 10 65 5%
CPU_NMI AA35 CPU_NMI 1/20W
MF
MCP_CPU_COMP_VCC AK38 OUT 10 65
A 65
65 MCP_CPU_COMP_GND AK37
CPU_COMP_VCC
CPU_COMP_GND
CPU_SMI*
CPU_PWRGD
AC35
AA32
CPU_SMI_L
CPU_PWRGD
OUT 10 65
2 201
10 13 65
OUT PAGE TITLE
AC34 FSB_CPURST_L
R1431 1 1
R1436
CPU_RESET*
CPU_DPRSLPVR D2 PM_DPRSLPVR
OUT
OUT
10 13 65
53 65
MCP CPU Interface
49.9 49.9 V34 DRAWING NUMBER SIZE
1% 1% CPU_SLP* FSB_CPUSLP_L
1/20W
MF
1/20W
MF CPU_DPSLP* Y32 CPU_DPSLP_L
OUT 10 65
10 65 Apple Inc. 051-8379 D

OUT
201 2 2 201 U33 REVISION
CPU_DPWR* FSB_DPWR_L 10 65 R
CPU_STPCLK* Y34 CPU_STPCLK_L

OUT
10 65
4.4.0
OUT
AA34 CPU_DPRSTP_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
CPU_DPRSTP* OUT 10 53 65
14 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1400
MCP89U-A01
U1400
MCP89U-A01
BGA BGA
SYMBOL 2 OF 11 SYMBOL 3 OF 11
66 27 MEM_A_DQ<63> AN6 MDQ0_63 MDQS0_7_P AR4 MEM_A_DQS_P<7> 27 66 66 29 MEM_B_DQ<63> AM1 MDQ1_63 MDQS1_7_P AN2 MEM_B_DQS_P<7> 29 66
BI BI BI BI
66 27 MEM_A_DQ<62> AN4 MDQ0_62 MDQS0_7_N AR5 MEM_A_DQS_N<7> 27 66 66 29 MEM_B_DQ<62> AN1 MDQ1_62 MDQS1_7_N AN3 MEM_B_DQS_N<7> 29 66
BI BI BI BI
66 27 MEM_A_DQ<61> AT4 MDQ0_61 MDQS0_6_P AT6 MEM_A_DQS_P<6> 27 66 66 29 MEM_B_DQ<61> AT1 MDQ1_61 MDQS1_6_P AY5 MEM_B_DQS_P<6> 29 66
BI BI BI BI
66 27 BI MEM_A_DQ<60> AU3 MDQ0_60 MDQS0_6_N AU6 MEM_A_DQS_N<6> BI 27 66 66 29 BI MEM_B_DQ<60> AU1 MDQ1_60 MDQS1_6_N AY4 MEM_B_DQS_N<6> BI 29 66
AM7 AN11 AM3 AV11
D 66 27
66 27
BI
BI
MEM_A_DQ<59>
MEM_A_DQ<58> AN7
MDQ0_59
MDQ0_58
MDQS0_5_P
MDQS0_5_N AM11
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
BI
BI
27 66
27 66
66 29
66 29
BI
BI
MEM_B_DQ<59>
MEM_B_DQ<58> AM2
MDQ1_59
MDQ1_58
MDQS1_5_P
MDQS1_5_N AW11
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
BI
BI
29 66
29 66
D
66 27 MEM_A_DQ<57> AT5 MDQ0_57 MDQS0_4_P AT12 MEM_A_DQS_P<4> 27 66 66 29 MEM_B_DQ<57> AR2 MDQ1_57 MDQS1_4_P AV14 MEM_B_DQS_P<4> 29 66
BI BI BI BI
AT3 AR12 AR1 AW14
MEMORY PARTITION 0
66 27 BI MEM_A_DQ<56> MDQ0_56 MDQS0_4_N MEM_A_DQS_N<4> BI 27 66 66 29 BI MEM_B_DQ<56> MDQ1_56 MDQS1_4_N MEM_B_DQS_N<4> BI 29 66
66 27 MEM_A_DQ<55> AU5 MDQ0_55 MDQS0_3_P AR29 MEM_A_DQS_P<3> 26 66 66 29 MEM_B_DQ<55> AW3 MDQ1_55 MDQS1_3_P AW27 MEM_B_DQS_P<3> 28 66
BI BI BI BI
66 27 MEM_A_DQ<54> AV5 MDQ0_54 MDQS0_3_N AP29 MEM_A_DQS_N<3> 26 66 66 29 MEM_B_DQ<54> AW4 MDQ1_54 MDQS1_3_N AY27 MEM_B_DQS_N<3> 28 66
BI BI BI BI
66 27 BI MEM_A_DQ<53> AR6 MDQ0_53 MDQS0_2_P AR32 MEM_A_DQS_P<2> BI 26 66 66 29 BI MEM_B_DQ<53> AU8 MDQ1_53 MDQS1_2_P AV32 MEM_B_DQS_P<2> BI 28 66
66 27 BI MEM_A_DQ<52> AN9 MDQ0_52 MDQS0_2_N AP32 MEM_A_DQS_N<2> BI 26 66 66 29 BI MEM_B_DQ<52> AV8 MDQ1_52 MDQS1_2_N AW32 MEM_B_DQS_N<2> BI 28 66
66 27 BI MEM_A_DQ<51> AV3 MDQ0_51 MDQS0_1_P AV36 MEM_A_DQS_P<1> BI 26 66 66 29 BI MEM_B_DQ<51> AU2 MDQ1_51 MDQS1_1_P AY37 MEM_B_DQS_P<1> BI 28 66
66 27 BI MEM_A_DQ<50> AV4 MDQ0_50 MDQS0_1_N AU36 MEM_A_DQS_N<1> BI 26 66 66 29 BI MEM_B_DQ<50> AV2 MDQ1_50 MDQS1_1_N AY36 MEM_B_DQS_N<1> BI 28 66
66 27 MEM_A_DQ<49> AM8 MDQ0_49 MDQS0_0_P AN35 MEM_A_DQS_P<0> 26 66 66 29 MEM_B_DQ<49> AW6 MDQ1_49 MDQS1_0_P AN38 MEM_B_DQS_P<0> 28 66
BI BI BI BI
66 27 BI MEM_A_DQ<48> AN8 MDQ0_48 MDQS0_0_N AN34 MEM_A_DQS_N<0> BI 26 66 66 29 BI MEM_B_DQ<48> AV6 MDQ1_48 MDQS1_0_N AN39 MEM_B_DQS_N<0> BI 28 66
66 27 MEM_A_DQ<47> AP8 MDQ0_47 66 29 MEM_B_DQ<47> AY9 MDQ1_47

BI BI
MEMORY PARITION 1
MEM_A_DQ<46> AP9 MDQ0_46 MEM_B_DQ<46> AW9 MDQ1_46
66 27 BI
MRAS0* AR17 MEM_A_RAS_L 66 29 BI
MRAS1* AW18 MEM_B_RAS_L
MEM_A_DQ<45> AN12 MDQ0_45 OUT 26 27 32 66
MEM_B_DQ<45> AY11 MDQ1_45
OUT 28 29 32 66
66 27 BI
MCAS0* AM17 MEM_A_CAS_L 66 29 BI
MCAS1* AV17 MEM_B_CAS_L
MEM_A_DQ<44> AT11 MDQ0_44 OUT 26 27 32 66
OUT 28 29 32 66
66 27 BI
MWE0* AM18 MEM_A_WE_L 66 29 BI
MWE1* AY18 MEM_B_WE_L
66 27 MEM_A_DQ<43> AT8 MDQ0_43 OUT 26 27 32 66
66 29 MEM_B_DQ<43> AW8 MDQ1_43
OUT 28 29 32 66
BI BI
66 27 BI MEM_A_DQ<42> AR8 MDQ0_42 66 29 BI MEM_B_DQ<42> AY8 MDQ1_42
66 27 BI MEM_A_DQ<41> AT9 MDQ0_41 MBA0_2 AR26 MEM_A_BA<2> OUT 26 27 32 66 66 29 BI MEM_B_DQ<41> AU9 MDQ1_41 MBA1_2 AW24 MEM_B_BA<2> OUT 28 29 32 66
66 27 BI MEM_A_DQ<40> AM12 MDQ0_40 MBA0_1 AR18 MEM_A_BA<1> OUT 26 27 32 66 66 29 BI MEM_B_DQ<40> AU11 MDQ1_40 MBA1_1 AT18 MEM_B_BA<1> OUT 28 29 32 66
66 27 MEM_A_DQ<39> AP12 MDQ0_39 MBA0_0 AP17 MEM_A_BA<0> 26 27 32 66 66 29 MEM_B_DQ<39> AU12 MDQ1_39 MBA1_0 AV18 MEM_B_BA<0> 28 29 32 66
BI OUT BI OUT
66 27 MEM_A_DQ<38> AN14 MDQ0_38 66 29 MEM_B_DQ<38> AU14 MDQ1_38
BI BI
MEM_A_DQ<37> AT14 MDQ0_37 MEM_B_DQ<37> AV15 MDQ1_37
66 27 BI
MA0_15 AN26 MEM_A_A<15> 66 29 BI
MA1_15 AU24 MEM_B_A<15>
MEM_A_DQ<36> AR14 MDQ0_36 OUT 9 66
MEM_B_DQ<36> AU15 MDQ1_36
OUT 9 66
66 27 BI
MA0_14 AP26 MEM_A_A<14> 66 29 BI
MA1_14 AV24 MEM_B_A<14>
MEM_A_DQ<35> AR11 MDQ0_35 OUT 26 27 32 66
MEM_B_DQ<35> AW12 MDQ1_35
OUT 28 29 32 66
66 27 BI
MA0_13 AR15 MEM_A_A<13> 66 29 BI
MA1_13 AU17 MEM_B_A<13>
MEM_A_DQ<34> AP11 MDQ0_34 OUT 26 27 32 66
MEM_B_DQ<34> AV12 MDQ1_34
OUT 28 29 32 66
66 27 BI
MA0_12 AR24 MEM_A_A<12> 66 29 BI
MA1_12 AY24 MEM_B_A<12>
MEM_A_DQ<33> AM15 MDQ0_33 OUT 26 27 32 66
OUT 28 29 32 66
66 27 BI AP23 MEM_A_A<11> 66 29 BI AW23 MEM_B_A<11>
C 66 27 BI MEM_A_DQ<32>
MEM_A_DQ<31>
AN15
AR27
MDQ0_32
MDQ0_31
MA0_11
MA0_10 AP18 MEM_A_A<10>
OUT
OUT
26 27 32 66
26 27 32 66
66 29 BI MEM_B_DQ<32>
MEM_B_DQ<31>
AW15
AW26
MDQ1_32
MDQ1_31
MA1_11
MA1_10 AU18 MEM_B_A<10>
OUT
OUT
28 29 32 66
28 29 32 66
C
66 26 BI
MA0_9 AP24 MEM_A_A<9> 66 28 BI
MA1_9 AY23 MEM_B_A<9>
MEM_A_DQ<30> AT27 MDQ0_30 OUT 26 27 32 66
OUT 28 29 32 66
66 26 BI
MA0_8 AN24 MEM_A_A<8> 66 28 BI
MA1_8 AU23 MEM_B_A<8>
MEM_A_DQ<29> AM30 MDQ0_29 OUT 26 27 32 66
OUT 28 29 32 66
66 26 BI
MA0_7 AR23 MEM_A_A<7> 66 28 BI
MA1_7 AV23 MEM_B_A<7>
MEM_A_DQ<28> AN30 MDQ0_28 OUT 26 27 32 66
MEM_B_DQ<28> AW29 MDQ1_28 OUT 28 29 32 66
66 26 BI
MA0_6 AM23 MEM_A_A<6> 66 28 BI
MA1_6 AT21 MEM_B_A<6>
MEM_A_DQ<27> AN27 MDQ0_27 OUT 26 27 32 66
OUT 28 29 32 66
66 26 BI
MA0_5 AM24 MEM_A_A<5> 66 28 BI
MA1_5 AT23 MEM_B_A<5>
MEM_A_DQ<26> AP27 MDQ0_26 OUT 26 27 32 66
OUT 28 29 32 66
66 26 BI
MA0_4 AN23 MEM_A_A<4> 66 28 BI
MA1_4 AU21 MEM_B_A<4>
MEM_A_DQ<25> AN29 MDQ0_25 OUT 26 27 32 66
OUT 28 29 32 66
66 26 BI
MA0_3 AR21 MEM_A_A<3> 66 28 BI
MA1_3 AV21 MEM_B_A<3>
MEM_A_DQ<24> AM29 MDQ0_24 OUT 26 27 32 66
MEM_B_DQ<24> AU29 MDQ1_24 OUT 28 29 32 66
66 26 BI
MA0_2 AP20 MEM_A_A<2> 66 28 BI
MEM_A_DQ<23> AT30 MDQ0_23 OUT 26 27 32 66
MEM_B_DQ<23> AW30 MDQ1_23
OUT 28 29 32 66
66 26 BI
MA0_1 AP21 MEM_A_A<1> 66 28 BI
MA1_1 AW21 MEM_B_A<1>
MEM_A_DQ<22> AT32 MDQ0_22 OUT 26 27 32 66
OUT 28 29 32 66
66 26 BI
MA0_0 AR20 MEM_A_A<0> 66 28 BI
66 26 MEM_A_DQ<21> AP33 MDQ0_21 OUT 26 27 32 66
66 28 MEM_B_DQ<21> AY33 MDQ1_21
OUT 28 29 32 66
BI BI
66 26 BI MEM_A_DQ<20> AR33 MDQ0_20 =PP1V05_S0_MCP_M2CLK_DLL 8 23 66 28 BI MEM_B_DQ<20> AW33 MDQ1_20
66 26 MEM_A_DQ<19> AP30 MDQ0_19 +VIO_M2CLK_DLL AJ30 550 mA 66 28 MEM_B_DQ<19> AY29 MDQ1_19
BI BI
66 26 MEM_A_DQ<18> AR30 MDQ0_18 +VIO_M2CLK_DLL AK30 66 28 MEM_B_DQ<18> AY30 MDQ1_18
BI BI
66 26 MEM_A_DQ<17> AM33 MDQ0_17 +VIO_M2CLK_DLL AK31 66 28 MEM_B_DQ<17> AU32 MDQ1_17
BI BI
66 26 MEM_A_DQ<16> AN33 MDQ0_16 PP1V05_S0_MCP_PLL_FSBMEM 23 66 28 MEM_B_DQ<16> AY32 MDQ1_16
BI BI
66 26 MEM_A_DQ<15> AU35 MDQ0_15 +VIO_PLL_MEM AH29 20 mA 70 mA 66 28 MEM_B_DQ<15> AW35 MDQ1_15
BI BI
66 26 MEM_A_DQ<14> AV35 MDQ0_14 +VIO_PLL_MEM AH30 66 28 MEM_B_DQ<14> AY35 MDQ1_14
BI BI
66 26 MEM_A_DQ<13> AT37 MDQ0_13 +VIO_PLL_MEM AJ31 66 28 MEM_B_DQ<13> AV39 MDQ1_13
BI BI =PP1V5R1V35_S3_MCP_MEM
66 26 MEM_A_DQ<12> AT38 MDQ0_12 25 mA 66 28 MEM_B_DQ<12> AU39 MDQ1_12
8
BI BI
66 26 MEM_A_DQ<11> AT33 MDQ0_11 +VIO_PLL_FSB AF29 66 28 MEM_B_DQ<11> AV33 MDQ1_11
BI BI 1
66 26 BI MEM_A_DQ<10> AT35 MDQ0_10 +VIO_PLL_FSB AF30 66 28 BI MEM_B_DQ<10> AU33 MDQ1_10 R1520
AV37 AF31 25 mA AW38 1K
66 26 BI MEM_A_DQ<9> MDQ0_9 +VIO_PLL_FSB 66 28 BI MEM_B_DQ<9> MDQ1_9 5%
AU38 AV38 1/20W
66 26 BI MEM_A_DQ<8> MDQ0_8 66 28 BI MEM_B_DQ<8> MDQ1_8 MF
66 26 MEM_A_DQ<7> AR35 MDQ0_7 +VIO_PLL_CPU AG29 66 28 MEM_B_DQ<7> AR40 MDQ1_7 2 201
BI BI
AN36 AG30 AR39 AM6
B 66 26
66 26
BI
BI
MEM_A_DQ<6>
MEM_A_DQ<5> AM35
MDQ0_6
MDQ0_5
+VIO_PLL_CPU
+VIO_PLL_CPU AG31
66 28
66 28
BI
BI
MEM_B_DQ<6>
MEM_B_DQ<5> AM39
MDQ1_6
MDQ1_5
MRESET0* MEM_RESET_L OUT 26 27 28 29
B
66 26 BI MEM_A_DQ<4> AM34 MDQ0_4 66 28 BI MEM_B_DQ<4> AM38 MDQ1_4 MCLK1A_1_P AV20 MEM_B_CLK_P<1> OUT 9 66
MEM_A_DQ<3> AR36 MDQ0_3 MEM_B_DQ<3> AT40 MDQ1_3 MCLK1A_1_N AW20 MEM_B_CLK_N<1>

66 26 BI
MCLK0A_1_P AM21 MEM_A_CLK_P<1> 66 28 BI OUT 9 66
MEM_A_DQ<2> AR37 MDQ0_2 OUT 9 66

66 26 BI
MCLK0A_1_N AN21 MEM_A_CLK_N<1> 66 28 BI
66 26 MEM_A_DQ<1> AM36 MDQ0_1 OUT 9 66
66 28 MEM_B_DQ<1> AN40 MDQ1_1 MCLK1A_0_P AT20 MEM_B_CLK_P<0> 28 29 32 66
BI BI OUT
MEM_A_DQ<0> AM37 MDQ0_0 MEM_B_DQ<0> AM40 MDQ1_0 MCLK1A_0_N AU20 MEM_B_CLK_N<0>
66 26 BI
MCLK0A_0_P AM20 MEM_A_CLK_P<0> 26 27 32 66
66 28 BI OUT 28 29 32 66
OUT
MEM_A_DM<7> AN5 MDQM0_7 MCLK0A_0_N AN20 MEM_A_CLK_N<0> MEM_B_DM<7> AR3 MDQM1_7
66 27 OUT OUT 26 27 32 66 66 29 OUT
MCS1A_1* AT15 MEM_B_CS_L<1>
MEM_A_DM<6> AM9 MDQM0_6 MEM_B_DM<6> AY6 MDQM1_6
OUT 28 29 32 66
66 27 OUT 66 29 OUT
MCS1A_0* AY17 MEM_B_CS_L<0>
66 27 OUT MEM_A_DM<5> AR9 MDQM0_5 MCS0A_1* AP15 MEM_A_CS_L<1> OUT 26 27 32 66 66 29 OUT MEM_B_DM<5> AV9 MDQM1_5 OUT 28 29 32 66
MEM_A_DM<4> AM14 MDQM0_4 MCS0A_0* AN18 MEM_A_CS_L<0> =PP1V5R1V35_SW_MCP_MEM MEM_B_DM<4> AY14 MDQM1_4
66 27 OUT OUT 26 27 32 66 23 21 20 66 29 OUT
MODT1A_1 AT17 MEM_B_ODT<1>
MEM_A_DM<3> AT29 MDQM0_3 MEM_B_DM<3> AV27 MDQM1_3 OUT 28 29 32 66
66 26 OUT 66 28 OUT
MODT1A_0 AW17 MEM_B_ODT<0>
MEM_A_DM<2> AN32 AP14 MEM_A_ODT<1> MEM_B_DM<2> AU30 OUT 28 29 32 66
66 26 OUT
AT36
MDQM0_2 MODT0A_1
AN17
OUT 26 27 32 66 R15101 66 28 OUT
AW37
MDQM1_2
66 26 OUT MEM_A_DM<1> MDQM0_1 MODT0A_0 MEM_A_ODT<0> OUT 26 27 32 66 40.2 66 28 OUT MEM_B_DM<1> MDQM1_1 AT24
AN37 1% AR38 MCKE1A_1 MEM_B_CKE<1> OUT 21 28 29 32 66
66 26 OUT MEM_A_DM<0> MDQM0_0 1/20W 66 28 OUT MEM_B_DM<0> MDQM1_0 AT26
AM27 MF MCKE1A_0 MEM_B_CKE<0> OUT 21 28 29 32 66
MCKE0A_1 MEM_A_CKE<1> OUT 21 26 27 32 66 201 2
MCKE0A_0 AM26 MEM_A_CKE<0> 21 26 27 32 66 66 AL23 MEM_COMP_GND
MCP_MEM_COMP_GND
OUT
66 AL24 MEM_COMP_VDD
MCP_MEM_COMP_VDD
R15111
40.2
1%
1/20W
MF
201 2
PAGE TITLE
MCP Memory Interface

DRAWING NUMBER SIZE

REVISION
R
4.4.0
15 OF 110
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used. IV ALL RIGHTS RESERVED 15 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U1400
MCP89U-A01
BGA
SYMBOL 4 OF 11
9 IN PEG_CLKREQ_L V1 PEA_CLKREQ*/GPIO_49 PE0_REFCLK_P V5 PEG_CLK100M_P OUT 9 67
PE0_REFCLK_N V4 PEG_CLK100M_N OUT 9 67

U1
D 34 IN AP_CLKREQ_L PEB_CLKREQ*/GPIO_50
PE1_REFCLK_P V2
V3
PCIE_CLK100M_AP_P OUT 7 34 67 D
U4 PE1_REFCLK_N PCIE_CLK100M_AP_N OUT 7 34 67
9 IN ENET_CLKREQ_L PEC_CLKREQ*/GPIO_51
PE2_REFCLK_P U3 TP_PCIE_CLK100M_PE2P
PCIE_WAKE_L U7 U2 TP_PCIE_CLK100M_PE2N PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1
34 7 IN PE_WAKE* PE2_REFCLK_N
PE1 ports are Gen1-only. 2 RCs: x1, x1
PCI EXPRESS
9 IN =PEG_D2R_P<4> Y4 PE0_RX4_P PE0_TX4_P Y3 =PEG_R2D_C_P<4> OUT 9
9 IN =PEG_D2R_N<4> Y5 PE0_RX4_N PE0_TX4_N Y2 =PEG_R2D_C_N<4> OUT 9
9 =PEG_D2R_P<5> AA9 PE0_RX5_P PE0_TX5_P AA7 =PEG_R2D_C_P<5> 9 If PE0[3:0] are not used,
IN OUT
9 =PEG_D2R_N<5> AA8 PE0_RX5_N PE0_TX5_N AA6 =PEG_R2D_C_N<5> 9 +VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND
IN OUT
67 34 7 IN PCIE_AP_D2R_P AA4 PE1_RX0_P PE1_TX0_P AA2 PCIE_AP_R2D_C_P OUT 34 67
67 34 7 IN PCIE_AP_D2R_N AA5 PE1_RX0_N PE1_TX0_N AA3 PCIE_AP_R2D_C_N OUT 34 67

If PE0[4:5] and PE1[0:1] are not used,
TP_PCIE_PE1_D2RP Y7 PE1_RX1_P PE1_TX1_P Y8 TP_PCIE_PE4_R2D_CP +VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND
TP_PCIE_PE1_D2RN Y6 PE1_RX1_N PE1_TX1_N Y9 TP_PCIE_PE4_R2D_CN
23 PP3V3_S0_MCP_PLL_HVDD
W10 +3.3V_PLL_HVDD PEX_RST* U6 PCIE_RESET_L OUT 25
PP1V05_S0_MCP_PLL_PEXSATA AG10 1
23
AG11
+VIO_PLL_PE R1600
+VIO_PLL_PE 22K
AG12 5%
+VIO_PLL_PE 1/20W
MF
2 201
AH10 +VIO_PLL_XREF_XS
C AE10
AE11
+VIO_PLL_SATA
+VIO_PLL_SATA
C
AF12 +VIO_PLL_SATA
AF10 +VIO_PLL_H
AF11 +VIO_PLL_H PEX0_TERM_P U5 67 MCP_PEX0_TERMP
R16101
2.49K
1%
1/20W
MF
201 2
PLACE_NEAR=U1400.U5:12.7 mm
B B
PAGE TITLE
MCP PCIe Interfaces

DRAWING NUMBER SIZE

REVISION
R
4.4.0
16 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U1400
MCP89U-A01 D
D BGA
SYMBOL 5 OF 11
PP3V3_S0_MCP_DAC
RGB
24
140 mA K30 +3.3V_RGBDAC DDC_CLK0/GPIO_38 G30 AUD_IP_PERIPHERAL_DET 7 17 37

IN
F30 MIKEY_MIC_LOAD_DET RGB DAC Disable:
DDC_DATA0/GPIO_39 IN 17
9 TP_MCP_RGB_DAC_VREF J29 RGB_DAC_VREF Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).
Connect +3.3V_RGBDAC pin to GND.
NOTE: No Composite/S-Video/Component Video support on MCP89
67 9 DP_IG_ML0_P<3> H27 DP0_3_P/TMDS0_TXC_P IFPA_TXC_P K24 =MCP_IFPA_TXC_P 9
OUT OUT
DP_IG_ML0_N<3> J27 K23 =MCP_IFPA_TXC_N Interface Mode
67 9 OUT DP0_3_N/TMDS0_TXC_N IFPA_TXC_N OUT 9
DP_IG_ML0_P<2> D26 B23 =MCP_IFPA_TXD_P<0> MCP Signal TMDS/HDMI LVDS

67 9 OUT DP0_2_P/TMDS0_TX0_P IFPA_TXD0_P OUT 9
67 9 DP_IG_ML0_N<2> C26 DP0_2_N/TMDS0_TX0_N IFPA_TXD0_N C23 =MCP_IFPA_TXD_N<0> 9 =MCP_IFPA_TXC_P/N TMDS_IG_TXC_P/N LVDS_IG_A_CLK_P/N

OUT OUT
=MCP_IFPA_TXD_P/N<0> TMDS_IG_TXD_P/N<0> LVDS_IG_A_DATA_P/N<0>
FLAT PANEL
67 9 DP_IG_ML0_P<1> F26 DP0_1_P/TMDS0_TX1_P IFPA_TXD1_P D23 =MCP_IFPA_TXD_P<1> 9
OUT OUT
DP_IG_ML0_N<1> E26 E23 =MCP_IFPA_TXD_N<1> =MCP_IFPA_TXD_P/N<1> TMDS_IG_TXD_P/N<1> LVDS_IG_A_DATA_P/N<1>
67 9 OUT DP0_1_N/TMDS0_TX1_N IFPA_TXD1_N OUT 9
=MCP_IFPA_TXD_P/N<2> TMDS_IG_TXD_P/N<2> LVDS_IG_A_DATA_P/N<2>
67 9 OUT DP_IG_ML0_P<0> H26 DP0_0_P/TMDS0_TX2_P IFPA_TXD2_P F23 =MCP_IFPA_TXD_P<2> OUT 9 =MCP_IFPA_TXD_P/N<3> (UNUSED) LVDS_IG_A_DATA_P/N<3>
67 9 DP_IG_ML0_N<0> G26 DP0_0_N/TMDS0_TX2_N IFPA_TXD2_N G23 =MCP_IFPA_TXD_N<2> 9 =MCP_IFPB_TXC_P/N (UNUSED) LVDS_IG_B_CLK_P/N
OUT OUT
H23 =MCP_IFPA_TXD_P<3> =MCP_IFPB_TXD_P/N<0> TMDS_IG_TXD_P/N<3> LVDS_IG_B_DATA_P/N<0>
F27 IFPA_TXD3_P OUT 9
9 OUT DP_IG_ML1_P<3> DP1_3_P/TMDS0B_TXC_P J23 =MCP_IFPB_TXD_P/N<1> TMDS_IG_TXD_P/N<4> LVDS_IG_B_DATA_P/N<1>
G27 IFPA_TXD3_N =MCP_IFPA_TXD_N<3> OUT 9
9 OUT DP_IG_ML1_N<3> DP1_3_N/TMDS0B_TXC_N =MCP_IFPB_TXD_P/N<2> TMDS_IG_TXD_P/N<5> LVDS_IG_B_DATA_P/N<2>
DP_IG_ML1_P<2> E27 J24 =MCP_IFPB_TXC_P =MCP_IFPB_TXD_P/N<3> (UNUSED) LVDS_IG_B_DATA_P/N<3>
9 OUT DP1_2_P/TMDS0_TX3_P IFPB_TXC_P OUT 9
DP_IG_ML1_N<2> D27 H24 =MCP_IFPB_TXC_N =MCP_IFPAB_DDC_CLK TMDS_IG_DDC_CLK LVDS_IG_DDC_CLK

9 OUT DP1_2_N/TMDS0_TX3_N IFPB_TXC_N OUT 9
=MCP_IFPAB_DDC_DATA TMDS_IG_DDC_DATA LVDS_IG_DDC_DATA
DP_IG_ML1_P<1> C27 G24 =MCP_IFPB_TXD_P<0>
C 67 9
67 9
OUT
OUT DP_IG_ML1_N<1> B27
DP1_1_P/TMDS0_TX4_P
DP1_1_N/TMDS0_TX4_N
IFPB_TXD4_P
IFPB_TXD4_N F24 =MCP_IFPB_TXD_N<0>
OUT
OUT
9
9 LVDS: Power +VDD_IFPx at 1.8V C

DP_IG_ML1_P<0> A29 E24 =MCP_IFPB_TXD_P<1> TMDS: Power +VDD_IFPx at 3.3V
67 9 OUT DP1_0_P/TMDS0_TX5_P IFPB_TXD5_P OUT 9
67 9 DP_IG_ML1_N<0> B29 DP1_0_N/TMDS0_TX5_N IFPB_TXD5_N D24 =MCP_IFPB_TXD_N<1> 9

OUT OUT
IFPB_TXD6_P C24 =MCP_IFPB_TXD_P<2> 9

OUT
IFPB_TXD6_N B24 =MCP_IFPB_TXD_N<2>
NOTE: 100K pull-downs required if 9 DP_IG_HPD0 C29 HPLUG_DET0/GPIO_20 OUT 9
IN
HPLUG_DET0/HPLUG_DET1 are not used. 9 DP_IG_HPD1 D30 HPLUG_DET1/GPIO_21 IFPB_TXD7_P J26 =MCP_IFPB_TXD_P<3> 9
IN OUT
17 SATARDRVR_A_EN E30 HPLUG_DET2/GPIO_22 IFPB_TXD7_N K26 =MCP_IFPB_TXD_N<3> 9
OUT OUT
67 17 9 DP_IG_AUX_CH0_P E29 DDC_CLK2/DP_AUX_CH0_P DDC_CLK1/GPIO_40 J30 =MCP_IFPAB_DDC_CLK 9

BI OUT
67 17 9 DP_IG_AUX_CH0_N D29 DDC_DATA2/DP_AUX_CH0_N DDC_DATA1/GPIO_41 H30 =MCP_IFPAB_DDC_DATA 9
BI BI
67 17 9 DP_IG_AUX_CH1_P G29 DDC_CLK3/DP_AUX_CH1_P

BI
67 17 9 DP_IG_AUX_CH1_N F29 DDC_DATA3/DP_AUX_CH1_N
BI
23 PP3V3_S0_MCP_PLL_DP_USB (GMUX_INT)
210 mA 180 mA L23 +3.3V_PLL_DP0 LCD_BKL_CTL/GPIO_57 B30 LCD_IG_BKLT_PWM 9
OUT
M23 +3.3V_PLL_DP0 LCD_BKL_ON/GPIO_59 C30 LCD_IG_BKLT_EN OUT 9
LCD_PANEL_PWR/GPIO_58 A30 LCD_IG_PWR_EN 9 59

OUT
30 mA L22 +3.3V_PLL_USB
M22 +3.3V_PLL_USB
24 =PP1V05_S0_MCP_PLL_IFP
60 mA L25 +VIO_PLL_IFPAB
M25 +VIO_PLL_IFPAB
23 PP1V05_S0_MCP_PLL_CORE L26 +VIO_PLL_CORE_LEG

M26
B 160 mA 40 mA
L27
+VIO_PLL_CORE_LEG
B
+VIO_PLL_SPPLL0
60 mA M27 +VIO_PLL_SPPLL0
L28 +VIO_PLL_V IFPAB_VPROBE C21 MCP_IFPAB_VPROBE 24 67
OUT
40 mA M28 +VIO_PLL_V B21
IFPAB_RSET MCP_IFPAB_RSET OUT 24 67
20 mA L24 +VIO_PLL_NV
M24 +VIO_PLL_NV
24 =PP3V3R1V8_S0_MCP_IFP_VDD
180 mA CKPLUS_WAIVE=PwrTerm2Gnd A23 +VDD_IFPA
CKPLUS_WAIVE=PwrTerm2Gnd A24 +VDD_IFPB
24 8 =PP1V05_S0_MCP_DP0_VDD
160 mA B26 +VIO_DP0
TMDS0_VPROBE H29 MCP_TMDS0_VPROBE
A27 OUT 24 67
DDC Mode Pull-downs A26

+VIO_DP0
+VIO_DP0 TMDS0_RSET K27 MCP_TMDS0_RSET OUT 24 67
NOTE: DP_AUX_CH1 also requires pull-downs if used for

dual-mode DisplayPort (DP++). If unused no pulls
are necessary, if used for TMDS/HDMI only then
only pull-ups are necessary.
R1710 100K 1 2 DP_IG_AUX_CH0_P 9 17 67

R1711 100K 5% 1/20W MF 201
1 2 DP_IG_AUX_CH0_N 9 17 67
5% 1/20W MF 201
R1712 100K 1 2 DP_IG_AUX_CH1_P 9 17 67
R1713 100K 1 2 5% 1/20W MF 201

DP_IG_AUX_CH1_N 9 17 67
A 5% 1/20W MF 201
PAGE TITLE
MCP Graphics
DRAWING NUMBER SIZE
051-8379 D
=PP3V3_S0_MCP_GPIO
GPIO Pull-Ups
8 18 19
R
Apple Inc. REVISION
4.4.0
R1780 10K 1 2 SATARDRVR_A_EN NOTICE OF PROPRIETARY PROPERTY: BRANCH
17
R1781 10K 5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE
1 2 AUD_IP_PERIPHERAL_DET 7 17 37 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
R1782 10K 5% 1/20W MF 201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 2 MIKEY_MIC_LOAD_DET
5% 1/20W MF 201
17
17 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U1400
MCP89U-A01
BGA External A
SYMBOL 6 OF 11
67 35 SATA_HDD_R2D_C_P AF1 SATA_A0_TX_P USB0_P E21 USB_EXTA_P 36 68
OUT BI
67 35 SATA_HDD_R2D_C_N AG1 SATA_A0_TX_N USB0_N D21 USB_EXTA_N 36 68
OUT BI
OHCI0/EHCI0
AirPort (PCIe Mini-Card)
AG3 F21
D 67 35 IN SATA_HDD_D2R_N SATA_A0_RX_N USB1_P USB_MINI_P BI 9 68
D
Internal 19.5K Pull-Downs on all USB pairs

67 35 SATA_HDD_D2R_P AG2 SATA_A0_RX_P USB1_N G21 USB_MINI_N 9 68
IN BI
Geyser Trackpad/Keyboard
USB2_P E20 USB_TPAD_P 46 68 71
BI
USB2_N D20 USB_TPAD_N 46 68 71
BI
67 9 SATA_ODD_R2D_C_P AF2 SATA_A1_TX_P External C
OUT
67 9 OUT SATA_ODD_R2D_C_N AF3 SATA_A1_TX_N USB3_P L21 USB_EXTC_P BI 9 68
SATA
19 17 8 =PP3V3_S0_MCP_GPIO K21
USB3_N USB_EXTC_N BI 9 68
USB
67 9 SATA_ODD_D2R_N AF5 SATA_A1_RX_N Bluetooth
IN
R18001 67 9 IN SATA_ODD_D2R_P AF4 SATA_A1_RX_P USB4_P A20 USB_BT_P BI 7 34 68 =PP3V3_S5_MCP_GPIO 8 19
100K A21 USB_BT_N
5% USB4_N BI 7 34 68
1/20W 1
Camera/External E R1851
OHCI1/EHCI1
MF
201 2 H21
USB5_P USB_CAMERA_P BI 7 37 68 8.2K
AG5 J21 5%
MXM_GOOD_L SATA_LED*/GPIO_30 USB5_N USB_CAMERA_N BI 7 37 68 1/20W
MF
SD Card/ExpressCard 2 201
67 MCP_SATA_TERMP AG4 SATA_TERMP USB6_P G20 USB_SDCARD_P 9 68
BI
USB6_N F20 USB_SDCARD_N 9 68
BI
1
R1805 EXTERNAL D R18501
Only USB8-11 support nV

H20 8.2K
2.49K USB7_P USB_EXTD_P BI 7 37 68 5%
USB JTAG in S3/S4/S5.

1% J20 1/20W
1/20W USB7_N USB_EXTD_N BI 7 37 68 MF
MF G5 201 2
2 201
V6 USB_OC0*/GPIO_25 H14 USB_EXTA_OC_L 36
AM4 NC USB_OC1*/GPIO_26 G12 USB_EXTD_OC_L 7 37
H15
AK36 USB_RBIAS_GND L19 68 MCP_USB_RBIAS_GND
1
B15 MCP_RGMII_VREF R1860
C RGMII_VREF IN 9
1%
887
1/20W
C
69 9 ENET_RXD<0> C15 RGMII_RXD0 RGMII_TXD0 F15 TP_ENET_TXD<0> MF
IN
69 9 ENET_RXD<1> H17 RGMII_RXD1 RGMII_TXD1 F17 TP_ENET_TXD<1> 2 201
IN
69 9 ENET_RXD<2> C17 RGMII_RXD2 RGMII_TXD2 J17 TP_ENET_TXD<2>
IN
69 9 ENET_RXD<3> G15 RGMII_RXD3 RGMII_TXD3 D15 TP_ENET_TXD<3>
IN
D17 G14
23 20 8 =PP3V3_ENET_MCP_RMGT 69 9
69 9
IN
IN
ENET_CLK125M_RXCLK
ENET_RX_CTRL A15
RGMII_RXCLK
RGMII_RXCTL LAN RGMII_TXCLK
RGMII_TXCTL C14
TP_ENET_CLK125M_TXCLK
TP_ENET_TX_CTRL
R18101 9 IN ENET_ENERGY_DET E17 RGMII_INTR/GPIO_35 RGMII_MDC E15 TP_ENET_MDC

49.9 H18
1% RGMII_MDIO ENET_MDIO BI 9 69
1/20W 23 PP3V3_ENET_MCP_PLL_MAC
MF J18
201 2 20 mA +3.3V_PLL_MAC_DUAL J14 TP_MCP_CLK25M_BUF0_R
BUF_25MHZ
69 MCP_MII_COMP_VDD K15 RGMII_COMP_VDD
69 MCP_MII_COMP_GND K14 RGMII_COMP_GND RGMII_RESET* G17 TP_ENET_RESET_L
R18111 Internal MAC Disable:

49.9
1%
1/20W Connect RGMII_RXD<0:3> together to 10K pull-down.
MF
201 2 Connect RGMII_RXCLK to 10K pull-down.
Connect RGMII_RXCTL to 10K pull-down.
Connect RGMII_INTR to 10K pull-down (if not used as GPIO).
+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail.
RGMII_COMP_VDD/_GND must remain connected as shown.
Connect RGMII_VREF to 10K pull-down.
Connect RGMII_MDIO to 10K pull-down.
B All other pins can be left TP or NC. B
PAGE TITLE
MCP SATA, USB & Ethernet

DRAWING NUMBER SIZE

REVISION
R
4.4.0
18 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_S0_MCP_GPIO 8 17 18 19
2
OMIT_TABLE
R1961
U1400
MCP89U-A01
10K
5%
1/20W
MF
23 8 =PP3V3R1V5_S0_MCP_HDA BGA 201 R1950
SYMBOL 7 OF 11 22
1
70 mA J12 +VDD_HDA HDA_SDATA_OUT B3 68 19 HDA_SDOUT_R 1 2 HDA_SDOUT 7 37 68
OUT
70 mA 5%
1/20W
R1951 MF
D R19001 HDA_SDIN0 C3 B4 HDA_BIT_CLK_R 22

201
HDA_BIT_CLK
D
49.9
1%
1/20W
MF
68 37 7 IN HDA_SDATA_IN0
(IPD)
HDA HDA_BITCLK 68 19 1
5%
1/20W
MF
2
R1952
OUT 7 37 68
201 2 201
MCP_HDA_PULLDN_COMP A5 C4 HDA_RST_R_L 1
22 2 HDA_RST_L
68 HDA_PULLDN_COMP HDA_RESET* 68 19
OUT 7 37 68
(IPD)
5%
1/20W
R1953 MF
201
HDA_SYNC A4 68 19 HDA_SYNC_R 1
22 2 HDA_SYNC OUT 7 37 68
BUF_SIO_CLK Frequency
5%
1/20W
Frequency HDA_SYNC
MF
201
68 40 38 7 BI LPC_AD<0> R1910 22 1 2 LPC_AD_R<0> H1 LPC_AD0 (IPU) LPC_SERIRQ H5 LPC_SERIRQ BI 7 38 40 24 MHz 1
R1911 22 5% 1/20W MF 201 H2 (IPU)
68 40 38 7 BI LPC_AD<1> 1 2 LPC_AD_R<1> LPC_AD1 (IPU)
68 40 38 7 BI LPC_AD<2> R1912 22 1 2 5% 1/20W MF 201
LPC_AD_R<2> H3 LPC_AD2 (IPU) R1960 14.31818 MHz 0
R1913 5% 1/20W MF 201 H4 F3 22
68 40 38 7 BI LPC_AD<3> 22 1 2
5% 1/20W MF 201
LPC_AD_R<3> LPC_AD3 (IPU)
LPC LPC_FRAME* LPC_FRAME_R_L 1
5%
1/20W
MF
2 LPC_FRAME_L OUT 7 38 40 68
19 MLB_RAM_CFG1 F2 LPC_DRQ0*/GPIO_43 201

(IPU)
(IPD) LPC_RESET* F5 LPC_RESET_L OUT 19 25 68 BIOS Boot Select
PM_CLKRUN_L F1 LPC_CLKRUN*/GPIO_42 (IPU) LPC_CLK0 F4 LPC_CLK33M_SMC_R
40 38 7 IN OUT 25 68
I/F LPC_FRAME#
SMC_WAKE_SCI_L D14 A11 MCP_CPU_VTT_EN_L LPC 0
(IPU-S5)
38 IN SIO_PME*/GPIO_31 MISC_VDDEN0/GPIO_47 19
23 20 8 PP3V3_G3_RTC J11 F14
13 OUT PM_LATRIGGER_L EXT_SMI*/GPIO_32 MISC_VDDEN1/GPIO_48 MLB_RAM_CFG0 19
AUD_I2C_INT_L F6 E11 MLB_RAM_CFG2 SPI 1
(IPU)
37 7 IN A20GATE/GPIO_55 MISC_VDDEN2/GPIO_17 19
38 SMC_RUNTIME_SCI_L D3 KBRDRSTIN*/GPIO_56 MISC_VDDEN3/GPIO_18 F11 SMC_ADAPTER_EN 38 39 57

IN IN
R19201 1
R1921 MISC_VDDEN4/GPIO_19 G11 LPCPLUS_GPIO BI 7 19 40 NOTE: MCP89 does not support FWH, only
49.9K 49.9K
C 1%
1/20W
MF
1%
1/20W
MF
38 IN PM_PWRBTN_L H12 PWRBTN* (IPU-S5)
MEM_VDD_SEL/GPIO_46 D11 MCP_MEM_VDD_SEL_1V5 OUT 9 LPC ROMs. So Apple designs will
not use LPC for BootROM override.
C
201 2 PM_SYSRST_DEBOUNCE_L F12 RSTBTN* (IPU-S5) FANCTL0/GPIO_61 D8 MLB_RAM_CFG3
2 201 25 IN 19
FANRPM0/GPIO_60/MGPIO_2 E8 MEM_EVENT_L IN 19 38
FANCTL1/GPIO_62 F8 ENET_LOW_PWR
RTC_RST_L D18 RTC_RST* OUT 19
FANRPM1/GPIO_63/MGPIO_3 G7 SDCARD_RESET IN 19 SPI Frequency Select

PM_RSMRST_L F18 PWRGD_SB (IPD) SLP_S3* A8 PM_SLP_S3_L
38
25
IN
MCP_PS_PWRGD E9 PWRGD (IPD) SLP_RMGT* C9 PM_SLP_RMGT_L
OUT 7 38 39 57
57
Frequency SPI_DO SPI_CLK
IN OUT
(IPD) SLP_S5* B8 PM_SLP_S4_L NOTE: MCP SLP_S5# pin
OUT 7 19 38 57
has the behavior

25.0 MHz 0 0
39 MCP_WAKE_REQ_L E18 MCP_WAKE_REQ* MCP_VID0/GPIO_13 E3 MCP_VID<0> 19 54
OUT OUT
E4 of Intels SLP_S4#
PM_BATLOW_L A9 MCP_VID1/GPIO_14 MCP_VID<1> OUT 19 54 31.2 MHz 0 1
HDA Output Caps 38
57 21
IN
OUT MCP_MEM_VDD_EN B11

MCP_WAKE_DIS*
(IPU-S5)
MCP_MEMVDD_EN/GPIO_44
MCP_VID2/GPIO_15
MCP_VID3/GPIO_16
E5
D6
MCP_VID<2>
MCP_VID<3>
OUT
OUT
19 54
19 54
signal.
42.7 MHz 1 0
For EMI Reduction on HDA interface MCP_MEM_VTT_EN C11 H10 SPI_CS0_R_L
MEMVTT_EN/GPIO_45 SPI_CS0*/GPIO_10
21 OUT
SPI_CLK/GPIO_11 G8 SPI_CLK_R
OUT 40 68
62.5 MHz 1 1
HDA_SDOUT_R SM_INTRUDER_L G18 OUT 40 68
HDA_BIT_CLK_R
19 68
19 68
FIXME: AUD_IPHS_SWITCH_EN WAS GPIO_2
D5
INTRUDER*
MISC SPI_DI/GPIO_08
SPI_DO/GPIO_09
B9
E14
SPI_MISO
SPI_MOSI_R OUT
IN 19 40 68
40 68
NOTE: 42 & 62 MHz use FAST_READ command.
Straps not provided on this page.
HDA_RST_R_L 19 68 39 19 OUT SMC_IG_THROTTLE_L MGPU_PIO0/GPIO_6 E1
E6 SPKR/GPIO_1 MCP_SPKR OUT 39
HDA_SYNC_R 19 68 37 19 7 OUT AUD_IPHS_SWITCH_EN MGPU_PIO1/GPIO_7
22 19 GFXVCORE_PWR_EN F9 MGPU_PIO2/GPIO_23 THERM_DIODE_P C2 MCP_THMDIODE_P 44 71
OUT OUT 1
C1950 1 C1952 1 47 40 19 7 BI SPIROM_USE_MLB G9 MGPU_PIO3/GPIO_24 THERM_DIODE_N D1 MCP_THMDIODE_N OUT 44 71
R1970
10PF 10PF 10K
5% 5% C5 SMBUS_MCP_0_CLK 5% MCP_SPKR:
25V 25V D12 SMB_CLK0 OUT 41 68 1/20W
NPO 2 NPO 2 13 IN JTAG_MCP_TDI JTAG_TDI (IPU) C8 MF
201 201 C12 SMB_DATA0 SMBUS_MCP_0_DATA BI 41 68
2 201 0 = USER mode (Normal boot mode)
13 OUT JTAG_MCP_TDO JTAG_TDO B6
B12 SMB_CLK1/MSMB_CLK SMBUS_MCP_1_CLK OUT 41 68 1 = SAFE mode (For ROMSIP recovery)
13 IN JTAG_MCP_TMS JTAG_TMS (IPU) C6
E12 SMB_DATA1/MSMB_DATA SMBUS_MCP_1_DATA
B 1 C1951 1 C1953 13 IN JTAG_MCP_TRST_L JTAG_TRST* (IPD)
SMB_ALERT*/GPIO_64 D9 AP_PWR_EN
BI 41 68
Connects to SMC for automatic recovery. B
10PF 10PF 13 IN JTAG_MCP_TCK A12 JTAG_TCK OUT 19 34 57
5% 5%
2 25V 2 25V SUS_CLK/GPIO_34 H9 PM_CLK32K_SUSCLK_R OUT 25 68
NPO NPO
201 201 MCP_CLK25M_XTALIN A14 XTALIN
25 IN
TEST_MODE_EN A6 MCP_TEST_MODE_EN
MCP_CLK25M_XTALOUT B14 XTALOUT
25 OUT
PKG_TEST B20
PKG_TEST2 C20 =PP3V3_S3_MCP_GPIO
25 RTC_CLK32K_XTALIN B18 XTALIN_RTC NO STUFF
19 8
IN
RTC_CLK32K_XTALOUT C18 1 1 1
25 OUT XTALOUT_RTC R1959 R1966 R1975 DRAM_CFG3:H DRAM_CFG2:H DRAM_CFG0:H
10K 10K 1K
R19301 1 5% 5% 1% R19761 1
R1978 1
R1957
GPIO Pull-Ups/Downs 10K
5%
1/20W
R1931
5%
100K
1/20W
1/20W
MF
2 201
1/20W
MF
2 201
1/20W
MF
2 201
10K
5%
1/20W
MF
5%
10K
1/20W
MF
GPIO43 has
internal ~9K
pull-up.
10K
5%
1/20W
MF
=PP3V3_S5_MCP_GPIO 8 18 MF MF 2012 2201 2201
201 2 2 201
=PP3V3_S3_MCP_GPIO 8 19
19 MLB_RAM_CFG3
=PP3V3_S0_MCP_GPIO 8 17 18 19
19 MLB_RAM_CFG2
R1991 10K 19 MLB_RAM_CFG1
1 2 SMC_IG_THROTTLE_L 19 39
R1981 10K 5% 1/20W MF 201 19 MLB_RAM_CFG0
1 2 AUD_IPHS_SWITCH_EN 7 19 37
R1999 100K 1 2
5% 1/20W MF 201
GFXVCORE_PWR_EN DRAM_CFG3:L DRAM_CFG2:L DRAM_CFG1:L DRAM_CFG0:L
19 22
R1986 100K 1 2 5% 1/20W MF 201

SPIROM_USE_MLB 7 19 40 47
R19771 1
R1979 R19561 1
R1958
5% 1/20W MF 201 10K 10K 470 10K
5% 5% 5% 5%
R1983 10K MCP_CPU_VTT_EN_L 1/20W 1/20W 1/20W 1/20W
R1987 100K
1
1
2
2 5% 1/20W MF 201
LPCPLUS_GPIO
19
7 19 40
Platform-Specific Connections MF
2012
MF
2201
MF
2012
MF
2201
5% 1/20W MF 201
R1989 10K
R1965
1 2 MEM_EVENT_L 19 38 33
5% 1/20W MF 201 LPC_RESET_L 1 2 LPC_PWRDWN_L
R1990 10K 1 2 ENET_LOW_PWR 19
68 25 19 IN
5%
OUT 7 38 40
R1980 10K 5% 1/20W MF 201

1 2 SDCARD_RESET 1/20W
A 5% 1/20W MF 201
19
MF
201 SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
R1992 100K 1 2 MCP_VID<0> 19 54
PM_SLP_S4_L PM_SLP_S5_L
PAGE TITLE
R1993 100K 1 2 5%
5%
1/20W
1/20W
MF
MF
201
201
MCP_VID<1> 19 54
57 38 19 7 IN
MAKE_BASE=TRUE OUT 38
MCP HDA, LPC & MISC
R1994 100K 1 2 MCP_VID<2> DRAWING NUMBER SIZE
R1995 100K 1 2
5% 1/20W MF 201
MCP_VID<3>
19 54
NOTE: MCP SLP_S5# signal has the 051-8379 D
5% 1/20W MF 201
19 54
behavior of Intes SLP_S4# signal Apple Inc. REVISION
R1998 20K 1 2 SPI_MISO 19 40 68
R
4.4.0
5% 1/20W MF 201
R1996 10K 1 2 AP_PWR_EN 19 34 57 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
19 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.
OMIT_TABLE
OMIT_TABLE U1400 U1400
MCP89U-A01 U1400
U1400 MCP89U-A01 BGA MCP89U-A01
MCP89U-A01 23 8 =PPVCORE_S0_MCP BGA =PPVCORE_SW_MCP_GFX 22 24 SYMBOL 10 OF 11
BGA
SYMBOL 9 OF 11 SYMBOL 11 OF 11
BGA 8450 mA (0.85V) N7 +VDD_COREA +VDD_COREB M9 15350 mA (0.85V) AL34 G13 B16 B36
23 8 =PP1V05_SW_MCP_FSB SYMBOL 8 OF 11 =PP1V5R1V35_SW_MCP_MEM 15 21 23
N2 K2 AT10 E10 E16 AB37
C32 AK19 +VDD_COREA +VDD_COREB
2000 mA +VTT_CPU +VDD_MEM 4300 mA N11 L7 AE4 B10 AP16 AE2
E33 AJ23 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R12 M7 K37 AM32 AL36 AL7
L29 AJ24 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P9 Y23 AL25 AU25 G19 D13
AA29 AK21 +VDD_COREA +VDD_COREB
D E32
+VTT_CPU
+VTT_CPU
+VDD_MEM
+VDD_MEM AJ17
R8
N4
+VDD_COREA +VDD_COREB M2
AB23
T36
T37
AY38
W4
AA21
K16
T39
AH4
D
AA30 AK15 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R5 M11 AB2 AU10 K28 AB7
L31 AK5 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R3 M12 AB4 D10 D25 AH36
T30 AJ26 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P3 L8 C40 H31 AL16 AC17
N30 AK13 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P4 M8 B5 AL31 AP4 AH5
M31 AK16 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P8 M10 G4 U31 G25 AL33
F33 AJ19 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R2 L10 AE8 AT31 K25 AW10
H33 AK12 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P1 M6 AW34 AH31 E31 W17
J32 AK4 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R9 L12 AC20 AN25 G16 G39
B33 AK26 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM N5 K10 AE5 AC21 AP13 AB39
G33 AK20 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM N10 K7 W18 AA22 U22 AH39
B32 AJ27 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P10 M1 AT16 AN16 AP28 AL5
J33 AJ10 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R1 K8 AB5 AE31 AT28 AW39
F32 AJ12 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM P2 K5 N34 AU34 H16 AN10
H32 AK17 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM R4 L9 AT2 AW19 AH33 AB8
G32 AK23 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM N8 M3 W20 G10 AT22 N39
A33 AJ2 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM
POWER I
R10 +VDD_COREA +VDD_COREB J4 AW16 B22 AL8 N36
D32 AK3
POWER II
+VTT_CPU +VDD_MEM P5 M4 D7 B19 AA1 N37
AB30 AJ22 +VDD_COREA +VDD_COREB
+VTT_CPU +VDD_MEM AD24 L11 B2 B34 AP37 AE29
AB29
C33
D33
+VTT_CPU
+VTT_CPU
+VDD_MEM
+VDD_MEM
AJ21
AK14
AK22
R7
P6
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREB
+VDD_COREB
+VDD_COREB
L5
J2
G37
D16
E22
AC18
W22
H19
GND AW28
AU28
+VTT_CPU +VDD_MEM R6 J1 K39 K34 A3 E19
A32
M29
+VTT_CPU
+VTT_CPU
+VDD_MEM
+VDD_MEM
AK8
AK27 NOTE: VDD_COREx_SENSE signals should NOT
be used for remote sensing unless
AB24
AC24
+VDD_COREA
+VDD_COREA
+VDD_COREA
+VDD_COREB
+VDD_COREB
+VDD_COREB
J7
M5
G31
B7
GND AL22
AP36
AH8
G28 GND GND
L16
K22
M30 +VTT_CPU +VDD_MEM AJ4
COREA/COREB are powered by separate P11 +VDD_COREA +VDD_COREB L4 L15 G34 R31 AW22
R30 +VTT_CPU +VDD_MEM AK29
regulators. P12 L3 W19 P31 AW25 T34
C P30
L32
+VTT_CPU
+VTT_CPU
+VDD_MEM
+VDD_MEM
AK18
AK24 Instead connect regulator sense point P7
+VDD_COREA
+VDD_COREA
+VDD_COREB
+VDD_COREB J3 Y10 GND GND U21 AP39 AN22 C
as close to COREB FET as possible. R11 +VDD_COREA +VDD_COREB K11 AW2 H25 AB33 D31
T29 +VTT_CPU +VDD_MEM AJ9
AD23 +VDD_COREA +VDD_COREB J6 AH7 B31 B25 AE30
L30 +VTT_CPU +VDD_MEM AK11
Y24 +VDD_COREA +VDD_COREB L2 B13 AU4 U10 T8
U30 +VTT_CPU +VDD_MEM AK6
AA24 +VDD_COREA +VDD_COREB L1 AE37 AA19 W34 M16
P29 +VTT_CPU +VDD_MEM AK2
N12 +VDD_COREA +VDD_COREB J5 AV1 W8 U19 M15
R29 +VTT_CPU +VDD_MEM AK25
AD17 +VDD_COREA +VDD_COREB L6 AN19 AT19 K12 M17
V30 +VTT_CPU +VDD_MEM AJ28
AD18 +VDD_COREA +VDD_COREB K4 AP10 AT13 E34 M18
U29 +VTT_CPU +VDD_MEM AK9
AD19 +VDD_COREA +VDD_COREB V23 W33 AH2 AL28 M19
V29 +VTT_CPU +VDD_MEM AK28
AD20 +VDD_COREA +VDD_COREB V17 AB36 AP19 AE34 M20
Y30 +VTT_CPU +VDD_MEM AJ11
AD21 +VDD_COREA +VDD_COREB V19 K13 A38 AT39 M21
Y29 +VTT_CPU +VDD_MEM AJ5
AD22 +VDD_COREA +VDD_COREB V18 AU13 AT34 AP5 AE7
W29 +VTT_CPU +VDD_MEM AJ29
U24 +VDD_COREA +VDD_COREB V20 AA23 AE39 W21 W5
W30 +VTT_CPU +VDD_MEM AJ3
V24 +VDD_COREA +VDD_COREB V21 AA31 AA18 D34 W7
N29 +VTT_CPU +VDD_MEM AJ20
W24 +VDD_COREA +VDD_COREB V22 Y31 AT25 E25 AP2
K31 +VTT_CPU +VDD_MEM AK10
=PP1V05_S0_MCP_FSB T11 +VDD_COREA +VDD_COREB AB21 AE33 AW31 K36 AL10
23 14 8
+VDD_MEM AJ18
200 mA AC29 +VTT_CPU2 T12 +VDD_COREA +VDD_COREB Y17 AY3 U23 D19 AP34
+VDD_MEM AK1
AD29 +VTT_CPU2 U11 +VDD_COREA +VDD_COREB Y18 N33 D22 Y1 U18
+VDD_MEM AJ1
AC30 +VTT_CPU2 V11 +VDD_COREA +VDD_COREB Y19 T2 W36 W23 T7
+VDD_MEM AJ7
AD30 +VTT_CPU2 +VDD_COREB Y20 B39 W39 AC22 W31
+VDD_MEM AJ8
AB31 +VTT_CPU2 TP_MCP_VDDCOREA_SENSEP U9 +VDD_COREA_SENSE +VDD_COREB Y21 T4 W37 H22 AL39
+VDD_MEM AJ25
AC31 +VTT_CPU2 TP_MCP_VDDCOREA_SENSEN U8 GND_COREA_SENSE +VDD_COREB Y22 AH37 AC23 H8 T31
+VDD_MEM AJ16
AD31 +VTT_CPU2 =PP1V05_S0_MCP_PE_DVDD +VDD_COREB AB22 V31 AP22 K19 N31
+VDD_MEM AJ15 23 8
AC32 +VTT_CPU2 400 MA AD8 +VIO_PE_DVDD +VDD_COREB AB17 AU37 AN13 G2 AA17
+VDD_MEM AK7
(PE0[5:0]
PE1[1:0]) AD6 +VIO_PE_DVDD +VDD_COREB AB18 AW5 AP31 E2 T10
=PP3V3_S0_MCP_HVDD V9 +3.3V_HVDD +VDD_MEM AJ6
23 8
30 mA AC8 +VIO_PE_DVDD +VDD_COREB AB19 AU7 AU31 T5 K33
AJ13
B V10
H11
+3.3V
+VDD_MEM
+VDD_MEM AJ14
AC9
AD9
+VIO_PE_DVDD +VDD_COREB AB20
L13
AT7
AN28
AL19
AL2
AC19
AN31
E13
AL13
B
+3.3V AL11 +VIO_PE_DVDD +VDD_COREB
K29 +VDD_MEM AC7 L14 D4 AA20 AL37 AP7
23 8 =PP3V3_S0_MCP +3.3V AL12 +VIO_PE_DVDD +VDD_COREB
250 mA +VDD_MEM AC10 M13 AU19 E28 AU16 U17
AL14 +VIO_PE_DVDD +VDD_COREB
+VDD_MEM AD7 M14 AP25 AH34 AB34 W2
AL15 +VIO_PE_DVDD +VDD_COREB
+VDD_MEM AD11 AU22 B28 U20 AK34
L18 AL17 +VIO_PE_DVDD
23 8 =PP0V9_S5_MCP_VDD_AUXC +VDD_DUAL_AUXC +VDD_MEM AD10 AW13 AV40 G22 AK35
K18 AL18 +VIO_PE_DVDD
150 mA +VDD_DUAL_AUXC +VDD_MEM AC11 T33 D28 AW36 H6
AL20 +VIO_PE_DVDD J9
A18 +VDD_MEM AC12 +VDD_COREB_SENSE TP_MCP_VDDCOREB_SENSEP E7 H28 AL4 H7
23 19 8 PP3V3_G3_RTC +3.3V_VBAT AL21 +VIO_PE_DVDD J8
+VDD_MEM AD12 GND_COREB_SENSE TP_MCP_VDDCOREB_SENSEN AW7 G36 C1 V7
?? uA (G3) L20 AL26 +VIO_PE_DVDD
5 mA (S0) +3.3V_DUAL_USB +VDD_MEM AE12 H13 AE36 E39 V8
+VIO_PE_DVDD
200 mA K20 +3.3V_DUAL_USB +VDD_MEM AL27
PP1V05_S0_MCP_PE_AVDD PP1V05_S0_MCP_SATA_AVDD D37 AM5
+VDD_MEM AL29 23 23
1000 MA AA10 +VIO_PE_AVDD +VIO_SATA_AVDD AF6 300 mA

J15 +3.3V_DUAL +VDD_MEM AL30
U12 +VIO_PE_AVDD +VIO_SATA_AVDD AG8
=PP3V3_S5_MCP (PE0[5:0], PE1[1:0]) AB10 AF7
23 8 +VIO_PE_AVDD +VIO_SATA_AVDD
240 mA 40 mA +VDD_DUAL_RMGT K17 =PP0V9_ENET_MCP_RMGT 8 23
V12 +VIO_PE_AVDD +VIO_SATA_AVDD AF8
L17 140 mA W11 AG9
+VDD_DUAL_RMGT +VIO_PE_AVDD +VIO_SATA_AVDD
W12 +VIO_PE_AVDD +VIO_SATA_AVDD AG6
+3.3V_DUAL_RMGT A17 =PP3V3_ENET_MCP_RMGT 8 18 23
Y11 +VIO_PE_AVDD +VIO_SATA_AVDD AF9
B17 300 mA Y12 AG7
+3.3V_DUAL_RMGT +VIO_PE_AVDD +VIO_SATA_AVDD
AA11 +VIO_PE_AVDD
AA12 =PP1V05_S0_MCP_SATA_DVDD 8 23
+VIO_PE_AVDD AD1
AB11 +VIO_SATA_DVDD 100 mA
+VIO_PE_AVDD AD2
AB12 +VIO_SATA_DVDD
+VIO_PE_AVDD AD3
+VIO_SATA_DVDD
+VIO_SATA_DVDD AD4
A +VIO_SATA_DVDD
+VIO_SATA_DVDD
AC3
AC4 SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
PAGE TITLE
AC5
+VIO_SATA_DVDD
+VIO_SATA_DVDD AD5 MCP Power & Ground
AC6 DRAWING NUMBER SIZE
+VIO_SATA_DVDD
+VIO_SATA_DVDD AC1 Apple Inc. 051-8379 D
AC2 REVISION
+VIO_SATA_DVDD R
4.4.0
20 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C2300 helps reduce input rail

droop during Q2300 turn-on.
PLACE_NEAR=Q2300.9:2 mm
8 =PP1V5R1V35_S0_MCPDDRFET
CRITICAL Q2300
C2300 1
Part STMFS4854N
100UF CRITICAL
20% 9
6.3V
CERM-X5R 2
STMFS4855NS Type N-Channel
1206-1
Q2300 Rds(on) 10 mOhm @3.2V
D DFN
Loading 4.3 A (EDP)
NC 8 NC
21 8 =PP5V_S3_MCPDDRFET
4 G
KELVIN 6 MCPDDRFET_KELVIN
SENSE
OUT 43
S
C2305
1
1
C VCC 0.1UF
20% 7 1 2 3
K1
5 C
U2305 10V
2 CERM
SLG5AP031 402 NC
MCPDDRFET_SENSE
MCP_MEM_VDD_EN 2 TDFN 5 OUT 43
57 19 IN EN D
G 7 MCPMEM_GATE
CRITICAL PP1V5R1V35_SW_MCP
MCPMEM_CNFG 3 6 (G driven to VCC) MIN_LINE_WIDTH=0.6 mm
CNFG S MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE (OR 1.35V)
1 DONE 8 TP_MCPMEM_DONE
R2305 =PP1V5R1V35_SW_MCP_MEM 15 20 23
THRM
560K GND PAD 4250 mA
9
1%
1/20W
MF NV Requirements:
2 201 - Min Ramp-Up Time: 20 uS (10% to 90%)
<R1> - Max Ramp-Up Time: 65 uS (ENABLE to 90%)
- FET Ron <= 3.8 mOhms
Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms) NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.
Gated Rail Savings: 120mW
DIMM CKE Clamps

CKE must be held low to keep memory in self-refresh.
Clamps enable before MCP89 MEMVDD rail switched off.
CRITICAL
B 21 8 =PP5V_S3_MCPDDRFET Q2355
Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.
Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.
B
NTUD3170NZXXG Q2355/Q2356 chosen for low output capacitance.
SOT-963
R23501
10K 3 MEM_A_CKE<0> BI 15 26 27 32 66
5%
1/20W D
MF
201 2
MEMVTT_EN_L 5 G
S
Q2350 4
SSM3K15FV D 3
SOD-VESM-HF 6 MEM_A_CKE<1> BI 15 26 27 32 66
1 G S 2 2 G
S
19 IN MCP_MEM_VTT_EN
1
NO STUBS on CKE signals!

CRITICAL
Q2356
NTUD3170NZXXG
SOT-963
3 MEM_B_CKE<0> BI 15 28 29 32 66
A 5 G
PAGE TITLE
S
4 MCP89 Memory Rail Gating

DRAWING NUMBER SIZE
6 MEM_B_CKE<1> BI 15 28 29 32 66

D REVISION
R
4.4.0
2 G NOTICE OF PROPRIETARY PROPERTY: BRANCH
S
1 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
23 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C2400 helps reduce input rail

droop during Q2400 turn-on.
PLACE_NEAR=C2400.1:1 mm
8 =PPVCORE_S0_MCPGFXFET XW2400
SM
1 2 MCPCORES0_VSEN_P OUT 54 71
CRITICAL
1 C2400 PLACE_NEAR=Q2400.5:2 mm
100UF
20%
6.3V
2 CERM-X5R XW2401
SM
1206-1
1 2 MCPCORES0_VSEN_N OUT 54 71
=PP5V_S0_MCPFSBFET
8
Q2400
5 6 7 8
Part Si4838BDY
CRITICAL
C2405
1
1 Type N-Channel
C VCC 0.1UF
20%
D
Q2400 Rds(on) 3.2 mOhm @2.5V C
U2405 10V
2 CERM 4 G
SI4838BDY
SO-8
SLG5AP033 402
S Loading 15.35 A (EDP)
GFXVCORE_PWR_EN 2 TDFN
19 IN EN D 5
G 7 MCPGFX_GATE 1 2 3
CRITICAL PPVCORE_SW_MCP_GFX
MCPGFX_CNFG 3 6 (G driven to VCC) MIN_LINE_WIDTH=0.6 mm
CNFG S MIN_NECK_WIDTH=0.12 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE
DONE 8 TP_MCPGFX_DONE
1 C2406 THRM
=PPVCORE_SW_MCP_GFX 20 24
820PF GND PAD
10%
9
50V
2 CERM
402 NV Requirements:
- Min Ramp-Up Time: 100 uS (10% to 90%)
<C1> - Max Ramp-Up Time: 1500 uS (ENABLE to 90%)
- FET Ron <= 2.5 mOhms
Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF) NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.
Gated Rail Savings: 860mW
B B
PAGE TITLE
MCP89 GFX Core Rail Gating

DRAWING NUMBER SIZE

REVISION
R
4.4.0
24 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP Non-GFX Core Power MCP 1.05V PCIe Analog Power
L2560
20 8 =PPVCORE_S0_MCP 8 =PP1V05_S0_MCP_AVDD_UF 30-OHM-5A PP1V05_S0_MCP_PE_AVDD 20
1 2 MIN_LINE_WIDTH=0.4 MM
8450 mA (0.85V) 800 mA MIN_NECK_WIDTH=0.2 MM500
mA
0603 VOLTAGE=1.05V
OMIT_TABLE
OMIT_TABLE
C2500 1 1 C2501 1 C2502 1 C2503 1 C2504 1 C2505 1 C2506 1 C2507 1 C2508 C2560 1 1 C2561 1 C2559 1 C2562 1 C2563 1 C2564 1 C2565 1 C2566
10UF 4.7UF 1.0UF 0.22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 10% 10% 10UF 4.7UF 4.7UF 1.0UF 1.0UF 0.1UF 0.1UF 0.1UF
6.3V 2 4V
2 X5R-1 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V
2 X5R 2 6.3V 6.3V
2 X5R 20% 20% 20% 20% 20% 10% 10% 10%
X5R X5R X5R X5R X5R X5R 6.3V 2 4V
2 X5R-1 2 4V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
603-1 402 0201 201 201 201 201 201 201 X5R X5R-1 X5R X5R X5R X5R X5R
603-1 402 402 0201 0201 201 201 201
D MCP Memory Power L2567 MCP 1.05V SATA Analog Power D

21 20 15 =PP1V5R1V35_SW_MCP_MEM 30-OHM-5A PP1V05_S0_MCP_SATA_AVDD 20
4300 mA (1.5V) MIN_NECK_WIDTH=0.2 MM300 mA
0603 VOLTAGE=1.05V
OMIT_TABLE
C2510 1 1 C2511 1 C2512 1 C2513 1 C2514 1 C2515 1 C2516 1 C2517 1 C2518 1 C2519 C2567 1 1 C2568 1 C2569
4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10UF 4.7UF 0.1UF
4V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 6.3V 2 6.3V 20% 20% 10%
X5R-1 2 X5R X5R X5R X5R X5R 2 X5R X5R 2 X5R X5R 6.3V 2 4V
2 X5R-1 2 6.3V
402 201 201 201 201 201 201 201 201 201 X5R X5R
603-1 402 201
CRITICAL
MCP CPU FSB (VTT) Power MCP S0 FSB (VTT) Power MCP 1.05V CPU/FSB/MEM PLL Power
L2570
20 8 =PP1V05_SW_MCP_FSB 20 14 8 =PP1V05_S0_MCP_FSB 8 =PP1V05_S0_MCP_PLL_UF 220-OHM-2.2A PP1V05_S0_MCP_PLL_FSBMEM 15
2000 mA 200 mA 555 mA MIN_NECK_WIDTH=0.2 MM 70 mA
0603 VOLTAGE=1.05V
OMIT_TABLE
C2520 1 1 C2521 1 C2522 1 C2523 C2524 1 1 C2525 C2570 1 1 C2571 1 C2572 1 C2573
10UF 4.7UF 1.0UF 1.0UF 4.7UF 1.0UF 4.7UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 10% 10% 10%
6.3V 2 4V 2 6.3V 2 6.3V 4V 2 6.3V 4V 2 6.3V 6.3V 2 6.3V
X5R
603-1
2 X5R-1
402
X5R
0201
X5R
0201
X5R-1 2
402
X5R
0201
X5R-1 2
PLACE_NEAR=R2570.1:50 mil 402
R2570 X5R
201
2 X5R
201
X5R
201
1
0.33 2
GND_MCP_PLL_FSB
MIN_LINE_WIDTH=0.25 MM 5%
MIN_NECK_WIDTH=0.25 MM 1/16W
VOLTAGE=0V MF
CRITICAL 0402
MCP 0.9V AUX Core Power MCP 0.9V MAC/SMU Power MCP 1.05V PCIe/SATA PLL Power
L2575
20 8 =PP0V9_S5_MCP_VDD_AUXC 20 8 =PP0V9_ENET_MCP_RMGT 220-OHM-2.2A PP1V05_S0_MCP_PLL_PEXSATA 16
150 mA 140 mA MIN_NECK_WIDTH=0.2 MM 325 mA
0603 VOLTAGE=1.05V
C 1 C2526
0.1UF
1 C2527
0.1UF
C2528
4.7UF
1 1 C2529
0.1UF
C2575 1
4.7UF
1 C2576
0.1UF
1 C2577
0.1UF
1 C2578
0.1UF
1 C2579
0.1UF
C
10% 10% 20% 10% 20% 10% 10% 10% 10%
6.3V
2 6.3V
4V
2 6.3V
4V
2 6.3V
6.3V
2 6.3V
6.3V
2 X5R X5R X5R-1 2 X5R X5R-1 2 X5R 2 X5R X5R 2 X5R
201 201 402 201 402 201 201 201 201
CRITICAL
MCP 1.05V PCIE Digital Power MCP 1.05V SATA Digital Power MCP 1.05V Core/Misc PLL Power
L2580
20 8 =PP1V05_S0_MCP_PE_DVDD 20 8 =PP1V05_S0_MCP_SATA_DVDD 220-OHM-2.2A PP1V05_S0_MCP_PLL_CORE 17
200 mA 100 mA MIN_NECK_WIDTH=0.2 MM 160 mA
0603 VOLTAGE=1.05V
C2530 1 C2538 1 1 C2531 1 C2532 1 C25331 C25341 C2535 C2536 1 1 C2537 C2580 1 1 C2581 1 C2582 1 C2583 1 C2584
4.7UF 4.7UF 1.0UF 1.0UF 0.1UF 0.1UF 0.1UF 4.7UF 0.1UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 20% 10% 20% 10% 10% 10% 10%
4V 4V
2 6.3V 2 6.3V 2 6.3V 2 6.3V
4V
2 6.3V
4V
2 6.3V
6.3V
2 6.3V
6.3V 6.3V
X5R-1 2 X5R-1 2 2 X5R X5R X5R X5R X5R X5R-1 2 X5R X5R-1 2 X5R 2 X5R X5R 2 X5R
402 402 0201 0201 201 201 201 402 201 402 201 201 201 201
MCPHVDD:P3V3
CRITICAL
MCP 3.3V PCIe/SATA I/O PLL Power
MCP 1.05V Memory DLL Power
L2590 MCP 3.3V PLL Power
20 8 =PP3V3_S0_MCP_HVDD 8 =PP3V3_S0_MCP_PLL_UF FERR-240-OHM-200MA PP3V3_S0_MCP_PLL_HVDD 16
15 8 =PP1V05_S0_MCP_M2CLK_DLL 30 mA 260 mA 1 2 MIN_NECK_WIDTH=0.2 MM 50 mA
0402 VOLTAGE=3.3V
550 mA
C2540 1 C2541 1 1 C2542 MCPHVDD:P2V5 MCPHVDD:P2V5
CRITICAL HVDDLDO:ADJ C2590 1 1 C2591
4.7UF 4.7UF 0.1uF 4.7UF 0.1UF
20%
4V
20%
6.3V 2
20%
10V R25901 C2592 1 OMIT_TABLE R25911 20%
6.3V 2
20%
10V
X5R-1 2 2 CERM 665K 2 CERM
402
CERM
603 402 10K
5%
1.0UF
20%
6.3V 2
U2590 1%
1/20W
CERM
603 402
1/20W MIC5365-2.5V MF
B MF
201 2
X5R
0201 1 VIN SC70 VOUT 5 201 2
<Ra> B
P2V8HVDD_EN 3 EN NC 4 P2V8HVDD_FB
MCP 3.3V I/O Power MCP 3.3V/1.5V HDA Power GND HVDDLDO:ADJ
=PP3V3_S0_MCP =PP3V3R1V5_S0_MCP_HDA 2
20 8 19 8 R25921
250 mA 70 mA 316K
1%
1/20W
MF
C2543 1 1 C2544 1 C2545 1 C2546 1 C2547 C2548 1 1 C2549 201 2
4.7uF 0.1uF 0.1uF 0.1uF 0.1uF 4.7UF 0.1UF <Rb> Vout = 0.8V * (Ra + Rb) / Rb, Rb ~ 320kOhms
20% 20% 20% 20% 20% 20% 10%
6.3V 2 10V
2 CERM 10V
2 CERM 10V
2 CERM
10V
2 CERM 6.3V 2 2 6.3V
CERM CERM X5R
603 402 402 402 402 603 201
353S2988 1 IC,MIC5366,LDO REG,2.5V,150MA,SC70 U2590 CRITICAL HVDDLDO:FIXED
MCP 3.3V AUX/USB Power 353S2979 1 IC,LDO,TPS717,ADJ,150MA,3%,SC70,HF U2590 CRITICAL HVDDLDO:ADJ
=PP3V3_S5_MCP MCP 2.0V-3.3V RTC Power
20 8 CRITICAL
PP3V3_G3_RTC L2595 MCP 3.3V DP & USB PLL Power
240 mA 20 19 8
? uA (G3) 220-OHM-2.2A PP3V3_S0_MCP_PLL_DP_USB 17

C2550 1 1 C2551 5 mA (S0) C2552 1 1 2 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
210 mA
4.7uF 0.1uF 4.7UF 0603
20% 20% 20%
6.3V 2
CERM
10V
2 CERM 6.3V 2
CERM C2595 1 1 C2596 1 C2597
603 402 603 4.7UF 0.1UF 0.1uF
20% 20% 20%
6.3V 10V
2 R2595 2 CERM 2 10V
PLACE_NEAR=R2595.1:50 mil CERM
603 402
CERM
402
1
0.33 2
GND_MCP_PLL_DP_USB
MCP 3.3V MAC/SMU Power MIN_LINE_WIDTH=0.25 MM 5%
1/16W
MIN_NECK_WIDTH=0.25 MM
CRITICAL MF
A 20 18 8 =PP3V3_ENET_MCP_RMGT
300 mA
MCP 3.3V MAC PLL POWER L2555
VOLTAGE=0V
0402
8 =PP3V3_ENET_MCP_PLL_MAC FERR-240-OHM-200MA PP3V3_ENET_MCP_PLL_MAC 18
PAGE TITLE
C2553 1 1 C2554 20 mA 1
0402
2 MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
20 mA MCP Standard Decoupling
4.7uF 0.1uF DRAWING NUMBER SIZE
20%
6.3V 2
20%
10V
2 CERM
C2555 1 1 C2556
CERM
603 402
4.7UF 0.1UF REVISION
20% 20% R
6.3V
CERM 2 2 10V
CERM 4.4.0
603 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
25 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP GFX Core Power
22 20 =PPVCORE_SW_MCP_GFX
15350 mA (0.85V)
OMIT_TABLE
MCP 3.3V RGBDAC Power
C2600 1 1 C2601 1 C2602 1 C2603 1 C2604 1 C2605 1 C2606 1 C2607 1 C2608 1 C2609 1 C2610 1 C2611 1 C2612
10UF 4.7UF 1.0UF 1.0UF 0.22UF 0.22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF GND_MCP_DAC_P3V3 PP3V3_S0_MCP_DAC 17
20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% MIN_LINE_WIDTH=0.4 MM
6.3V 2 4V
2 X5R-1 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V
2 X5R 2 6.3V 6.3V
2 X5R 2 6.3V 2 6.3V 2 6.3V 2 6.3V MIN_NECK_WIDTH=0.2 MM 140 mA
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R 1
603-1 402 0201 0201 201 201 201 201 201 201 201 201 201 R2670 VOLTAGE=0V
MAKE_BASE=TRUE
0
5%
1/20W
MF If RGBDAC is used, requires ferrite (155S0382)
201 2
D plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap. D
If RGBDAC is not used, tie to GND.
=PP3V3R1V8_S0_MCP_IFP_VDD 17
=PP1V05_S0_MCP_PLL_IFP 17
MCP 1.05V DisplayPort Power

17 8 =PP1V05_S0_MCP_DP0_VDD
160 mA
C2640 1 1 C2641
4.7UF 0.1UF
20% 10%
4V 2 6.3V
X5R-1 2 X5R
402 201
C C
67 17 MCP_TMDS0_RSET 67 17 MCP_IFPAB_RSET
67 17 MCP_TMDS0_VPROBE 67 17 MCP_IFPAB_VPROBE NO STUFF
1 1
NO STUFF R2650 NO STUFF R2655
C2650 1
1%
1K C2655 1 1K
1%
0.1UF 1/20W 0.1UF 1/20W
10% MF 10% MF
6.3V 2 6.3V 2
X5R 2 201 X5R 2 201
201 201
B B
PAGE TITLE
MCP Graphics Support

DRAWING NUMBER SIZE

REVISION
R
4.4.0
26 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections

RTC Crystal
C2810 LPC Reset (Unbuffered)
R2810 12PF
0
RTC_CLK32K_XTALOUT 1 2 RTC_CLK32K_XTALOUT_R 1 2
19 IN
NO STUFF 5% R2881
5%
1/20W CRITICAL PLACEMENT_NOTE=Place close to U1400 33
1 MF 25V LPC_RESET_L 1 2 LPCPLUS_RESET_L
R2811 68 19 IN OUT 7 40
4
201 NP0-C0G
D 10.0M
5%
1/20W
Y2810
32.768K
201 5%
1/20W
MF R2883
D
MF 7X1.5X1.4-SM 201 33
C2811
1
0201 1 2 SMC_LRESET_L 38
2 OUT
12PF
PLACEMENT_NOTE=Place close to U1400 5%
RTC_CLK32K_XTALIN 1 2 1/20W
19 OUT MF
201
5%
25V
NP0-C0G
201
MCP 25MHz Crystal

C2815 PCIE Reset (Unbuffered)
R2815 12PF
0
MCP_CLK25M_XTALOUT 1 2 MCP_CLK25M_XTALOUT_R 1 2
19 IN
NO STUFF 5% R2891
1/20W 5%
0
1 MF 25V PCIE_RESET_L 1 2 PCA9557D_RESET_L
R2816 CRITICAL 16 IN OUT 33
3
201 NP0-C0G
MAKE_BASE=TRUE
201
4
1M 5%
5%
Y2815 NC 1/20W
2
25.0000M MF
1/20W
MF SM-3.2X2.5MM
NC R2893 201
C2816
1
201 0
2 1 2 BKLT_PLT_RST_L
12PF OUT 63
MCP_CLK25M_XTALIN 1 2 5%
19 OUT 1/20W
MF
5% 201 R2894
25V
0
NP0-C0G 1 2 AP_RESET_L
OUT 34
201
5%
1/20W
MF
201
C C
R2825
PLACEMENT_NOTE=Place close to U1400 33
68 19 LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC 38 68
IN OUT
5%
1/20W
MF R2826
201 33
1 2 LPC_CLK33M_LPCPLUS 7 40 68
OUT
5% PLACEMENT_NOTE=Place close to U1400
1/20W
MF
201
B B
R2829
22
68 19 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 38 68
PLACEMENT_NOTE=Place close to U1400 5%

1/20W
MF
201
MCP S0 PWRGD & CPU_VLD

8 =PP3V3_S5_MCPPWRGD
System Reset Circuit

1
C2850 38 IN PM_SYSRST_L
0.1UF
10%
XDP
6.3V
A 2
X5R
201
13 10 XDP_DBRESET_L 1
R2896
0
2 1
R2899
33
2
10K pull-up to 3.3V S0 inside MCP
PM_SYSRST_DEBOUNCE_L 19
IN OUT PAGE TITLE
5
5%
1/20W
MF
OMIT
R2897
1
5%
1/20W
MF
1
NO STUFF
C2899
SB Misc
1
74LVC1G08GW 201 201
1.0UF DRAWING NUMBER SIZE
ALL_SYS_PWRGD 0
57 49 38 IN B SOT353
4 MCP_PS_PWRGD 19
5%
20%
6.3V
U2850 Y OUT 1/16W 2
X5R
2
MF-LF
0201
REVISION
53 VR_PWRGOOD_DELAY R
IN A 402
SILK_PART=SYS RST
2
4.4.0
3
PLACEMENT_NOTE=Place R2897 on BOTTOM
28 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
33 29 28 27 26 PPVREF_S3_MEM_VREFCA
33 29 28 27 26 PPVREF_S3_MEM_VREFCA 33 29 28 27 26 PPVREF_S3_MEM_VREFCA
33 29 28 27 26 PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A
33 29 28 27 26 PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A
PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
33 29 28 27 26 33 29 28 27 26
C3102
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C31001 C3101
1 1
C3112
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C31101 C3111
1 1
C31201 C3121
1 1 C3122 C31301 C3131
1 1 C3132
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
0.47UF 2 0.47UF 2 2 4V 20% 20% VDD VDDQ 20% 0.47UF 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
CERM-X5R-1 CERM-X5R-1 CERM-X5R-1 0.47UF 2 0.47UF 2 2 4V 20% 20% VDD VDDQ 20% 20% 20% VDD VDDQ 20%
201 201 201 CERM-X5R-1 CERM-X5R-1 CERM-X5R-1 0.47UF 2 0.47UF 2 2 4V 0.47UF 2 0.47UF 2 2 4V
4V 4V 201 201 201 CERM-X5R-1 CERM-X5R-1 CERM-X5R-1 CERM-X5R-1 CERM-X5R-1 CERM-X5R-1
U3100 4V 4V
U3110
201
4V
201
4V
201 201
4V
201
4V
201
G1 ODT
MEM_A_ODT<0>
FBGA
OMIT_TABLE FBGA U3120 U3130
128MX8-SDRAM-1066MHZ
MT41J128M8HX-187E
66 32 27 26 15
G1 ODT
MEM_A_ODT<0> OMIT_TABLE FBGA FBGA
MT41J128M8HX-187E
66 32 27 26 15
G1 ODT
MEM_A_ODT<0> OMIT_TABLE G1 ODT
MEM_A_ODT<0> OMIT_TABLE
MT41J128M8HX-187E
MT41J128M8HX-187E
66 32 27 26 15 66 32 27 26 15
29 28 27 26 15
MEM_RESET_L N2 RESET*
29 28 27 26 15
MEM_RESET_L
N2 RESET*
R3100 240 29 28 27 26 15 N2 RESET*
MEM_RESET_L 29 28 27 26 15 N2 RESET*
MEM_RESET_L
1 H8
2 MEM_A_ZQ0 ZQ R3110 1 240 2 MEM_A_ZQ1
H8 ZQ
MF 1%1/20W201 R3120 1 240 2MEM_A_ZQ2H8 ZQ R3130 1 240 2 MEM_A_ZQ3
H8 ZQ
MF 1%1/20W201
66 32 27 26 15 MEM_A_A<0> K3 A0 DQ0 B3MEM_A_DQ<7> 15 66 MF 1%1/20W201 MF 1%1/20W201
66 32 27 26 15 MEM_A_A<0>K3 A0 DQ0 B3MEM_A_DQ<8> 15 66
66 32 27 26 15 MEM_A_A<1> L7 A1 DQ1 C7MEM_A_DQ<1> 15 66 66 32 27 26 15 MEM_A_A<0>K3 A0 DQ0 B3MEM_A_DQ<19> 15 66 66 32 27 26 15 MEM_A_A<0>K3 A0 DQ0 B3MEM_A_DQ<28> 15 66
66 32 27 26 15 MEM_A_A<1>L7 A1 DQ1 C7MEM_A_DQ<14> 15 66
66 32 27 26 15 MEM_A_A<2> L3 A2 DQ2 C2MEM_A_DQ<0> 15 66 66 32 27 26 15 MEM_A_A<1>L7 A1 DQ1 C7MEM_A_DQ<17> 15 66 66 32 27 26 15 MEM_A_A<1>L7 A1 DQ1 C7MEM_A_DQ<25> 15 66
66 32 27 26 15 MEM_A_A<3> K2 C8MEM_A_DQ<3> 66 32 27 26 15 MEM_A_A<2>L3 A2 C2MEM_A_DQ<23> 66 32 27 26 15 MEM_A_A<2>L3 A2 C2MEM_A_DQ<27>
C 66 32 27 26 15 MEM_A_A<4> L8
A3
A4
DQ3
DQ4 E3MEM_A_DQ<4>
15 66
15 66
66 32 27 26 15 MEM_A_A<3>
66 32 27 26 15 MEM_A_A<4>
K2 A3
L8 A4
DQ3
DQ4
C8MEM_A_DQ<12> 15 66
E3MEM_A_DQ<10> 15 66 66 32 27 26 15 MEM_A_A<3>K2 A3
DQ2
DQ3 C8MEM_A_DQ<20>
15 66
15 66 66 32 27 26 15 MEM_A_A<3>K2 A3
DQ2
DQ3 C8MEM_A_DQ<26>
15 66
15 66
C
66 32 27 26 15 MEM_A_A<5> L2 A5 DQ5 E8MEM_A_DQ<2> 15 66 66 32 27 26 15 MEM_A_A<4>L8 A4 DQ4 E3MEM_A_DQ<22> 15 66 66 32 27 26 15 MEM_A_A<4>L8 A4 DQ4 E3MEM_A_DQ<29> 15 66
66 32 27 26 15 MEM_A_A<5>L2 A5 DQ5 E8MEM_A_DQ<11> 15 66
66 32 27 26 15 MEM_A_A<6> M8 A6 DQ6 D2MEM_A_DQ<5> 15 66 66 32 27 26 15 MEM_A_A<5>L2 A5 DQ5 E8MEM_A_DQ<16> 15 66 66 32 27 26 15 MEM_A_A<5>L2 A5 DQ5 E8MEM_A_DQ<24> 15 66
66 32 27 26 15 MEM_A_A<6>M8 A6 DQ6 D2MEM_A_DQ<13> 15 66
66 32 27 26 15 MEM_A_A<7> M2 A7 DQ7 E7MEM_A_DQ<6> 15 66 66 32 27 26 15 MEM_A_A<6>M8 A6 DQ6 D2MEM_A_DQ<18> 15 66 66 32 27 26 15 MEM_A_A<6>M8 A6 DQ6 D2MEM_A_DQ<30> 15 66
66 32 27 26 15 MEM_A_A<7>M2 A7 DQ7 E7MEM_A_DQ<15> 15 66
66 32 27 26 15 MEM_A_A<8> N8 A8 66 32 27 26 15 MEM_A_A<7>M2 A7 DQ7 E7MEM_A_DQ<21> 15 66 66 32 27 26 15 MEM_A_A<7>M2 A7 DQ7 E7MEM_A_DQ<31> 15 66
66 32 27 26 15 MEM_A_A<8>N8 A8
66 32 27 26 15 MEM_A_A<9> M3 A9 DQS C3MEM_A_DQS_P<0> 15 66 66 32 27 26 15 MEM_A_A<8>N8 A8 66 32 27 26 15 MEM_A_A<8>N8 A8
66 32 27 26 15 MEM_A_A<9>M3 A9 DQS C3MEM_A_DQS_P<1> 15 66
66 32 27 26 15 MEM_A_A<10> H7 A10/AP 66 32 27 26 15 MEM_A_A<9>M3 A9 DQS C3MEM_A_DQS_P<2> 66 32 27 26 15 MEM_A_A<9>M3 A9 DQS C3MEM_A_DQS_P<3>
DQS* D3MEM_A_DQS_N<0> 15 66 66 32 27 26 15 H7 A10/AP
MEM_A_A<10> 15 66 15 66
66 32 27 26 15 MEM_A_A<11> M7 A11 DQS* D3MEM_A_DQS_N<1> 15 66 H7 A10/AP

66 32 27 26 15 MEM_A_A<10> H7 A10/AP
66 32 27 26 15 MEM_A_A<10>
M7 A11
66 32 27 26 15 MEM_A_A<11> DQS* D3MEM_A_DQS_N<2> 15 66 DQS* D3MEM_A_DQS_N<3> 15 66
66 32 27 26 15 MEM_A_A<12> K7 A12/BC* B7MEM_A_DM<0> M7 A11
66 32 27 26 15 MEM_A_A<11> M7 A11
66 32 27 26 15 MEM_A_A<11>
DM/TDQS 15 66 K7 A12/BC*
66 32 27 26 15 MEM_A_A<12>
B7MEM_A_DM<1>
66 32 27 26 15 MEM_A_A<13> N3 A13 DM/TDQS K7 A12/BC*
66 32 27 26 15 MEM_A_A<12> K7 A12/BC*
66 32 27 26 15 MEM_A_A<12>
N3 A13
66 32 27 26 15 MEM_A_A<13>
15 66
DM/TDQS B7MEM_A_DM<2> DM/TDQS B7MEM_A_DM<3>
TDQS* A7 NC 66 32 27 26 15 N3 A13
MEM_A_A<13> 15 66
66 32 27 26 15 N3 A13
MEM_A_A<13> 15 66
J2 BA0
MEM_A_BA<0> TDQS* A7 NC
66 32 27 26 15
66 32 27 26 15 J2 BA0
MEM_A_BA<0> TDQS* A7 NC TDQS* A7 NC
66 32 27 26 15 K8 BA1
MEM_A_BA<1> 66 32 27 26 15 J2 BA0
MEM_A_BA<0> 66 32 27 26 15 J2 BA0
MEM_A_BA<0>
66 32 27 26 15 K8 BA1
MEM_A_BA<1>
J3 BA2
MEM_A_BA<2> A3 NC K8 BA1
MEM_A_BA<1> K8 BA1
MEM_A_BA<1>
66 32 27 26 15
66 32 27 26 15 J3 BA2
MEM_A_BA<2> A3 NC 66 32 27 26 15 66 32 27 26 15
66 32 27 26 15 J3 BA2
MEM_A_BA<2> A3 NC 66 32 27 26 15 J3 BA2
MEM_A_BA<2> A3 NC
32 27 26 21 15 G9 CKE
MEM_A_CKE<0>
66 66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0>
66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0> 66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0>
66 32 27 26 15 F7 CK
MEM_A_CLK_P<0>
66 32 27 26 15 F7 CK
MEM_A_CLK_P<0>
66 32 27 26 15 G7 CK*
MEM_A_CLK_N<0> 66 32 27 26 15 F7 CK
MEM_A_CLK_P<0> 66 32 27 26 15 F7 CK
MEM_A_CLK_P<0>
NC F1 MEM_A_ODT<1> 15 26 G7 CK*
MEM_A_CLK_N<0>
27 32 66 27 26 15
66 32 NC F1 MEM_A_ODT<1> 15 26 27 32 66 66 32 27 26 15 G7 CK*
MEM_A_CLK_N<0> 66 32 27 26 15 G7 CK*
MEM_A_CLK_N<0>
66 32 27 26 15 H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 15 21 26 27 32 66
NC F1 MEM_A_ODT<1> 15 26 27 32 66
NC F1 MEM_A_ODT<1> 15 26 27
H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 15 21
H9 MEM_A_ZQ0 26 66 32 27 26 15 26 27 32 66
66 32 27 26 15 H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 15 21 26 66 32 27 26 15 H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 32 66
15 21 26
66 32 27 26 15 H1 NC
MEM_A_CS_L<1> H9 MEM_A_ZQ1 26 27 32 66 27 32 66
N7 H1 NC
MEM_A_CS_L<1> H9 MEM_A_ZQ2 26 H9 MEM_A_ZQ3 26
66 32 27 26 15
N7 H1 NC
MEM_A_CS_L<1> H1 NC
MEM_A_CS_L<1>
66 32 27 26 15 F3 RAS*
MEM_A_RAS_L J7 NC MEM_A_A<14> 15 26 27 32 66
66 32 27 26 15
N7 66 32 27 26 15
N7
F3 RAS*
MEM_A_RAS_L J7 NC MEM_A_A<14> 15
66 32 27 26 15 26 27 32 66
66 32 27 26 15 F3 RAS*
MEM_A_RAS_L J7 NC MEM_A_A<14> 15 26 66 32 27 26 15 F3 RAS*
MEM_A_RAS_L J7 NC MEM_A_A<14> 66
15 26
66 32 27 26 15 G3 CAS*
MEM_A_CAS_L 27 32 66 27 32
66 32 27 26 15 G3 CAS*
MEM_A_CAS_L
66 32 27 26 15 G3 CAS*
MEM_A_CAS_L 66 32 27 26 15 G3 CAS*
MEM_A_CAS_L
66 32 27 26 15 MEM_A_WE_LH3 WE*
66 32 27 26 15 MEM_A_WE_LH3 WE*
66 32 27 26 15 MEM_A_WE_LH3 WE* 66 32 27 26 15 MEM_A_WE_LH3 WE*
B VSS VSSQ
VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A14/A15 FOR 2G/4G MONO ONLY
CS1 IS FOR 2G DDP RANK CONTROL
PAGE TITLE
DDR3 DRAM Channel A (0-31)

DRAWING NUMBER SIZE

REVISION
R
4.4.0
31 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
29 28 27 26 PPVREF_S3_MEM_VREFCA
33 33 29 28 27 26 PPVREF_S3_MEM_VREFCA
29 28 27 26 PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A 30 27 26 8 =PPLVDDR_S3_MEM_A
33 33 29 28 27 26 PPVREF_S3_MEM_VREFDQ
PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_A
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
33 29 28 27 26 33 29 28 27 26
C3202
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C32001 C3201
1 1
C3212
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C32101 C3211
1 1
C32201 C3221
1 1 C3222 C32301 C3231
1 1 C3232
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
U3200 4V 4V
U3210
201
4V
201
4V
201 201
4V
201
4V
201
G1 ODT
MEM_A_ODT<0>
FBGA
MT41J128M8HX-187E
66 32 27 26 15
G1 ODT
MEM_A_ODT<0> OMIT_TABLE FBGA FBGA
MT41J128M8HX-187E
66 32 27 26 15
G1 ODT
MEM_A_ODT<0> OMIT_TABLE G1 ODT
MEM_A_ODT<0> OMIT_TABLE
MT41J128M8HX-187E
MT41J128M8HX-187E
66 32 27 26 15 66 32 27 26 15
29 28 27 26 15
MEM_RESET_LN2 RESET*
29 28 27 26 15
MEM_RESET_L
N2 RESET* MEM_RESET_L
N2 RESET*
R3200 1 240 2 MEM_A_ZQ8
H8 ZQ 240 MEM_A_ZQ9
29 28 27 26 15 29 28 27 26 15
R3210 1 2 H8
MF 1%1/20W201 ZQ R3220 1 240 2 MEM_A_ZQ10
H8 ZQ R3230 1 240 2 MEM_A_ZQ11
H8 ZQ
MF 1%1/20W201
66 32 27 26 15 MEM_A_A<0> K3 A0 DQ0 B3MEM_A_DQ<39> 15 66 MF 1%1/20W201 MF 1%1/20W201
66 32 27 26 15 MEM_A_A<0>K3 A0 DQ0 B3MEM_A_DQ<41> 15 66
66 32 27 26 15 MEM_A_A<1> L7 A1 DQ1 C7MEM_A_DQ<33> 15 66 66 32 27 26 15 MEM_A_A<0>K3 A0 DQ0 B3MEM_A_DQ<50> 15 66 66 32 27 26 15 MEM_A_A<0>K3 A0 DQ0 B3MEM_A_DQ<59> 15 66
66 32 27 26 15 MEM_A_A<2> L3 A2 DQ2 C2MEM_A_DQ<34> 15 66 66 32 27 26 15 MEM_A_A<1>L7 A1 DQ1 C7MEM_A_DQ<49> 15 66 66 32 27 26 15 MEM_A_A<1>L7 A1 DQ1 C7MEM_A_DQ<57> 15 66
66 32 27 26 15 MEM_A_A<3> K2 A3 DQ3 C8MEM_A_DQ<35> 15 66 66 32 27 26 15 MEM_A_A<2>L3 A2 DQ2 C2MEM_A_DQ<55> 15 66 66 32 27 26 15 MEM_A_A<2>L3 A2 DQ2 C2MEM_A_DQ<63> 15 66
66 32 27 26 15 MEM_A_A<3>K2 C8MEM_A_DQ<45>
C 66 32 27 26 15 MEM_A_A<4>
66 32 27 26 15 MEM_A_A<5>
L8 A4
L2 A5
DQ4
DQ5
E3MEM_A_DQ<36>
E8MEM_A_DQ<37>
15 66
15 66
66 32 27 26 15 MEM_A_A<4>L8
A3
A4
DQ3
DQ4 E3MEM_A_DQ<43>
15 66
15 66
66 32 27 26 15 MEM_A_A<3>
66 32 27 26 15 MEM_A_A<4>
K2 A3
L8 A4
DQ3
DQ4
C8MEM_A_DQ<51>
E3MEM_A_DQ<48>
15 66
15 66
66 32 27 26 15 MEM_A_A<3>
66 32 27 26 15 MEM_A_A<4>
K2 A3
L8 A4
DQ3
DQ4
C8MEM_A_DQ<56>
E3MEM_A_DQ<58>
15 66
15 66
C
66 32 27 26 15 MEM_A_A<5>L2 A5 DQ5 E8MEM_A_DQ<40> 15 66
66 32 27 26 15 MEM_A_A<6> M8 A6 DQ6 D2MEM_A_DQ<38> 15 66 66 32 27 26 15 MEM_A_A<5>L2 A5 DQ5 E8MEM_A_DQ<53> 15 66 66 32 27 26 15 MEM_A_A<5>L2 A5 DQ5 E8MEM_A_DQ<61> 15 66
66 32 27 26 15 MEM_A_A<6>M8 A6 DQ6 D2MEM_A_DQ<47> 15 66
66 32 27 26 15 MEM_A_A<7> M2 A7 DQ7 E7MEM_A_DQ<32> 15 66 66 32 27 26 15 MEM_A_A<6>M8 A6 DQ6 D2MEM_A_DQ<54> 15 66 66 32 27 26 15 MEM_A_A<6>M8 A6 DQ6 D2MEM_A_DQ<62> 15 66
66 32 27 26 15 MEM_A_A<7>M2 A7 DQ7 E7MEM_A_DQ<42> 15 66
66 32 27 26 15 MEM_A_A<8> N8 A8 66 32 27 26 15 MEM_A_A<7>M2 A7 DQ7 E7MEM_A_DQ<52> 15 66 66 32 27 26 15 MEM_A_A<7>M2 A7 DQ7 E7MEM_A_DQ<60> 15 66
66 32 27 26 15 MEM_A_A<8>N8 A8
66 32 27 26 15 MEM_A_A<9> M3 A9 DQS C3MEM_A_DQS_P<4> 66 32 27 26 15 MEM_A_A<8>N8 A8 66 32 27 26 15 MEM_A_A<8>N8 A8
15 66
66 32 27 26 15 MEM_A_A<9>M3 A9 DQS C3MEM_A_DQS_P<5> 15 66
66 32 27 26 15 MEM_A_A<10>H7 A10/AP 66 32 27 26 15 MEM_A_A<9>M3 A9 DQS C3MEM_A_DQS_P<6> 15 66 66 32 27 26 15 MEM_A_A<9>M3 A9 DQS C3MEM_A_DQS_P<7> 15 66
DQS* D3MEM_A_DQS_N<4> H7
66 32 27 26 15 MEM_A_A<10> A10/AP
66 32 27 26 15 MEM_A_A<11>M7 A11 15 66
DQS* D3MEM_A_DQS_N<5> 15 66 66 32 27 26 15 H7 A10/AP
MEM_A_A<10> 66 32 27 26 15 H7 A10/AP
MEM_A_A<10>
M7
66 32 27 26 15 MEM_A_A<11> A11 DQS* D3MEM_A_DQS_N<6> 15 66 DQS* D3MEM_A_DQS_N<7> 15 66
66 32 27 26 15 MEM_A_A<12>K7 A12/BC* M7 A11
66 32 27 26 15 MEM_A_A<11> M7 A11
66 32 27 26 15 MEM_A_A<11>
DM/TDQS B7MEM_A_DM<4> 15 66 K7
66 32 27 26 15 MEM_A_A<12> A12/BC*
66 32 27 26 15 MEM_A_A<13>N3 A13 DM/TDQS B7MEM_A_DM<5> 15 66 K7 A12/BC*
66 32 27 26 15 MEM_A_A<12> K7 A12/BC*
66 32 27 26 15 MEM_A_A<12>
N3
66 32 27 26 15 MEM_A_A<13> A13 DM/TDQS B7MEM_A_DM<6> DM/TDQS B7MEM_A_DM<7>
TDQS* A7 NC N3 A13
66 32 27 26 15 MEM_A_A<13>
15 66
N3 A13
66 32 27 26 15 MEM_A_A<13>
15 66
66 32 27 26 15 J2 BA0
MEM_A_BA<0> TDQS* A7 NC
66 32 27 26 15 J2 BA0
MEM_A_BA<0> TDQS* A7 NC TDQS* A7 NC
66 32 27 26 15 K8 BA1
MEM_A_BA<1> NC 66 32 27 26 15 J2 BA0
MEM_A_BA<0> 66 32 27 26 15 J2 BA0
MEM_A_BA<0>
66 32 27 26 15 K8 BA1
MEM_A_BA<1> NC
66 32 27 26 15 J3 BA2
MEM_A_BA<2> A3 NC 66 32 27 26 15 K8 BA1
MEM_A_BA<1> NC 66 32 27 26 15 K8 BA1
MEM_A_BA<1> NC
J3 BA2
MEM_A_BA<2> A3 NC
NC
66 32 27 26 15
66 32 27 26 15 J3 BA2
MEM_A_BA<2> A3 NC 66 32 27 26 15 J3 BA2
MEM_A_BA<2> A3 NC
66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0> NC
NC 66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0> NC NC
NC 66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0> 66 32 27 26 21 15 G9 CKE
MEM_A_CKE<0>
66 32 27 26 15 F7 CK
MEM_A_CLK_P<0> NC NC NC
66 32 27 26 15 F7 CK
MEM_A_CLK_P<0> NC
66 32 27 26 15 G7 CK*
MEM_A_CLK_N<0>
F1 MEM_A_ODT<1> 66 32 27 26 15 F7 CK
MEM_A_CLK_P<0> NC 66 32 27 26 15 F7 CK
MEM_A_CLK_P<0> NC
NC 15 26 27 66 32 27 26 15 G7 CK*
MEM_A_CLK_N<0>
32 66 NC F1 MEM_A_ODT<1> 15 G7 CK*
MEM_A_CLK_N<0> G7 CK*
MEM_A_CLK_N<0>
66 32 27 26 15 H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 15 21 26 27 32 66
26 27 32 66 66 32 27 26 15 NC F1 MEM_A_ODT<1> 66 32 27 26 15
15 26 27 32 66
NC F1 MEM_A_ODT<1> 15 26 27 32
66 32 27 26 15 H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 15 21 26 27 32 66 66
H9 MEM_A_ZQ8 27 H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> H2 CS*
MEM_A_CS_L<0> F9 MEM_A_CKE<1> 15
66 32 27 26 15 H1 NC
MEM_A_CS_L<1> H9 MEM_A_ZQ9 27 66 32 27 26 15 15 21 26 27 32 66 26 15
66 32 27 32
21 26 27
66
N7 66 32 27 26 15 H1 NC
MEM_A_CS_L<1> H9 MEM_A_ZQ10 27 H9 MEM_A_ZQ11 27
N7 H1 NC
MEM_A_CS_L<1> H1 NC
MEM_A_CS_L<1>
F3 RAS*
MEM_A_RAS_L J7 NC 66 32 27 26 15
N7 66 32 27 26 15
N7
66 32 27 26 15
66 32 27 26 15 F3 RAS*
MEM_A_RAS_L J7 NC
MEM_A_A<14> 15 26 27 32 66 66 32 27 26 15 F3 RAS*
MEM_A_RAS_L J7 NC 66 32 27 26 15 F3 RAS*
MEM_A_RAS_L J7 NC
66 32 27 26 15 G3 CAS*
MEM_A_CAS_L MEM_A_A<14> 15 26 27 32 66
66 32 27 26 15 G3 CAS*
MEM_A_CAS_L MEM_A_A<14> 15 26 27 32 66 MEM_A_A<14> 15 26 27
66 32 27 26 15 G3 CAS*
MEM_A_CAS_L 66 32 27 26 15 G3 CAS*
MEM_A_CAS_L 32 66
66 32 27 26 15 MEM_A_WE_LH3 WE*
66 32 27 26 15 MEM_A_WE_LH3 WE*
VSS VSSQ 66 32 27 26 15 MEM_A_WE_LH3 WE* 66 32 27 26 15 MEM_A_WE_LH3 WE*
B VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
PAGE TITLE
DDR3 DRAM Channel A (32-63)

DRAWING NUMBER SIZE

REVISION
R
4.4.0
32 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
33 29 28 27 26 PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_B 31 29 28 8 =PPLVDDR_S3_MEM_B
33 29 28 27 26 PPVREF_S3_MEM_VREFDQ 31 29 28 8 =PPLVDDR_S3_MEM_B 31 29 28 8 =PPLVDDR_S3_MEM_B
PPVREF_S3_MEM_VREFDQ PPVREF_S3_MEM_VREFDQ
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
33 29 28 27 26 33 29 28 27 26
C3302
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C33001 C3301
1 1
C3312
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C33101 C3311
1 1
C33201 C3321
1 1 C3322 C33301 C3331
1 1 C3332
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
U3300 4V 4V
U3310
201
4V
201
4V
201 201
4V
201
4V
201
G1 ODT
MEM_B_ODT<0>
FBGA
MT41J128M8HX-187E
66 32 29 28 15
G1 ODT
MEM_B_ODT<0> OMIT_TABLE FBGA FBGA
MT41J128M8HX-187E
66 32 29 28 15
G1 ODT
MEM_B_ODT<0> OMIT_TABLE G1 ODT
MEM_B_ODT<0> OMIT_TABLE
MT41J128M8HX-187E
MT41J128M8HX-187E
66 32 29 28 15 66 32 29 28 15
29 28 27 26 15
MEM_RESET_L N2 RESET*
29 28 27 26 15 MEM_RESET_L
N2 RESET*
R3300 240 29 28 27 26 15 N2 RESET*
MEM_RESET_L 29 28 27 26 15 N2 RESET*
MEM_RESET_L
1 H8
2 MEM_B_ZQ0 ZQ R3310 1 240 2 MEM_B_ZQ1
H8 ZQ
MF 1%1/20W201 R3320 1 240 2MEM_B_ZQ2H8 ZQ R3330 1 240 2 MEM_B_ZQ3
H8 ZQ
MF 1%1/20W201
66 32 29 28 15 MEM_B_A<0> K3 A0 DQ0 B3MEM_B_DQ<1> 15 66 MF 1%1/20W201 MF 1%1/20W201
66 32 29 28 15 MEM_B_A<0>K3 A0 DQ0 B3MEM_B_DQ<14> 15 66
66 32 29 28 15 MEM_B_A<1> L7 A1 DQ1 C7MEM_B_DQ<4> 15 66 66 32 29 28 15 MEM_B_A<0>K3 A0 DQ0 B3MEM_B_DQ<16> 15 66 66 32 29 28 15 MEM_B_A<0>K3 A0 DQ0 B3MEM_B_DQ<30> 15 66
66 32 29 28 15 MEM_B_A<1>L7 A1 DQ1 C7MEM_B_DQ<9> 15 66
66 32 29 28 15 MEM_B_A<2> L3 A2 DQ2 C2MEM_B_DQ<2> 15 66 66 32 29 28 15 MEM_B_A<1>L7 A1 DQ1 C7MEM_B_DQ<22> 15 66 66 32 29 28 15 MEM_B_A<1>L7 A1 DQ1 C7MEM_B_DQ<29> 15 66
MEM_B_A<3> K2 C8MEM_B_DQ<3> 66 32 29 28 15 MEM_B_A<2>L3 A2 C2MEM_B_DQ<21> 66 32 29 28 15 MEM_B_A<2>L3 A2 C2MEM_B_DQ<24>
C 66 32 29 28 15
66 32 29 28 15 MEM_B_A<4> L8
A3
A4
DQ3
DQ4 E3MEM_B_DQ<0>
15 66
15 66
66 32 29 28 15 MEM_B_A<3>
66 32 29 28 15 MEM_B_A<4>
K2 A3
L8 A4
DQ3
DQ4
C8MEM_B_DQ<12> 15 66
E3MEM_B_DQ<10> 15 66 66 32 29 28 15 MEM_B_A<3>K2 A3
DQ2
DQ3 C8MEM_B_DQ<20>
15 66
15 66 66 32 29 28 15 MEM_B_A<3>K2 A3
DQ2
DQ3 C8MEM_B_DQ<28>
15 66
15 66
C
66 32 29 28 15 MEM_B_A<5> L2 A5 DQ5 E8MEM_B_DQ<5> 15 66 66 32 29 28 15 MEM_B_A<4>L8 A4 DQ4 E3MEM_B_DQ<19> 15 66 66 32 29 28 15 MEM_B_A<4>L8 A4 DQ4 E3MEM_B_DQ<27> 15 66
66 32 29 28 15 MEM_B_A<5>L2 A5 DQ5 E8MEM_B_DQ<13> 15 66
66 32 29 28 15 MEM_B_A<6> M8 A6 DQ6 D2MEM_B_DQ<6> 15 66 66 32 29 28 15 MEM_B_A<5>L2 A5 DQ5 E8MEM_B_DQ<18> 15 66 66 32 29 28 15 MEM_B_A<5>L2 A5 DQ5 E8MEM_B_DQ<25> 15 66
66 32 29 28 15 MEM_B_A<6>M8 A6 DQ6 D2MEM_B_DQ<11> 15 66
66 32 29 28 15 MEM_B_A<7> M2 A7 DQ7 E7MEM_B_DQ<7> 15 66 66 32 29 28 15 MEM_B_A<6>M8 A6 DQ6 D2MEM_B_DQ<17> 15 66 66 32 29 28 15 MEM_B_A<6>M8 A6 DQ6 D2MEM_B_DQ<31> 15 66
66 32 29 28 15 MEM_B_A<7>M2 A7 DQ7 E7MEM_B_DQ<15> 15 66
66 32 29 28 15 MEM_B_A<8> N8 A8 66 32 29 28 15 MEM_B_A<7>M2 A7 DQ7 E7MEM_B_DQ<23> 15 66 66 32 29 28 15 MEM_B_A<7>M2 A7 DQ7 E7MEM_B_DQ<26> 15 66
66 32 29 28 15 MEM_B_A<8>N8 A8
66 32 29 28 15 MEM_B_A<9> M3 A9 DQS C3MEM_B_DQS_P<0> 15 66 66 32 29 28 15 MEM_B_A<8>N8 A8 66 32 29 28 15 MEM_B_A<8>N8 A8
66 32 29 28 15 MEM_B_A<9>M3 A9 DQS C3MEM_B_DQS_P<1> 15 66
66 32 29 28 15 MEM_B_A<10> H7 A10/AP 66 32 29 28 15 MEM_B_A<9>M3 A9 DQS C3MEM_B_DQS_P<2> 66 32 29 28 15 MEM_B_A<9>M3 A9 DQS C3MEM_B_DQS_P<3>
DQS* D3MEM_B_DQS_N<0> 15 66 66 32 29 28 15 H7 A10/AP
MEM_B_A<10> 15 66 15 66
66 32 29 28 15 MEM_B_A<11> M7 A11 DQS* D3MEM_B_DQS_N<1> 15 66 H7 A10/AP

66 32 29 28 15 MEM_B_A<10> H7 A10/AP
66 32 29 28 15 MEM_B_A<10>
M7 A11
66 32 29 28 15 MEM_B_A<11> DQS* D3MEM_B_DQS_N<2> 15 66 DQS* D3MEM_B_DQS_N<3> 15 66
66 32 29 28 15 MEM_B_A<12> K7 A12/BC* B7MEM_B_DM<0> M7 A11
66 32 29 28 15 MEM_B_A<11> M7 A11
66 32 29 28 15 MEM_B_A<11>
DM/TDQS 15 66 K7 A12/BC*
66 32 29 28 15 MEM_B_A<12>
B7MEM_B_DM<1>
66 32 29 28 15 MEM_B_A<13> N3 A13 DM/TDQS K7 A12/BC*
66 32 29 28 15 MEM_B_A<12> K7 A12/BC*
66 32 29 28 15 MEM_B_A<12>
N3 A13
66 32 29 28 15 MEM_B_A<13>
15 66
DM/TDQS B7MEM_B_DM<2> DM/TDQS B7MEM_B_DM<3>
TDQS* A7 NC 66 32 29 28 15 N3 A13
MEM_B_A<13> 15 66
66 32 29 28 15 N3 A13
MEM_B_A<13> 15 66
J2 BA0
MEM_B_BA<0> TDQS* A7 NC
66 32 29 28 15
66 32 29 28 15 J2 BA0
MEM_B_BA<0> TDQS* A7 NC TDQS* A7 NC
66 32 29 28 15 K8 BA1
MEM_B_BA<1> 66 32 29 28 15 J2 BA0
MEM_B_BA<0> 66 32 29 28 15 J2 BA0
MEM_B_BA<0>
66 32 29 28 15 K8 BA1
MEM_B_BA<1>
J3 BA2
MEM_B_BA<2> A3 NC K8 BA1
MEM_B_BA<1> K8 BA1
MEM_B_BA<1>
66 32 29 28 15
66 32 29 28 15 J3 BA2
MEM_B_BA<2> A3 NC 66 32 29 28 15 66 32 29 28 15
66 32 29 28 15 J3 BA2
MEM_B_BA<2> A3 NC 66 32 29 28 15 J3 BA2
MEM_B_BA<2> A3 NC
32 29 28 21 15 G9 CKE
MEM_B_CKE<0>
66 66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0>
66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0> 66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0>
66 32 29 28 15 F7 CK
MEM_B_CLK_P<0>
66 32 29 28 15 F7 CK
MEM_B_CLK_P<0>
66 32 29 28 15 G7 CK*
MEM_B_CLK_N<0> 66 32 29 28 15 F7 CK
MEM_B_CLK_P<0> 66 32 29 28 15 F7 CK
MEM_B_CLK_P<0>
NC F1 MEM_B_ODT<1> 15 28 G7 CK*
MEM_B_CLK_N<0>
29 32 66 29 28 15
66 32 NC F1 MEM_B_ODT<1> 15 28 29 32 66 66 32 29 28 15 G7 CK*
MEM_B_CLK_N<0> 66 32 29 28 15 G7 CK*
MEM_B_CLK_N<0>
66 32 29 28 15 H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 15 21 28 29 32 66
NC F1 MEM_B_ODT<1> 15 28 29 32 66
NC F1 MEM_B_ODT<1> 15 28 29
H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 15 21
H9 MEM_B_ZQ0 28 66 32 29 28 15 28 29 32 66
66 32 29 28 15 H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 15 21 28 29 32 66 28 15 H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 32 66
15 21 28
66 32 29 28 15 H1 NC
MEM_B_CS_L<1> H9 MEM_B_ZQ1 28 66 32 29 29 32 66
N7 H1 NC
MEM_B_CS_L<1> H9 MEM_B_ZQ2 28 H9 MEM_B_ZQ3 28
66 32 29 28 15
N7 H1 NC
MEM_B_CS_L<1> H1 NC
MEM_B_CS_L<1>
66 32 29 28 15 F3 RAS*
MEM_B_RAS_L J7 NC MEM_B_A<14> 15 28 29 32 66
66 32 29 28 15
N7 66 32 29 28 15
N7
F3 RAS*
MEM_B_RAS_L J7 NC MEM_B_A<14> 15
66 32 29 28 15 28 29 32 66
66 32 29 28 15 F3 RAS*
MEM_B_RAS_L J7 NC MEM_B_A<14> 15 28 29 32 66 28 15 F3 RAS*
MEM_B_RAS_L J7 NC MEM_B_A<14> 66
15 28
66 32 29 28 15 G3 CAS*
MEM_B_CAS_L 66 32 29 29 32
66 32 29 28 15 G3 CAS*
MEM_B_CAS_L
66 32 29 28 15 G3 CAS*
MEM_B_CAS_L 66 32 29 28 15 G3 CAS*
MEM_B_CAS_L
66 32 29 28 15 MEM_B_WE_LH3 WE*
66 32 29 28 15 MEM_B_WE_LH3 WE*
66 32 29 28 15 MEM_B_WE_LH3 WE* 66 32 29 28 15 MEM_B_WE_LH3 WE*
B VSS VSSQ
VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
PAGE TITLE
DDR3 DRAM Channel B (0-31)

DRAWING NUMBER SIZE

REVISION
R
4.4.0
33 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
29 28 27 26 PPVREF_S3_MEM_VREFCA
33 33 29 28 27 26 PPVREF_S3_MEM_VREFCA
29 28 27 26 PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_B 31 29 28 8 =PPLVDDR_S3_MEM_B
33 33 29 28 27 26 PPVREF_S3_MEM_VREFDQ 31 29 28 8 =PPLVDDR_S3_MEM_B
PPVREF_S3_MEM_VREFDQ =PPLVDDR_S3_MEM_B PPVREF_S3_MEM_VREFDQ
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
33 29 28 27 26 33 29 28 27 26
C3402
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
C34001 C3401
1 1
C3412
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
0.47UF C34101 1
C3411 1
C34201 C3421
1 1 C3422 C34301 C3431
1 1 C3432
VREFDQ
VREFCA
20% 20% VDD VDDQ 20% 0.47UF
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
U3400 4V 4V
U3410
201
4V
201
4V
201 201
4V
201
4V
201
G1 ODT
MEM_B_ODT<0>
FBGA
MT41J128M8HX-187E
66 32 29 28 15
G1 ODT
MEM_B_ODT<0> OMIT_TABLE FBGA FBGA
MT41J128M8HX-187E
66 32 29 28 15
G1 ODT
MEM_B_ODT<0> OMIT_TABLE G1 ODT
MEM_B_ODT<0> OMIT_TABLE
MT41J128M8HX-187E
MT41J128M8HX-187E
66 32 29 28 15 66 32 29 28 15
29 28 27 26 15
MEM_RESET_LN2 RESET*
29 28 27 26 15
MEM_RESET_L
N2 RESET*
R3400 1 240 2 MEM_B_ZQ8
H8 ZQ 240 MEM_B_ZQ9
29 28 27 26 15 29 28 27 26 15
R3410 1 2 H8
MF 1%1/20W201 ZQ R3420 1 240 2 MEM_B_ZQ10
H8 ZQ R3430 1 240 2 MEM_B_ZQ11
H8 ZQ
MF 1%1/20W201
66 32 29 28 15 MEM_B_A<0> K3 A0 DQ0 B3MEM_B_DQ<38> 15 66 MF 1%1/20W201 MF 1%1/20W201
66 32 29 28 15 MEM_B_A<0>K3 A0 DQ0 B3MEM_B_DQ<43> 15 66
66 32 29 28 15 MEM_B_A<1> L7 A1 DQ1 C7MEM_B_DQ<33> 15 66 66 32 29 28 15 MEM_B_A<0>K3 A0 DQ0 B3MEM_B_DQ<49> 15 66 66 32 29 28 15 MEM_B_A<0>K3 A0 DQ0 B3MEM_B_DQ<61> 15 66
66 32 29 28 15 MEM_B_A<2> L3 A2 DQ2 C2MEM_B_DQ<35> 15 66 66 32 29 28 15 MEM_B_A<1>L7 A1 DQ1 C7MEM_B_DQ<53> 15 66 66 32 29 28 15 MEM_B_A<1>L7 A1 DQ1 C7MEM_B_DQ<57> 15 66
66 32 29 28 15 MEM_B_A<3> K2 A3 DQ3 C8MEM_B_DQ<32> 15 66 66 32 29 28 15 MEM_B_A<2>L3 A2 DQ2 C2MEM_B_DQ<55> 15 66 66 32 29 28 15 MEM_B_A<2>L3 A2 DQ2 C2MEM_B_DQ<58> 15 66
66 32 29 28 15 MEM_B_A<3>K2 C8MEM_B_DQ<47>
C 66 32 29 28 15 MEM_B_A<4>
66 32 29 28 15 MEM_B_A<5>
L8 A4
L2 A5
DQ4
DQ5
E3MEM_B_DQ<37>
E8MEM_B_DQ<36>
15 66
15 66
66 32 29 28 15 MEM_B_A<4>L8
A3
A4
DQ3
DQ4 E3MEM_B_DQ<44>
15 66
15 66
66 32 29 28 15 MEM_B_A<3>
66 32 29 28 15 MEM_B_A<4>
K2 A3
L8 A4
DQ3
DQ4
C8MEM_B_DQ<48>
E3MEM_B_DQ<50>
15 66
15 66
66 32 29 28 15 MEM_B_A<3>
66 32 29 28 15 MEM_B_A<4>
K2 A3
L8 A4
DQ3
DQ4
C8MEM_B_DQ<56>
E3MEM_B_DQ<59>
15 66
15 66
C
66 32 29 28 15 MEM_B_A<5>L2 A5 DQ5 E8MEM_B_DQ<45> 15 66
66 32 29 28 15 MEM_B_A<6> M8 A6 DQ6 D2MEM_B_DQ<34> 15 66 66 32 29 28 15 MEM_B_A<5>L2 A5 DQ5 E8MEM_B_DQ<51> 15 66 66 32 29 28 15 MEM_B_A<5>L2 A5 DQ5 E8MEM_B_DQ<60> 15 66
66 32 29 28 15 MEM_B_A<6>M8 A6 DQ6 D2MEM_B_DQ<46> 15 66
66 32 29 28 15 MEM_B_A<7> M2 A7 DQ7 E7MEM_B_DQ<39> 15 66 66 32 29 28 15 MEM_B_A<6>M8 A6 DQ6 D2MEM_B_DQ<54> 15 66 66 32 29 28 15 MEM_B_A<6>M8 A6 DQ6 D2MEM_B_DQ<62> 15 66
66 32 29 28 15 MEM_B_A<7>M2 A7 DQ7 E7MEM_B_DQ<40> 15 66
66 32 29 28 15 MEM_B_A<8> N8 A8 66 32 29 28 15 MEM_B_A<7>M2 A7 DQ7 E7MEM_B_DQ<52> 15 66 66 32 29 28 15 MEM_B_A<7>M2 A7 DQ7 E7MEM_B_DQ<63> 15 66
66 32 29 28 15 MEM_B_A<8>N8 A8
66 32 29 28 15 MEM_B_A<9> M3 A9 DQS C3MEM_B_DQS_P<4> 66 32 29 28 15 MEM_B_A<8>N8 A8 66 32 29 28 15 MEM_B_A<8>N8 A8
15 66
66 32 29 28 15 MEM_B_A<9>M3 A9 DQS C3MEM_B_DQS_P<5> 15 66
66 32 29 28 15 MEM_B_A<10>H7 A10/AP 66 32 29 28 15 MEM_B_A<9>M3 A9 DQS C3MEM_B_DQS_P<6> 15 66 66 32 29 28 15 MEM_B_A<9>M3 A9 DQS C3MEM_B_DQS_P<7> 15 66
DQS* D3MEM_B_DQS_N<4> H7
66 32 29 28 15 MEM_B_A<10> A10/AP
66 32 29 28 15 MEM_B_A<11>M7 A11 15 66
DQS* D3MEM_B_DQS_N<5> 15 66 66 32 29 28 15 H7 A10/AP
MEM_B_A<10> 66 32 29 28 15 H7 A10/AP
MEM_B_A<10>
M7
66 32 29 28 15 MEM_B_A<11> A11 DQS* D3MEM_B_DQS_N<6> 15 66 DQS* D3MEM_B_DQS_N<7> 15 66
66 32 29 28 15 MEM_B_A<12>K7 A12/BC* M7 A11
66 32 29 28 15 MEM_B_A<11> M7 A11
66 32 29 28 15 MEM_B_A<11>
DM/TDQS B7MEM_B_DM<4> 15 66 K7
66 32 29 28 15 MEM_B_A<12> A12/BC*
66 32 29 28 15 MEM_B_A<13>N3 A13 DM/TDQS B7MEM_B_DM<5> 15 66 K7 A12/BC*
66 32 29 28 15 MEM_B_A<12> K7 A12/BC*
66 32 29 28 15 MEM_B_A<12>
N3
66 32 29 28 15 MEM_B_A<13> A13 DM/TDQS B7MEM_B_DM<6> DM/TDQS B7MEM_B_DM<7>
TDQS* A7 NC N3 A13
66 32 29 28 15 MEM_B_A<13>
15 66
N3 A13
66 32 29 28 15 MEM_B_A<13>
15 66
66 32 29 28 15 J2 BA0
MEM_B_BA<0> TDQS* A7 NC
66 32 29 28 15 J2 BA0
MEM_B_BA<0> TDQS* A7 NC TDQS* A7 NC
66 32 29 28 15 K8 BA1
MEM_B_BA<1> 66 32 29 28 15 J2 BA0
MEM_B_BA<0> 66 32 29 28 15 J2 BA0
MEM_B_BA<0>
66 32 29 28 15 K8 BA1
MEM_B_BA<1>
66 32 29 28 15 J3 BA2
MEM_B_BA<2> A3 NC 66 32 29 28 15 K8 BA1
MEM_B_BA<1> 66 32 29 28 15 K8 BA1
MEM_B_BA<1>
J3 BA2
MEM_B_BA<2> A3 NC
66 32 29 28 15
66 32 29 28 15 J3 BA2
MEM_B_BA<2> A3 NC 66 32 29 28 15 J3 BA2
MEM_B_BA<2> A3 NC
66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0>
66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0>
66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0> 66 32 29 28 21 15 G9 CKE
MEM_B_CKE<0>
66 32 29 28 15 F7 CK
MEM_B_CLK_P<0>
66 32 29 28 15 F7 CK
MEM_B_CLK_P<0>
66 32 29 28 15 G7 CK*
MEM_B_CLK_N<0>
F1 MEM_B_ODT<1> 66 32 29 28 15 F7 CK
MEM_B_CLK_P<0> 66 32 29 28 15 F7 CK
MEM_B_CLK_P<0>
NC 15 28 29 32 66 29 28 15 G7 CK*
MEM_B_CLK_N<0>
66 32 NC F1 MEM_B_ODT<1> 15 G7 CK*
MEM_B_CLK_N<0> G7 CK*
MEM_B_CLK_N<0>
66 32 29 28 15 H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 15 21 28 29 32 66
28 29 32 66 66 32 29 28 15 NC F1 MEM_B_ODT<1> 66 32 29 28 15
15 28 29 32 66
NC F1 MEM_B_ODT<1> 15 28 29 32
66 32 29 28 15 H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 15 21 28 29 32 66 66
H9 MEM_B_ZQ8 29 H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> H2 CS*
MEM_B_CS_L<0> F9 MEM_B_CKE<1> 15
66 32 29 28 15 H1 NC
MEM_B_CS_L<1> H9 MEM_B_ZQ9 29 66 32 29 28 15 15 21 28 66 32 29 28 15
29 32 66 32
21 28 29
66
N7 66 32 29 28 15 H1 NC
MEM_B_CS_L<1> H9 MEM_B_ZQ10 29 H9 MEM_B_ZQ11 29
N7 H1 NC
MEM_B_CS_L<1> H1 NC
MEM_B_CS_L<1>
F3 RAS*
MEM_B_RAS_L J7 NC 66 32 29 28 15
N7 66 32 29 28 15
N7
66 32 29 28 15
66 32 29 28 15 F3 RAS*
MEM_B_RAS_L J7 NC
MEM_B_A<14> 15 28 29 32 66 66 32 29 28 15 F3 RAS*
MEM_B_RAS_L J7 NC 66 32 29 28 15 F3 RAS*
MEM_B_RAS_L J7 NC
66 32 29 28 15 G3 CAS*
MEM_B_CAS_L MEM_B_A<14> 15 28 29 32 66
66 32 29 28 15 G3 CAS*
MEM_B_CAS_L MEM_B_A<14> 15 28 29 32 66 MEM_B_A<14> 15 28 29
66 32 29 28 15 G3 CAS*
MEM_B_CAS_L 66 32 29 28 15 G3 CAS*
MEM_B_CAS_L 32 66
66 32 29 28 15 MEM_B_WE_LH3 WE*
66 32 29 28 15 MEM_B_WE_LH3 WE*
VSS VSSQ 66 32 29 28 15 MEM_B_WE_LH3 WE* 66 32 29 28 15 MEM_B_WE_LH3 WE*
B VSS VSSQ
VSS VSSQ VSS VSSQ B
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
PAGE TITLE
DDR3 DRAM Channel B (32-63)

DRAWING NUMBER SIZE

REVISION
R
4.4.0
34 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 30 27 26 8 =PPLVDDR_S3_MEM_A 30 27 26 8 =PPLVDDR_S3_MEM_A D
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
1 C3500
2.2UF
1 C3510
2.2UF
1 C3520
2.2UF
1 C3530
2.2UF
1 C3540
2.2UF
1 C3550
2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE

1 C3501
2.2UF
1 C3511
2.2UF
1 C3521
2.2UF
1 C3531
2.2UF
1 C3541
2.2UF
1 C3551
2.2UF
20% 20% 20% 20% 20% 20%
6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
1 C3512
2.2UF
1 C3542
2.2UF
2 CAPS ALONG PACKAGE EDGE 20% 20% 2 CAPS ALONG PACKAGE EDGE
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
C C
OMIT_TABLE
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
1 C3504
2.2UF
1 C3514
2.2UF
1 C3524
2.2UF
1 C3534
2.2UF
1 C3544
2.2UF
1 C3554
2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT_TABLE
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
1 C3505
2.2UF
1 C3515
2.2UF
1 C3525
2.2UF
1 C3535
2.2UF
1 C3545
2.2UF
1 C3555
2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
1 C3516
2.2UF
1 C3546
2.2UF
20% 20%
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
B B
PAGE TITLE
DDR BYPASSING 1
DRAWING NUMBER SIZE

REVISION
R
4.4.0
35 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 31 29 28 8 =PPLVDDR_S3_MEM_B 31 29 28 8 =PPLVDDR_S3_MEM_B D
OMIT_TABLE OMIT_TABLE OMIT_TABLE
OMIT_TABLE
C3600
2.2UF
1 C3610
2.2UF
1 C3620
2.2UF
1 C3630
2.2UF
1 C3640
2.2UF
1 C3650
2.2UF
20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM CERM CERM CERM CERM CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
1 C3601
2.2UF
1 C3611
2.2UF
1 C3621
2.2UF
1 C3631
2.2UF
1 C3641
2.2UF
1 C3651
2.2UF
20% 20% 20% 20% 20% 20%
6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
1 C3612
2.2UF
1 C3642
2.2UF
2 CAPS ALONG PACKAGE EDGE 20% 20% 2 CAPS ALONG PACKAGE EDGE
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
C C
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
1 C3604
2.2UF
1 C3614
2.2UF
1 C3624
2.2UF
1 C3634
2.2UF
1 C3644
2.2UF
1 C3654
2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
1 C3605
2.2UF
1 C3615
2.2UF
1 C3625
2.2UF
1 C3635
2.2UF
1 C3645
2.2UF
1 C3655
2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT_TABLE
OMIT_TABLE
1 C3616
2.2UF
1 C3646
2.2UF
20% 20%
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
B B
PAGE TITLE
DDR BYPASSING 2
DRAWING NUMBER SIZE

REVISION
R
4.4.0
36 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
MEM CLOCK TERMINATION
Place RC end termination after last DRAM =PPDDRVTT_S0_MEM_A
Place Source Cterm at neckdown at first DRAM 8
RP3702 36 1
R3700
30 C3700 66 27 26 21 15 IN MEM_A_CKE<1>
MEM_A_WE_L RP3702 36 2
8
7 5%1/32W 4X0201 1 C3710
2
66 27 26 15 IN
66 27 26 15 MEM_A_CLK_N<0> 1 2 MEM_A_CLK_TERM_R
VOLTAGE=0V 66 27 26 15 MEM_A_A<6> RP3706 36 4 5 5%1/32W 4X0201 0.47UF
5% IN
RP3702 5%1/32W 4X0201 20%
1/20W 0.1UF MEM_A_BA<2> 36 3 6 2 4V
C3704
3.3PF
1 MF
201
10%
X5R
66 27 26 15
66 27 26 15
IN
MEM_A_ODT<1> RP3701 36 1 8 5%1/32W 4X0201 CERM-X5R-1
201
D 5%
25V
CERM2 R3701
201
6.3V 66 27 26 15
IN
IN MEM_A_ODT<0> RP3701 36 3 6 5%1/32W 4X0201
5%1/32W 4X0201
D
201 30 1 C3712 1 C3713
66 27 26 15 MEM_A_CLK_P<0> 1 2
66 27 26 15 MEM_A_A<10> RP3702 36 4 5
0.47UF 0.47UF
5%
1/20W
IN
MEM_A_A<13> RP3707 36 3 6 5%1/32W 4X0201 20% 20%
2 4V 4V
66 27 26 15 IN
MF
201 66 27 26 15 IN MEM_A_A<2> RP3704 36 1 8 5%1/32W4X0201 CERM-X5R-12 CERM-X5R-1
201 201
66 27 26 15 IN MEM_A_A<3> R3792 36 1 2 5%1/32W 4X0201
MEM_A_A<11> RP3707 36 2 7 5%1/20W 201
R3704
30 C3702
66 27 26 15
66 27 26 15
IN
IN MEM_A_A<5> R3793 36 1 2 5%1/32W 4X0201 1 C3714 1 C3715
RP3703 36 2 7 5%1/20W 201 0.47UF 0.47UF
2
66 29 28 15 MEM_B_CLK_N<0> 1 2MEM_B_CLK_TERM_R 66 27 26 21 15 IN MEM_A_CKE<0> 20% 20%
5%
VOLTAGE=0V
MEM_A_A<1> RP3704 36 3 6 5%1/32W 4X0201
2 4V
CERM-X5R-12
4V
C3706 1 1/20W
MF
0.1UF
10%
66 27 26 15
66 27 26 15
IN
MEM_A_A<12> RP3703 36 4 5 5%1/32W 4X0201 201
CERM-X5R-1
201
IN
3.3PF
5%
201 X5R
201 66 27 26 15 IN MEM_A_BA<1> RP3704 36 2 7 5%1/32W4X0201
25V 6.3V RP3706 36 3 5%1/32W 4X0201
CERM2
201
R3705
30
66 27 26 15
66 27 26 15
IN MEM_A_A<8>
MEM_A_A<0> RP3703 36 3
6
6 5%1/32W 4X0201 1 C3716 1 C3717
66 29 28 15 MEM_B_CLK_P<0> 1 2
66 27 26 15
IN
MEM_A_BA<0> RP3703 36 1 8 5%1/32W 4X0201 0.47UF 0.47UF
5% IN
RP3704 36 4 5%1/32W 4X0201 20% 20%
1/20W
MF 66 27 26 15 IN MEM_A_A<14> 5 2 4V
CERM-X5R-12
4V
CERM-X5R-1
201 5%1/32W 4X0201 201 201
66 27 26 15 IN MEM_A_CS_L<0> R3790 36 1 2 1 C3718

MEM_A_CS_L<1> R3791 36 1 2 5%1/20W 201 0.47UF
IN
RP3706 5%1/20W 201 20%
66 27 26 15 IN MEM_A_A<4> 36 2 7 2 4V
CERM-X5R-1
66 27 26 15 IN MEM_A_A<7> RP3706 36 1 8 5%1/32W4X0201 201
66 27 26 15 IN MEM_A_CAS_L RP3701 36 4 5 5%1/32W 4X0201
66 27 26 15 MEM_A_RAS_L RP3701 36 2 7 5%1/32W 4X0201
66 27 26 15
IN
IN MEM_A_A<9> RP3707 36 1 8 5%1/32W 4X0201 1 C3720
C 5%1/32W 4X0201 0.47UF
20%
2 4V
C
CERM-X5R-1
201
=PPDDRVTT_S0_MEM_B
8
66 29 28 15 IN MEM_B_ODT<0> RP3715 36 3 6
66 29 28 15 IN MEM_B_CAS_L RP3715 36 4 5 5%1/32W 4X0201 1 C3722
66 29 28 15 MEM_B_A<8> RP3711 36 1 8 5%1/32W 4X0201 0.47UF
IN
RP3709 5%1/32W 4X0201 20%
66 29 28 15 IN MEM_B_BA<2> 36 1 8 2 4V
CERM-X5R-1
66 29 28 15 IN MEM_B_RAS_L RP3715 36 2 7 5%1/32W 4X0201 201
66 29 28 15 IN MEM_B_ODT<1> RP3715 36 1 8 5%1/32W 4X0201
5%1/32W 4X0201
66 29 28 15 IN MEM_B_BA<0> RP3709 36 3 6
1 C3724
0.47UF
MEM_B_A<7> RP3710 36 3 6 5%1/32W 4X0201 20%
2 4V
66 29 28 15 IN
66 29 28 15 MEM_B_A<0> RP3708 36 1 8 5%1/32W 4X0201 CERM-X5R-1
201
66 29 28 15
IN
IN MEM_B_A<10> RP3709 36 2 7 5%1/32W 4X0201
66 29 28 15 IN MEM_B_A<5> RP3711 36 2 7 5%1/32W 4X0201
66 29 28 21 15 IN MEM_B_CKE<0> RP3709 36 4 5 5%1/32W 4X0201
66 29 28 15 MEM_B_A<6> RP3711 36 3 6 5%1/32W 4X0201 1 C3726 1 C3727
B 66 29 28 15
IN
IN MEM_B_A<12> RP3708
RP3713
36 2
36 1
7 5%1/32W4X0201
5%1/32W 4X0201
0.47UF 0.47UF
20% 20% B
66 29 28 15 IN MEM_B_CS_L<1> 8 2 4V 4V
CERM-X5R-12 CERM-X5R-1
66 29 28 15 IN MEM_B_A<2> RP3708 36 3 6 5%1/32W 4X0201 201 201
66 29 28 15 MEM_B_CS_L<0> RP3713 36 4 5 5%1/32W4X0201
66 29 28 15
IN
IN MEM_B_A<14> RP3710 36 2 7 5%1/32W4X0201
66 29 28 15 IN MEM_B_A<4> RP3710 36 4 5 5%1/32W 4X0201 1 C3728 1 C3729
66 29 28 15 MEM_B_BA<1> RP3708 36 4 5 5%1/32W4X0201 0.47UF 0.47UF
20% 20%
66 29 28 15
IN
IN MEM_B_A<13> RP3710 36 1 8 5%1/32W 4X0201
2 4V 4V
5%1/32W 4X0201 201 201
MEM_B_A<3> RP3714 36 1 8
66 29 28 15
66 29 28 15
IN
IN MEM_B_A<1> RP3714 36 2 7 5%1/32W 4X0201 1 C3730
0.47UF
MEM_B_WE_L RP3713 36 3 6 5%1/32W 4X0201 20%
2 4V
66 29 28 15 IN
66 29 28 21 15 IN MEM_B_CKE<1> RP3713 36 2 7 5%1/32W 4X0201 CERM-X5R-1
201
66 29 28 15 MEM_B_A<9> RP3714 36 3 6 5%1/32W 4X0201
66 29 28 15
IN
IN MEM_B_A<11> RP3714 36 4 5 5%1/32W 4X0201
5%1/32W 4X0201 1 C3732 1 C3733
0.47UF 0.47UF
20% 20%
2 4V 4V
201 201
PAGE TITLE
Memory Active Termination

DRAWING NUMBER SIZE

REVISION
R
4.4.0
37 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
=PP3V3_S3_VREFMRGN
8
buffers at once or VRef source may be overloaded.
OMIT
VREFMRGN:YES
R3900 R3921
SHORT2 52 8 =PPVTT_S3_DDR_BUF
1 PP3V3_S3_VREFMRGN_DAC 200 PLACE_NEAR=U3230.E1.1:2.54MM
MIN_LINE_WIDTH=0.3 mm 10mA max load 1 2
NONE MIN_NECK_WIDTH=0.2 mm
NONE VOLTAGE=3.3V 1%
NONE
402
VREFMRGN:YES VREFMRGN:YES 1/20W
MF
C3900 1 1 C3901 VREFMRGN:YES
CRITICAL
201
PPVREF_S3_MEM_VREFDQ
2.2UF 0.1UF CRITICAL C3920 1 VREFMRGN:YES MIN_LINE_WIDTH=0.3 mm
26 27 28 29
20% 10%
0.1UF
B1 U3920 MIN_NECK_WIDTH=0.2 mm
D
6.3V 2
CERM
402-LF
6.3V
2 X5R
201
VREFMRGN:YES
U3900
10%
6.3V 2
X5R
A2
V+
MAX4253
UCSP
A1
R3922
133
VOLTAGE=0.75V
D
8
201 VREFMRGN_DQ_BUF 1 2
VDD
=I2C_VREFDACS_SCL 6 SCL 1 VREFMRGN_DQ_DRAM A3 A4 VREFMRGN:YES 1%
1/20W
PLACE_NEAR=R3921.2:1MM
41 IN MSOP VOUTA V- MF
B4 201
DAC5574
41 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2
9 A0 VOUTC 4 VREFMRGN_CA_DRAM
Addr=0x98(WR)/0x99(RD) 10 A1 VREFMRGN_MEMVREG_FBVREF
VOUTD 5 VREFMRGN:YES
NOTE: MEMVREG and FRAMEBUF share R3923
GND
1
200 2 PLACE_NEAR=U3230.J8:2.54MM
1
3 a DAC output, cannot enable VREFMRGN:YES
both at the same time! R3920 1%
1/20W
100K MF
201
5%
1/20W CRITICAL PPVREF_S3_MEM_VREFCA 26 27 28 29
MF B1 U3920 VREFMRGN:YES MIN_LINE_WIDTH=0.3 mm
201 C2 MIN_NECK_WIDTH=0.15 MM
MAX4253 R3924 VOLTAGE=0.75V
2
V+ UCSP
OMIT C1 133
VREFMRGN_CA_BUF 1 2
R3910 C3 C4 VREFMRGN:YES 1% PLACE_NEAR=R3923.2:1MM
SHORT2 V- 1/20W
1 PP3V3_S3_VREFMRGN_CTRL B4
MF
MIN_LINE_WIDTH=0.3 mm 201
NONE MIN_NECK_WIDTH=0.2 mm
NONE VOLTAGE=3.3V CRITICAL
NONE VREFMRGN:YES
16
402 VREFMRGN:YES
C3910 1 VREFMRGN:YES
0.1UF VCC
10% 1
6.3V 2
X5R U3910 R3925
201 PCA9557 100K
5%
QFN 1/20W
(OD) P0 6 NC MF
3 A0 P1 7 VREFMRGN_DQ_DRAM_EN 2 201
C Addr=0x30(WR)/0x31(RD) 4 A1
5 A2
P2 9
P3 10
NC
VREFMRGN_CA_DRAM_EN
C
P4 11 NC
P5 12 VREFMRGN_MEMVREG_EN
41 IN =I2C_PCA9557D_SCL 1 SCL P6 13 NC(RSVD for FBVREF)
41 BI =I2C_PCA9557D_SDA 2 SDA P7 14 VREFMRGN_CPUGTLREF_EN
THRM RESET* 15
PAD GND
17
25 IN PCA9557D_RESET_L 8
RST* on platform reset so that system

watchdog will disable margining.
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
Required zero ohm resistors when no VREF margining circuit stuffed

VREFMRGN:YES
CRITICAL
117S0002 2 RES,MF,1/20W,0.0 OHM,5,0201,SMD R3921,R3923 VREFMRGN:NO C3940 1 B1 U3940 VREFMRGN:YES
0.1UF C2 MAX4253
10%
6.3V 2 V+ UCSP R3942
B X5R
201
C1 VREFMRGN_MEMVREG_BUF
22.6K2
1 DDRREG_FB OUT 52 B
C3 C4 VREFMRGN:YES 1%
1/20W
PLACE_NEAR=R7320.2:1mm
V- MF
B4 201
Page Notes VREFMRGN:YES

1
Power aliases required by this page: R3940 CRITICAL
- =PP3V3_S3_VREFMRGN 100K B1 U3940 VREFMRGN:YES
5% A2
- =PPVTT_S3_DDR_BUF 1/20W MAX4253 R3944
MF V+ UCSP
2 201 A1 267
Signal aliases required by this page: VREFMRGN_CPUGTLREF_BUF 1 2 CPU_GTLREF OUT 10 65
- =I2C_VREFDACS_SCL A3 A4 VREFMRGN:YES 1%
1/20W
PLACE_NEAR=R1005.2:1mm
- =I2C_VREFDACS_SDA V- MF
B4 201
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page: VREFMRGN:YES
VREFMRGN:YES - Stuffs VREF Margining 1
R3945
Circuitry. 100K
5%
VREFMRGN:NO - Bypasses VREF Margining 1/20W
MF
Circuitry. 2 201
A MEM VREF DQ MEM VREF CA MEM VREG CPU GTLREF (FSB) SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
PAGE TITLE
DAC Channel: A C D D FSB/DDR3 Vref Margining

DRAWING NUMBER SIZE
PCA9557D Pin: 1 3 5 7 Apple Inc. 051-8379 D
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 0.7V (DAC: 0x8B) R
4.4.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.998V - 1.002V (+/- 498mV) 0.200V - 1.050V (+/- 500mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 1.501V (0x00 - 0x74) 0.000V - 1.191V (0x00 - 0x5C) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
VRef current: +3.4mA - -3.4mA (- = sourced) +33uA - -33uA (- = sourced) +750uA - -528uA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
39 OF 110
SHEET
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 9.24mV / step @ output III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3V S3 WLAN FET
MOSFET TPCP8102
CHANNEL P-TYPE
RDS(ON) 20-30 MOHM @2.5V
LOADING 0.750 A (EDP)
D D
CRITICAL CRITICAL
Q4050
R4052
0.020
TPCP8102
AIRPORT 1%
0.25WMIN_LINE_WIDTH=1 mm
23V1K-SM
5 6 7 8
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm
MF-LFVOLTAGE=3.3V
1 2 3
805
VOLTAGE=3.3V
PP3V3_WLAN_F
1 2PP3V3_WLAN_R =PP3V3_S3_WLAN
S
D
39 7
3 4
R4051
1
4G
C4021
0.1UF
1 1 C4020
10UF
C4051 1
0.033UF 10K
10% 20% 10% 5%
6.3V 1/20W
X5R 2 2 10V
X5R C4050 16V 2
X5R MF
CRITICAL 201 805 0.1UF 402 R4050
100K
2201
J4001
SSD-K99
1 2 P3V3WLAN_SS1 2 PM_WLAN_EN_L
IN 57
PLACEMENT_NOTE=Place close to Q4050. 10% 5%

F-RT-SM1 16V 1/20W
X5R MF
1 PLACEMENT_NOTE=Place close to Q4050. 402 201
2 WIFI_EVENT_LOUT 7 38 39
3
4 ISNS_AIRPORT_P
2 0.1UF
OUT 42 71
5 67 7 PCIE_AP_R2D_N 1 PCIE_AP_R2D_C_N
IN 16 67 ISNS_AIRPORT_N
OUT 42 71
6 10% 6.3V 201 X5R
7 C4030
PLACEMENT_NOTE=Place close to J4001.
8 PLACEMENT_NOTE=Place close to J4001.
9
10 67 7 PCIE_AP_R2D_P
C4031
1 2 PCIE_AP_R2D_C_P 16 67
IN
C 11
12
0.1UF10% 6.3VX5R201 C
PCIE_CLK100M_AP_N
IN 7 16 67
13 PCIE_CLK100M_AP_P
IN 7 16 67
14
15
16
17
18 PCIE_AP_D2R_P
OUT 7 16 67
PCIE_AP_D2R_N
OUT 7 16 67
19
20
21 PCIE_WAKE_L
OUT 7 16
514S0335
BLUETOOTH USB_BT_NBI 7 18 68
USB_BT_PBI 7 18 68
=PP3V3_S3_BT 7 8
B B
1 C4032
0.1UF
10%
6.3V
2 X5R
201
=PP3V3_S3_WLAN 8 34
PLACE_NEAR=J4001.27:1.5mm
DLY = 60 MS +/- 20% C4053 1
0.1UF 10%
CRITICAL 6.3V
1
X5R 2
VDD
201
U4002
R4053
100K
1R40541
232K
SLG4AP016V
TDFN
AP_RESET_L
IN 25
5% 1% 2
1/20W 1/20W SENSE +
MF MF 0.7V - AP_PWR_EN IN
2012 2012 19 57
P3V3WLAN_VMON DLY
7 AP_RESET_CONN_L
4 RESET* AP_CLKREQ_L
OUT 16
MR* 3
EN 6
OUT 8
7 AP_CLKREQ_Q_L 7 IN (OD)
THRM
PAD GND
5
A R4055
100K
1
1% PAGE TITLE
1/20W
MF
2012
X21 WIRELESS CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
4.4.0
40 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
1 C4501
0.1UF
20% CRITICAL
10V
2 CERM
402
R4599
0.003
PLACE_NEAR=J4501.1:1.5mm 1%
1W
MF
SATA SSD PP3V3_S0_HDD_R
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=5V
2
4
0612
1
3
=PP3V3_S0_HDD
C CRITICAL
ISNS_HDD_POUT
C
J4501
SSD-K99
42 71
F-RT-SM1
ISNS_HDD_N OUT 42 71
1 TP_SSD_RSRVD
2
3
4 67 7 SATA_HDD_D2R_C_P C45161 2 SATA_HDD_D2R_P OUT 18 67
5 0.01UF 10%10V X5R 201
6 PLACE_NEAR=J4501.4:1.5MM
PLACE_NEAR=J4501.3:1.5MM
7 67 7 SATA_HDD_D2R_C_N C4515 1 2 SATA_HDD_D2R_N OUT 18 67
8 0.01UF 10%10V X5R 201
9
10
12
67 7 SATA_HDD_R2D_N C45111 2 SATA_HDD_R2D_C_N
IN 18 67
0.01UF 10%10V X5R 201

13
14
NC 67 7 SATA_HDD_R2D_P C45101 2 SATA_HDD_R2D_C_P
IN 18 67
NC 0.01UF 10%10V X5R 201
15
R4510
17 0
18 SMC_HDD_OOB_TEMP_CONN 1 2 SMC_HDD_OOB_TEMP 7 38
5%
1/20W
MF
19 201
20
B 21
R4511
0
B
SMC_HDD_TEMP_CTL_CONN 1 2 SMC_HDD_TEMP_CTL 7 38
5%
1/20W
MF
201
PAGE TITLE
SATA CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
4.4.0
45 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Port Power Switch

CRITICAL CRITICAL
U4690 L4605 Right USB Port
8 =PP5V_S3_RTUSB FERR-220-OHM-2.5A
TPS2052B
2 IN OUT1
7 PP5V_S3_RTUSB_A_ILIM 1 2 7 PP5V_S3_RTUSB_A_F
MSOP MIN_LINE_WIDTH=0.5 mm 0603 MIN_LINE_WIDTH=0.5 mm
8 MIN_NECK_WIDTH=0.375 mm MIN_NECK_WIDTH=0.375 mm
USB_EXTA_OC_L VOLTAGE=5V VOLTAGE=5V
18 OUT
=USB_PWR_EN
OC1*
3 EN1 OUT2 6
C4605 1 PLACE_NEAR=J4600.1:3 mm
57 37 7 IN 0.01uF CRITICAL
5 OC2* 20%
16V
4 EN2 CERM 2
402 CRITICAL J4600
CRITICAL OMIT_TABLE OMIT_TABLE L4600 USB-RIGHT-K99
F-RT-TH
C4696 1 C4690 1 1 C4691 GND TPAD 1 C4695 90-OHM-100MA
DLP11S 5
100UF 10UF 0.1UF 1 9 10UF SYM_VER-1
PLACE_NEAR=D4600.2:2 mm
20% 20% 20% 20%
6.3V 2 6.3V 2 2 10V 6.3V
2 X5R 71 68 USB_EXTA_MUXED_N 4 3 71 USB_LT1_N
POLY-TANT X5R CERM 1 VBUS
CASE-B2-SM 603 402 603
2 D-
71 68 USB_EXTA_MUXED_P 1 2 71 USB_LT1_P 3 D+
C PLACE_NEAR=D4600.3:2 mm 4 GND
C
4 3 5 2
6
IO
NC
IO
NC
VBUS 6
GND 1 514-0740
USB/SMC Debug Mux
8 =PP3V42_G3H_SMCUSBMUX D4600
RCLAMP0502N D4600.4 PLACE_NEAR=J4600.3:2 mm
SLP1210N6 D4600.5 PLACE_NEAR=J4600.2:2 mm
SMC_DEBUG:YES 1 CRITICAL
C4650 1 R4650
0.1UF CRITICAL 10K
10% 5%
SMC_DEBUG:YES
9
6.3V 2 1/20W
X5R MF
201 VCC 2 201
40 39 38 7 SMC_RX_L 5 M+ Y+ 1 (USB_EXTA_MUXED_P)
IN
SMC_TX_L 4 M- Y- 2 (USB_EXTA_MUXED_N)
40 39 38 7 OUT U4650
PI3USB102ZLE
68 18 USB_EXTA_P 7 D+ TQFN
BI
68 18 USB_EXTA_N 6 D-
BI
8 OE* SEL 10 USB_DEBUGPRT_EN_L IN 38
GND SEL=0 Choose SMC

SEL=1 Choose USB
3
SIGNAL_MODEL=USB_MUX
B SMC_DEBUG:NO
R4651
B
1
0 2
5%
1/20W
MF
201
SMC_DEBUG:NO
R4652
1
0 2
5%
1/20W
MF
201
PAGE TITLE
External USB Connectors

DRAWING NUMBER SIZE

REVISION
R
4.4.0
46 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LIO CONNECTOR
J4700
AXK736327G
F-ST-SM
37
1 2
3 4
68 19 7 HDA_SYNC 5 6 USB_EXTD_P 7 18 68
C 68 19 7 HDA_SDIN0 7
9
8
10
USB_EXTD_N 7 18 68 C
68 19 7 HDA_BIT_CLK 11 12 USB_CAMERA_P 7 18 68
68 19 7 HDA_SDOUT 13 14 USB_CAMERA_N 7 18 68
=PP3V3_S0_AUDIO 7 8
15 16
41 7 =I2C_MIKEY_SCL 17 18 SPKRAMP_INR_P 7 48 71 C4700 1
41 7 =I2C_MIKEY_SDA 19 20 SPKRAMP_INR_N 7 48 71
0.1UF
10%
41 7 =I2C_LIO_SCL 21 22 6.3V
X5R
2 PLACE_NEAR=J4700.20:1.5mm
41 7 =I2C_LIO_SDA 23 24 USB_EXTD_OC_L 7 18 201
19 7 AUD_I2C_INT_L 25 26 =USB_PWR_EN 7 36 57 =PP3V42_G3H_ONEWIRE 7 8
17 7 AUD_IP_PERIPHERAL_DET 27 28 SMC_BC_ACOK 7 9 38 39
C4710 1
19 7 AUD_IPHS_SWITCH_EN 29 30 SYS_ONEWIRE 7 38
0.1UF
48 7 AUD_GPIO_3 31 32 10%
6.3V
68 19 7 HDA_RST_L 33 34 =PP1V8R1V5_S0_AUDIO 7 8
X5R
201
35 36
C4720 1
0.1UF
38 10%
6.3V
X5R
201
516S0862
B B
A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
LIO CONNECTORS
DRAWING NUMBER SIZE

REVISION
R
4.4.0
47 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
39 PP3V3_S5_AVREF_SMC
39 8 =PP3V3_S5_SMC
D OMIT_TABLE
D
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906
22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 2 10V 2 10V 2 10V 2 10V
X5R-CERM-1 2 CERM CERM CERM CERM
603 402 402 402 402
SMC_P10
U4900 SMC_PM_G2_EN
(EXCARD_PWR_EN) 39 B12 P10 H8S2117 P60 L13 OUT 7 57
BYPASS=U4900.E1:D2:5 mm
39 OUT SMC_RSTGATE_L A13 P11 LGA-HF P61 K12 NC
R4999 PLACE_NEAR=C4920.1:2 mm SMC_VCL
57 49 25 IN ALL_SYS_PWRGD A12 P12 (1 OF 3) P62 K11 NC 4.7
57 RSMRST_PWRGD B13 P13 P63 J12 NC 1 2 PP3V3_S5_SMC_AVCC
IN
OMIT_TABLE SMC_ADAPTER_EN MIN_LINE_WIDTH=0.25 MM C4907 1
M12
H10
L11
NC D11 P14 P64 K13 OUT 19 39 57 5% MIN_NECK_WIDTH=0.10 MM 0.47UF
B1
M1
E1
1/20W VOLTAGE=3.3V
19 OUT PM_RSMRST_L C13 P15 P65 J10 NC MF
201
C4920 1 20%
4V
53 IMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L 39
0.1UF CERM-X5R-1 2
OUT IN 20% 201
PM_PWRBTN_L SMC_BIL_BUTTON_L 10V AVCC VCC VCL AVREF
19 OUT D10 P17 P67 H12 IN 39
CERM 2
402
U4900 R49091 1
R4901
39 SMC_P20 D13 P20 P70 N10 SMC_CPU_ISENSE IN 43 BYPASS=U4900.M12:L9:5 mm NC E5 NC 10K 10K
E11 P21 P71 M11 SMC_CPU_VSENSE H8S2117 5%
1/20W
5%
1/20W
NC IN 42
LGA-HF MF MF
NC D12 P22 P72 L10 SMC_GPU_ISENSE IN 39 201 2 2 201
(3 OF 3)
NC F11 P23 P73 N11 SMC_GPU_VSENSE IN 39
MD1 D1 SMC_MD1 IN 7 40
39 SMC_P24 E13 P24 P74 N12 SMC_DCIN_ISENSE IN 43 OMIT_TABLE
MD2 H1 SMC_KBC_MDE
NC E12 P25 P75 M13 SMC_PBUS_VSENSE IN 42 50 40 39 7 IN SMC_RESET_L D3 RES*
43 SMC_BMON_MUX_SEL F13 P26 P76 N13 SMC_BATT_ISENSE IN 43
39 SMC_XTAL A3 XTAL
NC E10 P27 P77 L12 SMC_NB_MISC_ISENSE IN 39
39 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI IN 7 40
68 40 19 7 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 19
68 40 19 7 BI LPC_AD<1> D9 P31 P81 B6 NC

68 40 19 7 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 7 19 40
ETRST H3 SMC_TRST_L IN 7 40
LPC_AD<3> LPC_PWRDWN_L
C 68 40 19 7
68 40 19 7
BI
IN LPC_FRAME_L
B7
A8
P33
P34
P83
P84
D5
A6 SMC_TX_L
IN
OUT
7 19 40
7 36 38 39 40 AVSS L9 1 1 1
NO STUFF C
25 IN SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L IN 7 36 38 39 40 VSS R4902 R4998 R4903
LPC_CLK33M_SMC 10K 10K 0
68 25 IN D7 P36 P86 C6 (OC) SMB_MGMT_CLK BI 41 5% 5% 5%
1/20W 1/20W 1/20W
XW4900
D2
L3
F10
B11
C5
40 19 7 BI LPC_SERIRQ D6 P37 MF MF MF
P90 J4 SMC_ONOFF_L IN 7 39 46 SM 2 201 2 201 2 201
35 7 OUT SMC_HDD_TEMP_CTL D4 P40 P91 G3 SMC_BC_ACOK IN 7 9 37 39 2 1
35 7 IN SMC_HDD_OOB_TEMP A5 P41 P92 H2 SMC_PME_S4_L IN 39 46
41 BI SMB_MGMT_DATA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 7 19 39 57
39 OUT SMS_ONOFF_L A1 P43 P94 H4 PM_SLP_S4_L IN 7 19 57
NC C2 P44 P95 G4 PM_SLP_S5_L IN 19

GND_SMC_AVSS 39 42 43
NC B2 P45 P96 F4 PM_CLK32K_SUSCLK IN 25 68
39 OUT SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMB_0_S0_DATA BI 41
39 OUT SMC_SYS_KBDLED C3 P47
40 39 38 36 7 OUT SMC_TX_L G2 P50

40 39 38 36 7 IN SMC_RX_L F3 P51
41 BI SMB_0_S0_CLK (OC) E4 P52
SMC_PA0
U4900 SMC_CASE_OPEN
(DEBUG_SW_1) 39 N3 PA0 H8S2117 PE0 K1 IN 39
(DEBUG_SW_2) 39 SMC_PA1 N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 7 39 40
25 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 7 39 40
36 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 PE3 J1 SMC_TDO OUT 7 39 40
MEM_EVENT_L OMIT_TABLE SMC_TMS

19 BI (OC) N2 PA4 PE4 K4 IN 7 39 40
B 39 34 7
37 7
BI
BI
WIFI_EVENT_L
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5 SMC_G3H_POWERON_L IN 39
B
PF1 N5 SMC_SYS_LED OUT 39
19 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID IN 7 39 46 49
NC B8 PB0 PF3 L5 NC
19 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5 NC
39 IN SMC_ODD_DETECT B9 PB2 PF5 N4 SMC_MCP_SAFE_MODE OUT 39
39 OUT SMC_SLPS5_L A10 PB3 PF6 L4 NC

(EXCARD_CP) 39 SMC_PB4 C10 PB4 PF7 M4 NC
NC B10 PB5
PG0 M8 NC
(EXCARD_OC_L) 39 SMC_DP_HPD_L C11 PB6
PG1 N7 =SMC_SMS_INT IN 39 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
39 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMB_BSA_DATA BI 41 If SMS interrupt is not used, pull up to SMC rail.
45 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMB_BSA_CLK BI 41
39 OUT SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMB_A_S3_DATA BI 41
39 OUT SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMB_A_S3_CLK BI 41
39 OUT SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMB_B_S0_DATA BI 41
45 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMB_B_S0_CLK BI 41
39 IN SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 39
39 IN SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP OUT 39
39 IN SMC_FAN_3_TACH J13 PC7
PH2 J2 NC H8S2117-R:
39 IN SMS_X_AXIS M10 PD0 PH3 A4 SMC_PH3 39 (SMC_PECI)
39 IN SMS_Y_AXIS N9 PD1 PH4 B3 NC (SMC_PECI_VREF)
39 IN SMS_Z_AXIS K10 PD2 PH5 C4 NC (SMC_PECI_VSTP)
39 IN SMC_ANALOG_ID L8 PD3
39 IN SMC_NB_CORE_ISENSE M9 PD4
SMC_NB_DDR_ISENSE N8
A 39
39
IN
IN SMC_ADC14 K9
PD5
PD6 SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
42 39 IN SMC_ADC15 L7 PD7 PAGE TITLE
SMC
DRAWING NUMBER SIZE

REVISION
R
4.4.0
49 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC Reset "Button", Supervisor & AVREF Supply SMC FSB to 3.3V Level Shifting
8 =PP3V3_S0_SMC
39 38 8 =PP3V3_S5_SMC
8 =PPVIN_S5_SMCVREF
Desktops: 5V 1 1
R5061 R5060
Mobiles: 3.42V 100K 10K
1 5% 5%
R5000 1/20W
3
1/20W
C5020 1 1K MF MF
TO SMC
0.47UF V+ VIN
5% 2 201 2 201
10%
6.3V
CERM-X5R 2
U5010 1/20W
MF SMC_PROCHOT_3_3_L OUT 38
402 VREF-3.3V-VDET-3.0V 2 201
(IPU) DFN
D 46 7
46 39 38 7
IN
IN
SMC_TPAD_RST_L
SMC_ONOFF_L
6 MR1*
7 MR2*
SN0903048 RESET* 5 SMC_RESET_L OUT 7 38 40 50 6
D
(IPU) PP3V3_S5_AVREF_SMC
38
D Q5060
SMC_MANUAL_RST_L 4 DELAY REFOUT 8 MIN_NECK_WIDTH=0.1 mm DMB53D0UV
THRM VOLTAGE=3.3V SOT-563
OMIT GND PAD CPU_PROCHOT_BUF 2 G
1
R5001 OMIT_TABLE
9
0 C5001 1
C5025 1 1 C5026 TO CPU
5% 0.01UF
10uF 0.01UF
R5062 3
1/10W 10%
10V 20% 10% CPU_PROCHOT_L 1
3.3K 2
CPU_PROCHOT_L_R 5 Q5060 S
MF-LF X5R 2 6.3V 2 2 10V
65 14 10 BI
DMB53D0UV
2603 201 X5R X5R 5% 1
SILK_PART=SMC_RST 603 201 1/20W SOT-563
MF 4
PLACEMENT_NOTE=Place R5001 on BOTTOM side 201
GND_SMC_AVSS 6 D
38 42 43
Q5059
MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V SSM6N37FEAPE
SOT563
Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.
1 S G 2
SMC_PROCHOT IN 38
Debug Power "Buttons" PM_THRMTRIP_L

SMC Aliases 65 14 10 OUT
SMC_ONOFF_L OUT 7 38 39 46
OMIT OMIT 42 SMC_LCDBKLT_ISENSE SMS_X_AXIS 38

3 D Q5059
OUT
MAKE_BASE=TRUE SSM6N37FEAPE
R50141 1
R5015 42 SMC_WLAN_ISENSE SMS_Y_AXIS OUT 38 SOT563
0 0 MAKE_BASE=TRUE
5% 5%
1/10W 1/10W 42 SMC_HDD_ISENSE SMS_Z_AXIS OUT 38
MF-LF MF-LF MAKE_BASE=TRUE
603 2 2 603 SMC_CSREG_ISENSE SMC_ADC14 4 S G 5
43 OUT 38
SILK_PART=PWR_BTN SILK_PART=PWR_BTN
C PLACEMENT_NOTEs:
MAKE_BASE=TRUE
SMC_LCDBKLT_VSENSE
MAKE_BASE=TRUE
SMC_ADC15 OUT 38 42
SMC_THRMTRIP IN 38 C
Place R5014 on TOP side 43 SMC_MCP_CORE_ISENSE SMC_NB_CORE_ISENSE OUT 38
MAKE_BASE=TRUE
Place R5015 on BOTTOM side SMC_MCP_DDR_ISENSE SMC_NB_DDR_ISENSE
43
SMC Pull-ups
42 SMC_1V5S3_ISENSE SMC_NB_MISC_ISENSE OUT 38
MAKE_BASE=TRUE 39 38 8 =PP3V3_S5_SMC
TP_SMC_ANALOG_ID SMC_ANALOG_ID OUT 38
MAKE_BASE=TRUE
TP_SMC_GPU_ISENSE SMC_GPU_ISENSE OUT 38 38 SMC_PA0 R5091 100K 1 2
SMC Crystal Circuit 42
MAKE_BASE=TRUE
SMC_MCP_VSENSE SMC_GPU_VSENSE OUT 38
38 SMC_PA1 R5092
R5088
100K
10K
1 2 5%
5%
1/20W
1/20W
MF
MF
201
201
MAKE_BASE=TRUE 38 SMC_PB4 1 2
5% 1/20W MF 201
R5010 C5010 38 IN SMC_GFX_THROTTLE_L SMC_IG_THROTTLE_L OUT 19
15PF MAKE_BASE=TRUE
SMC_ONOFF_L R5070 10K
0 1 2 46 39 38 7 1 2
SMC_XTAL 1 2 SMC_XTAL_R 5% 1/20W MF 201
38
5%
39 OUT SMS_INT_L =SMC_SMS_INT IN 38 49 46 38 7 SMC_LID R5071 100K 1 2
MAKE_BASE=TRUE 5% 1/20W MF 201
1/20W
MF
CRITICAL 5%
25V 40 38 36 7 SMC_TX_L R5073 10K 1 2
1 R5074 5% 1/20W MF 201
201 Y5010 NPO
201 19 IN MCP_WAKE_REQ_L SMC_G3H_POWERON_L
MAKE_BASE=TRUE
OUT 38 39 40 38 36 7 SMC_RX_L 100K 1 2
5% 1/20W MF 201
20.00MHZ
5X3.2-SM
C5011 40 38 7 SMC_TMS R5077 10K 1 2
2
15PF R5096 40 38 7 SMC_TDO R5078 10K 1 2 5% 1/20W MF 201
1 2 R5079 10K 5% 1/20W MF 201
38 SMC_EXTAL 0 40 38 7 SMC_TDI 1 2
38 IN SMC_MCP_SAFE_MODE 1 2 MCP_SPKR OUT 19
R5080 10K 5% 1/20W MF 201
5% 40 38 7 SMC_TCK 1 2
25V 5% 5% 1/20W MF 201
1/20W
NPO
201
MF
201
38 SMC_ODD_DETECT R5040 10K 1 2
38 SMC_BIL_BUTTON_L R5081 10K 1 2 5% 1/20W MF 201
R5087 470K 1 5% 1/20W MF 201
38 37 9 7 SMC_BC_ACOK 2
DP_PWR:S0 SMC_GFX_OVERTEMP_L R5094 10K 1 2
5% 1/20W MF 201
38
R5020 39 38 SMC_G3H_POWERON_L R5098 100K 2 1 5% 1/20W MF 201
B 57 38 19 7 IN PM_SLP_S3_L 1
0 2 DP_PWR_EN
MAKE_BASE=TRUE
5% 1/20W MF 201
B
DP_PWR:SMC 5%
1/20W =DP_PWR_EN SMS_INT_L R5093 10K 1 2
OUT 61 39
R5021 MF 5% 1/20W MF 201
201
0
38 IN SMC_SLPS5_L 1 2 34 7 PP3V3_WLAN_F
5%
1/20W NO STUFF
MF
201
DP_PWR:SMC WIFI_EVENT_L R5089 10K 1 2
38 34 7
R5022 5% 1/20W MF 201
System (Sleep) LED Circuit 39 38 OUT SMC_DP_HPD_L 1
0 2 DP_EXT_HPD_L IN 61 8 =PP3V3_SMC_PME
5%
1/20W
PLACE_NEAR=Q9441.2:5 mm
=PP5V_S3_SYSLED
MF
201
46 38 SMC_PME_S4_L R5076 100K 1 2
8 5% 1/20W MF 201
SIL SIL
R50311 1 Unused Pins
523
R5030
40.2
SMC Pull-downs
1% 1% 38 IN SMS_ONOFF_L TP_SMS_ONOFF_L
MAKE_BASE=TRUE
1/16W
MF-LF
1/16W
MF-LF 57 38 19 SMC_ADAPTER_EN R5085 10K 1 2
402 2 2 402 R5086 10K 5% 1/20W MF 201
38 SMC_CASE_OPEN 1 2
5% 1/20W MF 201
SYS_LED_ILIM 38 IN SMC_SYS_KBDLED TP_SMC_SYS_KBDLED
MAKE_BASE=TRUE DP_PWR:S0
SYS_LED_L_VDIV 38 IN SMC_FAN_1_CTL TP_SMC_FAN_1_CTL 39 38 SMC_DP_HPD_L R5090 100K 1 2
MAKE_BASE=TRUE 5% 1/20W MF 201
SIL TP_SMC_FAN_1_TACH SMC_FAN_1_TACH OUT 38
R50321 MAKE_BASE=TRUE
1.47K
1% 6 5 4 38 IN SMC_FAN_2_CTL NC_SMC_FAN_2_CTL
1/16W MAKE_BASE=TRUE NO_TEST=TRUE
MF-LF D B E
402 2 SIL NC_SMC_FAN_2_TACH SMC_FAN_2_TACH OUT 38
A SYS_LED_L Q5030
MAKE_BASE=TRUE
SMC_FAN_3_CTL
NO_TEST=TRUE
NC_SMC_FAN_3_CTL SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A

DMB54D0UV 38 IN
MAKE_BASE=TRUE NO_TEST=TRUE PAGE TITLE
Q1
Q2
SOT-563
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE NO_TEST=TRUE
SMC_FAN_3_TACH OUT 38 SMC Support
DRAWING NUMBER SIZE
S G C 38 SMC_RSTGATE_L TP_SMC_RSTGATE_L Apple Inc. 051-8379 D

IN
MAKE_BASE=TRUE REVISION
1 2 3 R
38 IN SMC_P10 TP_SMC_P10
MAKE_BASE=TRUE
4.4.0
SMC_P20 TP_SMC_P20 NOTICE OF PROPRIETARY PROPERTY: BRANCH
38 IN
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
38 IN SMC_SYS_LED SYS_LED_ANODE OUT 49 38 IN SMC_P24 TP_SMC_P24 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE
38 SMC_PH3 TP_SMC_PH3
50 OF 110
IN
MAKE_BASE=TRUE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
D 55909-0374
M-ST-SM
D
8 7 =PP3V3_S5_LPCPLUS 31 32
8 7 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 7 25 68
68 38 19 7 BI LPC_AD<0> 3 4 LPC_AD<2> BI 7 19 38 68
68 38 19 7 BI LPC_AD<1> 5 6 LPC_AD<3> BI 7 19 38 68
7 8
68 40 7 SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 7 19 47
68 40 7 SPI_ALT_MISO 11 12 SPI_ALT_CLK 7 40 68
68 38 19 7 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L 7 40 68
38 19 7 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 7 19 38
39 38 7 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 7 19 38
25 7 IN LPCPLUS_RESET_L 19 20 SMC_TDI OUT 7 38 39
39 38 7 OUT SMC_TDO 21 22 SMC_TCK OUT 7 38 39
38 7 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 7 38 39 50
38 7 OUT SMC_MD1 25 26 SMC_NMI OUT 7 38
39 38 36 7 IN SMC_TX_L 27 28 SMC_RX_L OUT 7 36 38 39

29 30 LPCPLUS_GPIO OUT 7 19
33 34
516S0573
C C
SPI Bus Series Termination
SPI_ALT_MISO 7 40 68
SPI_ALT_MOSI 7 40 68
SPI_ALT_CLK 7 40 68
SPI_ALT_CS_L 7 40 68
LPCPLUS LPCPLUS LPCPLUS LPCPLUS

1 1 1 1
R5128 R5127 R5126 R5125
0 47 47 47
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
2 201 2 201 2 201 2 201
R5110 R5120
15 47
68 19 IN SPI_CS0_R_L 1 2 68 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 47 68
5% 5%
1/20W 1/20W
R5111 MF R5121 MF
201 201
SPI_CLK_R 1
15 2 68 SPI_CLK 1
47 2 SPI_MLB_CLK
68 19 IN OUT 47 68
5% 5%
1/20W 1/20W
R5112 MF R5122 MF
201 201
15 47
68 19 IN SPI_MOSI_R 1 2 68 SPI_MOSI 1 2 SPI_MLB_MOSI OUT 47 68
5% 5%
1/20W 1/20W
MF R5123 MF
B 68 19 OUT SPI_MISO
201
1
15 2
201
SPI_MLB_MISO IN 47 68
B
5%
1/20W
MF
201
EFI Debug ROM

8 =PP3V3_S0_DEBUGROM
EFI_DEBUG EFI_DEBUG
EFI_DEBUG
R51011 1
R5103 C5101 1
0 0 0.1UF 8 EFI_DEBUG
5% 5% 20%
1/20W 1/20W 10V VCC
MF MF CERM 2
201 2 2 201 402 U5101
DEBUGROM_E2 3 E2 M24M01-R =I2C_DEBUGROM_SDA
SO8N SDA 5 BI 41
DEBUGROM_E1 2 E1
A NO STUFF NO STUFF 7 WC*
CRITICAL SCL 6 =I2C_DEBUGROM_SCL IN 41
R51021 1
R5104 E0/NC0 1 NC
PAGE TITLE
5%
0 0
5%
VSS
4
LPC+SPI Debug Connector
1/20W 1/20W DRAWING NUMBER SIZE
MF MF
201 2 2 201 Apple Inc. 051-8379 D
REVISION
R
4.4.0
Write: 0xAC/0xAE NOTICE OF PROPRIETARY PROPERTY: BRANCH
Read: 0xAD/0xAF THE INFORMATION CONTAINED HEREIN IS THE
51 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP89 SMBus "0" Connections SMC "0" SMBus Connections SMC "Battery A" SMBus Connections
8 =PP3V3_S0_SMBUS_MCP_0 8 =PP3V3_S0_SMBUS_SMC_0_S0 8 =PP3V42_G3H_SMBUS_SMC_BSA
NO STUFF NO STUFF
MCP89 R52001 1
R5201 LP8545 (Bklt) SMC R52501 1
R5251 SMC R52801 1
R5281 Battery Charger
1K 1K 2.0K 2.0K 2.61K 2.61K
U1400 5% 5% U9701 U4900 5% 5% U4900 1% 1% ISL6259 - U7000
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
(MASTER) MF MF (Write: 0x58 Read: 0x59) (MASTER) MF MF (MASTER) MF MF (Write: 0x12 Read: 0x13)
201 2 2 201 201 2 2 201 201 2 2 201
D 68 19 SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
=I2C_BKL_1_SCL 62 38 SMB_0_S0_CLK 70 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
38 SMB_BSA_CLK 70 7 SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
=SMBUS_CHGR_SCL 50
D
68 19 SMBUS_MCP_0_DATA =I2C_BKL_1_SDA 62 38 SMB_0_S0_DATA 70 SMBUS_SMC_0_S0_SDA 38 SMB_BSA_DATA 70 7 SMBUS_SMC_BSA_SDA =SMBUS_CHGR_SDA 50
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
DPI2C:SMC DPI2C:SMC
DPI2C:MCP
XDP Connector R5241 R52421 1
R5243 Internal DP Battery
0 0
J1300 0 5% 5% J9000 J6950
(MASTER)
2
5%
1 1/20W
MF
201 2
1/20W
MF
2 201
(See Table) Battery (See Table)
1/20W
=I2C_XDP_SCL
MF
201 71 I2C_TCON_SCL =I2C_TCON_SCL Battery Manager - (Write: 0x16 Read: 0x17) =SMBUS_BATT_SCL
13 7 59 49
MAKE_BASE=TRUE Battery LED Driver - (Write: 0x36 Read: 0x37)
13 =I2C_XDP_SDA DPI2C:MCP 71 I2C_TCON_SDA =I2C_TCON_SDA 7 59 Battery Temp - (Write: 0x90 Read: 0x91) =SMBUS_BATT_SDA 49
MAKE_BASE=TRUE
R5240
2
0 1
(* = Multiple options)
Vref DACs 5%
1/20W
MF Internal DP K16 K99
U3900 Samsung LGD Samsung LGD AUO
(Write: 0x98 Read: 0x99)
201
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88)
Parade T-con - (0x10-0x1F or 0x30-0x3F)
N
Y
Y
N
*
*
Y
N
*
*
SMC "Management" SMBus Connections The bus formerly known as "Battery B"
33 =I2C_VREFDACS_SCL DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N
8 =PP3V3_S5_SMBUS_SMC_MGMT
33 =I2C_VREFDACS_SDA
Margin Control
SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC
U4900
R52901
2.0K
5%
1
R5291
2.0K
5%
1/20W 1/20W
U3910 =PP3V3_S3_SMBUS_SMC_A_S3 (MASTER) MF MF
8 201 2 2 201
C 38 SMB_MGMT_CLK 70 SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
C
33 =I2C_PCA9557D_SCL
SMC R52701 1
R5271 Left I/O Board 38 SMB_MGMT_DATA 70 SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
33 =I2C_PCA9557D_SDA 1K 1K
U4900 5% 5% J4700
1/20W 1/20W
(MASTER) MF MF (See Table)
201 2 2 201
Trackpad
EFI Debug Serial
U5101
Mikey
J4700 (LIO Connector)
38
38
SMB_A_S3_CLK
SMB_A_S3_DATA
70 SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
70 SMBUS_SMC_A_S3_SDA
=I2C_LIO_SCL
=I2C_LIO_SDA
7 37
7 37
J5700
MAKE_BASE=TRUE
(Write: 0xAC/0xAE (Write: 0x72 Read: 0x73)
Read: 0xAD/0xAF) =I2C_TPAD_SCL 7 46
40 =I2C_DEBUGROM_SCL =I2C_MIKEY_SCL 7 37
=I2C_TPAD_SDA
40 =I2C_DEBUGROM_SDA =I2C_MIKEY_SDA 7 37
Left I/O Board 7 46
ALS - N/A (Feature Removed)

Finstack Temp - (Write: 0x98 Read: 0x99)
MCP89 SMBus "1" Connections SMC "B" SMBus Connections

8 =PP3V3_S0_SMBUS_MCP_1 8 =PP3V3_S0_SMBUS_SMC_B_S0
NO STUFF NO STUFF
MCP89 R52301 1
R5231 SMC R52601 1
R5261 CPU Temp
2.0K 2.0K 4.7K 4.7K
U1400 5% 5% U4900 5% 5% EMC1413: U5515
B (Write: 0xE0 Read: 0xE1)
1/20W
MF
201 2
1/20W
MF
2 201
(MASTER)
1/20W
MF
201 2
1/20W
MF
2 201
(Write: 0x98 Read: 0x99) B
68 19 SMBUS_MCP_1_CLK 38 SMB_B_S0_CLK 70 SMBUS_SMC_B_S0_SCL =I2C_CPUTHMSNS_SCL 44
68 19 SMBUS_MCP_1_DATA 38 SMB_B_S0_DATA 70 SMBUS_SMC_B_S0_SDA =I2C_CPUTHMSNS_SDA 44
1 1
R5235 R5236
0 0
MCP89 SMBus 1 is slave port to 5% 5%
1/20W 1/20W
access internal thermal diodes. MF MF
201 2 2 201
Another slave port is available
at 0x10/0x11, probably not used.
MCP Temp
EMC1413: U5535
(Write: 0xD8 Read: 0xD9)
=I2C_MCPTHMSNS_SCL 44
=I2C_MCPTHMSNS_SDA 44
PAGE TITLE
K16/K99 SMus Connections

DRAWING NUMBER SIZE

REVISION
R
4.4.0
52 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR3 1V5R1V35 Current Sense / Filter
CPU Voltage Sense / Filter
8 =PP3V3_S3_1V5S3ISNS
8 7 PPVCORE_S0_CPU
XW5309
SM R5309
4.53K2
1 2 CPUVSENSE_IN 1 SMC_CPU_VSENSE OUT 38
PLACE_NEAR=L7400.2:5 MM 1%
1/20W 1 C5360
3
MF
201
1 C5309 V+
0.1UF
0.22UF 10%
20% 2 6.3V
2 6.3V
X5R U5360 X5R
201 R5365
201 INA210 4.53K2
D GND_SMC_AVSS 38 39 42 43
71 52 IN ISNS_1V5_S3_N 5 IN- SC70 OUT 6 ISNS_1V5S3_IOUT 1
1%
SMC_1V5S3_ISENSE OUT 39
D
Place RC close to SMC
71 52 IN ISNS_1V5_S3_P 4 IN+
(500V/V)
REF 1 GAIN: 200X 1/20W
MF
201
1 C5365
0.22UF
SCALE: 0.4A / V 20%
GND 2 6.3V
X5R
EDP Current: 7 A MAX VOUT: 3.5V 201
2
Max Vdiff: 13.0 mV (CLIPS AT 6.6A) GND_SMC_AVSS
MCP Voltage Sense / Filter WF: Verify SO-DIMM current!
PLACEMENT_NOTEs:
38 39 42 43
8 7 PPVCORE_S0_MCP XW5359
SM R5359 Place close to SMC
MCPVSENSE_IN 4.53K2 (For R and C)
1 2 1 SMC_MCP_VSENSE OUT 39
PLACE_NEAR=R7525.2:5 MM 1%
1/20W
MF
201
1 C5359
0.22UF
AirPort Current Sense / Filter
20%
2 6.3V
X5R 8 =PP3V3_S3_WLANISNS
201
GND_SMC_AVSS 38 39 42 43

1 C5370
3
V+
0.1UF
10%
2 6.3V
U5370 X5R
201 R5375
INA210 14.53K2
PBUS Voltage Sense Enable & Filter 71 34 IN ISNS_AIRPORT_N 5 IN- SC70 OUT 6 ISNS_P5VWLAN_IOUT SMC_WLAN_ISENSE OUT 39
1%
71 34 IN ISNS_AIRPORT_P 4 IN+
(200V/V)
REF 1 Gain: 200x 1/20W
MF
201
1 C5375
0.22UF
Q5315 GND Scale: 0.25A / V 20%
2 6.3V
NTUD3169CZ MAX VOUT: 3V X5R
C 201
C
2
SOT-963
N-CHANNEL 6 PBUSVSENS_EN_L (CLIPS AT 0.825A) GND_SMC_AVSS 38 39 42 43
D PLACEMENT_NOTEs:
EDP Current: 0.727 A?
R53161 Max Vdiff: 14.6 mV Place close to SMC
100K
57 IN =PBUSVSENS_EN 2 G 1% WF: Verify Airport current! (For R and C)
S 1/20W
MF
Enables PBUS VSense 201 2
divider when high.
1
3 PBUS_G3H_VSENSE HDD Current Sense / Filter
D
1 8 =PP3V3_S0_HDDISNS
R5317
5 G
27.4K
1%
S 1/20W
49 8 7 PPBUS_G3H MF
201 2 RTHEVENIN = 4573 Ohms
4 1 C5380
3
P-CHANNEL SMC_PBUS_VSENSE OUT 38 V+
0.1UF
10%
R5315 1 2 6.3V
100K
U5380 X5R
201 R5385
R53181 1 C5315 INA211
1%
1/20W 5.49K ISNS_HDD_N 5 IN- SC70 OUT 6 ISNS_P5VHDD_IOUT 14.53K2 SMC_HDD_ISENSE
MF 1% 0.22UF 71 35 IN OUT 39
201 2 1/20W 20% 1%

2 6.3V
PBUSVSENS_EN_L_DIV
MF
201 2 X5R
201 71 35 IN ISNS_HDD_P 4 IN+
(500V/V)
MF
201
1 C5385
0.22UF
GND_SMC_AVSS 38 39 42 43 SCALE: 0.667A / V 20%
GND 2 6.3V
X5R
MAX VOUT: 3.54V 201
2
(CLIPS AT 2.2A) GND_SMC_AVSS 38 39 42 43
PLACEMENT_NOTEs:
EDP Current: 1.2 A?
Max Vdiff: 24.0 mV Place close to SMC
B WF: Verify SSD current! (For R and C) B
LCD Backlight Driver Input Current Sense / Filter
8 =PP3V3_S0_BKLTISNS
1 C5390
3
V+
0.1UF
10%
2 6.3V
U5390 X5R
201 R5395
INA211 14.53K2
71 62 IN ISNS_LCDBKLT_N 5 IN- SC70 OUT 6 ISNS_LCDBKLT_IOUT SMC_LCDBKLT_ISENSE OUT 39
1%
71 62 IN ISNS_LCDBKLT_P 4 IN+
(500V/V)
MF
201
1 C5395
0.22UF
62 59 7 PPVOUT_SW_LCDBKLT
XW5310
SM GND SCALE: 0.2A / V 20%
2 6.3V
MAX VOUT: 3.33V X5R
1 2 LCDBKLT_VSEN 201
2
(CLIPS AT 0.66A)
PLACE_NEAR=D9701.2:5 MM PLACEMENT_NOTEs: GND_SMC_AVSS 38 39 42 43
R53191 EDP Current: ??? A Place close to SMC

1M
1% Max Vdiff: ??? mV (For R and C)
1/20W
MF WF: Verify LCD backlight current!
2012 R5321 PLACE_NEAR=U4900:5 MM
LCDBKLT_VSEN_DIV 1 226K 2 SMC_ADC15 OUT 38 39
1%
A R5320 1 1/20W
MF
201
PLACE_NEAR=U4900:5 MM
OMIT_TABLE SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
47K 1 C5310 PAGE TITLE
1%
1/20W
MF
2.2UF
20%
6.3V
Voltage & Current Sensing
2012 2 X5R DRAWING NUMBER SIZE
0402
REVISION
R
DIVIDER: 1/22 4.4.0
53 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DCIN (AMON) Current Sense, RMUX & Filter
ISL6259 Gain: 20x MCP MEM VDD Current Sense / Filter

R5481 8 =PP3V3_S0_MCPDDRISNS
CHGR_AMON 1
150K 2 SMC_DCIN_ISENSE
50 IN OUT 38
1%
D Sense R: R7020
From charger
1/20W
MF
201
NOSTUFF
R5482 1
1 C5487 C5400 1
0.1UF
D
Value: 20 mOhm 133K 0.0068UF 10%
MAX VOUT: 1.24V
1%
1/16W
MF-LF
402 2
10%
25V
2 CERM
6.3V 2
X5R
201
U5400
OPA330
402 5
21 IN MCPDDRFET_KELVIN 1 +IN
SC70-5
V+ 4 MCPDDR_SENSE_AMP
3
21 IN MCPDDRFET_SENSE -IN V-
PLACEMENT_NOTEs:
2
Place close to SMC
(For Rs and C) R54101
0
5%
1/20W R54111
MF 0
201 2 5%
1/20W
MF
MCPDDR_SENSE_E 2012
NOSTUFF
Battery (BMON) Current Sense, MUX & Filter CRITICAL
1 C5434
0.1UF
For engineering, stuff BMON:ENG Q5401 10%
2 2SA2154MFV-YAE 2 6.3V
X5R
8 =PP3V42_G3H_BMON_ISNS For production, stuff BMON:PROD SOD 201
1 MCPDDR_SENSE_B
BMON:ENG BMON:ENG
PLACEMENT_NOTE=Place near sense resistor CRITICAL
1 C5418 C5459 1 R5417
3
BMON:ENG 3
V+
0.1UF 0.1UF 4.53K2
10% 10% MCPDDR_SENSE_C 1 SMC_MCP_DDR_ISENSE
2 6.3V 6.3V 2 39
Charger/Load side
U5403 X5R X5R U5413 1%
OUT
201 201 NC7SB3157P6XG
CHGR_CSO_R_P 5 IN-
INA214
SC70 OUT 6 BMON_INA_OUT 1 B1 SC70 SEL 6 SMC_BMON_MUX_SEL R5412 1 1/16W
MF-LF
402
1 C5435
70 50 IN IN 38
118 0.22UF
BMON:ENG 1% PLACEMENT_NOTEs: 20%
GAIN: 100X 1 ISL6259 Gain: 36x 2 6.3V
C
C 70 50 IN CHGR_CSO_R_N 4 IN+
(100V/V)
REF 1 2 GND VCC 5
INA213 Gain: 50x
1/16W
MF-LF
402 2 Place close to SMC
X5R
402
GND SCALE: 1A / V R5401 (For R and C) GND_SMC_AVSS 38 39 42 43

Battery side 0
MAX VOUT: 3.00V 3 4 300K 2
BMON_AMUX_OUT SMC_BATT_ISENSE
2
1 38
OUT
NOTE: Monitoring current from (CLIPS AT 3.3A) B0 A
1%
battery to PBUS (battery VER 1 BMON:ENG 1/20W
discharge) across R7050 BMON:PROD 1 MF 1 C5490
R5423 201
0.0033UF
R5431 100K 10%
50V
5% 2 CERM
0 1/20W 402
50 IN CHGR_BMON 1 2 MF
5% 2 201 GND_SMC_AVSS 38 39 42 43
Sense R: R7050
From charger
Gain: 36x 1/20W
MF
201
PLACEMENT_NOTEs:
Value: 10 mOhm
Scale: 2.778A / V
Max Vdiff: 80mV R5431: PLACE_NEAR=U5413:2 mm
Max VOut: 2.88V (For R and C)
Chipset Regulators High-Side Current Sense / Filter
=PPBUS_G3H_R_IN
8 =PP3V3_S0_CSREGISNS
VERIFY ALL RESISTOR AND GAINS
8
1 C5417
3
CRITICAL 0.1UF
V+
R5492 1 3 10%
6.3V
2 X5R
0.002
1%
U5402 201 R5418
1W INA210 4.53K2
B MF
0612 2 4
71 ISNS_CSREG_N 5 IN- SC70 OUT 6 CSREG_IOUT 1
1%
SMC_CSREG_ISENSE OUT 39
B
71 ISNS_CSREG_P 4 IN+
(200V/V)
MF
201
1 C5436
0.22UF
8 =PPBUS_G3H_R_OUT 20%
GND SCALE: 2.5A / V 6.3V
2 X5R
MAX VOUT: 3.352V 402 CPU VCore Load Side Current Sense / Filter
2
PLACEMENT_NOTEs: R5471
15.0K2
Place close to SMC 53 IN IMVP6_PMON 1 SMC_CPU_ISENSE OUT 38
(For R and C) 1%
1/16W NOSTUFF
1
MF-LF
402 R5480 1 C5470
17.4K 0.068UF
1% 10%
PLACEMENT_NOTEs: 1/16W
MF-LF 2 10V
CERM
402 2 402
MCP VCore Current Sense Filter Place close to SMC
(For Rs and C)
R5416
4.53K2
8 =PP3V3_S0_MCPCOREISNS 54 IN MCPCORES0_IMON 1 SMC_MCP_CORE_ISENSE OUT 39
1%
1/20W
MF
201
1 C5472
1 C5420 0.22UF
3
20%
V+
0.1UF 6.3V
2 X5R
10%
2 6.3V 201
(Sense R "output") U5420 X5R
201 R5415 GND_SMC_AVSS 38 39
INA214 0
42 43
9 IN =MCPCOREISNS_N 5 IN- SC70 OUT 6 MCPCORE_IOUT 1 2 PLACEMENT_NOTEs:

A 9 =MCPCOREISNS_P 4 IN+ REF 1
Gain: 100x 5%
1/20W
MF
Place close to SMC SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
IN PAGE TITLE
(100V/V) 201 (For R and C)
(Sense R "input")
GND
Scale: 10A / V
MAX VOUT: 2.38V
Current Sensing
NOTE: Do not stuff R5415 and DRAWING NUMBER SIZE
2
Sense R is R7525, 1mOhm

Max Vdiff = 24.8mV R7593 at the same time! Apple Inc. 051-8379 D
REVISION
R
4.4.0
54 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU T-Diode Thermal Sensor

D 8 =PP3V3_S0_CPUTHMSNS R5515 FIXME: OFFGRID D
47
1 2 PP3V3_S0_CPUTHMSNS_R
5% MIN_NECK_WIDTH=0.25 mm
1/20W VOLTAGE=3.3V
MF
201
1 C5515
0.1UF
CPU_THERMD_P 10%
R5516 1
1
71 10 BI 1 6.3V
2 X5R R5517
VDD 201 10K 10K
1% 5%
C5521 1 U5515 1/20W 1/20W
CPU Thermal Diode 2.2NF EMC1413

MF
201
MF
201
10% DFN 2 2
10V 2
X5R 2 DP1 THERM*/ADDR 7 CPUTHMSNS_THERM_L
201
71 10 CPU_THERMD_N 3 DN1CRITICAL ALERT* 8 CPUTHMSNS_ALERT_L
BI
DRAMTHMSNS_D2_P 4 DP2/DN3 SMDATA 9 =I2C_CPUTHMSNS_SDA 41

BI
DRAM/SSD Temperature
Addr: 0x98(Wr)/0x99(Rd)
CRITICAL
3 C5520 1 5 DN2/DP3 SMCLK 10 =I2C_CPUTHMSNS_SCL BI 41
2.2NF GND THRM_PAD
Q5501 1 10%
10V 2 6 11
BC846BMXXH X5R PLACEMENT_NOTE=Place U5515 near CPU
SOT732-3 201 Local sensor for CPU Proximity
2 71 DRAMTHMSNS_D2_N
PLACEMENT_NOTE=Place Q5501 near DRAMs below MCP
C C
MCP T-Diode Thermal Sensor

8 =PP3V3_S0_MCPTHMSNS R5535
1
47 2 PP3V3_S0_MCPTHMSNS_R
1/20W VOLTAGE=3.3V
MF
201
1 C5535
0.1UF R5536 1 1
R5537
10%
71 19 MCP_THMDIODE_P 6.3V
2 X5R 15K 10K
BI
201 1% 5%
VDD 1/20W 1/20W
C5522 1 U5535 MF
201
MF
201
MCP Thermal Diode 2.2NF EMC1413 2 2
10%
10V 2 DFN
X5R MCPTHMSNS_THERM_L Addr: 0xD8(Wr)/0xD9(Rd)
B 201 DP1 THERM*/ADDR
CRITICAL MCPTHMSNS_ALERT_L
B
71 19 BI MCP_THMDIODE_N DN1 ALERT*
71 MLBR_THMDIODE_P DP2/DN3 SMDATA =I2C_MCPTHMSNS_SDA BI 41
3 DN2/DP3 SMCLK =I2C_MCPTHMSNS_SCL BI 41

CRITICAL C5523 1 GND THRM_PAD
2.2NF
Q5535
BC846BMXXH
1 10%
10V 2
PLACEMENT_NOTE=Place U5535 near MCP
X5R
SOT732-3 201 Local sensor for MCP Proximity
2
71 MLBR_THMDIODE_N
PLACEMENT_NOTE=Place Q5535 near J9000
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE

REVISION
R
4.4.0
55 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C
FAN CONNECTOR C
8 =PP5V_S0_FAN
8 =PP3V3_S0_FAN
CRITICAL
R56601 J5600
FF14A-4C-R11DL-B-3H
47K 5% NC
F-RT-SM
5
R5665 2
1/20W
MF
201 1 5V DC
38 SMC_FAN_0_TACH 1 47K 2 FAN_RT_TACH
7 2 TACH
5% 3
1/20W
MF 4 MOTOR CONTROL
201 GND
NC 6
R56611
100K
5% Q5660 518S0793
1
1/20W
MF SSM3K15FV
G
201 2 SOD-VESM-HF
FAN_RT_PWM
D
7
SMC_FAN_0_CTL
3
2
38
B B
PAGE TITLE
Fan
DRAWING NUMBER SIZE

REVISION
R
4.4.0
56 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IPD Flex Connector

IPD_3V3:S5
R5730
D 8 =PP3V3_S5_TPAD 1
0 2
D
5% 1/16W MF-LF
402 CRITICAL
IPD_3V3:S3
R5731 J5700
FF14A-14C-R11DL-B-3H
0 F-RT-SM
8 =PP3V3_S3_TPAD1 2 7 PP3V3_TPAD_CONN
VOLTAGE=3.3V MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm 15
5% 1/16W MF-LF
402
C5700 1 1
0.1UF
10%
39 38 OUT SMC_PME_S4_L 2
6.3V
X5R 2 3
201
PLACE_NEAR=J5700.1:1.5MM 4
71 46 7 BI USB_TPAD_CONN_P 5
71 46 7 USB_TPAD_CONN_N 6
BI
7
L5720 46 41 7 BI =I2C_TPAD_SDA 8
FERR-120-OHM-1.5A 46 41 7 BI =I2C_TPAD_SCL 9
56
PP5V_S5_LDO 1 2 7 PP5V_TPAD_FILT 10
VOLTAGE=5V MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm11
0402-LF 46 39 38 7 OUT SMC_ONOFF_L
C5710 1 49 46 39 38 7 IN SMC_LID 12
0.1uF 13
20%
10V
2 46 39 7 OUT SMC_TPAD_RST_L 14
CERM
402
=PP3V42_G3H_TPAD
8 7
518S0794 C
C
C5720 1
0.1UF
10%
6.3V
X5R 2
201
L5710
90-OHM
DLP0NS
SYM_VER-1
71 68 18 USB_TPAD_P 4 3 USB_TPAD_CONN_P 7 46 71
BI BI
71 68 18 BI USB_TPAD_N 1 2 USB_TPAD_CONN_N BI 7 46 71
=I2C_TPAD_SDA 7 41 46
=I2C_TPAD_SCL 7 41 46
C5732 1 SMC_ONOFF_L 7 38 39 46
B 100PF
10%
25V
2
B
X7R-CERM
201 C5733 1 SMC_LID 7 38 39 46 49
PLACE_NEAR=J5700.8:1.5MM100PF
10%
25V
X7R-CERM 2 C5734 1 SMC_TPAD_RST_L 7 39 46
201
PLACE_NEAR=J5700.9:1.5mm100PF
10%
25V
X7R-CERM 2 C5735 1
100PF
10%
25V
X7R-CERM 2 C5736 1
201 100PF
PLACE_NEAR=J5700.12:1.5MM 10%
25V
X7R-CERM 2
201
PAGE TITLE
WELLSPRING 1
DRAWING NUMBER SIZE

REVISION
R
4.4.0
57 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PP3V3_S5_ROM
SPI:31MHZ&SPI:62MHZ SPI:41MHZ&SPI:62MHZ
R61501 1
R6101 C6100 1 CRITICAL 1
R6151
8
10K 3.3K 10K
C 5%
1/20W
MF
5%
1/20W
MF
0.1UF
10%
6.3V 2
VCC
U6100
5%
1/20W
MF
C
201 2 X5R
2 201 201 32MBIT 2 201
SOP
68 40 IN SPI_MLB_CLK 6 SCLK SI/SIO0 5 SPI_MLB_MOSI IN 40 68
MX25L3205DM2I-12G
SPI_MLB_CS_L 1 CE* OMIT_TABLE

68 40 IN
SO/SIO1 2 SPI_MLB_MISO OUT 40 68
SPI_WP_L 3 WP*/ACC
40 19 7 IN SPIROM_USE_MLB 7 HOLD*
SPI:25MHZ&SPI:41MHZ GND SPI:25MHZ&SPI:31MHZ
R61521 1
R6153
4
NOTE: If HOLD* is asserted
10K 10K
ROM will ignore SPI cycles. 5% 5%
1/20W 1/20W
MF MF
201 2 2 201
MCP89 SPI Frequency Select

Frequency SPI_MOSI SPI_CLK
25.0 MHz 0 0
31.2 MHz 0 1
B 41.7 MHz 1 0 B
62.5 MHz 1 1
NOTE: 42 & 62 MHz use FAST_READ command.
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
4.4.0
61 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER AMPLIFIERS
APN:353S2888
SPEAKER LOWPASS 80 HZ < FC < 132 HZ

D D
GAIN 6DB
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25 mm

R6614 MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
0
8 =PP5V_S3_AUDIO_AMP 1 2 PP5V_S3_U6610
5%
1/16W
MF-LF
402
C6607 1 NOSTUFF CRITICAL
A1
0.1UF
10%
6.3V 2
R66131 1
C6601 MIN_LINE_WIDTH=0.30 mm
X5R PVDD 100K 47UF MIN_NECK_WIDTH=0.20 MM
201 5% 20%
CRITICAL 1/20W 2 6.3V SPKRAMP_R_P_OUT
C6610 U6610 MF
201 2
POLY-TANT
2012-LLP
7 49
0.1UF MAX98300 MIN_LINE_WIDTH=0.30 mm

WLP
71 37 7 SPKRAMP_INR_P 1 2 71 MAX98300_R_P A3 IN+ OUT+ B1 MIN_NECK_WIDTH=0.20 MM
IN
71 MAX98300_R_N B3 IN- OUT- C1 SPKRAMP_R_N_OUT 7 49
CRITICAL 10%
6.3V
C6611 X5R
201 C2 SHDN*
0.1UF R_SPKRAMP_SHDN GAIN C3 R_AMP_GAIN
71 37 7 SPKRAMP_INR_N 1 2
IN B2 NC NOSTUFF
10% 1
6.3V
X5R R6610 R6612
201 PGND
100K
0
C 37 7 IN AUD_GPIO_3 1 2 5%
1/20W C
A2
MF
1 5% 2 201
R6611 1/20W
MF
100K 201
5%
1/20W
MF
2 201
B B
A SYNC_MASTER=AUDIO SYNC_DATE=02/09/2010 A
PAGE TITLE
AUDI0: SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
4.4.0
66 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MLB TO LIO POWER CABLE CONNECTOR
J6900
WTB-PWR-M82
M-RT-SM
1 =PP18V5_DCIN_CONN 7 8
MIN_LINE_WIDTH=1mm
2 MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
3 1
C6905 APN:518S0519
4 0.01UF
CRITICAL
20%
5 50V
J6903
D 6 =PP5V_S3_LIO_CONN 7 8
2
CERM
603
78171-0002
M-RT-SM
D
3
518S0508 1 C6906
0.01UF
48 7 SPKRAMP_R_P_OUT 1
10% IN
2
10V
48 7 SPKRAMP_R_N_OUT 2
X5R IN
201
SPKR
8 =PP3V3_S3_DBGLEDS
S3_S0_LED
1 S3_S0_LED
1
R6940 R6941
1K
1K 5%
5% 1/16W
1/16W MF-LF
MF-LF 2 402
2 402
ITS_ALIVE CORE_VOLTAGES_ON_R
SIL ON MLB FOR DEVELOPMENT ONLY
SIL
D6900 C
C SYS_LED_ANODE
39 A K 998-3029
A S3_S0_LED A S3_S0_LED
D6910 D6920 GREEN-3.6MCD J6955
GREEN-3.6MCD GREEN-3.6MCD 2.0X1.25MM-SM HALL-SENSOR-MLB-PADS-K99
2.0X1.25MM-SM 2.0X1.25MM-SM SM
K K 8 1
NC NC
8 7 =PP3V42_G3H_HALL 7 2
6 3
CORE_VOLTAGES_ON 5 4
NC NC
R6961 OMIT_TABLE
3 S3_S0_LED 1
0 2
7 SMC_LID_R SMC_LID 7 38 39 46
D 5% NOSTUFF
Q6940 1/20W 1
C6955
2N7002DW-X-G MF
SOT-363 ALL_SYS_PWRGD 201 0.001UF
S G 5 25 38 57
10%
50V
2 CERM
402
4
HALL EFFECT PADS

S3 AND S0 INDICATOR LEDS FOR DEVELOPMENT ONLY
B B
CRITICAL
D6905
BAT30CWFILM
SOT-323 3.425V "G3Hot" Supply
42 8 7 PPBUS_G3H 1
Supply needs to guarantee 3.31V delivered to SMC VRef generator
3 PPVIN_G3H_P3V42G3H
R6905 MIN_LINE_WIDTH=0.4 mm
10 MIN_NECK_WIDTH=0.2 mm
50 PPDCIN_G3H_OR_PBUS 1 2 PPDCIN_G3H_OR_PBUS_R 2 VOLTAGE=18.5V
VOLTAGE=18.5V
5% MIN_LINE_WIDTH=0.6MM
1/8W MIN_NECK_WIDTH=0.25MM P3V42G3H_BOOST
MF-LF DIDT=TRUE
805
3
1 1
C6990 C6994
2.2UF VIN BOOST 0.22UF
10% 20%
CRITICAL
CRITICAL 25V
X5R-CERM
2 U6990 6.3V
X5R
2 L6995
J6950 BATTERY CONNECTOR
603 LT3470A 201 33UH-20%-0.39A-0.435OHM
=PP3V42_G3H_REG 8
BAT-K99 8 SHDN* DFN SW 4 P3V42G3H_SW 1 2
F-RT-TH MIN_LINE_WIDTH=0.5 mm Vout = 3.425V
BIAS 2 MIN_NECK_WIDTH=0.25 mm
DP418C-SM
POS 1 50 7 PPVBAT_G3H_CONN CRITICAL SWITCH_NODE=TRUE DIDT=TRUE
7 NC 60MA MAX OUTPUT
POS 2 NC
FB 1 <Ra>
POS 3 (Switcher limit)
7 SYS_DETECT_L THRM R6995
1
SCL 4 GND PAD 1

C6995
348K
5
9
SDA 5 =SMBUS_BATT_SDA 22PF 1%
5%
1/20W
SYS_DETECT 6 41 2
50V
MF CRITICAL
CERM
7 201 201
2 1
OMIT_TABLE
NEG =SMBUS_BATT_SCL 41 C6999
A NEG 8
9
CRITICAL
D6950 1
C6950 1
C6951 1
P3V42G3H_FB
<Rb>
10UF
20%
6.3V
1
NEG RCLAMP2402B R6950 2

X5R PAGE TITLE
SHLD_PIN 10
SC-75
NOSTUFF
10K
5%
1/20W
0.1UF
10%
25V
2
1UF
10%
16V
2
R6996
200K
1 603-1
DC-In & Battery Connectors

SHLD_PIN 11 MF
X5R X5R
1% DRAWING NUMBER SIZE
402 402
SHLD_PIN 12
201
2
1/20W
MF
3
201
SHLD_PIN 13 2
REVISION
R
4.4.0
Vout = 1.25V * (1 + Ra / Rb) THE INFORMATION CONTAINED HEREIN IS THE
518-0369 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
69 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
This node is powered

through body diodes:
Inrush Limiter
Reverse-Current Protection * DCIN through Q7080.
* PBUS through Q7085,
Charger TOP FETs and
Q7055.
FROM ADAPTER
CRITICAL CRITICAL
PPDCIN_G3H_OR_PBUS
8 =PPDCIN_S5_CHGR Q7080
SI5419DU MIN_LINE_WIDTH=0.6 mm
49
Q7085
SI5419DU
POWERPAK MIN_NECK_WIDTH=0.25 mm POWERPAK
VOLTAGE=18.5V PPDCIN_G3H_INRUSH
D 1
5A 5A
1
VOLTAGE=18.5V D
D
5 1 1 5
S
R7080 C7085 1 R7085
100K 470K
G
0.1UF
5% 1%
10%
1/20W 25V 1/20W
4
MF 2 MF
X5R
201 201
2 402 2
CHGR_SGATE_DIV CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
1 1
R7081 R7086
62K 332K
5% 1%
CRITICAL 1/20W 1/20W
MF MF
201 201
D7005 2 2
BAT30CWFILM
SOT-323 (CHGR_SGATE) (CHGR_AGATE)
1
R7005
20
3 CHGR_DCIN_D_R 1 2
(CHGR_DCIN)
R7021
10
5% 1 2
2 1/20W CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV MF 5%
201 1/20W 70 CHGR_CSI_R_P 3 1
1 R7020
C7020 MF
DIVIDER SETS ACIN THRESHOLD AT 12.18V 201 0.020
0.047UF 0.5%
10% 1W
16V
Input impedance of ~40K meets 2 70 CHGR_CSI_R_N MF-LF
30mA max load

X7R R7022 0612
402 4 2
sparkitecture requirements 10
1 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.2 mm 4.7 5% MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.1 mm 1 2 PP5V1_CHGR_VDDP 1/20W MIN_NECK_WIDTH=0.4 mm CRITICAL CRITICAL PLACE_NEAR=Q7030.5:1.5mm
VOLTAGE=5.1V MIN_LINE_WIDTH=0.2 mm MF VOLTAGE=18.5V
1 1 1 1 1
5% MIN_NECK_WIDTH=0.2 mm 201
C7030 C7031 C7035 C7036 C7037
57 8 =PP3V42_G3H_CHGR 1/16W VOLTAGE=5.1V
MF-LF 33UF-0.06OHM 33UF-0.06OHM 1UF 1UF 0.001UF
1 1 1 10% 10% 10%
402 C7001 C7022 C7021 20% 20%
25V 25V 50V
2 25V 2 25V 2 2 2
1UF 0.1UF 0.1UF POLY-TANT POLY-TANT X5R X5R X7R
C
1
R7010
30.1K
1%
C7002
1UF
10%
1
1
10%
10V
X5R
402
2
10%
25V
X5R
402
2 2
10%
25V
X5R
402
CASE-D3L CASE-D3L 603-1 603-1 402
C
1/20W
10V
2
NO STUFF R7002
X5R
19
20
MF GND_CHGR_AGND 100K
402
201 50 5%
2
1/20W 5
MF VDD VDDP
R7000 2
201 OMIT_TABLE
12 VHST CRITICAL DCIN 2 CHGR_DCIN
D CRITICAL
0 Max Current = 8A
40 39 38 7 IN SMC_RESET_L 1 2 CHGR_RST_L 13 SMB_RST_N Q7030
SGATE 26 CHGR_SGATE PLACE_NEAR=U7000.25:2mm
5% 41 IN =SMBUS_CHGR_SCL 11 SCL 4 G
1/20W U7000 AGATE 1 CHGR_AGATE 1
C7025
RJK0332DPB-01
MF 41 BI =SMBUS_CHGR_SDA 10 SDA TQFN
0.22UF
LFPAK-SM
CSIP f = 400 kHz

ISL6259HRTZ
201 28 70 CHGR_CSI_P
4 10%
57 IN CHGR_VFRQ VFRQ 10V
6
CSIN 27 70 CHGR_CSI_N 2
CERM S
CHGR_CELL CELL 402
CRITICAL CRITICAL
TO SYSTEM
Float CELL for 1S
3
BOOT 25 CHGR_BOOT L7030 F7040
CHGR_ACIN ACIN DIDT=TRUE 1 2 3 4.7UH-9.5A
UGATE 24 CHGR_UGATE 7AMP-24V
GATE_NODE=TRUE DIDT=TRUE
1 2
1
CHGR_ICOMP 5 ICOMP PHASE 23 CHGR_PHASE =PPBUS_G3H 8
R7013 CHGR_VCOMP 7
VCOMP MIN_NECK_WIDTH=0.2 mm
IHLP4040DZ-SM
100 LGATE 21 CHGR_LGATE SWITCH_NODE=TRUE 1206-1
1% CHGR_VNEG 8 VNEG GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE
1/20W
1
MF
R7015 70 CHGR_CSO_P 18 CSOP BGATE 16 CHGR_BGATE
201
2 17
220K 70 CHGR_CSO_N CSON 20V/V AMON 9 CHGR_AMON
OUT 43
THRM_PAD
5%
1/20W 36V/V BMON 15 CHGR_BMON
OUT 43
MF PPVBAT_G3H_CHGR_REG
1 1
201 C7050 (OD) ACOK 14 =CHGR_ACOK 9 MIN_LINE_WIDTH=0.6 mm
R7011 OUT
(AGND)
2
PGND
MIN_NECK_WIDTH=0.25 MM CRITICAL CRITICAL CRITICAL PLACE_NEAR=L7030.2:1.5mm

10.5K 0.47UF
VOLTAGE=8.4V
1% CHGR_VCOMP_R 10%
5
1 1 1 1
C7045
10V C7040 C7041 C7043
1/20W 2
X5R
62UF 62UF 62UF 1000PF
MF
29
22
402
20% 20% 20% 10%
201 353S2392 CRITICAL 16V
2 1
C7015 2 11V 2 11V 2 11V 2 X7R
ELEC ELEC ELEC
470PF Q7035 CASE-B2 CASE-B2 CASE-B2 201
10% 4
16V RJK0305DPB
2
X5R-X7R LFPAK-HF
201 R7050
0.01
B 1
0.5%
1W
MF
0612-3
CRITICAL
B
R7016 XW7000 1 2 3 1 2
3.01K SM
Q7055
3 4
1% SI7615DN
1/20W 1 2 (GND) PWRPK-1212-8
MF TO/FROM BATTERY
201 PLACE_NEAR=U7000.29:1mm
2
PLACE_NEAR=U7000.22:1mm
S
PPVBAT_G3H_CHGR_R
3
CHGR_VNEG_R MIN_LINE_WIDTH=0.6 mm
D
MIN_NECK_WIDTH=0.25 MM PPVBAT_G3H_CONN 7 49
5
VOLTAGE=8.4V MIN_LINE_WIDTH=0.6 mm
1 R7051
1
C7016 (CHGR_CSO_P) 2.2 1 2 70 43 CHGR_CSO_R_P VOLTAGE=8.4V
5% 1/20W MF 201
G
470PF
10%
(CHGR_CSO_N) R7052 0 1 2 70 43 CHGR_CSO_R_N
16V
2 5% 1/20W MF 201
4
X5R-X7R
201
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
1 1 1 1 1
C7042 C7011 C7000 C7005 C7026
0.1UF 0.01UF 1UF 0.22UF 1000PF * R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE
10% 10% 10% 20% 10%
6.3V 10V 10V 25V 16V
2
X5R X5R
2 2
X5R X5R
2
X7R
2 DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
201 201 402-1 603 201
C7012 1 C7013 1 1 C7014 1 C7017
50 GND_CHGR_AGND
0.01UF 0.1UF 1UF 10UF
10% 10% 10% 10%
10V 25V 25V 25V
VOLTAGE=0V
X5R
2 X5R
2 2 X5R
2 X5R
201 402 603-1 805
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE

REVISION
R
4.4.0
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT

70 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8
=PPVIN_S5_P5VP3V3
PLACE_NEAR=Q7220.5.2:1.5mm
CRITICAL 56 P5VP3V3_VREG5 CRITICAL PLACE_NEAR=Q7260.2:1.5mm

C7240 1 1 C7270 1
C7241 C7282 1 1
C7281 1 C7283
62UF 1000PF 1UF 51 8 =PP5V_S3_REG 62UF 1UF 1000PF
20% 10% 10% 51 P5VP3V3_VREG3 20% 10% 10%
11V 2 2 16V
X7R 2
16V
X5R
11V 2 2
16V
X5R 2 16V
X7R
ELEC ELEC
CASE-B2 201 402 CASE-B2 402 201
C7200 1 51 P5VP3V3_VREF2
1UF OMIT_TABLE OMIT_TABLE
23
29
22
13
10%
2
16V
X5R 2 C7201 1
C7203 1 1
C7205
5 P5VS3_VBST_R 402 0.22UF 1UF 10UF P3V3S5_VBST_R
V5SW
VIN
VREG5
VREG3
VREF2
MIN_LINE_WIDTH=0.6 mm 10% 10% 20%
10V 6.3V 6.3V MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm CERM 2 CERM 2 2 X5R MIN_NECK_WIDTH=0.2 mm
2
3
7
CRITICAL D DIDT=TRUE 402 402 603 DIDT=TRUE
F=400KHZ Q7220 1
C7224 R72451 6 SKIPSEL1
2
R7264 C7264 1
CRITICAL
RJK03E0DNS G 4
0.1UF 5%
0 19 SKIPSEL2
CRITICAL 0
5% 0.1UF
VIN/D1
Q7260
51 8 =PP5V_S3_REG HWSON-8 10%
1/16W
14 OCSEL U7201 1/16W 10%
SIZ700DT =PP3V3_S5_REG 8 57
C Vout = 5.0V S
2
25V
X5R
402
MF-LF
402 2 QFN
EN 12 =P5V3V3_REG_EN IN 57 MF-LF
1 402
25V
X5R
402
2
1
POWERPAIR-6X3.7
Vout = 3.3V C
TPS51980
GHS/G1
CRITICAL P5VS3_VBST 31 VBST1 VBST2 26 P3V3S5_VBST CRITICAL
5.6A MAX OUTPUT L7220 MIN_LINE_WIDTH=0.6 mm DIDT=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm VSW/S1/D2 8 L7260
5.3A MAX OUTPUT
3 2 1 MIN_NECK_WIDTH=0.2 mm 1 DRVH1 MIN_NECK_WIDTH=0.2 mm
2.5UH-14A P5VS3_DRVH DRVH2 24 P3V3S5_DRVH 2.5UH-14A
PLACE_NEAR=L7220.1:3mm MIN_LINE_WIDTH=0.6 mm DIDT=TRUE GATE_NODE=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm F=400KHZ
1 2 MIN_NECK_WIDTH=0.2 mm 32 SW1 MIN_NECK_WIDTH=0.2 mm 1 2
P5VS3_LL SW2 25 P3V3S5_LL
PCMC063T-SM MIN_LINE_WIDTH=0.6 mm DIDT=TRUE SWITCH_NODE=TRUE SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm CRITICAL
PLACE_NEAR=L7220.2:3mm MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 6 GLS/G2
PCMC063T-SM
P5VS3_DRVL 30 DRVL1 DRVL2 27 P3V3S5_DRVL 150UF-0.018OHM-1.8A
OMIT
CRITICAL 2 2 MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE GATE_NODE=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
mm
2 2 C7290
1 1 1 C7272
1
C7250 1
5 P5VS3_CSP1 7 CSP1 CSP2 18 P3V3S5_CSP2 10UF C7292 1000PF
C7252 XW7220 XW7221 GND/S2 XW7260 XW7261 20% 20% 10%
150UF 10UF SM SM
C7218 NO STUFF P5VS3_CSN1 8 CSN1 CSN2 17 P3V3S5_CSN2 C7288 SM SM
2
6.3V 6.3V 2 2 16V
X7R
20% 20%
10V CRITICAL D
R7248 X5R
603
TANT
201
0.1UF 0.1UF PLACE_NEAR=L7260.1:3mm
5
6.3V 2
X5R 2 1 1 P5VP3V3_VREG3 1 0 2 P5VS3_FUNC 11 MODE
1 1 CASE-B2-SM
POLY-TANT
CASE-B2-SM 805 Q7225 1 2 51 RF 3 P3V3S5_RF 1 2 PLACE_NEAR=L7260.2:1.5mm
5% 1/20W 201
RJK03E0DNS G 4 MF P5VS3_VFB1 9 VFB1 VFB2 16 P3V3S5_VFB2
1 C7271 HWSON-8 10% P5VS3_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 10%
PLACE_NEAR=L7260.2:3mm
1000PF PLACE_NEAR=L7220.1:3mm 16V 16V
10% X5R X5R
2 16V
X7R 2 S 402 P5VS3_EN_R 4 EN1 EN2 21 P3V3S5_EN_R 402
201 2
5 PGOOD1 PGOOD2 20
XW7222
PLACE_NEAR=L7220.1.2:1.5mm R7247 R7246 XW7262
SM
3 2 1
1
1.87K2 1 GND THRM_PAD 1
1.87K2
1 SM
1 R7236 1 NO STUFF R7238 1 NO STUFF
R7237 R7239
28
33
1% 6.04K 6.04K 1% 1
P5VS3_VFB1-R 1/20W 1% 20K XW7200 353S2678 1
R7206 1% 20K 1/20W
1
MF
201
1/20W
MF
1%
1/20W
1
R7249 SM
249K
1/20W
MF
1%
1/20W
MF
201 R7216 PLACE_NEAR=L7260.2:3mm
2
201 MF 0 1 2 1%
2
201 MF 3.16K P3V3S5_VFB2_R
201 5% 1/20W 201 1%
P5VS3_COMP1_R 2
1/20W MF
2
1/20W
1
R7256 C7237 1
MF
201
2
201 P3V3S5_COMP2_R MF
2 201
1
R7260
1
R7220 3.16K C7236 1 100PF
2
C7238 1
C7239 1
1% 0.01UF 10%
PLACE_NEAR=U7201.28:1mm 0.01UF 100PF 23.2K
41.2K 1/20W 25V
P3V3S5_CSP2_R 1%
10% 10% 10%
1% MF 10V X7R-CERM 2 10V 25V 1/20W
1/20W 201 2 X5R 2 201 X5R 2 X7R-CERM 2 MF
MF 201 201 201 2 201
2 201 P5VS3_CSP1_R
B 1
51 P5VP3V3_VREF2 51 P5VP3V3_VREF2
1
B
R7221 R7261
10K 10K
1% 57 OUT P5VS3_PGOOD 1%
1/20W 1/20W
MF MF
2 201 57 OUT P3V3S5_PGOOD 2 201
GND_P5VP3V3_SGND
VOLTAGE=0V
PLACE_NEAR=U7201.4:2mm PLACE_NEAR=U7201.21:2mm
1 1
R7251 R7252
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
402
2 2 402
57 IN =P5VS3_EN 57 IN =P3V3S5_EN
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE

REVISION
R
4.4.0
72 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PPVIN_S3_DDRREG
8 =PPVIN_S0_DDRREG_LDO
PLACE_NEAR=Q7330.1:1.5mm
OMIT_TABLE
CRITICAL CRITICAL
C7355 1
C7332 C7333
10UF C7330 1 C7331 1 1
1UF
1
1000PF
20%
6.3V 2
62UF 62UF 10% 10%
X5R 20% 20% 16V
11V 2 11V 2 2 X5R 16V
2 X7R
603 ELEC ELEC
CASE-B2 CASE-B2 402 201
8 =PP5V_S3_DDRREG R7305
1
4.7 2 PP5V_S3_DDRREG_V5FILT
1/16W VOLTAGE=5V
MF-LF
402 R73101 5
12K
1% D
1/20W
8 =PP3V3_S3_PDCISENS MF CRITICAL
C7300 1 C7305 1 201 2
Q7330
15
14
23
4.7UF 1UF
1 10% 10% SIS426DN
R7380 10V 2
X5R
10V
X5R 2 V5IN V5FILT VLDOIN (DDRREG_DRVH) 4
PWRPK-12128
100K 805 402-1 MIN_LINE_WIDTH=0.6 mm G
1/20W S
DDRREG_VDDQSNS
C MF
201 2
6 COMP
CRITICAL
VDDQSNS 8
1 2 3 CRITICAL
L7330
C
57 IN =DDRVTT_EN 10 S3 VTT Enable
MODE 4 C7325 0.82UH-20%-13A-0.0067OHM
=DDRREG_EN 0.1UF
57 IN 11 S5 VDDQ/VTTREF Enable
VBST 22 DDRREG_VBST (DDRREG_VBST) 1 2 1 2 PPDDR_S3_REG_R
OUT DDRREG_PGOOD 13 PGOOD VDDQ PGOOD U7300 DIDT=TRUE MIN_LINE_WIDTH=0.6 mm IHLP2525CZ-SM MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm 10% MIN_NECK_WIDTH=0.2 MM
TPS51116 VOLTAGE=1.5V
33 8 =PPVTT_S3_DDR_BUF DRVH 21 DDRREG_DRVH 16V
X5R 5
10mA max load QFN GATE_NODE=TRUE 402 CRITICAL
5 VTTREF DIDT=TRUE D
8 =PPVTT_S0_DDR_LDO
Vout = VDDQSNS/2 SYM (2 OF 2) LL 20 DDRREG_LL (DDRREG_LL) CRITICAL R7350 2 4
ISNS_1V5_S3_P OUT 42 71
24 VTT SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm 0.002
Vout = VTTREF
DIDT=TRUE MIN_NECK_WIDTH=0.17 mm Q7335 1%
1/4W ISNS_1V5_S3_N
XW7360
SM
DRVL 19 DDRREG_DRVL
GATE_NODE=TRUE
(DDRREG_DRVL)
MIN_LINE_WIDTH=0.6 mm 4 SIS426DN MF-LF
1206
OUT 42 71
DIDT=TRUE MIN_NECK_WIDTH=0.17 mm G PWRPK-12128 1 3 =PPDDR_S3_REG 8

1 2 DDRREG_VTTSNS 2 VTTSNS
CS 16 DDRREG_CS S
7 NC0 PLACE_NEAR=R7350.1:1.5MM CRITICAL
Vout = 1.501V / 1.352V
OMIT_TABLE OMIT_TABLE NC 1 2 3
C7360 1 1 C7361 NC 12 NC1 VDDQSET 9 33 DDRREG_FB C7346 1 C7341 1 13A Max Output
1000PF 330UF
22UF 22UF VTTGND THRM_PAD GND PGND CS_GND PLACE_NEAR=Q7335.1:1 mm 10%
16V 20% f = 400 kHz
20% 20% 2 2.5V 2
6.3V 2 6.3V XW7335 X7R TANT
1
25
18
17
X5R-CERM-1 2 X5R-CERM-1 SM
201 CASE-B2-SM
603 603
DDRREG_CSGND (DDRREG_CSGND) 1 2 CRITICAL OMIT_TABLE PLACE_NEAR=L7330.2:1 MM
XW7300 MIN_NECK_WIDTH=0.1 mm 1
C7340 1 C7345 2
330UF 10UF
SM
20% 20% XW7345
PLACE_NEAR=U7300.3:1 mm 1 2 PLACE_NEAR=U7300.25:1 mm 2 2.5V 2 6.3V
X5R
SM
TANT
CASE-B2-SM 603
1
LVDDR3:YES 1
C7320 1 R7320
B 1000PF
10%
16V
1%
15K
1/20W
B
(DDRREG_VDDQSNS) X7R 2 MF
C7350 1 MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm 201 2 201
33000PF <Ra>
10% (DDRREG_FB)
6.3V
X5R 2
201 LVDDR3:YES
GND_DDRREG_SGND (GND_DDRREG_SGND) 1
R7321
MIN_NECK_WIDTH=0.17 mm 18.7K
VOLTAGE=0V Vout = 0.75V * (1 + Ra / Rb) 1%
1/20W
MF
2 201
<Rb>
Use LVDDR3:YES for fixed 1.35V operation or LVDDR3:NO for fixed 1.5V operation.
114S0331 1 RES,15K,1%,1/16W,MF-LF,0402 R7321 LVDDR3:NO
PAGE TITLE
1.5V/1.35V LVDDR3 Supply

DRAWING NUMBER SIZE

REVISION
R
4.4.0
73 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IMVP6 CPU VCORE REGULATOR

D D
8 =PP3V3_S0_IMVP
8 =PPVIN_S5_CPU_IMVP
CRITICAL CRITICAL CRITICAL PLACE_NEAR=Q7400.1:1.5mm

1 1 1 1 C7453 1
C7458 C7459 C7456 1 C7457 1UF C7454
8 =PP5V_S0_CPU_IMVP 62UF 62UF 62UF 1UF
10%
10%
16V
1000PF
10%
20% 20% 20%
53 IMVP6_VBST_RC CRITICAL 2 11V 2 11V 2 11V
16V
2
X5R
2
16V
53 PP5V_S0_IMVP6_V5FILT ELEC ELEC ELEC 2
X5R
402
402 X7R
201
DIDT=TRUE CASE-B2 CASE-B2 CASE-B2
VOLTAGE=5V 1 C7412 Q7400
IRF6710
4.7UF
R74101 R74201 C7413 1 1 S1
1 10% R7415 C7414 1 1
0 0 R7411 2.2UF 2 6.3V
0 D NC
5%
1/20W
5%
1/20W
0
5%
20%
6.3V
2
X5R-CERM
603 5%
1/16W
1UF
10%
2
NC PWM FREQ. = 400KHZ
MF MF 1/20W
CERM1
MF-LF
16V
2 5
603 X5R-X7R
201 201 MF 402
2 2
2 201
PP1V7_S0_IMVP6_VREF
2 603-2 4 G 6 MAX CURRENT = 18A
21
53
VOLTAGE=1.7V CRITICAL DIDT=TRUE 3 S
GATE_NODE=TRUE
R74141 1 C7415
V5IN CRITICAL
R7480
3.01K
1%
100PF
5%
U7400 DIDT=TRUE CRITICAL
L7400
0.001
1%
1/20W
MF 2
25V
CERM
TPS51982RHB 0.36UH-30A-1.05MOHM 1W
MF-1
201
2 201 QFN (CPUIMVP_LL) 0612 =PPVCORE_S0_CPU_REG
53 IMVP6_DROOP 32 DROOP V5FILT 31 1 2 PPVCORE_S0_CPU_REG_R 2 1 8
C IMVP6_TONSEL 28 TONSEL
VBST 18 53 IMVP6_VBST DIDT=TRUE
SWITCH_NODE=TRUE
PCMC104T-SM
VOLTAGE=1.25V
4 3 C
6 VSNS DRVH 17 53 IMVP6_DRVH
5 GNDSNS LL 19 53 IMVP6_LL NCNC
DRVL 20 53 IMVP6_DRVL
1 VREF 1 2 6 7
22 PLACE_NEAR=R7480.1:1.5MM
16 PGOOD VR_PWRGOOD_DELAY OUT 25
D 1
65 12 11 IN CPU_VID<0> VID0 24 CRITICAL C7455
65 12 11 IN CPU_VID<1> 15 VID1
CLK_EN*
25
NC Q7451 1000PF
14 VR_ON IMVP_VR_ON IN 38 IRF6795 10%
65 12 11 IN CPU_VID<2> VID2 23 R7453 5 G DIRECTFET-MX 2 16V
13 DPRSLPVR IMVP6_DPRSLPVR 1 2
S
X7R
65 12 11 IN CPU_VID<3> VID3 9 DIDT=TRUE 201
NO STUFF DPRSTP* CPU_DPRSTP_L 499 1%
1 CPU_VID<4> 12 VID4
IN
GATE_NODE=TRUE
R7422 1R7421 65 12 11 IN 1/20W 201 MF 3 4
2.0K 10K 65 12 11 CPU_VID<5> 11 VID5 PWRMON 26 IMVP6_PMON 43
IN OUT
5% 5% 10 27
1/20W 1/20W 65 12 11 IN CPU_VID<6> VID6 TRIPSEL
MF MF 29 PM_DPRSLPVR IN 14 65
201
2 201 30 OSRSEL
2
53 IMVP6_ISLEW ISLEW 8
VR_TT* NC
4 7 NO STUFF
71 IMVP6_CS_P CSP THERM 1
71 IMVP6_CS_N 3 C7450
CSN
PGND
GND 100PF
5%
50V
CERM 2
402 R7451 470 1 2 71 IMVP6_CS_R_P
2
33
5% 1/20W MF 201
R7452 470 1 2 71 IMVP6_CS_R_N R7491
5% 1/20W MF 201 0
1 2 CPU_VCCSENSE_P 11 65
5%
1 C7460 65 IMVP6_VSEN_P 1/20W
MF
0.22UF 201
10%
2
10V
CERM
53 IMVP6_THERM 65 IMVP6_VSEN_N R7492
402
0
R74251 1 2 CPU_VCCSENSE_N 11 65
B 124K
1%
1
R7426
150K
C7452
100PF
10%
1
1 C7451
100PF
5%
1/20W
B
1/20W 5% MF
25V 10% 201
2
MF
201
2
1/20W
MF
201
X7R-CERM
201 2
25V
X7R-CERM OCP = 21.5MV / R7480 + 3.1A
2 201
53 GND_IMVP6_SGND VPMON = 90 X R7480 X VO X IO

VOLTAGE=0V
XW7400 18A @ 1V = 1.62V
1
SM
2
LOAD LINE = R7480 X 6 / (500U X R7414)
IMVP6_TRIPSEL
IMVP6_OSRSEL
MIN_LINE_WIDTH MIN_NECK_WIDTH
53
GND_IMVP6_SGND 0.50 MM 0.20 MM
53
IMVP6_DROOP 0.25 MM 0.20 MM
A SYNC_MASTER=POWER SYNC_DATE=07/13/2005 A
IMVP6_THERM 0.25 MM 0.20 MM PAGE TITLE
53
IMVP6_LL
MIN_LINE_WIDTH
1.5 MM
MIN_NECK_WIDTH
0.20 MM
53
53
IMVP6_ISLEW 0.25 MM 0.20 MM IMVP6 CPU VCore Regulator
53
PP1V7_S0_IMVP6_VREF 0.25 MM 0.20 MM DRAWING NUMBER SIZE
IMVP6_VBST 0.25 MM 0.20 MM
53
IMVP6_DRVH 1.5 MM 0.20 MM
53
PP5V_S0_IMVP6_V5FILT 0.25 MM 0.20 MM
53
REVISION
IMVP6_DRVL 1.5 MM 0.20 MM R
53
IMVP6_VBST_RC 1.5 MM 0.20 MM
4.4.0
53 I787 NOTICE OF PROPRIETARY PROPERTY: BRANCH
74 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PPVIN_S0_MCPCORE
D 8 =PP5V_S0_MCPREG
CRITICAL
D
R7560 CRITICAL CRITICAL PLACE_NEAR=Q7560.5:1.5mm
PP5V_S0_MCPREG_VDD 1
2.2
2 MCPCORES0_BOOT_R C7540 1
C7541 1 1
C7561 1
C7563
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.25 MM 62UF 62UF 1UF 1000PF
MIN_NECK_WIDTH=0.2 MM 5% MIN_NECK_WIDTH=0.2 MM 20% 20% 10% 10%
1/10W 11V 11V 16V 16V
VOLTAGE=5V DIDT=TRUE 2 2 2 X5R 2 X7R
MF-LF 1
C7562 2
R7565 ELEC ELEC
402 201
R7561 1 603
1UF C7564 1 CASE-B2 CASE-B2
1K
1
C7550 10%
0 0.22UF 5
16
22
5%
5%
1UF 2
16V
1/10W
5%
D
10% X5R 10V
1/20W 16V VDD PVCC 402 MF-LF CERM-X7R 2
CRITICAL
MF 2 X5R 1
603 603
201
2 402
U7500 Q7560
QFN (MCPCORES0_UGATE) 4
SIS426DN
MCPCORES0_RBIAS 1 RBIAS VIN 14
ISL9563B
PWRPK-12128
MIN_LINE_WIDTH=0.5 MM G CRITICAL
MCPCORES0_SOFT 2 SOFT GATE_NODE=TRUE S CRITICAL R7525
UGATE 18 MCPCORES0_UGATE DIDT=TRUE 0.001
1 2 3 L7560 1%
NOSTUFF MIN_LINE_WIDTH=0.25 MM 0.47UH-20%-0.0021OHM-26A
43 OUT MCPCORES0_IMON R7593 0 1 2 MCPCORES0_IMON_R 28 IMON BOOT 17 MCPCORES0_BOOT MIN_NECK_WIDTH=0.2 MM 1W
5% 1/20W MF 201 DIDT=TRUE MF-1 =PPMCPCORE_S0_REG 8 54
1 2 PPMCPCORE_S0_R 0612
57 OUT MCPCORES0_PGOOD 31 PGOOD PHASE 19 MCPCORES0_PHASE (MCPCORES0_PHASE) MIN_LINE_WIDTH=0.5 MM 1 2 MAX CURRENT: 15A
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.5 MM PCMB103T-SM MIN_NECK_WIDTH=0.2 MM
19 IN MCP_VID<0> R7590 0 1 2 MCP_VID0_REG 24 VID0 DIDT=TRUE MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V 3 4 CRITICAL (Q7560 Limit)
5% 1/20W MF 201 5
19 IN MCP_VID<1> R7591 0 1 2 MCP_VID1_REG 25 VID1 5 1 C7566 1
C7565 f = 300 kHz
5% 1/20W MF 201 D
19 IN MCP_VID<2> R7592 0 1 2 MCP_VID2_REG 26 VID2 CRITICAL CRITICAL D 10UF
20%
270UF
5% 1/20W MF 201 20%
19 IN MCP_VID<3> R7594 0 1 2 MCP_VID3_REG 27 VID3 CRITICAL PLACE_NEAR=R7525.1:1.5MM 2
4V
2 2V
5% 1/20W MF 201
23 NC
Q7565 Q7566 1 C7569
X5R
603
TANT
CASE-B4-SM
NC SIS426DN
57 =MCPCORES0_EN 29 VR_ON 4 SIS426DN 1000PF CRITICAL
IN PWRPK-12128 4 10%
G PWRPK-12128 16V
54 8 =PPMCPCORE_S0_REG MCPCORES0_FDE 30 AF_EN LGATE 21 MCPCORES0_LGATE
S
G 2 X7R C7567 1
C7568 1
32 FDE MIN_NECK_WIDTH=0.2 MM S 201 10UF 270UF
20% 20%
GATE_NODE=TRUE
1 MCPCORES0_VSEN 8 VSEN 1 2 3 4V 2V
R7563 DIDT=TRUE
1 2 3 X5R 2
TANT
2
MCPCORES0_RTN 603
100 9 RTN CASE-B4-SM
C 1%
1/20W
MF MCPCORES0_VW 4 VW
C
2 201
R7566 (MCPCORES0_VSEN)
20 VO 12 9 MCPCORES0_VO (MCPCORES0_VO)
71 22 IN MCPCORES0_VSEN_P 1 2
1% MCPCORES0_COMP 5 COMP OCSET 3 MCPCORES0_OCSET R7569

1/20W 9.76K
MF
201
1
C7570 1 2
1000PF MCPCORES0_FB 6 FB ISP 13 MCPCORES0_ISP 1%

10% 1/20W
16V 11 MCPCORES0_ISN 1
R7568 2 X7R ISN MF
R7573 1
20 201
MCPCORES0_VDIFF 7 VDIFF 201
10K
C7573
71 22 MCPCORES0_VSEN_N 1 2 ICOMP 10 MCPCORES0_ICOMP 1%
47PF
IN 5%
1/20W 25V
1% (MCPCORES0_RTN) PGND VSS THRM_PAD MF NP0-C0G 2
1/20W
MF 1
C7577 2 201 201 R7500
20
15
33
201
1 1 1000PF 100
R7571 R7572 1 2 9 MCPCORES0_ISP_R
1
C7576 10%
16V
1
C7578
100 147K 0.1UF 2 X7R 1000PF (MCPCORES0_ISN) 1%
1% 1% 1/16W
10% 201 10% MF-LF
1/20W 1/20W 16V 16V
MF MF 2 2 402
X7R-CERM X7R 1
2 201 201 2 402 201 R7575 C7575 1
22.1K 47PF
1%
1/20W 5%
25V
MF NP0-C0G 2
(MCPCORES0_VW) XW7561 2 201 201
SM
1
GND_MCPCORES0_AGND 1 2 (MCPCORES0_ICOMP)
C7579 1 R7576 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM PLACE_NEAR=U7500.33:1mm
0.001UF 6.98K VOLTAGE=0V
1%
10%
C7580 50V
2
1/20W
MF
X7R
560PF 402 2 201
1 2
10%
C7581
Vimon = 31 * Io * R7525 * (1 + R7575/R7573)
B R7577
150K
50V
CERM
402
100PF B
1 2 MCPCORES0_COMP_C 1 2 (MCPCORES0_COMP) OCP = R7569 X 10UA / ( R7525 X (1 + R7575 / R7573) )
1%
1/20W 5%
MF 50V
201 CERM
402 VID<3:0> VOLTAGE
(MCPCORES0_FB)
1100 0.9750V
C7582
R7578 4700PF 1101 0.9625V
200 1 2
1 2 MCPCORES0_VDIF_C (MCPCORES0_VDIFF)
1%
1110 0.9500V
1/20W 10%
MF
201 R7579
100V
CERM 1111 0.9375V
3.01K 402
1 2 0000 0.9250V
1%
1/20W
MF
0001 0.9125V
201
0010 0.9000V
0011 0.8875V
0100 0.8750V
0101 0.8625V
0110 0.8500V
0111 0.8375V
1000 0.8250V
1001 0.8125V
A 1010 0.8000V
PAGE TITLE
1011 0.7875V MCP VCore Regulator

DRAWING NUMBER SIZE

REVISION
R
4.4.0
K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 75 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PPVIN_S0_CPUVTTS0
8 =PP5V_S0_CPUVTTS0
CRITICAL CRITICAL
Place XW7610, XW7611 R76011 1 C7601 C7620 1 C7621 1 1 C7622
at desired location for 2.2 10UF 62UF 62UF 1000PF
5% 20% 20% 20% 10%
remote sensing. 1/10W
10V
2 X5R CPUVTTS0_VBST 11V 2 11V 2 2 16V
X7R
MF-LF MIN_LINE_WIDTH=0.3 mm ELEC ELEC
603 2
603
MIN_NECK_WIDTH=0.2 mm CASE-B2 CASE-B2 201
55 8 =PPCPUVTT_S0_REG XW7610
SM
DIDT=TRUE
C7630 1 5
PLACE_NEAR=Q7630.1:1.5mm
PP5V_S0_CPUVTTS0_VCC 1UF
1 2 71 CPU_VTTSENSE_P MIN_LINE_WIDTH=0.6 mm 10%
MIN_NECK_WIDTH=0.2 mm 16V 2 D CRITICAL
VOLTAGE=5V
13
14
1 2 CPU_VTTSENSE_N X5R
71
402 Q7630
SM VCC PVCC CPUVTTS0_DRVH 4 G RJK03E0DNS
XW7611 R76041 2
R7644 U7600 MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
HWSON-8
3.01K 3.01K DIDT=TRUE
1%
1/20W
1%
1/20W
ISL95870 S CRITICAL
MF
201 2
MF
=CPUVTTS0_EN 3 EN
UTQFN
BOOT 12 CRITICAL
R7640
1 201 57 IN
1 2 3 0.001
<Ra> CPUVTTS0_FB 6 FB
CRITICAL
UGATE 11
L7630 1%
1W
0.82UH-20%-13A-0.0067OHM MF-1 =PPCPUVTT_S0_REG
C CPUVTTS0_SREF 4 SREF PHASE 10 CPUVTTS0_LL
1 2 PPCPUVTT_S0_REG_R
2
0612
1
Vout = 1.05V
8 55
C
MIN_NECK_WIDTH=0.2 mm IHLP2525CZ-SM MIN_NECK_WIDTH=0.2 mm 4 3 CRITICAL
CPUVTTS0_VO 8 VO LGATE 15 SWITCH_NODE=TRUE VOLTAGE=1.05V
DIDT=TRUE 5 PLACE_NEAR=L7630.2:1.5mm C7649 1 11.5A Max Output
CPUVTTS0_OCSET 7 OCSET
CRITICAL
C7623 1 270UF
20% f = 300 kHz
D 1000PF 2V 2
CPUVTTS0_PGOOD 9 10% TANT
57 OUT PGOOD
CPUVTTS0_DRVL 4 G
Q7635 16V 2
X7R CASE-B4-SM
CPUVTTS0_RTN 2 RTN MIN_LINE_WIDTH=0.6 mm RJK03E0DNS 201 CRITICAL OMIT_TABLE
MIN_NECK_WIDTH=0.2 mm HWSON-8
CPUVTTS0_FSEL 5 FSEL
GATE_NODE=TRUE
DIDT=TRUE
1
C7648 1 C7647
1 1 270UF 10UF
R7605 R7645 GND PGND S
20% 20%
2.74K 2.74K 1 2 2V 2 6.3V
X5R
R7603 TANT
16
1% 1%
1/20W
MF
1/20W
MF
C7602 1
0
1 2 3 CASE-B4-SM 603
201 2 2.2UF
2 201 10% 5%
1/20W
<Rb> 16V 2
X5R MF
603 2 201
71 CPUVTTS0_CS_P
C7604 1 1 C7605 1 C7603
1000PF 1000PF 0.047UF 71 CPUVTTS0_CS_N
10% 10% 10% 1
16V 2
X7R 2 16V
X7R 2 16V
X7R XW7600 R7641
201 201 402 SM 1.78K
1%
CPUVTTS0_AGND 1 2 1/20W
MF
201 2 C7640
VOLTAGE=0V 1000PF
2 1
5%
25V 1
NP0-C0G
402
R7642
1.78K
1%
1/20W
MF
B (CPUVTTS0_OCSET) 2 201 B
(CPUVTTS0_VO)
OCP = R7641 x 8.5uA / R7640
Vout = 0.5V * (1 + Ra / Rb)
PAGE TITLE
CPUVTT (1.05V) Power Supply

DRAWING NUMBER SIZE

REVISION
R
4.4.0
76 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V S0 Regulator
8 =PP3V3_S0_P1V5S0 PLACE_NEAR=U7710.1:1.5mm
PLACE_NEAR=U7710.1:1.5mm
1
C7710
1 C7712
1000PF
D 2
22UF
20%
CERM
10%
2 16V
X7R CRITICAL
D
6.3V
805
201 L7710
2.2UH-3.25A =PP1V5_S0_REG 8
P1V5S0_SW 1 2
1
VIN
MIN_NECK_WIDTH=0.2 mm IHLP1616BZ-SM
Vout = 1.508V
SWITCH_NODE=TRUE
U7710 DIDT=TRUE
C7711 1
1
R7711 MAX CURRENT = 1.5A
ISL8009B 47PF 100K
DFN 5% 1%
1/20W
f = 1.6MHZ
25V
P1V5S0_EN 2 EN CRITICAL LX 8 NP0-C0G 2 MF
57 IN 201 2 201
57 OUT P1V5S0_PGOOD 3 POR VFB 6 P1V5S0_FB <Ra> PLACE_NEAR=L7710.2:1.5mm
4 SKIP RSI 5
1 C7715 1 C7716
1 22UF 1000PF
R7712 20% 10%
GND THRM_PAD 113K 2 6.3V
CERM 2 16V
X7R
7 9 1% 805 201
1/20W
MF
2 201
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
1.05V S0 MCP PLL LDO MCPPLL_R:REG
8 =PP3V3_S0_MCP_PLL_VLDO
IPD_5V:S5_INT =PP1V05_S0_MCP_PLL_UF_R R7745
MCPPLL_R:LDO 8
PLACE_NEAR=J5700.10:1.5mm 0
R7761 R77431 1 2
5.0V S5 IPD LDO P5VP3V3_VREG5 1

5%
0 2
8 =PP1V5_S0_MCP_PLL_VLDO
100
5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
=PP1V05_S0_MCP_PLL_OR
C 1/16W
MF-LF
402
MCPPLL_R:LDO
402 2
PP3V3_S0_MCP_PLL_LDO_BIAS
MCPPLL_R:LDO
8
C
IPD_5V:S3 R77501 MIN_LINE_WIDTH=0.6 mm R7744
=PP5V_S3_TPAD 0 MIN_NECK_WIDTH=0.2 mm CRITICAL PP1V05_S0_MCP_PLL_REG 1
0 2
8
R7760 5% VOLTAGE=3.3V
4
0 1/16W MCPPLL_LDO MIN_LINE_WIDTH=0.6 mm
MF-LF MCPPLL_LDO
MIN_NECK_WIDTH=0.2 mm 5%
1 2 402 2 BIAS VOLTAGE=1.05V 1
1/16W Vout = 1.05V
=PPBUS_5V_S5 5% R7746 MF-LF
402
8 U7760 1/16W
MF-LF
PP1V5_S0_MCPPLLLDO
1 IN0 OUT0 9 1.37K Max Current = 0.5A
MIC5235-2.5V 402 PP5V_S5_LDO 46 MCPPLL_LDO MIN_NECK_WIDTH=0.2 mm 2 IN1 OUT1 10 1%
1/20W
SOT23-5 VOLTAGE=5V VOLTAGE=1.5V MF MCPPLL_LDO
1 IN OUT 5
C7741 1 U7740 201 2 1 C7742
1UF <Ra>
OMIT_TABLE 10% 5 EN FB 8 MCPPLLLDO_FB 4.7UF
6.3V 2 20%
IPD_5V:S5_EXT
57 IN P5V_S5_EN 3 EN NC 4 NC 1 C7760 Vout = 5.0V CERM
402 TPS74701 MCPPLL_LDO 4V
2 X5R
SON 1 402
IPD_5V:S5_EXT GND 2.2UF MAX CURRENT = 0.016A MCPPLLLDO_SS 7 SS PG 3 R7747
C7761 1 20%
10V MCPPLL_LDO MCPPLL_LDO
4.42K
2
1UF 2 X5R-CERM 1%
GND THRML_PAD 1/20W
10%
16V 2
402 C7740 1 1 C7743 MF
201 2
X5R 1UF 2.2NF
<Rb>
11
402 10% 10%
6.3V 2 2 10V
CERM X5R
402 201
Vout = 0.8V * (1 + Ra / Rb)

MCPPLL_LDO
R7748
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 0
BOMOPTIONs: MCPPLLLDO_PGOOD_R 1 2 MCPPLLLDO_PGOOD OUT 57
353S3034 1 IC,LDO,MIC5235,5V,1%,150MA,SOT23-5 U7760 IPD_5V:S5_EXT 5%

1/20W
MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER. MF
MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY. 201
TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE.
B TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE. B
MCP 0.9V S5 (AUXC) Switcher

PLACE_NEAR=U7750.1:1.5mm
57 8 =PP3V3_S5_P0V9S5
CRITICAL PLACE_NEAR=U7750.1:1.5mm
1 1 C7752
C7750 1000PF
22UF 10%
2 6.3V 16V
2 X7R
20% CRITICAL
CERM 201
805 L7750
2.2UH-3.25A =PP0V9_S5_REG 8
1 P0V9S5_SW
1 2 Vout = 0.902V
VIN MIN_NECK_WIDTH=0.2 mm IHLP1616BZ-SM
SWITCH_NODE=TRUE MAX CURRENT = 1.5A
U7750 DIDT=TRUE
C7751 1
1
R7751
ISL8009B
47PF 1%
2.55K f = 1.6MHZ
DFN 5% 1/20W
CRITICAL 25V
=P0V9S5_EN 2 EN LX 8 NP0-C0G 2 MF
CRITICAL
57 IN 201 2 201 PLACE_NEAR=L7750.2:1.5mm
P0V9S5_PGOOD 3 POR VFB 6 P0V9S5_FB <Ra> 1 C7755 1 C7756
57 OUT 22UF
20% 1000PF
A 4 SKIP RSI 5 1
R7752
2 6.3V
CERM
805
10%
2 16V
X7R SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
GND THRM_PAD 20K 201 PAGE TITLE
7 9 1%
1/20W
MF
Misc Power Supplies
2 201 DRAWING NUMBER SIZE
<Rb> Apple Inc. 051-8379 D
REVISION
Vout = 0.8V * (1 + Ra / Rb) R
4.4.0
77 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP3V3_S0_PWRCTL
Power Control Signals
S5 Rail Enables & PGOOD S0 Rail PGOOD Circuitry R78201
10K
5%
State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
1/20W
8 =PP3V42_G3H_PWRCTL MF Run (S0) 1 1 1
R7840 201 2
0 Sleep (S3) 1 1 0
U7750 EN tied to VIN 51 IN P5VS3_PGOOD 1 2
C7840 1 CRITICAL 5% Soft-Off (S5) 1 0 0
1
0.1UF =PP3V3_S5_P0V9S5 8 56 1/20W
10%
6.3V
VDD MF
201 R7841 Battery Off (G3Hot) 0 0 0
X5R 2 0
38 7 IN SMC_PM_G2_EN 201 U7840 =P0V9S5_EN OUT 56 51 IN P3V3S5_PGOOD 1 2
MAKE_BASE=TRUE SLG4AP012 S0 Rail PGOOD (ISL Version) 5%
D 51 OUT =P5V3V3_REG_EN TDFN

Internal pull-ups 100K +/- 20% R7842
1/20W
MF
201
D
8 7 PP5V_S0 1 0 2
2 IN_A OUT_A* 4 P3V3S5_EN_L OUT 57 56 IN P1V5S0_PGOOD
1 R7846 (IPD) (OD,IPU) S0PGOOD_ISL 5%
OUT_A 3 P3V3S5_EN =P3V3S5_EN OUT 51 R78701 1/20W
0 71 8 7 PP3V3_S5 6 IN_B (OD,IPU) MAKE_BASE=TRUE MF
R7843
5% 10K 201
1/16W Threshold: ?? 2:1 + NO STUFF 1%
MCPCORES0_PGOOD 1
0 2
MF-LF 1/16W
2 402 DLY > 10 ms 1.3V -
1 C7801 MF-LF
402 2
54 IN
5%
33000PF 1/20W
56 OUT P5V_S5_EN 10%
R7844 MF
NO STUFF S5PGOOD_DLY 7 DLY_1C
DLY OUT_B 8 2 6.3V
X5R PP3V3_S0_VMON 201
(OD,IPU) MIN_LINE_WIDTH=0.2 MM 0
1 C7846 201
S0PGOOD_ISL
VOLTAGE=3.3V
55 IN CPUVTTS0_PGOOD 1 2
0.47UF 1 C7841 THRM 5%
10% 1 S0PGOOD_ISL CRITICAL
2 10V 220PF GND PAD R7871 1/20W
MF
R7845
X5R 10% 20.0K C7870 1 S0PGOOD_ISL
9
201
7
402 25V 0
2 X7R-CERM 1% 0.1uF
201 1/16W 20% VDD VDDA 56 IN MCPPLLLDO_PGOOD 1 2
MF-LF 10V
402 2 5%
CERM 2
402 U7870 1/20W
MF
ISL88042IRTJJZ 201
TDFN
PP3V3_S0 3 V2MON
(IPU)
1
S0PGOOD_ISL
71 57 8 7 MR* NC
56 IN P0V9S5_PGOOD RSMRST_PWRGD OUT 38
R7872
MAKE_BASE=TRUE 71 57 8 7 PP1V5_S0 5 V3MON
10
57 8 7 PP1V05_S0 6 V4MON RST* 8 S0PGOOD_RST_L 1 2 ALL_SYS_PWRGD OUT 25 38 49
MAKE_BASE=TRUE
5%
GND THRM_PAD
S3 Rail Enables Worst-Case Thresholds: 1/20W
MF
9
VDD: 2.9140V 353S2718 201
V2MON: 3.000V
R7813 V3MON: 0.610V
0 V4MON: 0.610V
57 38 19 7 IN PM_SLP_S4_L 2 1 P5VS3_EN =P5VS3_EN OUT 51
MAKE_BASE=TRUE
5%
1/20W NO STUFF
C MF
201 1 C7813
0.068UF
S0 Rail PGOOD (BJT Version) C
10%
10V =PP3V3_S5_VMON
2 CERM 8
402 S0PGOOD_BJT
71 57 8 7 PP3V3_S0 R78261
R7812 S0PGOOD_BJT 150K
0 P3V3S3_EN =P3V3S3_EN 1 1%
1 2
OUT 58
R7821 1/20W S0PGOOD_BJT
MAKE_BASE=TRUE MF
5% 15K 201 2 R7828
1/20W NO STUFF 1%
MF 1/20W S0PGOOD_BJT 10
201 1 C7812 MF S0PGOOD_BJT_L S0PGOOD_BJT 1 2
0.47UF
10%
2 201 R7823 5%
1K 1/20W
2 10V VMON_3V3_DIV 1 2 VMON_Q2_BASE MF
4
X5R Need to re-characterize for power sequencing! 201
402
R7811
5%
1/20W
MF
201
5
Q1
ISL6259 Frequency Select
1
5.1K 2 DDRREG_EN =DDRREG_EN Q2 =PP3V42_G3H_CHGR
OUT 52 S0PGOOD_BJT CRITICAL 50 8
MAKE_BASE=TRUE 8
5%
1/20W =USB_PWR_EN R7824 NC S0PGOOD_BJT VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH
R7810 1 MF
201 1 C7810
OUT 7 36 37
71 57 8 7 PP1V5_S0 1
1K 2 VMON_Q3_BASE 7
Q3
Q7820 R78611
100K 0.47UF 5% ASMCC0179 10K
5% 10% 2 5%
1/20W 1/20W DFN2015H4-8 1/20W
MF 2 10V MF NC MF
X5R
201 2 402 Need to re-characterize for power sequencing! 201 1 201 2
Q4
S0PGOOD_BJT VFRQ:SLPS4&VFRQ:SLPS3 CHGR_VFRQ OUT 50
R7825 Q7860
1K SSM3K15FV D 3 VFRQ:LOW
PP1V05_S0 1 2 VMON_Q4_BASE 353S2809 VFRQ:SLPS4
3
57 8 7
1
SOD-VESM-HF
R7860
B
ENET Rail Enables 1
S0PGOOD_BJT
R7822
7.15K
5%
1/20W
MF
201 Worst-Case Thresholds:
VMON_EMITTER
S0PGOOD_BJT 57 38 19 7 PM_SLP_S4_L
R7864
1
0 2
5%
10K
1/20W
MF B
19 IN PM_SLP_RMGT_L =P3V3ENET_EN OUT 58 1% Q2: 0.XXXV R78271 5%
2 201
MAKE_BASE=TRUE 1/20W 1/20W 1 G S 2
=P0V9ENET_EN OUT 58 MF Q3: 0.640V 100 MF
201
2 201 Q4: 0.660V
5%
1/20W CHGR_VFRQ_GATE
MF VFRQ:SLPS3
201 2
3.3V w/Divider: 2.345V R7863
0
PM_SLP_S3_L
S0 Rail Enables 57 39 38 19 7 1
5%
1/20W
MF
2
201
R7859
57 39 38 19 7 IN PM_SLP_S3_L 2
100
5%
1 PM_SLP_S3_R_L
MAKE_BASE=TRUE
=P5VS0_EN OUT 58 WLAN Enable Generation
1/20W
2 2 2 2
=PBUSVSENS_EN OUT 42 "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
MF
201 R7881 R7880 R7882 R7884
33K 22K 15K 5.1K NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
5% 5% 5% 5%
R78791 1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
NOTE: "AC" term valid only when Q7891 is stuffed
100K 1 201 1 201 1 201 1 201
5%
1/20W
MF P3V3S0_EN =P3V3S0_EN OUT 58
201 2 MAKE_BASE=TRUE
PM_WLAN_EN_L OUT 34
56 P1V5S0_EN =P1V5S0_EN OUT
MAKE_BASE=TRUE Pull-up is with power FET.
MCPCORES0_EN =MCPCORES0_EN D 6
Q7890
CPUVTTS0_EN =CPUVTTS0_EN OUT 55
SSM6N37FEAPE
MAKE_BASE=TRUE SOT563
=PP3V3_S5_REG NO STUFF
1 C7881 1 C7880 1 C7882 1 C7884 51 8
0.47UF
10%
0.47UF
10%
0.47UF
10%
0.47UF
10% 2 G S 1 1R7899
2 10V 2 10V 2 10V 2 10V 0
A X5R
402
X5R
402
X5R
402
X5R
402 34 19 IN AP_PWR_EN AC_OR_S0_L 5%
1/10W
MF-LF
WLAN_PCTL:SW PAGE TITLE
2 603
WLAN_PCTL:HW
Q7891 D 3 1 R7891 6 D WLAN_PCTL:HW
Q7891
P3V3_BLEED Power Sequencing
SSM6N37FEAPE SSM6N37FEAPE DRAWING NUMBER SIZE
0 D 3
SOT563 5%
1/16W
SOT563 Q7890 Apple Inc. 051-8379 D
SSM6N37FEAPE
VTT Rail Enable VTT rail must ramp up in about
the same time as MEMVDD rail (Q2300).
5 G S 4
MF-LF
2 402
1 S G 2
SOT563 R
NOTICE OF PROPRIETARY PROPERTY:

REVISION
BRANCH
4.4.0
39 38 19 IN SMC_ADAPTER_EN
21 19 IN MCP_MEM_VDD_EN =DDRVTT_EN OUT 52 5 G S 4 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
57 IN P3V3S5_EN_L THE POSESSOR AGREES TO THE FOLLOWING: PAGE
78 OF 110
57 39 38 19 7 IN PM_SLP_S3_L III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S3 FET CRITICAL

Q7910
3.3V ENET Switch
FDC638P_G
SM
=PP3V3_S3_FET U7980
6
8
8 =PP3V3_S5_P3V3ENETFET TPS22924 =PP3V3_ENET_FET 9
CSP
8 =PP3V3_S5_P3V3S3FET 5
A2 A1
4
2 Q7910 B2 VIN VOUT B1
U7980
1 CRITICAL
MOSFET FDC638P =P3V3ENET_EN C2 ON
R79121 1 C7911 57 IN
GND
Part TPS22924C
10K 0.033UF Type P-Channel OMIT_TABLE
5% Type Load Switch
3 C7980 1 D
C1
1/20W 10%
D MF
201 2 R7910
16V
2 X5R
402
C7910
0.01UF
Rds(on) 65 mOhm @2.5V 1UF
10%
6.3V
R(on) 18 mOhm Typ
47K ID(max) 2.0 A @85C CERM 2 50 mOhm Max
P3V3S3_EN_L 1 2 P3V3S3_SS 1 2
402
Q7903 5%
1/20W 10% Loading 1.274 A (EDP) I(max) 2 A
SSM3K15FV MF 10V
D 3 201 X5R Loading 0.4 A (EDP)
SOD-VESM-HF 201
1 G S 2
57 IN =P3V3S3_EN
0.9V ENET FET

3.3V S0 FET CRITICAL
Q7930
8 =PP0V9_ENET_P0V9ENETFET
TPCP8102
23V1K-SM
=PP3V3_S0_FET 8 C7990 1 3
0.1UF
10% CRITICAL
5 6 7 8
=PP3V3_S5_P3V3S0FET 6.3V D
1 2 3
8 X5R 2
Q7930 =PP3V3_S5_P0V9ENETFET R7990 201 Q7990
D
8
100K 2 G SI2312BDS
1 P0V9ENET_SS 1
1 MOSFET TPCP8102 S
SOT23
R7932
G
5%
1 C7931 1/20W
4
100K 0.033UF Type P-Channel MF D 6
5%
1/20W 10% R79921 201 Q7991 2
=PP0V9_ENET_FET
2 16V Rds(on) 14 mOhm @4.5V 69.8K SSM6N37FEAPE 8
C MF
201 2 R7930
47K
X5R
402
C7930
0.01UF
1%
1/20W
SOT563 C
P3V3S0_EN_L 1 2 P3V3S0_SS 1 2 ID(max) 7.2 A @85C MF
201 2 Q7990
Q7905 5%
1/20W 10% Loading 3.294 A (EDP) R7991 2 G S 1 C7991 1
MOSFET SI2312BDS
SSM3K15FV D 3 MF 10V 10K 0.01UF
201 X5R
201
P0V9ENET_EN_L 1 2 10%
10V 2
SOD-VESM-HF
1% X5R Type N-Channel
1/20W 201
D 3 MF Rds(on) 37 mOhm @2.5V
Q7991 201 P0V9ENET_EN_L_RC
SSM6N37FEAPE ID(max) 3.25 A @85C
1 G S 2 SOT563
=P3V3S0_EN Loading 0.140 A (EDP)

57 IN
5 G S 4
57 IN =P0V9ENET_EN
5V S0 FET CRITICAL
Q7940
FDC638P_G
SM
6 =PP5V_S0_FET 8
8 =PP5V_S3_P5VS0FET 5
4
2
1 Q7940
1 C7941 1 Part FDC638P
R7942 0.033UF
10% 3
47K 16V 2 Type P-Channel
5% X5R
1/20W
B MF
201 2 R7940
402
C7940
0.01UF
Rds(on) 65 mOhm @2.5V B
P5VS0_EN_L 1
47K 2 P5VS0_SS 1 2 ID(max) 2.0 A @85C
Q7945 5%
1/20W 10% Loading 0.100 A (EDP)
SSM3K15FV MF 16V
D 3 201 CERM
SOD-VESM-HF 402
1 G S 2
57 IN =P5VS0_EN
PAGE TITLE
Power FETs
DRAWING NUMBER SIZE

REVISION
R
4.4.0
79 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LCD Connector
Internal DP Connector: 518S0787
CRITICAL
J9000
CABLINE-CA
F-RT-SM
Pull-ups on panel side, PPVOUT_SW_LCDBKLT
31
62 42 7
4.7 kOhm to 3.3V
41 7 BI =I2C_TCON_SDA 1
2
NC
3
4
5
NC
62 7 OUT LED_RETURN_6 6
41 7 IN =I2C_TCON_SCL
LED Backlight I/F
C CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP
62 7
62 7
OUT LED_RETURN_3
LED_RETURN_2
9
10
C
OUT
12
NC
R9060 13
CRITICAL 0
DP_INT_HPD 1 2 7 DP_INT_HPD_CONN 14
8 =PP3V3_S0_LCD U9000 9 OUT
5% 15
FPF1009 1/20W
LCD_IG_PWR_EN 1 ON MFET-2X2 L9004 MF
201
16 DisplayPort I/F
17 9 IN FERR-120-OHM-1.5A 17
2 VIN_1 VOUT_1 4 PP3V3_SW_LCD_UF 1 2 7 PP3V3_SW_LCD 18
MIN_LINE_WIDTH=0.30 MM 0402-LF MIN_LINE_WIDTH=0.30 MM 19
3 VIN_2
MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
VOUT_2 5 VOLTAGE=3.3V VOLTAGE=3.3V
C9015 1 1
R9070 20
THRM 1000PF 100K DP_INT_AUX_CH_C_N 21
GND PAD C9024 10%
16V 5%
71 7
6 7 OMIT_TABLE 0.1uF X7R 2 1/20W 71 7 DP_INT_AUX_CH_C_P 22

R90141 1 C9009 C9011 1 1 C9012 71 9 BI DP_INT_AUX_CH_N 1 2 (DP_INT_AUX_CH_C_N) 201 MF
2 201
23
1K 0.1UF 0.1UF 10UF
5% 10% 10% 20% 10%
71 7 DP_INT_ML_F_P<0> 24
1/20W
MF
6.3V
2 X5R
6.3V
X5R 2
6.3V
2 X5R 16V
X5R
C9025 71 7 DP_INT_ML_F_N<0> 25
201 2 201 201 603 402 0.1uF 26
71 9 BI DP_INT_AUX_CH_P 1 2 (DP_INT_AUX_CH_C_P) 71 7 DP_INT_ML_F_P<1> 27
10%
16V CRITICAL 71 7 DP_INT_ML_F_N<1> 28
C9020 X5R
402 FL9000 29
0.1uF 12-OHM-100MA 30
71 9 IN DP_INT_ML_P<0> 1 2 71 DP_INT_ML_C_P<0> 1
TCM1210-4SM
SYM_VER-2 4
10% 33
16V
X5R
C9021 34
402 0.1uF 2 3
71 9 IN DP_INT_ML_N<0> 1 2 71 DP_INT_ML_C_N<0> 35
B C9022
10%
16V CRITICAL
36
37
B
0.1uF
X5R
402 FL9001
12-OHM-100MA
38
71 9 IN DP_INT_ML_P<1> 1 2 71 DP_INT_ML_C_P<1> 1
TCM1210-4SM
SYM_VER-2 4
39
40
10%
16V
X5R
C9023 41
402 0.1uF 2 3
71 9 IN DP_INT_ML_N<1> 1 2 71 DP_INT_ML_C_N<1>
32
10%
16V R90501 1
R9080 PLACEMENT_NOTE=PLACE CLOSE TO J9000
X5R
402
100K
5% 5%
100K C9017 1
1/20W 1/20W 1000PF

MF MF 5%
50V
201 2 2 201 C0G-CERM 2
603
PAGE TITLE
Internal DisplayPort Connector

DRAWING NUMBER SIZE

REVISION
R
4.4.0
90 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C9300
0.1UF
9 BI DP_EXT_AUX_CH_P 1 2 DP_AUX_CH_C_P BI 9
10%
6.3V
X5R
201
S 4
1 S
D 3
6 D
DP_EXT_DDC_CLK
CKPLUS_WAIVE=PdifPr_badTerm CKPLUS_WAIVE=PdifPr_badTerm
C SIGNAL_MODEL=DP_AUXCH_FET SIGNAL_MODEL=DP_AUXCH_FET C
Q9300 Q9300
5 G
G 2
(DP_CA_DET_RC)
SSM6N37FEAPE SSM6N37FEAPE
SOT563 SOT563
C9301
0.1UF
9 DP_EXT_AUX_CH_N 1 2 DP_AUX_CH_C_N 9
BI BI
10%
6.3V
X5R
201
S 4
1 S
D 3
6 D
DP_EXT_DDC_DATA
SIGNAL_MODEL=DP_AUXCH_FET SIGNAL_MODEL=DP_AUXCH_FET
Q9302 DP_CA_DET_RC Q9302
5 G
G 2
SSM6N37FEAPE SSM6N37FEAPE
SOT563 SOT563
R9302
22
1 2 DP_CA_DET IN 9
5%
1/20W NOTE: Pulled up to 5V on DP connector page.
C9302 1 MF
201 FET speced for 1.5V Vgs operaiton.
3300PF
B 10%
10V
X7R 2
B
201
PAGE TITLE
External DisplayPort Support

DRAWING NUMBER SIZE

REVISION
R
4.4.0
93 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Port Power Switch

CRITICAL
L9400
FERR-120-OHM-3A
U9480
TPS2051B
D 8 =PP3V3_S5_DP_PORT_PWR
5 IN
SOT23
OUT 1
61 PP3V3_SW_DPILIM
1 2 7 PP3V3_SW_DPPWR
0603 MIN_LINE_WIDTH=0.50 MM
D
VOLTAGE=3.3V VOLTAGE=3.3V
=DP_PWR_EN 4 EN OC* 3 TP_DPPWR_OC_L
1 C9400
39 IN 0.01UF
GND 10%
2 X5R
10V
2
CRITICAL OMIT_TABLE OMIT_TABLE 201
C9487 1 C9480 1 1 C9481 C9485 1 1 C9486

100UF 22UF 0.1UF 0.1UF 10UF
20% 20% 10% 10% 20%
6.3V 2 6.3V 6.3V 6.3V 2 2 6.3V
POLY-TANT X5R-CERM-1 2 2 X5R X5R X5R
CASE-B2-SM 603 201 201 603
CRITICAL
3 DP_ESD
D9410
RCLAMP0524P
GND
SLP2510P8
HDMI_CEC CRITICAL
CRITICAL
FL9400
1
R9425 J9400 12-OHM-100MA
TCM1210-4SM
1M MINIDSPLYPRT-K99 1 SYM_VER-2 4 DP_EXT_ML_C_P<0> C9410 1 2 DP_EXT_ML_P<0>
IO
NC
IO
NC
IO
NC
IO
NC
71 9 71
F-RT-TH IN
5% 10% 6.3V X5R 201
1/20W 1 10 2 9 4 7 5 6 0.1UF
C MF
2 201 2 3 71 DP_EXT_ML_C_N<0> C9411 1 2 DP_EXT_ML_N<0>
10% 6.3V X5R 201
IN 9 71
C
CRITICAL R94201 2
HOT_PLUG_DETECT GND
1 CRITICAL
0.1UF
FL9403
12-OHM-100MA
100K
5% 4
CONFIG1
3 71 DP_EXT_ML_F_P<0> FL9401
1/20W ML_LANE0P
TCM1210-4SM 6 5 DP_EXT_ML_F_N<0> 12-OHM-100MA
MF 71
71 9 IN DP_EXT_ML_P<3> C9414 1 2 71 DP_EXT_ML_C_P<3>
10% 6.3V X5R 201
4 SYM_VER-2 1 201 2 8
CONFIG2 ML_LANE0N
7 1
TCM1210-4SM
SYM_VER-2 4 71 DP_EXT_ML_C_P<1> C9412 1 2 DP_EXT_ML_P<1>
0.1UF GND GND 10% 6.3V X5R 201 IN 9 71
71 DP_EXT_ML_F_P<3> 10 ML_LANE3P ML_LANE1P

9 71 DP_EXT_ML_F_P<1> 0.1UF
71 9 IN DP_EXT_ML_N<3> C9415 1 2 71 DP_EXT_ML_C_N<3>
10% 6.3V X5R 201
3 2 71 DP_EXT_ML_F_N<3> 12
ML_LANE3N ML_LANE1N
11 71 DP_EXT_ML_F_N<1> 2 3 71 DP_EXT_ML_C_N<1> C9413 1 2 DP_EXT_ML_N<1> 9 71
0.1UF 14 13 IN
GND GND 10% 6.3V X5R 201
0.1UF
71 9 BI DP_EXT_AUX_CH_C_P 16 AUX_CHP ML_LANE2P
15 71 DP_EXT_ML_F_P<2> CRITICAL
71 9 BI DP_EXT_AUX_CH_C_N 18
AUX_CHN ML_LANE2N
17 71 DP_EXT_ML_F_N<2> FL9402
20 19 12-OHM-100MA
=PP3V3_S0_DPCONN CRITICAL DP_PWR RETURN TCM1210-4SM
61 8
8 =PP5VR3V3_S0_DPCADET DP_ESD 1 SYM_VER-2 4 71 DP_EXT_ML_C_P<2> C9416 1 2 DP_EXT_ML_P<2>

10% 6.3V X5R 201 IN 9 71
R94211 D9411 SHIELD PINS 0.1UF

100K RCLAMP0524P C9417
R94431 R94421 5%
1/20W SLP2510P8
22 21 2 3 71 DP_EXT_ML_C_N<2> 1 2 DP_EXT_ML_N<2>
10% 6.3V X5R 201
IN 9 71
100K 100K MF CRITICAL 0.1UF

5% 5% 201 2
1/20W 1/20W DP_ESD
MF MF 2 IO
201 2 201 2 IO 1 D9411
9 NC NC 10 RCLAMP0524P
9 OUT DP_EXT_CA_DET SLP2510P8
GND
6
3 4 IO
Q9440 D IO 5
2N7002DW-X-G CRITICAL 7 NC NC 6
SOT-363 2
S G DP_CA_DET_Q_L DP_ESD
GND
1 NOTE: Q9440 must have Drain to Gate D9400
B Q9440
3
D
leakage of < 500 nA and gate to RCLAMP0504F
SC70-6-1
3 B
2N7002DW-X-G Source resistance of > 5 MOhm.
SOT-363 6
S G 5 DP_CA_DET_Q 1
DP to DVI/HDMI
4 1 2 5
R9422 Cable Adapter
1M (CA) has 100k
5% 4
1/20W pull-up to DP_PWR. 3
MF
201 2
61 8 =PP3V3_S0_DPCONN
R94451
10K
5%
1/20W
MF
201 2 PP3V3_SW_DPILIM 61
9 OUT DP_EXT_HPD
R94441
6 10K
5%
1/20W
Q9441 D MF
201 2
2N7002DW-X-G
SOT-363 2
S G
1 3
DP_EXT_HPD_L Q9441 D
A 39 OUT
2N7002DW-X-G
SOT-363
S G 5 DP_HPD_Q PAGE TITLE
4
DP Source must pull DisplayPort Connector
R94231 down HPD input with DRAWING NUMBER SIZE
100K
5%
greater than or equal
1/20W to 100K (DPv1.1a). REVISION
MF R
201 2 4.4.0
94 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
CRITICAL
D R9700
0.01 D
0.5%
1W 8 =PP5V_S0_BKL R9701
MF 0
63 62 PPBUS_SW_LCDBKLT_PWR 0612
1 2
1 2 PPBUS_SW_BKL 5%
CRITICAL CRITICAL
3 4 MIN_LINE_WIDTH=0.5mm
1/20W
MF
L9701 D9701 PPVOUT_SW_LCDBKLT
VOLTAGE=12.6V PLACE_NEAR=L9701.1:3mm 201 22UH-2.5A SOD-123 MIN_LINE_WIDTH=0.5 MM
7 42 59
PLACE_NEAR=L9701.1:3mm 1 2 PLACE_NEAR=U9701.21:3mm MIN_NECK_WIDTH=0.2 MM

1 2 PPBUS_SW_LCDBKLT_PWR_SW VOLTAGE=24V
IHLP2525CZ-SM MIN_LINE_WIDTH=0.5 MM
ISNS_LCDBKLT_P CRITICAL MIN_NECK_WIDTH=0.2 MM
VOLTAGE=24V RB160M-60G
71 42 OUT
C9712 1 1 C9713 NO STUFF
SWITCH_NODE=TRUE
DIDT=TRUE
1 C9796 1 C9797 1 C9799
71 42 OUT ISNS_LCDBKLT_N 10UF 0.1UF 220PF 10UF 10UF
10% 10% 1 1 10% 10% 10%
25V 2
X5R 2 25V
X5R
R9703 R9702 2 50V
X7R-CERM 2 50V
X5R 2 50V
X5R
805 402 0 0 402 1210-1 1210-1
5% 5%
1/20W 1/20W
MF MF
2 201 201 2
PPVIN_SW_BKL_R
VOLTAGE=5V
PLACE_NEAR=U9701.8:4mm PP5V_S0_BKL_VLDO
8 =PP3V3_S0_BKL_VDDIO MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
C9711 1 C9710 1 1 C9714
0.1UF 1UF 0.01UF
10% 10% 10%
6.3V 2 25V 2 2 10V
X5R X5R X7R
201 603-1 0201
22
23
C C
8
VDDIO VLDO VIN
CRITICAL
OMIT_TABLE U9701
LLP
LP8545SQX
6 GD SW 24
NC BKLT:PROD
R9741 BKL_FSET 5 FSET FB 21
R9717
10K 0
R9753 1 2 BKL_FLTR 20 FILTER OUT1 12 BKL_ISEN1 1 2 LED_RETURN_1 OUT 7 59
0 5% MIN_NECK_WIDTH=0.20 mm 5% MIN_NECK_WIDTH=0.20 mm
41 IN =I2C_BKL_1_SCL 1 2 1/20W BKL_ISET 3 ISET OUT2 13 BKL_ISEN2 1/16W
MF MF-LF
5% 201 402
R9757 1/20W BKL_SCL 10 SCLK OUT3 14 BKL_ISEN3
MF BKLT:PROD
0 201
41 BI =I2C_BKL_1_SDA 1 2 BKL_SDA 11 SDA OUT4 16 BKL_ISEN4 R9718
5%
BKL_PWM 2 PWM 17 BKL_ISEN5 0 LED_RETURN_2
Addr: 0x58(Wr)/0x59(Rd) 1/20W
MF
OUT5 1 2 OUT 7 59
201 MIN_NECK_WIDTH=0.20 mm 5% MIN_NECK_WIDTH=0.20 mm
R9731 TP_BKL_FAULT 7 FAULT OUT6 18 BKL_ISEN6 1/16W
MF-LF
PPBUS_SW_LCDBKLT_PWR 200K 2 402
63 62 1 BKL_EN 4 EN VSYNC 19 BKL_VSYNC_R
1%
BKLT:PROD
R9704 1/20W NO STUFF R9719
MF 1
R9715 R97551
1 GND_SW
33 201 1 C9723 0
9 GND_S
15 GND_L
9 IN LCD_BKLT_PWM 1 2 100K 0.1UF 10K 1 2 LED_RETURN_3 OUT 7 59
1% 10% THRM 5% MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
5% 1/20W 1/20W MIN_NECK_WIDTH=0.20 mm 5% MIN_NECK_WIDTH=0.20 mm
1/20W MF 2 25V PAD MF 1/16W
MF
201
1 C9704 2 201
X5R
402 201 2 MF-LF
402
25
33PF
5% BKLT:PROD
2 25V
NP0-C0G
201 R97161 1
R9714 R9720
B 90.9K
1%
Fpwm=9.62kHz 1/20W
18.2K
1%
1/20W I_LED=23.2mA MIN_LINE_WIDTH=0.5 mm
1
0 2 LED_RETURN_4
OUT 7 59 B
MF MF MIN_NECK_WIDTH=0.20 mm 5% MIN_NECK_WIDTH=0.20 mm
see spec for others 201 2 2 201
XW9710
SM
1/16W
MF-LF
402
GND_BKL_SGND 1 2
MIN_LINE_WIDTH=0.4 MM BKLT:PROD
VOLTAGE=0V R9721
0 LED_RETURN_5
I_LED=369/Riset 1 2
OUT 7 59
(EEPROM should set EN_I_RES=1) MIN_NECK_WIDTH=0.20 mm 5%
1/16W
MF-LF
402
BKLT:PROD
R9722
1
0 2 LED_RETURN_6 OUT 7 59
MIN_NECK_WIDTH=0.20 mm 5% MIN_NECK_WIDTH=0.20 mm
1/16W
MF-LF
402
FOR LP8543:
STUFF R9741
NO STUFF R9740, C9740, C9741, R9754

103S0198 3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719 BKLT:ENG 10.2 ohm resistors for current
103S0198 3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722 BKLT:ENG measurement on LED strings.
353S2896 1 IC,LP8545,LED BKLT CTRLR,PRODUCTIO,LLP24 U9701 CRITICAL PROJ:K16
A 353S2967 1 IC,LP8545,LED BKLT CTRLR,LLP24,K99 VER U9701 CRITICAL PROJ:K99
PAGE TITLE
LCD Backlight Driver

DRAWING NUMBER SIZE

REVISION
R
4.4.0
97 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D CRITICAL
Q9806 D
FDC638APZ_SBMS001
CRITICAL SSOT6-HF PPBUS_SW_LCDBKLT_PWR 62
F9800 MIN_LINE_WIDTH=0.4 mm
5 6
8 =PPBUS_S0_LCDBKLT 2AMP-32V VOLTAGE=8.4V
PPBUS_S0_LCDBKLT_FUSED
4
1 2
PPBUS S0 LCDBkLT FET
1 2
0603 VOLTAGE=8.4V
1
R9808 C9802 1 MOSFET FDC638APZ
301K 0.1UF
10% CHANNEL P-TYPE
3
1% 16V 2
1/20W X5R
MF 402
2 201 RDS(ON) 43 mOhm @4.5V
LCDBKLT_EN_DIV LOADING 0.4 A (EDP)
1
R9809
147K
1%
1/20W
MF
2 201
LCDBKLT_EN_L
Q9807 D 3
SSM6N37FEAPE
SOT563
5 G S 4
C 9 IN LCD_BKLT_EN LCDBKLT_DISABLE C
1
R9810 Q9807 D 6
10K SSM6N37FEAPE
5% SOT563
1/20W
MF
2201
2 G S 1
25 IN BKLT_PLT_RST_L
B B
PAGE TITLE
LCD Backlight Support

DRAWING NUMBER SIZE

REVISION
R
4.4.0
98 OF 110
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
ADDITIONAL CPU VCORE HF DECOUPLING

40x 1uF 0402
12 11 8 =PPVCORE_S0_CPU
D LAYOUT NOTE:
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
D
PLACE ON OPPOSITE SIDE OF CPU
C9900
2.2UF
C9901
2.2UF
C9902
2.2UF
C9903
2.2UF
C9904
2.2UF
C9905
2.2UF
C9906
2.2UF
C9907
2.2UF
C9908
2.2UF
C9909
2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
LAYOUT NOTE:
C9910
2.2UF
C9911
2.2UF
C9912
2.2UF
C9913
2.2UF
C9914
2.2UF
C9915
2.2UF
C9916
2.2UF
C9917
2.2UF
C9918
2.2UF
C9919
2.2UF
PLACE ON OPPOSITE SIDE OF CPU 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
LAYOUT NOTE: OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
PLACE ON OPPOSITE SIDE OF CPU C9920
2.2UF
C9921
2.2UF
C9922
2.2UF
C9923
2.2UF
C9924
2.2UF
C9925
2.2UF
C9926
2.2UF
C9927
2.2UF
C9928
2.2UF
C9929
2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C C
LAYOUT NOTE: OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
PLACE ON OPPOSITE SIDE OF CPU C9930
2.2UF
C9931
2.2UF
C9932
2.2UF
C9933
2.2UF
C9934
2.2UF
C9935
2.2UF
C9936
2.2UF
C9937
2.2UF
C9938
2.2UF
C9939
2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B B
PAGE TITLE
Additional CPU/GPU Decoupling

DRAWING NUMBER SIZE

REVISION
R
4.4.0
99 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
FSB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_D_L<15..0> 7 10 14
FSB_DSTB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DINV_L<0> 7 10 14
FSB_DSTB0 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<0> 7 10 14
FSB 4X Signal Groups

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
FSB_DSTB0 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<0> 7 10 14

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

FSB_DATA * =2x_DIELECTRIC ? FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ?
FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_DINV_L<1> 7 10 14
FSB_DSTB * =3x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? FSB_DSTB1 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<1> 7 10 14
D FSB_ADDR * =STANDARD ?
TABLE_SPACING_RULE_ITEM
FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ?


D

FSB_ADSTB * =2x_DIELECTRIC ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ? FSB_DINV_L<2>
FSB_DATA_GROUP2 FSB_55S FSB_DATA 7 10 14
FSB_1X * =STANDARD ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? FSB_DSTB2 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<2> 7 10 14

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right. FSB_DINV_L<3>
FSB_DATA_GROUP3 FSB_55S FSB_DATA 7 10 14
Signals within each 4x group should be matched within 5 ps of strobe. FSB_DSTB_L_P<3>
FSB_DSTB3 FSB_DSTB_55S FSB_DSTB 7 10 14
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps. FSB_DSTB_L_N<3>
FSB_DSTB3 FSB_DSTB_55S FSB_DSTB 7 10 14
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_A_L<16..3> 7 10 14
Signals
FSB 2X signals / groups shown in signal table on right.
FSB 2X
FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_REQ_L<4..0> 7 10 14
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps. FSB_ADSTB_L<0>
FSB_ADSTB0 FSB_55S FSB_ADSTB 7 10 14
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB_ADDR_GROUP1 FSB_55S FSB_ADDR FSB_A_L<35..17> 7 10 14
FSB 1X signals shown in signal table on right. FSB_ADSTB_L<1>
FSB_ADSTB1 FSB_55S FSB_ADSTB 7 10 14
Intel Design Guide recommends FSB signals be routed only on internal layers. FSB_ADS_L
FSB_1X FSB_55S FSB_1X 7 10 14
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. FSB_BREQ0_L FSB_55S FSB_1X FSB_BREQ0_L 10 14
FSB 1X Signals
FSB_1X FSB_55S FSB_1X FSB_BNR_L 10 14
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 FSB_BPRI_L
FSB_1X FSB_55S FSB_1X 10 14
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 FSB_DBSY_L
FSB_1X FSB_55S FSB_1X 10 14
FSB_DEFER_L
CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD
FSB_1X
FSB_1X
FSB_55S
FSB_55S
FSB_1X
FSB_1X FSB_DRDY_L
10 14
10 14
PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_1X FSB_55S FSB_1X FSB_HIT_L 7 10 14
FSB_1X FSB_55S FSB_1X FSB_HITM_L 7 10 14

CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
FSB_1X FSB_55S FSB_1X FSB_LOCK_L 7 10 14
FSB_CPURST_L
C CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
7 MIL 7 MIL FSB_CPURST_L
FSB_1X
FSB_55S
FSB_55S
FSB_1X
FSB_1X FSB_RS_L<2..0>
10 13 14
10 14
C
FSB_1X FSB_55S FSB_1X FSB_TRDY_L 10 14
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_ASYNC CPU_55S CPU_AGTL CPU_A20M_L 10 14
CPU_BSEL CPU_55S CPU_AGTL CPU_BSEL<2..0> 9 10

CPU_AGTL * =STANDARD ? CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ?
CPU_FERR_L CPU_55S CPU_8MIL CPU_FERR_L 10 14
CPU_8MIL * 8 MIL ? CPU_ASYNC CPU_55S CPU_AGTL CPU_IGNNE_L 10 14

CPU_INIT_L CPU_55S CPU_AGTL CPU_INIT_L 10 14

CPU_COMP * 25 MIL ?
CPU_ASYNC_R CPU_55S CPU_AGTL CPU_INTR 10 14
CPU_GTLREF * 25 MIL ? SR DG recommends at least 25 mils, >50 mils preferred CPU_ASYNC_R CPU_55S CPU_AGTL CPU_NMI 10 14
CPU_PROCHOT_L CPU_55S CPU_AGTL CPU_PROCHOT_L 10 14 39

CPU_ITP * =2:1_SPACING ?
CPU_PWRGD CPU_55S CPU_AGTL CPU_PWRGD 10 13 14
CPU_VCCSENSE * 25 MIL ? CPU_ASYNC CPU_55S CPU_AGTL CPU_SMI_L 10 14
CPU_ASYNC CPU_55S CPU_AGTL CPU_STPCLK_L 10 14

Most CPU signals with impedance requirements are 55-ohm single-ended. PM_THRMTRIP_L
PM_THRMTRIP_L CPU_55S CPU_8MIL 10 14 39
Some signals require 27.4-ohm single-ended impedance. FSB_CPUSLP_L
FSB_CPUSLP_L CPU_55S CPU_AGTL 10 14
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 CPU_FROM_SB CPU_55S CPU_AGTL CPU_DPSLP_L 10 14
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 CPU_DPRSTP_L CPU_55S CPU_AGTL CPU_DPRSTP_L 10 14 53
CPU_ASYNC CPU_55S CPU_AGTL FSB_DPWR_L 10 14
MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD

FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 10 14

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 10 14
FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_P 13 14

MCP_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD FSB_CLK_ITP_N
FSB_CLK_ITP CLK_FSB_100D CLK_FSB 13 14
TABLE_SPACING_RULE_HEAD
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_P 14
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_N 14

B MCP_FSB_COMP * 8 MIL ? CPU_IERR_L CPU_55S CPU_IERR_L 10

B
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4 PM_DPRSLPVR CPU_55S CPU_AGTL PM_DPRSLPVR 14 53
(See above) CPU_55S CPU_AGTL IMVP_DPRSLPVR

FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_VDD 14

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_GND 14
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_VCC 14

CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_GND 14
CPU_GTLREF CPU_50S CPU_GTLREF CPU_GTLREF 10 33

CPU_COMP CPU_50S CPU_COMP CPU_COMP<3> 10
CLK_FSB * =3x_DIELECTRIC ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC ? CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 10
CPU_COMP CPU_50S CPU_COMP CPU_COMP<1> 10

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 CPU_COMP<0>
CPU_COMP CPU_27P4S CPU_COMP 10
XDP_TDI CPU_55S CPU_ITP XDP_TDI 10 13
XDP_TDO CPU_55S CPU_ITP XDP_TDO 10 13
XDP_TMS CPU_55S CPU_ITP XDP_TMS 10 13
XDP_TCK CPU_55S CPU_ITP XDP_TCK 10 13
XDP_TRST_L CPU_55S CPU_ITP XDP_TRST_L 10 13
XDP_BPM_L CPU_55S CPU_ITP XDP_BPM_L<4..0> 10 13
XDP_BPM_L5 CPU_55S CPU_ITP XDP_BPM_L<5> 10 13
(FSB_CPURST_L) CPU_55S CPU_ITP XDP_CPURST_L 13
CPU_55S CPU_8MIL CPU_VID<6..0> 11 12 53
CPU_55S CPU_8MIL IMVP6_VID<6..0> 12
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 11 53
CPU_VCCSENSE_N
A CPU_VCCSENSE
(CPU_VCCSENSE)
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE IMVP6_VSEN_P
11 53
53 SYNC_MASTER=K16_MLB SYNC_DATE=07/07/2010 A
(CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N 53
PAGE TITLE
CPU/FSB Constraints
DRAWING NUMBER SIZE

REVISION
R
4.4.0
100 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Memory Bus Constraints Memory Net Properties
ALLOW ROUTE
NET_TYPE
MEM_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
MEM_A_CLK MEM_70D MEM_CLK MEM_A_CLK_P<5..0> 9 15 26 27 32
MEM_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_70D MEM_CLK MEM_A_CLK_N<5..0> 9 15 26 27 32
MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_A_CKE MEM_50S MEM_CTRL MEM_A_CKE<3..0> 15 21 26 27 32
MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_CS_L<3..0> 15 26 27 32
MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_ODT<3..0> 15 26 27 32
MEM_A_CMD MEM_50S MEM_CMD MEM_A_A<15..0> 9 15 26 27 32

MEM_A_CMD MEM_50S MEM_CMD MEM_A_BA<2..0> 15 26 27 32
D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

MEM_A_CMD MEM_50S MEM_CMD MEM_A_RAS_L 15 26 27 32 D
MEM_CLK2MEM * =4:1_SPACING ? NV DG says 3x inner, 4x outer MEM_A_CMD MEM_50S MEM_CMD MEM_A_CAS_L 15 26 27 32
MEM_A_CMD MEM_50S MEM_CMD MEM_A_WE_L 15 26 27 32

MEM_CTRL2CTRL * =2:1_SPACING ? NV DG says 2x inner, 4x outer
MEM_A_DQ_BYTE0 MEM_55S MEM_DATA MEM_A_DQ<7..0> 15 26

MEM_CTRL2MEM * =2.5:1_SPACING ? NV DG says 2x inner, 4x outer MEM_A_DQ<15..8>
MEM_A_DQ_BYTE1 MEM_55S MEM_DATA 15 26
MEM_CMD2CMD * =1.5:1_SPACING ? NV DG says 2x inner, 4x outer MEM_A_DQ_BYTE2 MEM_55S MEM_DATA MEM_A_DQ<23..16> 15 26


MEM_CMD2MEM * =3:1_SPACING ? NV DG says 2x inner, 4x outer MEM_A_DQ<39..32>
MEM_DATA2DATA * =1.5:1_SPACING ? NV DG says 2x inner, 4x outer MEM_A_DQ_BYTE5 MEM_55S MEM_DATA MEM_A_DQ<47..40> 15 27


MEM_DATA2MEM * =3:1_SPACING ? NV DG says 2x inner, 4x outer MEM_A_DQ<63..56>
MEM_DQS2MEM * =3:1_SPACING ? NV DG says 4x inner, 5x outer MEM_A_DM<0>

MEM_2OTHER * 25 MIL ? MEM_A_DQ_BYTE1 MEM_55S MEM_DATA MEM_A_DM<1> 15 26
MEM_A_DQ_BYTE2 MEM_55S MEM_DATA MEM_A_DM<2> 15 26
MEM_A_DM<3>
Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_55S
MEM_55S
MEM_DATA
MEM_DATA MEM_A_DM<4>
15 26
15 27
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQ_BYTE5 MEM_55S MEM_DATA MEM_A_DM<5> 15 27
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM
MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM

MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_P<0> 15 26
MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_N<0> 15 26

MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_DATA * MEM_CMD2MEM
MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_N<1> 15 26
MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS_P<2> 15 26
C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE

TABLE_SPACING_ASSIGNMENT_HEAD
SPACING_RULE_SET
MEM_A_DQS3
MEM_A_DQS3
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
15 26
15 26
C
MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS_P<4> 15 27

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_DATA MEM_CTRL * MEM_DATA2MEM
MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS_N<5> 15 27

MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA
MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS_P<7> 15 27

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_B_CLK MEM_70D MEM_CLK MEM_B_CLK_P<5..0> 9 15 28 29 32
MEM_B_CLK MEM_70D MEM_CLK MEM_B_CLK_N<5..0> 9 15 28 29 32

MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_CLK * * MEM_2OTHER
MEM_B_CKE MEM_50S MEM_CTRL MEM_B_CKE<3..0> 15 21 28 29 32

MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER
MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_CS_L<3..0> 15 28 29 32
MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_ODT<3..0> 15 28 29 32

MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DATA * * MEM_2OTHER MEM_B_CMD MEM_50S MEM_CMD MEM_B_A<15..0> 9 15 28 29 32

MEM_B_CMD MEM_50S MEM_CMD MEM_B_BA<2..0> 15 28 29 32

MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_DQS * * MEM_2OTHER
MEM_B_CMD MEM_50S MEM_CMD MEM_B_RAS_L 15 28 29 32
Need to support MEM_*-style wildcards! MEM_B_CMD MEM_50S MEM_CMD MEM_B_CAS_L

DDR3: MEM_B_CMD MEM_50S MEM_CMD MEM_B_WE_L
15 28 29 32
15 28 29 32
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps MEM_B_DQ_BYTE0 MEM_55S MEM_DATA MEM_B_DQ<7..0> 15 28
No DQS to clock matching requirement. MEM_B_DQ_BYTE1 MEM_55S MEM_DATA MEM_B_DQ<15..8> 15 28
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. MEM_B_DQ_BYTE2 MEM_55S MEM_DATA MEM_B_DQ<23..16> 15 28
CMD/CTRL signals should be matched within 150 ps. MEM_B_DQ_BYTE3 MEM_55S MEM_DATA MEM_B_DQ<31..24> 15 28
B All memory signals maximum length is 1.030 ps. MEM_B_DQ_BYTE4

MEM_B_DQ_BYTE5
MEM_55S
MEM_55S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
15 29
15 29
B
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3 MEM_B_DQ<55..48>
MEM_B_DQ_BYTE6 MEM_55S MEM_DATA 15 29
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ<63..56>
MEM_B_DQ_BYTE7 MEM_55S MEM_DATA 15 29
MCP MEM COMP Signal Constraints MEM_B_DQ_BYTE0 MEM_55S MEM_DATA MEM_B_DM<0> 15 28
ALLOW ROUTE
MEM_B_DQ_BYTE1 MEM_55S MEM_DATA MEM_B_DM<1> 15 28

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
MCP_MEM_COMP * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_B_DQ_BYTE3 MEM_55S MEM_DATA MEM_B_DM<3> 15 28


SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
MCP_MEM_COMP * =2x_DIELECTRIC ? MEM_B_DQ_BYTE7 MEM_55S MEM_DATA MEM_B_DM<7> 15 29
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2 MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS_P<0> 15 28
MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS_N<0> 15 28
MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_P<1> 15 28
A MEM_B_DQS6
MEM_B_DQS7
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
15 29
15 29
PAGE TITLE
MEM_B_DQS_N<7>
MEM_B_DQS7 MEM_70D MEM_DQS 15 29
Memory Constraints
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD 15 DRAWING NUMBER SIZE
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND 15
REVISION
R
4.4.0
MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27
101 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-Express MCP89 Net Properties
ALLOW ROUTE
NET_TYPE
PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
PCIE_90D PCIE PEG_R2D_P<15..0>
CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_90D PCIE PEG_R2D_N<15..0>
PEG_R2D PCIE_90D PCIE PEG_R2D_C_P<15..0>
PCIE_90D PCIE PEG_R2D_C_N<15..0>

PEG_D2R PCIE_90D PCIE PEG_D2R_P<15..0>
PCIE * =3X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? PCIE_90D PCIE PEG_D2R_N<15..0>
PCIE_90D PCIE PEG_D2R_C_P<15..0>

CLK_PCIE * 20 MIL ? PEG_D2R_C_N<15..0>
PCIE_90D PCIE
D MCP_PEX_COMP * 8 MIL ?
PCIE_90D PCIE PCIE_AP_R2D_P 7 34

D
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3 PCIE_90D PCIE PCIE_AP_R2D_N 7 34
PCIE_AP_R2D PCIE_90D PCIE PCIE_AP_R2D_C_P 16 34
PCIE_90D PCIE PCIE_AP_R2D_C_N 16 34
PCIE_AP_D2R_P
NEED PCIe Gen1/Gen2 notes! PCIE_AP_D2R PCIE_90D
PCIE_90D
PCIE
PCIE PCIE_AP_D2R_N
7 16 34
7 16 34
PCIE_90D PCIE PCIE_ENET_R2D_P

PCIE_90D PCIE PCIE_ENET_R2D_N
PCIE_ENET_R2D PCIE_90D PCIE PCIE_ENET_R2D_C_P
PCIE_90D PCIE PCIE_ENET_R2D_C_N
Analog Video Signal Constraints PCIE_ENET_D2R PCIE_90D PCIE PCIE_ENET_D2R_P
ALLOW ROUTE
PCIE_90D PCIE PCIE_ENET_D2R_N

ON LAYER?
PCIE_90D PCIE PCIE_ENET_D2R_C_P
CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD PCIE_90D PCIE PCIE_ENET_D2R_C_N
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
PCIE_90D PCIE PCIE_FW_R2D_P
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCIE_90D PCIE PCIE_FW_R2D_N
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_FW_R2D PCIE_90D PCIE PCIE_FW_R2D_C_P

CRT * 20 MIL ? CRT CRT * CRT_2CRT
PCIE_90D PCIE PCIE_FW_R2D_C_N
CRT_2CRT * 15 MIL ? PCIE_FW_D2R PCIE_90D PCIE PCIE_FW_D2R_P
PCIE_90D PCIE PCIE_FW_D2R_N

CRT_2CLK * 50 MIL ?
PCIE_90D PCIE PCIE_FW_D2R_C_P
CRT_2SWITCHER * 250 MIL ? PCIE_90D PCIE PCIE_FW_D2R_C_N
CRT_SYNC * =4x_DIELECTRIC ? MCP_PE0_REFCLK CLK_PCIE_100D CLK_PCIE PEG_CLK100M_P 9 16

CLK_PCIE_100D CLK_PCIE PEG_CLK100M_N 9 16

MCP_DAC_COMP * =2x_DIELECTRIC ?
PCIE_CLK100M_AP_P
C CRT signal single-ended impedence varies by location:
MCP_PE1_REFCLK CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE PCIE_CLK100M_AP_N
7 16 34
7 16 34
C
- 37.5-ohm from MCP to first termination resistor. MCP_PE2_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_P
- 50-ohm from first to second termination resistor. CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_N
- 75-ohm from output of three-pole filter to connector (if possible). MCP_PE3_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FW_P
R/G/B signals should be matched as close as possible and < 10 inches. CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FW_N
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1. MCP_PEX_CLK_COMP MCP_PEX_COMP MCP_PEX0_TERMP 16
CRT_IG_R_C_PR
Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD
CRT_RED
CRT_GREEN
CRT_50S
CRT_50S
CRT
CRT CRT_IG_G_Y_Y
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CRT_BLUE CRT_50S CRT CRT_IG_B_COMP_PB
CRT_SYNC CRT_50S CRT_SYNC CRT_IG_HSYNC

DP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
CRT_SYNC CRT_50S CRT_SYNC CRT_IG_VSYNC
LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_DAC_RSET MCP_DAC_COMP MCP_TV_DAC_RSET
MCP_DAC_VREF MCP_DAC_COMP MCP_TV_DAC_VREF

MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD
DP_INT_ML DP_90D DISPLAYPORT DP_IG_ML1_P<1..0> 9 17
DP_INT_ML DP_90D DISPLAYPORT DP_IG_ML1_N<1..0> 9 17

DP_INT_AUX_CH DP_90D DISPLAYPORT DP_IG_AUX_CH1_P 9 17
DISPLAYPORT * =3x_DIELECTRIC ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? DP_INT_AUX_CH DP_90D DISPLAYPORT DP_IG_AUX_CH1_N 9 17

LVDS * =3x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? DP_EXT_ML DP_90D DISPLAYPORT DP_IG_ML0_P<3..0> 9 17
DP_EXT_ML DP_90D DISPLAYPORT DP_IG_ML0_N<3..0> 9 17

LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils. DP_IG_AUX_CH0_P
DP_EXT_AUX_CH DP_90D DISPLAYPORT 9 17
NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm. DP_IG_AUX_CH0_N
DP_EXT_AUX_CH DP_90D DISPLAYPORT 9 17
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps.
DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. MCP_TMDS0_RSET MCP_DV_COMP MCP_TMDS0_RSET 17 24
Max trace length: LVDS 10 inches, DP 8.5 inches. MCP_TMDS0_VPROBE MCP_TMDS0_VPROBE 17 24
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2

B LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
B
SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_100D
LVDS_100D
LVDS
LVDS LVDS_IG_A_DATA_P<2..0>
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA_P<3>

SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK_P
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK_N
LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_P<2..0>

SATA * =3x_DIELECTRIC ? SATA TOP,BOTTOM =4x_DIELECTRIC ?
LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_N<2..0>
SATA_TERMP * 8 MIL ? LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA_N<3>
SATA intra-pair matching should be 1 ps.
Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3. MCP_IFPAB_RSET MCP_DV_COMP MCP_IFPAB_RSET 17 24
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6 MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE 17 24
SATA_HDD_R2D SATA_90D SATA SATA_HDD_R2D_C_P 18 35
SATA_90D SATA SATA_HDD_R2D_C_N 18 35
SATA_90D SATA SATA_HDD_R2D_P 7 35
SATA_90D SATA SATA_HDD_R2D_N 7 35
SATA_HDD_D2R SATA_90D SATA SATA_HDD_D2R_P 18 35
SATA_90D SATA SATA_HDD_D2R_N 18 35
SATA_90D SATA SATA_HDD_D2R_C_P 7 35
SATA_90D SATA SATA_HDD_D2R_C_N 7 35
SATA_ODD_R2D SATA_90D SATA SATA_ODD_R2D_C_P 9 18
SATA_90D SATA SATA_ODD_R2D_C_N 9 18
SATA_90D SATA SATA_ODD_R2D_P 9
A SATA_ODD_D2R
SATA_90D
SATA_90D
SATA
SATA
SATA_ODD_R2D_N
SATA_ODD_D2R_P
9
9 18
PAGE TITLE
SATA_ODD_D2R_N
SATA_90D
SATA_90D
SATA
SATA SATA_ODD_D2R_C_P
9 18
MCP Constraints 1
DRAWING NUMBER SIZE
SATA_90D SATA SATA_ODD_D2R_C_N
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP 18 REVISION
R
4.4.0
102 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPC Bus Constraints MCP89 Net Properties
ALLOW ROUTE
NET_TYPE
LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
LPC_AD LPC_55S LPC LPC_AD<3..0> 7 19 38 40
CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD LPC_FRAME_L LPC_55S LPC LPC_FRAME_L 7 19 38 40
LPC_RESET_L LPC_55S LPC LPC_RESET_L 19 25

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R 19 25

CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC 25 38

LPC * =1.5x_DIELECTRIC ?
CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS 7 25 40
CLK_LPC * =2x_DIELECTRIC ? USB_EXTA_P

USB_EXTA USB_90D USB 18 36
D SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.7

USB_90D USB USB_EXTA_N 18 36 D
USB_90D USB USB_EXTA_MUXED_P 36 71
USB_EXTA_MUXED_N
USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD
USB_MINI
USB_90D
USB_90D
USB
USB USB_MINI_P
36 71
9 18

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_90D USB USB_MINI_N 9 18
USB_EXTD USB_90D USB USB_EXTD_P 7 18 37

MCP_USB_RBIAS * =STANDARD 8 MIL 8 MIL =STANDARD =STANDARD =STANDARD
USB_90D USB USB_EXTD_N 7 18 37
USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF USB_CAMERA USB_90D USB USB_CAMERA_P 7 18 37
USB_90D USB USB_CAMERA_N 7 18 37

USB_BT USB_90D USB USB_BT_P 7 18 34

USB_90D USB USB_BT_N 7 18 34
USB * =2x_DIELECTRIC ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_TPAD USB_90D USB USB_TPAD_P 18 46 71
USB_90D USB USB_TPAD_N 18 46 71
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.8 USB_IR USB_90D USB USB_IR_P
USB_90D USB USB_IR_N
SMBus Interface Constraints USB_EXTB USB_90D USB USB_EXTB_P
ALLOW ROUTE
USB_90D USB USB_EXTB_N

ON LAYER?
USB_T57 USB_90D USB USB_T57_P
SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB USB_T57_N
USB_EXTC USB_90D USB USB_EXTC_P 9 18
USB_90D USB USB_EXTC_N 9 18

USB_SDCARD USB_90D USB USB_SDCARD_P 9 18
SMB * =2x_DIELECTRIC ? USB_90D USB USB_SDCARD_N 9 18
USB_WM USB_90D USB USB_WM_P

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.9 USB_90D USB USB_WM_N
MCP_USB_RBIAS_GND
C HD Audio Interface Constraints
MCP_USB_RBIAS MCP_USB_RBIAS 18
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_CLK 19 41

C
ON LAYER?
SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_0_DATA 19 41
HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD (SMBUS_SMC_MGMT_SCL) SMB_55S SMB SMBUS_MCP_1_CLK 19 41
(SMBUS_SMC_MGMT_SDA) SMB_55S SMB SMBUS_MCP_1_DATA 19 41

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK 7 19 37

HDA_55S HDA HDA_BIT_CLK_R 19

HDA * =2x_DIELECTRIC ?
HDA_SYNC HDA_55S HDA HDA_SYNC 7 19 37
MCP_HDA_COMP * 8 MIL ? HDA_55S HDA HDA_SYNC_R 19
HDA_RST_L HDA_55S HDA HDA_RST_R_L 19
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.10 HDA_55S HDA HDA_RST_L 7 19 37
HDA_SDIN0 HDA_55S HDA HDA_SDIN0 7 19 37
SIO Signal Constraints HDA_55S HDA HDA_SDIN_CODEC

ALLOW ROUTE
HDA_SDOUT HDA_55S HDA HDA_SDOUT 7 19 37

ON LAYER?
HDA_55S HDA HDA_SDOUT_R 19
CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

MCP_HDA_PULLDN_COMP MCP_HDA_COMP MCP_HDA_PULLDN_COMP 19
MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R 19 25

CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK 25 38
CLK_SLOW * =1.5x_DIELECTRIC ?
SPI_CLK SPI_55S SPI SPI_CLK_R 19 40
SPI_55S SPI SPI_CLK 40

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.11 SPI_MOSI_R
SPI_MOSI SPI_55S SPI 19 40
SPI_MOSI
SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD
SPI_MISO
SPI_55S
SPI_55S
SPI
SPI SPI_MISO
40
19 40

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_CS0 SPI_55S SPI SPI_CS0_R_L 19 40
SPI_55S SPI SPI_CS0_L 40
B SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

SPI_55S SPI SPI_MLB_CLK 40 47
B
SPI_55S SPI SPI_MLB_MOSI 40 47

SPI_55S SPI SPI_MLB_MISO 40 47
SPI * =1.5x_DIELECTRIC ? SPI_55S SPI SPI_MLB_CS_L 40 47
SPI_55S SPI SPI_ALT_CLK 7 40

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.12 SPI_ALT_MOSI
SPI_55S SPI 7 40
SPI_55S SPI SPI_ALT_MISO 7 40
SPI_55S SPI SPI_ALT_CS_L 7 40
PAGE TITLE
MCP Constraints 2
DRAWING NUMBER SIZE

REVISION
R
4.4.0
103 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP RGMII (Ethernet) Constraints RGMII Net Properties
ALLOW ROUTE
NET_TYPE
MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD
MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_VDD 18
ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_GND 18
MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0_R
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_MII_55S MCP_BUF0_CLK RTL8211_CLK25M_CKXTAL1
MCP_BUF0_CLK * =3:1_SPACING ? ENET_INTR_L ENET_MII_55S ENET_MII ENET_INTR_L

ENET_MDIO ENET_MII_55S ENET_MII ENET_MDIO 9 18

ENET_MII * 12 MIL ? ENET_MDC
ENET_MDC ENET_MII_55S ENET_MII
D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_PWRDWN_L D
ENET_RXCLK ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK_R
88E1116R (Ethernet PHY) Constraints ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK 9 18
ALLOW ROUTE
ENET_MII_55S ENET_MII ENET_RXD_R<3..0>

ON LAYER?
ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD<0> 9 18
ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD<3..1> 9 18
ENET_RXD ENET_MII_55S ENET_MII ENET_RX_CTRL 9 18

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_TXCLK ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK

ENET_TXD ENET_MII_55S ENET_MII ENET_TXD<0>

ENET_MDI * 25 MIL ? ENET_TXD<3..1>
ENET_TXD ENET_MII_55S ENET_MII
ENET_TXD ENET_MII_55S ENET_MII ENET_TX_CTRL
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
ENET_MII_55S ENET_MII ENET_RESET_L
SD Card Interface Constraints
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP Ethernet Net Properties

NET_TYPE
SD_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P<3..0>

ENET_MDI_100D ENET_MDI ENET_MDI_N<3..0>
SD_INTERFACE * =3X_DIELECTRIC ?
SD Card Net Properties

NET_TYPE
C SD_DATA SD_55S
SD_55S
SD_INTERFACE
SD_INTERFACE
SD_D<4..0>
SDCONN_DATA<4..0>
C
SD_55S SD_INTERFACE BCM57765_CR_DATA<4>
SD_DATA_R SD_55S SD_INTERFACE SD_D<7..5>
SD_55S SD_INTERFACE SDCONN_DATA<7..5>
SD_55S SD_INTERFACE BCM57765_CR_DATA<7..5>
SD_CLK SD_55S SD_INTERFACE SD_CLK
SD_55S SD_INTERFACE SD_CLK_R
SD_55S SD_INTERFACE SDCONN_CLK
SD_CMD SD_55S SD_INTERFACE SD_CMD
SD_55S SD_INTERFACE SDCONN_CMD
SD_55S SD_INTERFACE BCM57765_CR_CMD
NOTE: SD_D<7..5> are different to support

BCM5764M/BCM57765 co-layout.
B B
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER SIZE

REVISION
R
4.4.0
104 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC SMBus Net Properties
NET_TYPE
ON LAYER? ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM

SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 41
SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 41
SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL 41
SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA 41
SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 41
SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SDA 41
SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SCL 7 41
SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_BSA_SDA 7 41
D SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SCL 41 D

SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_MGMT_SDA 41
SMBus Charger Net Properties

NET_TYPE
CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P 50
1TO1_DIFFPAIR CHGR_CSI_N 50
1TO1_DIFFPAIR CHGR_CSI_R_P 50
1TO1_DIFFPAIR CHGR_CSI_R_N 50
CHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P 50
1TO1_DIFFPAIR CHGR_CSO_N 50
1TO1_DIFFPAIR CHGR_CSO_R_P 43 50
1TO1_DIFFPAIR CHGR_CSO_R_N 43 50
C C
B B
PAGE TITLE
SMC Constraints
DRAWING NUMBER SIZE

REVISION
R
4.4.0
106 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ALLOW ROUTE
Misc Net Properties Power Net Properties
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR
(USB_EXTA) USB_90D USB USB_EXTA_MUXED_P 36 68 CPUTHMSNS_D2 THERM_1TO1_55S THERM DRAMTHMSNS_D2_P 44

THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR
USB_EXTA_MUXED_N DRAMTHMSNS_D2_N
(USB_EXTA) USB_90D USB 36 68 THERM_1TO1_55S THERM 44
DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR (USB_EXTA) USB_90D USB USB_LT1_P 36 CPU_THERMD THERM_1TO1_55S THERM CPU_THERMD_P 10 44
(USB_EXTA) USB_90D USB USB_LT1_N 36 THERM_1TO1_55S THERM CPU_THERMD_N 10 44
(USB_TPAD) USB_90D USB USB_TPAD_P 18 46 68 MCPTHMSNS_D2 THERM_1TO1_55S THERM MLBR_THMDIODE_P 44
(USB_TPAD) USB_90D USB USB_TPAD_N 18 46 68 THERM_1TO1_55S THERM MLBR_THMDIODE_N 44
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT (USB_TPAD) USB_90D USB USB_TPAD_CONN_P 7 46 MCP_THMDIODE THERM_1TO1_55S THERM MCP_THMDIODE_P 19 44
(USB_TPAD) USB_90D USB USB_TPAD_CONN_N 7 46 THERM_1TO1_55S THERM MCP_THMDIODE_N 19 44
D SENSE * =1:1_SPACING ?
SMBUS_SMC_MGMT_SDA SMB_55S SMB I2C_SMC_SMS_SDA_R SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_1V5_S3_P 42 52

D
THERM * =1:1_SPACING ?
SMBUS_SMC_MGMT_SCL SMB_55S SMB I2C_SMC_SMS_SCL_R SENSE_1TO1_55S SENSE ISNS_1V5_S3_N 42 52
AUDIO * =1:1_SPACING ? SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_AIRPORT_P 34 42

SMB_55S SMB I2C_TCON_SCL 41
SENSE_1TO1_55S SENSE ISNS_AIRPORT_N 34 42
SMB_55S SMB I2C_TCON_SDA 41
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_CSREG_P 43
SMB_55S SMB I2C_TCON_SCL_CONN
SENSE_1TO1_55S SENSE ISNS_CSREG_N 43
SMB_55S SMB I2C_TCON_SDA_CONN

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_HDD_P 35 42
SENSE_1TO1_55S SENSE ISNS_HDD_N 35 42

ENETCONN * 25 MILS ?
Graphics Net Properties SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_LCDBKLT_P 42 62
NET_TYPE SENSE_1TO1_55S SENSE ISNS_LCDBKLT_N 42 62
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

SENSE_DIFFPAIR SENSE_1TO1_55S SENSE CPUVTTS0_CS_P 55
GND * =STANDARD ? DP_90D DISPLAYPORT DP_INT_ML_P<1..0> 9 59 SENSE_1TO1_55S SENSE CPUVTTS0_CS_N 55

DP_90D DISPLAYPORT DP_INT_ML_N<1..0> 9 59 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE IMVP6_CS_P 53

MEM_POWER * =STANDARD ?
DP_90D DISPLAYPORT DP_INT_ML_C_P<1..0> 59 SENSE_1TO1_55S SENSE IMVP6_CS_N 53
DP_90D DISPLAYPORT DP_INT_ML_C_N<1..0> 59 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE IMVP6_CS_R_P 53
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DP_90D DISPLAYPORT DP_INT_ML_F_P<1..0> 7 59 SENSE_1TO1_55S SENSE IMVP6_CS_R_N 53
DP_90D DISPLAYPORT DP_INT_ML_F_N<1..0> 7 59

GND_P2MM * 0.20 MM 1000 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE CPU_VTTSENSE_P 55
DP_90D DISPLAYPORT DP_INT_AUX_CH_C_P 7 59
SENSE_1TO1_55S SENSE CPU_VTTSENSE_N 55

PWR_P2MM * 0.20 MM 1000 DP_90D DISPLAYPORT DP_INT_AUX_CH_C_N 7 59
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE MCPCORES0_VSEN_P 22 54
DP_90D DISPLAYPORT DP_INT_AUX_CH_P 9 59
SENSE_1TO1_55S SENSE MCPCORES0_VSEN_N 22 54
DP_90D DISPLAYPORT DP_INT_AUX_CH_N 9 59

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_POWER PP1V5R1V35_S3 7 8
(DP_EXT_ML) DP_90D DISPLAYPORT DP_EXT_ML_P<3..0> 9 61

MEM_CLK GND * GND_P2MM MEM_CLK MEM_POWER * PWR_P2MM
DP_90D DISPLAYPORT DP_EXT_ML_N<3..0> 9 61 SB_POWER PP3V3_S5 7 8 57
MEM_CMD GND * GND_P2MM MEM_CMD MEM_POWER * PWR_P2MM DP_90D DISPLAYPORT DP_EXT_ML_C_P<3..0> 61 SB_POWER PP3V3_S0 7 8 57
DP_90D DISPLAYPORT DP_EXT_ML_C_N<3..0> 61 SB_POWER PP1V5_S0 7 8 57
C MEM_CTRL
MEM_DATA
GND
GND
*
*
GND_P2MM
GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DATA
MEM_POWER
MEM_POWER
*
*
PWR_P2MM
PWR_P2MM
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT
DP_EXT_ML_F_P<3..0>
DP_EXT_ML_F_N<3..0>
61
61
GND GND C
(DP_EXT_AUX_CH) DP_90D DISPLAYPORT DP_EXT_AUX_CH_C_P 9 61

MEM_DQS GND * GND_P2MM MEM_DQS MEM_POWER * PWR_P2MM
DP_EXT_AUX_CH_C_N
DP_90D DISPLAYPORT 9 61
Audio Net Properties
NET_TYPE
CLK_PCIE GND * GND_P2MM CLK_FSB GND * GND_P2MM
SPKRAMP_INR DIFFPAIR AUDIO SPKRAMP_INR_P 7 37 48
PCIE GND * GND_P2MM CPU_COMP GND * GND_P2MM DIFFPAIR AUDIO SPKRAMP_INR_N 7 37 48

SATA GND * GND_P2MM CPU_GTLREF GND * GND_P2MM MAX98300_R DIFFPAIR AUDIO MAX98300_R_P 48
DIFFPAIR AUDIO MAX98300_R_N 48

USB GND * GND_P2MM CPU_VCCSENSE GND * GND_P2MM
CLK_PCIE SB_POWER * PWR_P2MM

SATA SB_POWER * PWR_P2MM

USB SB_POWER * PWR_P2MM

LVDS GND * GND_P2MM ENET_MDI GND * GND_P2MM
SD CARD READER LAYOUT RELAXATIONS

B PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
B
SD_55S * =STANDARD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP Fanout Constraint Relaxations TABLE_PHYSICAL_RULE_HEAD
ON LAYER?
MEM_40S * 0.09 MM 5.8 MM

MCP_DV_COMP TOP 0.1 MM 500 MIL

MCP_MEM_COMP TOP 0.1 MM 500 MIL

MCP_MII_COMP TOP 0.1 MM 500 MIL

MCP_USB_RBIAS TOP 0.1 MM 500 MIL

MCP_DV_COMP * 0.25 MM 250 MIL

PAGE TITLE
K16/K99 Specific Constraints

DRAWING NUMBER SIZE

REVISION
R
4.4.0
108 OF 110
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
K99 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO

(MIL or MM) VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD
ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
DEFAULT * Y 0.100 MM 0.076 MM 30 MM 0 MM 0 MM DEFAULT * 0.1 MM ? 2X_DIELECTRIC * 0.140 MM ?

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT STANDARD * =DEFAULT ? TABLE_SPACING_RULE_ITEM
3X_DIELECTRIC * 0.210 MM ?
D ALLOW ROUTE
BGA_P1MM * 0.1 MM ?
D
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
BGA_P2MM * 0.2 MM ? TABLE_SPACING_RULE_ITEM
27P4_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

1.5X_DIELECTRIC * 0.105 MM ?
BGA_P3MM * 0.3 MM ? TABLE_SPACING_RULE_ITEM
27P4_OHM_SE ISL3,ISL10 Y 0.250 MM 0.250 MM

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD
27P4_OHM_SE ISL4,ISL9 Y 0.250 MM 0.250 MM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

1:1_SPACING * 0.1 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
ON LAYER? 1.5:1_SPACING * 0.15 MM ?

40_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
1.8:1_SPACING * 0.18 MM ?
40_OHM_SE TOP,BOTTOM Y 0.170 MM 0.170 MM TABLE_SPACING_RULE_ITEM
40_OHM_SE ISL3,ISL4,ISL9,ISL10 Y 0.140 MM 0.140 MM TABLE_SPACING_RULE_ITEM
2.28:1_SPACING * 0.228 MM ?
2.5:1_SPACING * 0.25 MM ?
ALLOW ROUTE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
50_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.110 MM TABLE_SPACING_RULE_HEAD
50_OHM_SE ISL3,ISL4,ISL9,ISL10 Y 0.090 MM 0.090 MM TABLE_SPACING_RULE_ITEM
GND * =STANDARD ?
PP1V5_MEM * =STANDARD ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD
ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
C 55_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

GND_P2MM * 0.2 MM 1000
C
55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM TABLE_SPACING_RULE_ITEM
PWR_P2MM * 0.2 MM 1000
55_OHM_SE ISL3,ISL4,ISL9,ISL10 Y 0.076 MM 0.076 MM

NB_STATIC * =STANDARD ?
ON LAYER?
70_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

70_OHM_DIFF TOP,BOTTOM Y 0.175 MM 0.175 MM 0.130 MM 0.130 MM

70_OHM_DIFF ISL3,ISL10 Y 0.135 MM 0.135 MM 0.130 MM 0.130 MM

ON LAYER?



B 75_OHM_DIFF *
ON LAYER?
Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

B


ON LAYER?



ON LAYER?



TABLE_PHYSICAL_RULE_HEAD PAGE TITLE
ALLOW ROUTE
K99 RULE DEFINITIONS
100_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD DRAWING NUMBER SIZE


REVISION
R
100_OHM_DIFF ISL3,ISL10 Y 0.075 MM 0.075 MM 0.300 MM 0.300 MM 4.4.0

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
109 OF 110

1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG MURATA TAIYO YUDEN
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
138S0629 2 CAP, 1UF, 6.3V, 10%, 0402 C7203,C7980 CRITICAL SS_CAP_1UF 138S0628 2 CAP, 1UF, 6.3V, 10%, 0402 C7203,C7980 CRITICAL MU_CAP_1UF 138S0630 2 CAP, 1UF, 6.3V, 10%, 0402 C7203,C7980 CRITICAL TY_CAP_1UF
D D
2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS
138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALSS_CAP_2_2UF
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALMU_CAP_2_2UF
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALTY_CAP_2_2UF
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249

C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259

C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 138S0633 8 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALMU_CAP_2_2UF
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 138S0634 8 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALTY_CAP_2_2UF
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267

C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909

C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919

C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929

C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939

C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 138S0633 12 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALMU_CAP_2_2UF
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 138S0634 12 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALTY_CAP_2_2UF
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296

C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516

C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541

C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 138S0633 8 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALMU_CAP_2_2UF
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 138S0634 8 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALTY_CAP_2_2UF
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555

C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
C 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALSS_CAP_2_2UF

C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641 C
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310 138S0633 9 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALMU_CAP_2_2UF
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310 138S0634 9 CAP, 2.2UF, 6.3V, 20%, 0402 CRITICALTY_CAP_2_2UF
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS

138S0626 1 CAP, 10UF, 6.3V, 20%, 0603 C1280 CRITICAL SS_CAP_10UF 138S0625 1 CAP, 10UF, 6.3V, 20%, 0603 C1280 CRITICAL MU_CAP_10UF 138S0627 1 CAP, 10UF, 6.3V, 20%, 0603 C1280 CRITICAL TY_CAP_10UF
138S0626 8 CAP, 10UF, 6.3V, 20%, 0603 C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647CRITICAL SS_CAP_10UF 138S0625 8 CAP, 10UF, 6.3V, 20%, 0603 C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647CRITICAL MU_CAP_10UF 138S0627 8 CAP, 10UF, 6.3V, 20%, 0603 C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647CRITICAL TY_CAP_10UF
138S0626 8 CAP, 10UF, 6.3V, 20%, 0603 C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999CRITICAL SS_CAP_10UF 138S0625 8 CAP, 10UF, 6.3V, 20%, 0603 C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999CRITICAL MU_CAP_10UF 138S0627 8 CAP, 10UF, 6.3V, 20%, 0603 C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999CRITICAL TY_CAP_10UF
B 22UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS B

138S0635 4 CAP, 22UF, 6.3V, 20%, 0603 C1210,C1214,C1217,C1218 CRITICAL SS_CAP_22UF 138S0676 4 CAP, 22UF, 6.3V, 20%, 0603 C1210,C1214,C1217,C1218 CRITICAL MU_CAP_22UF 138S0688 4 CAP, 22UF, 6.3V, 20%, 0603 C1210,C1214,C1217,C1218 CRITICAL TY_CAP_22UF
138S0635 3 CAP, 22UF, 6.3V, 20%, 0603 C1223,C1226,C1227 CRITICAL SS_CAP_22UF 138S0676 3 CAP, 22UF, 6.3V, 20%, 0603 C1223,C1226,C1227 CRITICAL MU_CAP_22UF 138S0688 3 CAP, 22UF, 6.3V, 20%, 0603 C1223,C1226,C1227 CRITICAL TY_CAP_22UF
138S0635 5 CAP, 22UF, 6.3V, 20%, 0603 C1230,C4902,C7360,C7361,C9480 CRITICAL SS_CAP_22UF 138S0676 5 CAP, 22UF, 6.3V, 20%, 0603 C1230,C4902,C7360,C7361,C9480 CRITICAL MU_CAP_22UF 138S0688 5 CAP, 22UF, 6.3V, 20%, 0603 C1230,C4902,C7360,C7361,C9480 CRITICAL TY_CAP_22UF
PAGE TITLE
Acoustic Cap BOM Config Tables

DRAWING NUMBER SIZE

REVISION
R
4.4.0
110 OF 110
8 7 6 5 4 3 2 1

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8 7 6 5 4 3 2 1

SCHEMATIC MBA , MLB D

Page Contents Sync Page Contents Sync

3 Power Block Diagram K6_MLB 48 AUDI0: SPEAKER AMP AUDIO

15 MCP Memory Interface K16_MLB 60 External DisplayPort Support K16_MLB

20 07/07/2010 100 07/07/2010

20 MCP Power & Ground K16_MLB 65 CPU/FSB Constraints K16_MLB

23 07/07/2010 101 07/07/2010

21 MCP89 Memory Rail Gating K16_MLB 66 Memory Constraints K16_MLB

24 07/07/2010 102 07/07/2010

22 MCP89 GFX Core Rail Gating K16_MLB 67 MCP Constraints 1 K16_MLB

25 07/07/2010 103 07/07/2010

23 MCP Standard Decoupling K16_MLB 68 MCP Constraints 2 K16_MLB

26 07/07/2010 104 07/07/2010

28 12/11/2009 106 07/07/2010

31 07/07/2010 108 07/07/2010

32 07/07/2010 109 07/07/2010

33 07/07/2010 110 07/07/2010

40 LPC+SPI Debug Connector K16_MLB

Apple Inc. 051-8379 D

INTEL CPU J1300

1.6 GHZ XDP CONN

RTC XTAL VOLTAGE/CURRENT SENSOR

SSD MCP89U-A01 J5100

SATA SATA 2.0 3GBIT/S

CONN PCI-E USB_6

J4700 I2C HDA USB USB SPK

LIO FLEX CONN I2C

J4702 J4610 U6201

DRAM CFG CHART

SIZE CFG 2 DIE REV CFG 3

C 607-6999 CMN PTS,PCBA,MLB,K99 K99_COMMON

825-7557 1 LABEL,MLB,K16/K99 [EEE_DG4P] CRITICAL EEE:DG4P

639-1439 PCBA,MLB,1.4GHZ,EL 4GB,MU CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4H,DDR3:ELPIDA_4GB,CAPS:MU

639-1440 PCBA,MLB,1.4GHZ,EL 4GB,TY CAP,K99 K99_CMNPTS,CPU:1.4GHZ,EEE:DG4J,DDR3:ELPIDA_4GB,CAPS:TY

Apple Inc. 051-8379 D

138S0681 138S0638 ALL TAIYO YUDEN AS ALTERNATE

152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE

152S0847 152S0586 ALL MAGLAYERS AS ALTERNATE

353S2987 353S2988 HVDDLDO:FIXED ALL TPS71725DCK AS ALTERNATE FOR U2590

104S0023 104S0018 ALL CYNTEC/DALE AS ALTERNATES

107S0139 107S0075 ALL CYNCTEC AS ALTERNATE

138S0671 138S0673 ALL TAIYO AS ALTERNATE

155S0578 155S0367 ALL TAIYO AS ALTERNATE

376S0926 376S0610 ALL FAIRCHILD AS ALTERNATE

155S0457 155S0329 ALL MAGLAYERS AS ALTERNATE

377S0107 377S0066 ALL ONSEMI AS ALTERNATE

333S0565 4 ELPIDA,LVDDR3,1GBIT,7.5X10.6 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:ELPIDA_2GB

333S0565 4 ELPIDA,LVDDR3,1GBIT,7.5X10.6 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:ELPIDA_2GB

333S0565 4 ELPIDA,LVDDR3,1GBIT,7.5X10.6 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:ELPIDA_2GB

333S0565 4 ELPIDA,LVDDR3,1GBIT,7.5X10.6 U3400,U3410,U3420,U3430 CRITICAL DRAM_TYPE:ELPIDA_2GB

333S0555 4 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_4GB

HYNIX,LVDDR3,2GBIT,9X11.1 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_4GB

333S0555 4 HYNIX,LVDDR3,2GBIT,9X11.1 U3400,U3410,U3420,U3430 CRITICAL DRAM_TYPE:HYNIX_4GB

333S0556 4 SAMSUNG,LVDDR3,2GBIT,7.5X11.0 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:SAMSUNG_4GB

333S0556 4 SAMSUNG,LVDDR3,2GBIT,7.5X11.0 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:SAMSUNG_4GB

333S0556 4 SAMSUNG,LVDDR3,2GBIT,7.5X11.0 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:SAMSUNG_4GB

333S0556 4 SAMSUNG,LVDDR3,2GBIT,7.5X11.0 U3400,U3410,U3420,U3430 CRITICAL DRAM_TYPE:SAMSUNG_4GB

333S0557 4 MICRON,LVDDR3,2GBIT,9X11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:MICRON_4GB

BOM Groups 333S0557 4 MICRON,LVDDR3,2GBIT,9X11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:MICRON_4GB

BOM GROUP BOM OPTIONS 333S0557 4 MICRON,LVDDR3,2GBIT,9X11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:MICRON_4GB

K99_PROGPARTS BOOTROM:UNLOCKED,SMC:PROG 333S0566 4 ELPIDA,LVDDR3,2GBIT,9X11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:ELPIDA_4GB

K99_DEVEL:ENG BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LED 333S0566 4 ELPIDA,LVDDR3,2GBIT,9X11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_TYPE:ELPIDA_4GB