Lecture 05

Instruction Sets:
Characteristics and Functions

Taken from William Stallings Computer Organization and Architecture 8th Edition

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LECTURE OUTLINE

Instruction Set: Representation and Format

Types of Operations

Byte Ordering

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WHAT IS AN INSTRUCTION SET?
Instructions
Specify operations to be performed by a computer.

Words of a computers language.

Instruction set
Collection of the instructions of a computer.

Vocabulary of a computers language.

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ELEMENTS OF AN INSTRUCTION

Operation code (opcode)

Specifies the operation to be performed.
Operation Code Addresses
(Opcode) (operands)
Addresses (operands)
Provide more information about the operation.

May include:
Source operands: specify where operands come from.

Destination operands: specify where results go.

Next instruction reference: specifies where to fetch
next instruction from.

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INSTRUCTION REPRESENTATION

Instructions to be read by a computer contain strings of 1s and

0s (They are numbers) (Machine instructions).

Symbolic representations of machine instructions are used for

convenience (assembly language).

Even more convenient (High-level languages)

void main(){
int a,b,c; main: 0567
c = a+b;} ADD c,a,b

High-level language Assembly language Machine language

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 INSTRUCTION FORMAT

Defines the layout of the bits of an instruction in terms

of its constituent fields (What does each field
represent and how many bits is it?)
Common formats:
Opcode Opcode Address

(zero operand ) (one operand )

Opcode Address Address Opcode Add.1 Add. Add.

1 2 2 3

(two operands ) (three operands )

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 HOW MANY ADDRESSES
The number of addresses per instruction is a basic

design decision.

More addresses
Fewer addresses
More complex instructions
Less complex instructions
More registers
More instructions per program
Inter-register operations
Faster fetch/execution of
are quicker
instructions
Fewer instructions per program

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INSTRUCTION TYPES
Data processing: Arithmetic and logic instructions.

Data storage: movement of data into or out of register and or

memory locations.

Data movement: I/O instructions.

Control: test and branch instructions.

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INSTRUCTION SET DESIGN ISSUES

Operation repertoire: how Registers: Number of processor

many and which operations to
registers that can be referenced by
provide, and how complex they
instructions, and their use.
should be.

Data types: The various types Addressing: The mode or modes by

of data upon which operations which the address of an operand is
are performed. specified.
Instruction formats:
RISC v CISC
Size of various fields(e.g. opcode )
Number of addresses

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TYPES OF OPERATIONS

Data Transfer
I/O
Arithmetic
System Control
Logical
Transfer of Control
Conversion

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 DATA TRANSFER
Copy values from one location to another

(e.g. MOV, LEA, IN/OUT, PUSH/POP)

MOV destination, source
Destination: can be register or memory location
Source: can be register, memory location or an immediate number
e.g. MOV CX, 20 place the value 20 in CX register (CX20)
MOV CX, [20] copy value at memory location 20 to CX

CPU Memory CPU Memory

CX 0 19 78 CX 96 19 78
20 96 20 96
21 0 21 0
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 DATA TRANSFER CNTD

PUSH source

Used to transfer data to stack

Source: can be register or memory location

e.g. PUSH CX copy CX to stack

CPU Stack CPU

Stack
CX 96 23 CX 96
96
15
23
0
15

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 DATA TRANSFER CNTD

POP destination

Used to retrieve data from stack

Destination: can be register or memory location
e.g. POP BX copy data on top of stack to register BX

CPU Stack CPU Stack

BX 0 96 BX 96 23
23 15
15 0

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ARITHMETIC
(e.g. ADD, INC, SUB, DEC,MUL,DIV)

Signed Integer, Floating point ?

ADD destination, source

Destination: can be register or memory location
Source: can be register, memory location or an immediate
number
e.g. ADD CX, BX (CXCX+BX)
CPU CPU
BX 96 BX 96
CX 96 CX 192
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ARITHMETIC CNTD

DEC destination

Destination: can be register or memory location

e.g. DEC CX (CXCX-1)

CPU
CPU
CX 192 CX 191

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 ARITHMETIC CNTD

MUL source
Source: can be register or memory location

Destination is an accumulator register, AX

e.g. MUL BL (AXAL x BL)

CPU
CPU
BX 96
0 96 AX 960(03C0H)
03H C0H
AX 10
0 10
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LOGICAL

Operate on a bit-by-bit basis

(e.g. AND, OR, XOR, NOT, SHR, SHL)

e.g. AND CX, BX (CXCX AND BX)

CPU CPU
BX 96(60H)
BX 96 (60H)
CX 32(20H)
CX 191(BFH)

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SHIFT AND ROTATE OPERATIONS

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INPUT/OUTPUT

Instructions to read data from an input module

and to write data to an output module.

(e.g. IN, OUT)

IN accumulator, port OUT port, accumulator

Port: address of the I/O module (8-bits for 8086)

e.g. IN AL, 60H (read keyboard port)

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TRANSFER OF CONTROL
Instructions discussed so far execute sequentially.

Transfer of control instructions change the sequence of

execution (update value of the program counter (PC)).

Common transfer of control instructions:

Branch (Jump) instructions

Procedure call instruction

Skip instructions

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 TRANSFER OF CONTROL CNTD

Branch (Jump) Instruction

Has address of next instruction as an operand

Conditional branch: branch is made if a certain condition is met
e.g. JZ target (Jump to target address if result of previous
operation is zero)
e.g. SUB CX, 32 CX=CX-32;
JZ label If(CX==0)
{
label:
MOV BX, 10 BX=10;
}
Let label indicates the address 204
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 TRANSFER OF CONTROL CNTD

CPU Memory CPU Memory

BX 96 200 SUB CX,32 BX 96 200 SUB CX,32
CX 32 201 JZ 204 CX 0 201 JZ 204
202 202
PC (IP) 200 203 PC (IP) 201
203
ZF 0 204 MOV BX,10 204 MOV BX,10
ZF 1

CPU Memory CPU Memory

BX 96 200 SUB CX,32 BX 10 200 SUB CX,32
CX 0 201 JZ 204 CX 0 201 JZ 204
202 202
PC 204 203 PC 205
203
(IP) (IP)
204 MOV BX,10 204 MOV BX,10
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 TRANSFER OF CONTROL CNTD

Unconditional branch: branch is made without any condition

e.g. Jmp target (Jump to target address)

e.g. SUB CX, 32 CX=CX-32;

goto label;
Jmp label
label:
BX=10;
label:
MOV BX, 10
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 TRANSFER OF CONTROL CNTD

Procedure call Instructions

Instruct the processor to go and execute an entire procedure and

return.

Procedure:

Small, self-contained program within a larger program (like

function in high-level languages).

Allows same piece of code to be used many times.

e.g. CALL subroutine ..RET
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 TRANSFER OF CONTROL CNTD

CX=CX-32;
e.g. SUB CX, 32
Sub();
CALL sub


sub: Void sub()
MOV BX, 10 {
RET BX=10;
}
Let sub indicates the address 204

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 TRANSFER OF CONTROL CNTD
CPU Memory CPU Memory
BX 96 200 SUB CX,32 BX 96 200 SUB CX,32
CX 32 201 CALL 204 CX 0 201 CALL 204
202 202
PC (IP) 200 203 PC (IP) 201
203
204 MOV BX,10 204 MOV BX,10
205 RET 205 RET
CPU Memory CPU Memory
BX 96 200 SUB CX,32 BX 10 200 SUB CX,32
CX 0 201 CALL 204 CX 0 201 CALL 204
202 202
PC (IP) 204 203 PC (IP) 205
203
204 MOV BX,10 204 MOV BX,10
205 RET 205 RET
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 TRANSFER OF CONTROL CNTD

CPU Memory
BX 10 200 SUB CX,32
CX 0 201 CALL sub
202
PC 202 203
(IP)
204 MOV BX,10
205 RET

During a call operation the return address of memory has

to be saved first.
Generally the return address is saved in stack.
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NESTED PROCEDURE CALLS

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USE OF STACK TO IMPLEMENT THE ABOVE
NESTED SUBROUTINES

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BYTE ORDERING
The concept of endianness arises when it is necessary to treat a
multiple-byte entity as a single data item with a single address, even
though it is composed of smaller addressable units.

With respect to bytes, endianness has to do with the byte ordering

of multibyte scalar values.

What order do we read numbers that occupy more than one byte?

e.g. (numbers in hex to make it easy to read)

12345678 can be stored in 4x8bit locations as follows

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BYTE ORDER (EXAMPLE)
Address Value (1) Value(2)

184 12 78

185 34 56

186 56 34

186 78 12

Big Endian Little Endian

i.e. read top down or bottom up?

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BYTE ORDER NAMES

The problem is called Endian.

The system on the left has the most significant byte in the
lowest address which is called big-endian.

The system on the right has the most significant byte in the
highest address which is called little-endian.

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EXAMPLE OF C DATA STRUCTURE

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 CONTINUED

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 BIT ORDERING
In ordering the bits within a byte, we are faced with two questions:
1) Do you count the first bit as bit zero or as bit one?

2) Do you assign the lowest bit number to the bytes least significant bit?

The choice of big- or little-endian bit ordering within a byte is not always
consistent with big- or little-endian ordering of bytes within a multibyte
scalar. The programmer needs to be concerned with these issues when
manipulating individual bits.

Another area of concern is when data are transmitted over a bit-serial line.
The designer must make certain that incoming bits are handled properly.
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