FQA19N60

April 2000

QFET TM

FQA19N60
600V N-Channel MOSFET

General Description Features

These N-Channel enhancement mode power field effect 18.5A, 600V, RDS(on) = 0.38 @ VGS = 10 V
transistors are produced using Fairchilds proprietary, Low gate charge ( typical 70 nC)
planar stripe, DMOS technology. Low Crss ( typical 35 pF)
This advanced technology has been especially tailored to Fast switching
minimize on-state resistance, provide superior switching 100% avalanche tested
performance, and withstand high energy pulse in the Improved dv/dt capability
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.

D
!

"

! "
G! "
"

!
TO-3P S
G DS
FQA Series

Absolute Maximum Ratings

TC = 25C unless otherwise noted

Symbol Parameter FQA19N60 Units

VDSS Drain-Source Voltage 600 V
ID Drain Current - Continuous (TC = 25C) 18.5 A
- Continuous (TC = 100C) 11.7 A
IDM Drain Current - Pulsed (Note 1) 74 A
VGSS Gate-Source Voltage
30 V
EAS Single Pulsed Avalanche Energy (Note 2) 1150 mJ
IAR Avalanche Current (Note 1) 18.5 A
EAR Repetitive Avalanche Energy (Note 1) 30 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V
ns
PD Power Dissipation (TC = 25C) 300 W
- Derate above 25C 2.38 W/C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 C
Maximum lead temperature for soldering purposes,
TL 300 C
1/8 from case for 5 seconds

Thermal Characteristics
Symbol Parameter Typ Max Units
RJC Thermal Resistance, Junction-to-Case -- 0.42 CW
RCS Thermal Resistance, Case-to-Sink 0.24 -- CW
RJA Thermal Resistance, Junction-to-Ambient -- 40 CW

2000 Fairchild Semiconductor International Rev. A, April 2000

 FQA19N60
Electrical Characteristics




T C = 25C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 A 600 -- -- V
BVDSS Breakdown Voltage Temperature
ID = 250 A, Referenced to 25C -- 0.65 -- V/C
/ TJ Coefficient
IDSS VDS = 600 V, VGS = 0 V -- -- 10 A
Zero Gate Voltage Drain Current
VDS = 480 V, TC = 125C -- -- 100 A
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteristics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 A 3.0 -- 5.0 V
RDS(on) Static Drain-Source
VGS = 10 V, ID = 9.3 A -- 0.3 0.38
On-Resistance
gFS Forward Transconductance VDS = 50 V, ID = 9.3 A (Note 4) -- 16 -- S

Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V, -- 2800 3600 pF
Coss Output Capacitance f = 1.0 MHz -- 350 450 pF
Crss Reverse Transfer Capacitance -- 35 45 pF

Switching Characteristics
td(on) Turn-On Delay Time -- 65 140 ns
VDD = 300 V, ID = 18.5 A,
tr Turn-On Rise Time -- 210 430 ns
RG = 25
td(off) Turn-Off Delay Time -- 150 310 ns
(Note 4, 5)
tf Turn-Off Fall Time -- 135 280 ns
Qg Total Gate Charge VDS = 480 V, ID = 18.5 A, -- 70 90 nC
Qgs Gate-Source Charge VGS = 10 V -- 17 -- nC
Qgd Gate-Drain Charge (Note 4, 5) -- 33 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current -- -- 18.5 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 74 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 18.5 A -- -- 1.4 V
trr Reverse Recovery Time VGS = 0 V, IS = 18.5 A, -- 420 -- ns
Qrr Reverse Recovery Charge dIF / dt = 100 A/s (Note 4)
-- 4.7 -- C

Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 6.2mH, IAS = 18.5A, VDD = 50V, RG = 25 , Starting TJ = 25C
3. ISD
18.5A, di/dt
200A/s, VDD
BVDSS, Starting TJ = 25C
4. Pulse Test : Pulse width
300s, Duty cycle
2%
5. Essentially independent of operating temperature

2000 Fairchild Semiconductor International Rev. A, April 2000

FQA19N60

Typical Characteristics

VGS
Top : 15 V
10 V
8.0 V
7.0 V
6.5 V
6.0 V 1
1 Bottom : 5.5 V 10

ID , Drain Current [A]

ID , Drain Current [A]

10

150

10
0
25

10
0 -55


Notes :
Notes :
1. 250s Pulse Test 1. VDS = 50V
2. TC = 25 2. 250s Pulse Test

-1
10
10
-1
10
0
10
1 2 4 6 8 10
VDS , Drain-Source Voltage [V] VGS , Gate-Source Voltage [V]

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

1.2

1.0
IDR , Reverse Drain Current [A]
Drain-Source On-Resistance

VGS = 10V 1
0.8 10
RDS(ON) [
],

VGS = 20V

0.6

0
0.4 10
150
25


Notes :
0.2 1. VGS = 0V

Note : TJ = 25 2. 250s Pulse Test

0.0 -1
0 10 20 30 40 50 60 70 10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ID, Drain Current [A] VSD , Source-Drain Voltage [V]

Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage

Drain Current and Gate Voltage Variation vs. Source Current and
Temperature

5000 12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd VDS = 120V
10
4000 Ciss VDS = 300V
VGS, Gate-Source Voltage [V]

VDS = 480V
8
Coss
Capacitance [pF]

3000

2000

Notes : 4
Crss 1. VGS = 0 V
2. f = 1 MHz
1000 2

Note : ID = 18.5 A

0 0
-1 0 1 0 15 30 45 60 75
10 10 10
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

2000 Fairchild Semiconductor International Rev. A, April 2000

 FQA19N60
Typical Characteristics (Continued)

1.2 3.0

2.5
Drain-Source Breakdown Voltage

1.1

Drain-Source On-Resistance
BV DSS , (Normalized)

RDS(ON) , (Normalized)
2.0

1.0 1.5

1.0

0.9
Notes :
1. VGS = 0 V

Notes :
2. ID = 250 A 0.5 1. VGS = 10 V
2. ID = 9.3 A

0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
o o
TJ, Junction Temperature [ C] TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation

vs. Temperature vs. Temperature

20
Operation in This Area
is Limited by R DS(on)
2
10
16

100 s 10 s
ID, Drain Current [A]

ID, Drain Current [A]

1 ms 12
1
10 10 ms
DC
8

0
10

Notes :
1. TC = 25 C
o 4
o
2. TJ = 150 C
3. Single Pulse
-1
10 0
0 1 2 3
10 10 10 10 25 50 75 100 125 150

VDS, Drain-Source Voltage [V] TC, Case Temperature [
]

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
( t) , T h e r m a l R e s p o n s e

D = 0 .5

-1
N o te s :
10 0 .2
1 . Z
J C ( t) = 0 .4 2  /W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
0 .1 3 . T J M - T C = P D M * Z
J C ( t)

0 .0 5
PDM
0 .0 2

JC

t1
-2 0 .0 1
10 s i n g l e p u ls e t2
Z

-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10

t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]

Figure 11. Transient Thermal Response Curve

2000 Fairchild Semiconductor International Rev. A, April 2000

FQA19N60

Gate Charge Test Circuit & Waveform

VGS
Same Type
50K

as DUT Qg
12V 200nF
300nF 10V
VDS
VGS Qgs Qgd

DUT
3mA

Charge

Resistive Switching Test Circuit & Waveforms

RL VDS
VDS 90%

VGS VDD
RG
10%
VGS
10V DUT
td(on) tr td(off)
tf
t on t off

Unclamped Inductive Switching Test Circuit & Waveforms

L 1 BVDSS
VDS EAS = ---- L IAS2 --------------------
2 BVDSS - VDD
BVDSS
ID
IAS
RG
VDD ID (t)

10V DUT VDD VDS (t)

tp
tp Time

2000 Fairchild Semiconductor International Rev. A, April 2000

 FQA19N60
Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT +

VDS

I SD
L

Driver
RG
Same Type
as DUT VDD

VGS dv/dt controlled by RG

ISD controlled by pulse period

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

IFM , Body Diode Forward Current

I SD
( DUT ) di/dt

IRM

Body Diode Reverse Current

VDS
( DUT ) Body Diode Recovery dv/dt

VSD VDD

Body Diode
Forward Voltage Drop

2000 Fairchild Semiconductor International Rev. A, April 2000

FQA19N60

Package Dimensions

TO-3P
15.60 0.20
4.80 0.20
13.60 0.20

3.80 0.20
3.20 0.10 +0.15
9.60 0.20 1.50 0.05

18.70 0.20
12.76 0.20

19.90 0.20

23.40 0.20
13.90 0.20

2.00 0.20
3.50 0.20

3.00 0.20
16.50 0.30

1.00 0.20 1.40 0.20

+0.15
0.60 0.05
5.45TYP 5.45TYP
[5.45 0.30] [5.45 0.30]

2000 Fairchild Semiconductor International Rev. A, April 2000

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

2000 Fairchild Semiconductor International Rev. A, January 2000