Electrical Characterization of MOS Devices With Advanced Gate Stacks

June 11-12
2005
Electrical Characterization of
MOS Devices with Advanced
Gate Stacks
Eric M. Vogel Leader, CMOS and Novel Devices Group
and Director, NIST AML Nanofab
Semiconductor Electronics Division

Gaithersburg, MD 20899
Advanced Dielectrics
Ultrathin and high- gate dielectrics present numerous

challenges to MOS device characterization.
Eric M. Vogel June 11-12, 2005
Slide No. 2 Electrical Characterization of MOS Devices
Scope
This 2-part lecture will focus on the understanding necessary
to characterize MOS capacitors and gated diodes on bulk silicon
having advanced gate dielectrics using the most common lower
frequency (<~ 1 MHz) techniques: 1) Capacitance,
2) Conductance, 3) Charge-Pumping, 4) Tunneling.
For FET Parameter Extraction see G. Ghibaudo lecture

For LF Noise see C. Clayes lecture
For SOI see S. Cristoloveanu lecture and A. Zaslavsky lecture
For Reliability, Defect generation, and Device Instability see J.
Stathis lecture
For High Frequency Device Characterization see G. Dambrine
lecture
OUTLINE
Capacitance-Voltage
Conductance
Tunneling
Charge-Pumping

CAPACITANCE-VOLTAGE
Measurement Issues
Theory (Without Interface States)
Parameter Extraction
Including Interface States

C-V Measurement Issues
Conditions
Errors
Equivalent Circuits

Measurement Conditions
The ac voltage should be as small as possible

to ensure small signal approximation while
still allowing accurate measurement.
Assuming that the device capacitance is

properly extracted from the measured
capacitance, either parallel or series mode
may be used since the one can be derived from
the other (Cs=Cp*(1+D2), D=1/RpCp).
Quasi-static C-V measurements generally

can not be performed (using standard q-s meters) Cm Gm
due to the large leakage currents.

Measurement Errors
Relative Measurement Accuracy for HP4284A
The relative measurement Calculations from HP4284A Precision LCR Meter Operation Manual p. 9-7 to 9-15
accuracy of an LCR meter This is only valid for: medium/long integration
depends on the frequency 100Hz <= F <= 1MHz
1 m cable
and the nominal capacitance Vdc < 20 V
and conductance of the device 30mV <= Vac <= 150mV <or> Vac = 10mV,20mV,25mV
Cp-Gp measurement mode
under test. short and open correction performed
Input
C (F) 1.30E-10
We have developed a G (S) 1.00E-02
spreadsheet which calculates

F (Hz) 1.00E+03
Vac (Vrms) 5.00E-02
the relative measurement Output

accuracy of the HP4284A. C_relacc (+/-%)
G_relacc (+/-%)
1288.996212
D too large (D>0.1)* 1.05296E-05
(FYI: Cal
(FYI: Cal
D_relacc (+/-%) 157833.5641 (FYI: Cal

Measurement Errors
105 -11 -3
C = 10 F, G = 10 S
The relative capacitance
Capacitance Error (+/- %)

104 -6
C = 10-11 F, G = 10 S
measurement error
-10 -6
C = 10 F, G = 10 S
103
of an LCR meter increases 102
with: 101
decreasing frequency 100
increasing conductance 10-1
decreasing capacitance 10-2
102 103 104 105 106
Frequency (Hz)

Capacitor Equivalent Circuits
Cc Gc
Rs
Lo

Equivalent Circuits
Transistor
LCR Measurement Capacitor
Equivalent Circuit
Equivalent Circuit
Cm Gm Cc Gc
Rs
K. Ahmed, E. Ibok, G. Yeap, Q. Xiang,
B. Ogle, J. J. Wortman, and J. R. Hauser,
Lo IEEE Trans. Elec. Dev., vol. 46,
pp. 1650-1655, 1999.

Examples of Measured Behavior
600
500 F = 10 kHz 140 2

10 Hz
F = 1 MHz 3
Capacitance (pF)
120 10 Hz
Capacitance (pF)
4
400 10 Hz
100 105 Hz
300 106 Hz
80
200 60
ISSG 2.1 nm
-5 2
100 40 Area = 5x10 cm
20
0
-3 -2 -1 0 1 2 0
-3 -2 -1 0 1 2 3
Vg (V)
Vg (V)
For thicker dielectrics, a simple For thinner or leakier

reduction in capacitance at dielectrics, capacitance roll-
high frequencies due to series over, negative capacitance, and
resistance is many times increasing capacitance with
observed. bias is sometimes observed.
Modeling Measured Capacitance
Series resistance alone 1000

cannot explain an increase in
Correct Capacitance
800 Rs=20, L=0H
or negative measured
Capacitance (pF)
Rs=20, L=10H
600 Rs=20, L=45H
capacitance at high 400 Rs=103, L=0H
frequency. 200 F=1MHz
0
Inductance is necessary to
-200
observe an increase in or -3 -2 -1 0 1
negative capacitance at high Vg (V)
frequency. Gc (Gc Rs + 1) 2Cc2 Rs
Gm =
(G R c s C c Lo + 1) + (C c Rs + Gc Lo )
2 2 2 2
Cm =
( )
Cc 1 2Cc Lo Gc2 Lo
Eric (M. + 1) + (C R )
2
GR
c C
Vogel
s L 11-12,
June 2005
2
c o
2
c s + G L
c o
2

Correcting Measured Capacitance
Previous work provided methodologies to correct

measured capacitance for leakage and series resistance1,2.
Recent work has provided the methodology that includes a
series inductance3.
It is unknown whether the
series inductance is due to
measurement (e.g. cabling)4
or a physical phenomenon5.
1K. J.Yang and C. Hu, IEEE Trans. Elec. Dev., vol. 46, pp. 1500-1501, 1999.
2E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, IEEE Trans. Elec. Dev., vol. 47, p. 601, 2000.
3H.-T. Lue, C.-Y. Liu, and T.-Y. Tseng, IEEE Elec. Dev. Lett., vol. 23, pp. 553-555, 2002.
4A. Nara, N. Yasuda, H. Satake, and A. Toriumi, IEEE Trans. Semi. Manuf., vol. 15, pp. 209-213, 2002.
5M. Matsumura, and Y. Hirose, Jap. J. Appl. Phys., vol. 39, pp. L123-L125, 2000.

C-V Theory
Potential and Charge Balance

Built-in Voltage
Total Semiconductor Charge
Regions of Operation
Capacitance
Quantum Mechanical Effects

Equations for C-V
Potential Balance: Vg = Vsub V poly + Vox + Vbi
Charge Balance: Qsub (Vsub ) + Q poly (V poly ) + Qox = 0
To calculate C-V, we need to solve the above equations.
Vpoly is measured from the oxide-poly interface to the bulk of

the poly. Vpoly = 0 for metal gate electrodes.
Qox is charge in the oxide that is fixed with bias.
We will first neglect defects in the dielectric that change
occupancy with applied bias (interface states).
Vbi is the built-in potential between the gate and substrate.
Potential Balance
Vg = Vsub V poly + Vox + Vbi Potential balance

(E vac E f , poly ) @ poly bulk (E vac E f ,sub ) @ sub bulk
More later
Vbi =
q q
Q poly (V poly ) = CoxVox Using Gauss Law
Qsub
Vg = Vsub V poly + V fb
Cox
Qox
V fb = Vbi
Cox

Charge Density in a Semiconductor
= q ( p n + N d+ N a ) Classical Charge Density (cm-3) in

a Semiconductor
2Nv E gap 2 N c
F1 2 F1 2 +
t t
= q Nd Na

1 + 2 exp ( Ed Ec ) 1 + 4 exp ( Ea Ec )

t t
kT
F1/ 2 ( ) =
2 E t

0 1 + exp( E )
dE E f Ec q

Calculating the Built-in Voltage
(E vac E f , poly ) @ poly bulk (E vac E f ,sub ) @ sub bulk
Vbi =
q q
2Nv E gap 2 N c
F1 2 F1 2 +
t t E f Ec
= q Nd Na

1 + 2 exp ( Ed Ec ) 1 + 4 exp ( Ea Ec )
kT
t t t
2 E q
F1/ 2 ( ) = dE
1 + exp( E )
0
To calculate Vbi set = 0 and find Ef in the bulk of the

semiconductor.
Calculating Total Semiconductor Charge
Qsub (Vsub ) + Q poly (V poly ) + Qox = 0
2Nv E gap 2 N c
F1 2 F1 2 +
t t
= q Nd Na

1 + 2 exp ( Ed Ec ) 1 + 4 exp ( Ea Ec )

t t
To calculate Qsub(Vsub) or Qpoly(Vpoly), one must integrate from

the oxide/semi interface to the bulk of the semiconductor.

Calculating Total Semiconductor Charge
4Nv b E gap b Vsub E gap

F
3 2
3 2
F +
3 t t
4N b b + Vsub
c
F3 2 F3 2 +
3 t t

( E E )

Qsub = surf 1 + 2 exp b d c
2qt Vsub t
2surf = + ln +
d t
N
+ V ( E E )
1 + 2 exp b sub d c

t

( Ea E c ) b
bulk = (E f Ec ) bulk = b 1 + 4 exp
t

N a sub + ln
V
t ( Ea E c ) b Vsub
2 E3 2 1 + 4 exp
F3 / 2 ( ) = dE t
0 1 + exp( E )
Solving Potential and Charge Balance
Qsub
Potential Balance: Vg = Vsub V poly + V fb
Cox
Charge Balance: Qsub (Vsub ) + Q poly (V poly ) + Qox = 0
Given: Vg, Nsub, Npoly, Cox, Qox
The above 2 equations can be solved for 2 unknowns: Vsub, Vpoly

Regions of Operation
1.4 3e-6
1.2 Inversion
2e-6
1.0 Depletion
Ef-Ec=-nkT/q 1e-6
0.8
0.6 Depletion 0 Inversion
Vsub
Qsub
0.4 -1e-6 Accumulation
0.2
Ef-Ec=-Egap+nkT/q -2e-6
0.0
-0.2 Accumulation -3e-6
-0.4 -4e-6
-4 -3 -2 -1 0 1 2 3 4 -4 -3 -2 -1 0 1 2 3 4
Vg Vg
Accumulation occurs when the Ef is near the valence band.

Inversion occurs when the Ef is near the conduction band.

Common Approximations
3e-6
Qacc
Qinv = Cox (Vg-Vt) 2e-6
Depletion
1e-6
Qacc = Cox (Vg-Vfb)
Qsub 0 Inversion
-1e-6 Accumulation
-2e-6
-3e-6 Qinv
-4e-6
-4 -3 -2 -1 0 1 2 3 4
Vg

Quasi-static vs. Deep Depletion
4 3
Quasi-static 2 Quasi-static
3 Deep Depletion Deep Depletion
1
2
Vox
Vsub
0
1
-1
0
-2
-1 -3
-4 -3 -2 -1 0 1 2 3 4 -4 -3 -2 -1 0 1 2 3 4
Vg Vg
The previous analysis assumes minority carrier generation can
keep up with the dc bias (quasi-static).
However, deep depletion is typically seen for MOS capacitors
with ultra-thin oxides.
Calculating Capacitance
Total Device Capacitance: (

Ctot = (Csub ) + C
1 1
poly +C ox)
1 1
dQsub ( poly )
Substrate/Poly Capacitance: Csub ( poly ) =
dVsub ( poly )

Typical C-V Characteristics
1.2 1.2
1.0 1.0
0.8 0.8
C (F/cm )
C (F/cm )
17 -3
2
Nsub = 10 cm
2
14 -3
0.6 0.6 Nsub = 6x10 cm
LF LF
0.4 HF 0.4 HF
DD DD
0.2 0.2
0.0 0.0
-4 -3 -2 -1 0 1 2 3 4 -4 -3 -2 -1 0 1 2 3 4
Vg (V) Vg (V)
High frequency means that carriers can respond to the dc

signal but not the ac signal
Low Frequency means that carriers can respond to the dc
and ac signals.
Deep-depletion means Eric thatM.the carriers cannot respond to
Vogel June 11-12, 2005
Slideeither
No. 27 the dc or ac signals.
Electrical Characterization of MOS Devices
The previous analysis was based on a classical description

of charge in the semiconductor.
The large band bending in the semiconductor causes the

formation of a potential well.
This results in a quantization of the density of states and a

shifting of the carrier centroid away from the
semiconductor/insulator interface.
The most fundamental and computationally expensive

approach to handle these quantum-mechanical effects is to
solve the Schroedinger and Poisson equations together.
The splitting of energy levels and the shifting of the carriers

away from the interface leads to a decrease of the inversion
layer or accumulation layer charge density as a functio of the
surface potential as compared to classical simulation.
van Dort et al. pursued a more computationally efficient
approach of modeling these effects via an increase in the
effective bandgap of silicon.
Hareland et al. improved on van Dorts work by providing a
more detailed description of the bandgap widening based on a
comparison to a rigorous self-consistent Schroedinger-
Poisson solution.

13
E g = 5.92 10 8 si ( s )
23
4kTq
3.5
Classical
3.0
Quantum Mechanical 2.5

QM
C (F/cm )
Effects result in a drop of
2
2.0
the maximum capacitance 1.5
and a slight shift of the 1.0 Metal Gate
threshold voltage. Tox = 1.0 nm
0.5
Nsub = 2x1017cm-3
0.0
-4 -3 -2 -1 0 1 2 3 4
Vg (V)

C-V Parameter Extraction
Methodology
Oxide Thickness
Substrate Doping
Polysilicon Doping
Flatband Voltage
Oxide Charge and Workfunction

Parameter Extraction using Modeling
1.6
NCSU CVC program 1.4
fits experimental C-V 1.2
data using a model
C (F/cm )
1.0
2
that has the following 0.8 Vfb = -0.987 V
parameters: Vfb, Tox, Tox = 2.01 nm
0.6
Nsub, Npoly Nsub = 2.97x10
17
cm
-3
0.4
Measured Npoly = 1.61x10
20
cm
-3
NCSU CVC does not 0.2 Modeled

include interface 0.0
states. -4 -3 -2 -1 0 1 2 3
Vg (V)

Impact of Simulation Code
Simulators show a difference of 1.50
up to 20% in the calculated

accumulation capacitance. 1.25
This discrepancy leads to large

1.00
inaccuracies in the values of
C (F/cm )
2
dielectric thickness extracted 0.75
from C-V.
Possible reasons include: the 0.50
Tox = 2.0 nm
UTQuant [30]
use of approximations for

NIST
18 -3
Nsub = 10 cm Schred [32]
quantum effects vs. Schrdinger 0.25 Npoly = 1020 cm-3 NCSU [25]
NEMO [29]
n-channel, n-poly gate Berkeley [31]
equation, wave function 0.00
boundary conditions, and type of -3 -2 -1 0 1 2 3
carrier statistics. Vg (V)

Oxide Thickness Definitions
The Equivalent Oxide Thickness (EOT) is obtained from the

gate dielectric capacitance alone.
EOT must be determined from C-V measurements using a

fitting or extraction algorithm which includes QM effects,
polysilicon depletion, etc.
The Capacitance Equivalent Thickness (CET) is determined

by simply taking the SiO2xArea/Cmeas where Cmeas is the
measured capacitance in inversion or accumulation at some
defined voltage.

Oxide Thickness Definitions
EOT is the thickness of 2.0

SiO2 which would produce
the same capacitance as 1.5
that obtained from a high-K
EOT (nm)
dielectric.
1.0
In order to achieve a T(SiO2) = 1 nm, k(High-k) = 20

small EOT, the interfacial 0.5 T(SiO2) = 1 nm, k(High-k) = 40
thickness must be T(SiO2) = 0.5 nm, k(High-k) = 20
T(SiO2) = 0.5 nm, k(High-k) = 40
controlled. 0.0
0 1 2 3 4 5
Physical Thickness of High- Dielectric (nm)

Thickness Extraction
(
Ctot = (Csub ) + C
1 1
poly +C ox)
1 1
14
12 Ctot
The maximum capacitance in 10
Csub
Cox
accumulation is close to Cox.
C (F/cm )
8
2
6
4
The minimum capacitance is
2
due to the substrate 0
capacitance.
-4 -3 -2 -1 0 1 2 3 4
Vg (V)

Thickness Extraction
The capacitance in 1.75

accumulation (represented here 1.70
by CET) is not strongly impacted 1.65
by the substrate or polysilicon
CET (nm)
19 -3
1.60 Npoly = 10 cm
EOT = 1.0 nm
doping.
20 -3
1.55 Npoly = 10 cm
N-channel Device
Vg = -2 V Metal
1.50
The CET does depend strongly 1.45
on whether the gate is metal or 1.40

1015 1016 1017 1018 1019
polysilicon. Nsub (cm )
-3

Substrate Doping Extraction
The substrate doping strongly 1.2

impacts the minimum 1.0
capacitance but does not 0.8
C (F/cm )
strongly impact the maximum
2
0.6
capacitance in accumulation. 0.4
17 -3
Nsub = 10 cm
0.2 14 -3
Nsub = 6x10 cm
The minimum capacitance can 0.0
be used to determine substrate

-4 -3 -2 -1 0 1 2 3 4
doping. Vg (V)

Polysilicon Doping Extraction
3.0
Metal
The depletion of 2.5
polysilicon results in a large 2.0 Poly=1020 cm-3
C (F/cm )
drop of the capacitance.
2
1.5
The capacitance in 1.0

Tox = 1.0 nm
Poly=5x1019 cm-3
inversion can be used to 0.5 N = 2x1017cm-3

sub
determine polysilicon 0.0
doping. -4 -3 -2 -1 0 1 2 3 4
Vg (V)

Flatband Voltage Extraction
100
If the oxide capacitance
and substrate doping is 18
10
10-1
known, the flatband
17
10
Cfb/Cox
capacitance (and hence 10
16
Vfb) can be found. 10-2 10

15
-3
14 cm
0
=1
Na
There are numerous
sources of possible error 10-3
10-1 100 101
with this technique. Tox (nm)

Workfunction and Oxide Charge
Extraction
1
EOT
V fb = ms x ( x )dx
ox 0
1
EOT 1 EOT
V fb = ms x ( x )dx + x f 2bulk ( x )dx
ox 0 EOT 1
For a stacked dielectric

Extraction
1 1 2 R. Jha, et al., IEEE EDL 25, 420 (2004)
V fb = ms EOT
ox 2 f 1bulk

1
[Q + Q f 2 int f ( f 1bulk f 2bulk )EOT2 ]EOT
ox f 1int f
1 1
( )EOT Q f 1int f EOT2
ox 2 f 1bulk f 2 bulk 2

For a SiO2/high-k stack where EOT1(2) is the EOT of the high-
k (SiO2), Qf1(2)int are the charges at the high-k/SiO2 (SiO2/Si)
interface, f1(2)bulk are charges uniformly distributed within the
high-k (SiO2).
Extraction
R. Jha, et al., IEEE EDL 25, 420 (2004)
If interface charges dominate bulk charges:
V fb = ms
1
[Q ]EOT + [Q
1
EOT ]
ox f 1int f 1
ox f 2 int f
V fb = ms
1
[Q + Q f 2 int f ]EOT +
1
[Q EOT2 ]
ox f 1int f
ox f 1int f
The intercepts and slopes of Vfb vs. EOT with varying EOT1
and EOT2 can provide ms, Qf1intf, and Qf2intf.

Effective Workfunction
The vacuum work

function of a metal does
not necessarily equal the
effective work function of
the metal due to charge
transfer, defects, and
dipoles.

C-V Including Interface States
Theory
Interface State Capacitance
Interface State Density Extraction

Including Interface States
Qit is charge in the oxide that changes occupancy with bias.

Dita(d) is the density of acceptor(donor)-like interface states
Qsub (Vsub ) + Q poly (V poly ) + Qit (Vsub ) + Qox = 0
Qsub Qit (Vsub )

Vg = Vsub V poly + V fb
Cox Cox
Ec
qDita ( Et Ei )Fsa (( Et Ei ) (E f Ei ))
Qit (Vsub ) = dEt
Ev
+ qDitd ( Et Ei )Fsd (( Et Ei ) (E f Ei ))
(Et E f ) (Et E f )
1 1

Fsd (Et E f ) = 1 + 2 exp Fsa (Et E f ) = 1 + 0.25 exp
t t
At very high frequencies 0.35

(infinite), interface states do not 0.30
Capacitance (F/cm )
2
respond to the ac signal. 0.25
0.20
At very low frequencies Tox = 10 nm
0.15 Dit = 1012 cm-2eV-1
(quasi-static), interface states Ideal HF
HF with Dit
0.10
respond to the ac signal over QS with Dit
the entire bias range resulting 0.05

-3 -2 -1 0 1 2 3
in a capacitance. Vg (V)
(
Ctot = (Cit + Csub ) + C
1 1
poly +C ox)
1 1
Cit ,QS =
Qita + Qitd
Vsub
2.5

tan ( )P(V )dV
qDit Tox = 1.0 nm

1
Cit =
Capacitance (F/cm2)
2.0 Dit = 1012 cm-2eV-1
p
p s s
FET
= (c p )
1
1.5
p p s
Cap (102 Hz)
Cap (103 Hz)
1.0 Cap (104 Hz)
cp
p = capture cross section 0.5
Cap (105 Hz)
Cap (106 Hz)
vth
0.0
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Vg (V)
At intermediate frequencies, SRH theory must be used including

the effect of surface potential variation across the interfacial plane.
P(Vs) is the probability thatEric the band bending is V , ps is the free
M. Vogel June 11-12, 2005 s
carrier
Slide No. 48 concentration. Electrical Characterization of MOS Devices
Dit Extraction
4
EOT = 0.62 nm
Capacitance (F/cm )
3 Nsub = 4x1017 cm-3
Some have attempted
2
extracting Dit from the hump 2
Exp. Data (105 Hz)
Simulation:
observed in C-V using a 105 Hz (Dit profile 1)

s = 4 (kT/q)
quasi-static approach. 1 p = 10-14 cm2
Simulation:
Quasi-static (Dit profile 2)
Simulation: No Dit
Proper modeling requires 0
-2.0 -1.5 -1.0 -0.5 0.0
including the interface state Gate Voltage (V)
capacitance as a function of 10
frequency. 8 profile 1
profile 2
Dit (x10 cm eV )
-1
6
-2
4
12
Eric M. Vogel June-1.011-12, -0.5

2005 0.0 0.5 1.0

E - E (eV) t i
Dit Extraction on Thick Oxides
1) Low-High Frequency: A quasi-
static (QS) and a high-frequency 0.35
(HF) CV curve is measured and 0.30
Capacitance (F/cm )
2
interface state capacitance is
0.25
determined.
0.20
Tox = 10 nm
0.15
2) Terman: A HF CV curve is
12 -2 -1
Ideal HF Dit = 10 cm eV
HF with Dit
measured and compared to a 0.10
QS with Dit
theoretical ideal (no Dit) CV 0.05

-3 -2 -1 0 1 2 3
curve to obtain the amount of Vg (V)
voltage stretch-out.

Dit Extraction on Thin Dielectrics
1) Low-High Frequency: Quasi-
static measurements cannot be
performed on advanced
100
dielectrics due to leakage
current -1
Nit = 1012 cm-2
10
2) Terman: With decreasing

V (V)
11 -2
Nit = 10 cm
10-2
EOT (increasing dielectric
capacitance), the voltage 10-3
10
Nit = 10 cm
-2
shift (Qit/Cox) due to

charging of traps 10-4
(stretch-out) 0 2 4 6 8 10 12
becomes smaller. EOT (nm)

Dit Extraction
4
Dit can be extracted by
properly modeling the 17
Nsub = 4x10 cm
-3
Capacitance (F/cm )
frequency dependence of the 3 EOT = 0.62 nm
2
Dit profile 1
interface state capacitance. 5
F = 10 Hz
2
However the number of s = 4 (kT/q), p = 10-14 cm2

parameters that can provide 1
s = 1 (kT/q), p = 10-14 cm2
a reasonable fit is large. s = 4 (kT/q), p = 10
-17 2
cm
0
-2.0 -1.5 -1.0 -0.5 0.0
Gate Voltage (V)

CONDUCTANCE
Theory

Conductance Theory
rc ( x, t ) = c p p( x, t )nT f ( x, t ) (cm -3 s 1 ) Rate of hole capture
re ( x, t ) = e p nT [1 f ( x, t )] (cm -3 s 1 ) Rate of hole emission
i p ( x, t ) = q[rc ( x, t ) re ( x, t )] (A cm3 ) Hole recombination
current due to semi.
Applying small signal bulk traps
approximation
nT f 0 c p p0 ( x ) (mhos cm 3 )
q2
Gp = Hole conductance
kT due to semi. bulk
traps

Conductance Theory
[
G p = Cit (2 p ) ln 1 + ( p )
1 2
] Hole conductance due to
distribution of surface states
p is the hole capture cross - section
exp( Vsub )
1
p =
cp Na v is the thermal velocity
cp = p v
Including band bending fluctuations across the
interfacial plane with variance of banding bending, s
qD (2 )
2 1 2
Gp

= it
2 p
s
exp
2
2 s2
exp ( ) ln 1 (
+ ( p )2
)
exp 2 d

Conductance Theory
Cm Measured Capacitance
Gm Measured Conductance
Cc Capacitance corrected for Rs
Gc Conductance corrected for Rs
Gt DC Tunneling Conductance
Gac Gc corrected for Tunneling
Rs Series Resistance
Dit Interface State Density
Angular Frequency
Cx Oxide and Poly Capacitance
Gp Interface Trap Conductance
Conductance Parameter Extraction
1. Determine Rs (see previous section).

2. Determine Cox (see previous section).
3. Determine Gt = dIg(Vg)/dVg
4. Measure Cm(F) and Gm(F) for the gate biases
(trap energies) of interest.
5. Correct Cm and Gm for Rs using (see previous
section if inductance is an issue)
Cc =
Cm 2
CmCc Rs Gm
(1 Gm Rs ) + 2Cm2 Rs2 Gc = Gm Rs 1
2
6. Correct Gc for tunneling using

Gac = Gc Gt

16
Symbols: Experiment
7. Determine interface 14
Vg= -0.60 V
Lines: Model
trap conductance as
Gp/ (10 S/rad/cm )

2
12 tox = 2.0 nm
function of
10 Rs = 20
frequency for each -0.55 V -0.65 V
8
gate bias using -9 -0.70 V
6 -0.80 V
4
2
Gp C Gac2
= 2 x 0
Gc + 2 (C x Cc )2 102 103 104 105 106
Frequency (Hz)

7. Determine the peak 16

Symbols: Experiment
Vg= -0.60 V
frequency and G 14 Lines: Model
p
Gp/ (10 S/rad/cm )

associate
2
12 tox = 2.0 nm
fp
conductance for 10 Rs = 20
-0.55 V -0.65 V
each gate bias. 8
-9 -0.70 V
6 -0.80 V
8. Determine the 4
conductance at 5fp
2
or fp/5 for each gate
0
bias. 102 103 104 105 106
Gp Gp Frequency (Hz)
5 fp
fp 5
9. Determine s using 1.0

the following plot
and the previously 0.9
p
[<Gp>/]/[<Gpp>/]f
determined 0.8 High (5fp)
Gp Gp 0.7
5 fp
fp 5 0.6
Low (fp/5)
0.5
0.4
0 1 2 3 4 5
s (in units of kT/q)

0.4
0.3
10. Determine fd using
the following plot. fd(s) 0.2
0.1
0.0
0 1 2 3 4 5

2.7
2.6
2.5
11. Determine p using 2.4
p
the following plot. 2.3
2.2
2.1
2.0
1.9
0 1 2 3 4 5

7
12. Calculate the 6 ~2.0 nm RTO
interface state
cm eV )
-1
5
density and trap
-2
4
time constant using 2.0 nm, 20
10
3
Dit (10
2.2 nm, 20
2 1.8 nm, 20
Gp
Dit = [ f D ( s )q ]
1 2.0 nm, 10
1
fp
2.0 nm, 18
2.0 nm, 30
0
p -0.35 -0.30 -0.25 -0.20 -0.15
exp( Vsub )
1
p = = Et-Ei (eV)
p p vN a

Conductance of Ultra-thin Oxides
1e-7
Symbols: Experiment
Lines: Model
The very large 8e-8
tox = 1.4 nm
tunneling currents
Gp/ (S/rad/cm2)
Rs = 120
associated with ultra- 6e-8 Vg = -0.70
thin oxides begins to

4e-8
affect the conductance
Vg = -0.65
2e-8
Vg = -0.75
0
1e+3 1e+4 1e+5 1e+6
Frequency (Hz)

Sensitivity of Conductance with Rs
100
The expected 10-1
Gm (fp(Gp/)) (S/cm )
2
measured conductance
10-2 Gt = 0
was determined using
modeling for various 10-3 Rs, p
values of device 10-4 0 , 10-4 s
100 , 10-4 s
properties. -6
0 , 10 s
10-5 -6
100 , 10 s
-6
999 , 10 s
A smaller change in 10-6

109 1010 1011 1012 1013
expected Gm with Dit -2 -1
Dit (cm eV )
indicates less
sensitivity.

Sensitivity of Conductance with Gt
The expected 100

measured conductance
10-1 Rs = 0
was determined using
Gm (fp(Gp/)) (S/cm )
2
modeling for various 10-2
values of device 10-3

properties. 10-4
p , Gt
10-4 s, 0 S/cm2
10-4 s, 10-3 S/cm2
10-5 10-6 s, 0 S/cm2
A smaller change in 10-6 s, 10-3 S/cm2
10-6
expected Gm with Dit 109 1010 1011 1012 1013
indicates less Dit (cm-2eV-1)
sensitivity.

Interface State Time Constant
The time constant 1013 10-3
(capture cross-section)
ZrO2-SiN
of interface states can 1012 10-4
Dit (cm-2eV-1)
provide insights into its ZrO2-SiOx
(s)
physical nature. 1011
SiO2
10-5
In this case, the time Solid Symbols: D it

1010 10-6
constant for ZrO2 O pen Symbols:
stacks is observed to 109 10-7

be the same as SiO2. -0.30 -0.25 -0.20 -0.15 -0.10 -0.05
E - Ei (eV)

CHARGE PUMPING
Basic Theory
Including Spatial Distribution of Defects

2-Level Charge Pumping
tem,h tem,e
VH
G
Vth
S D
Va
Vfb
VL
Icp=qfANit
tr ton tf toff
Charge pumping measures electrically active defects in the gate

dielectric that are near the interface.
Controllable Parameters:
Amplitude, base voltage, rise time, fall time, on time, off time
Ec
E f ,inv
Eem,e
Eem ,h
E f ,acc
Ev
Vt
Vg
V fb tem,h tem2005
Eric M. Vogel June 11-12, ,e
Charge Pumping Theory
I cp ,max = fAg q Dit ( E )dE fAg q Dit E
E = Eem,e Eem,h
E = kT ln ( vn t )
(Ei E f ,inv ) kT
Eem,e i n i em ,e +e
E = kT ln ( vn t )
(E f ,acc Ei ) kT
Eem,h i p i em ,h + e
V fb Vt
tem,e ( h ) = t f (r )
Vg

Effect of Leakage on CP
1000
800
600
400
Leakage adds to the
Imeas (pA)
200
measured current and 0

-200 Due to leakage 2
10 Hz
is corrected by -400
-600
103 Hz
104 Hz
105 Hz
subtracting a low -800
-2.0 -1.5 -1.0 -0.5 0.0
frequency curve which Vbase (V)
is dominated by 1000
leakage. 800
Peak is proportional
to defect density
600
103 Hz
Icp (pA)
400 104 Hz
5
10 Hz
200
-200
Eric M. Vogel June-2.011-12,-1.5
-1.0 2005 -0.5 0.0
Vbase (V)
CP of Stacked Dielectrics
Defects distributed away from the interface can be measured

using charge pumping as a function of frequency.
C. E. Weintraub, E. M. Vogel, N. Yang, V. Misra, J. J. Wortman, J. J. Ganem,
and P. Masson, IEEE Trans. Elec. Dev., vol. 48, p. 2754, 2001.
Spatial Distribution of Defects
I cp , max = qAf N it (E , x ) F (E , x )dxdE

E ,x
(c +cp1+en+ep )Ton (c +cp2+en+ep )Toff
(e n1 1)(e n2 1)(cn2(cp1 +en) +cn1(cp2 +en) +(cp1 +cp2)ep)
F = (c +cp1+en+ep )Ton+(cn2+cp2+en+ep )Toff
(e n1 1)(cp1 +en +cn1 +ep)(cp2 +en +cn2 +ep)
Et Ei Ei Et
en ( Et ) = vth n ni e kT
, e p ( Et ) = vth p ni e kT
cn ( x ) = ns n ( x ) vth , c p ( x ) = ps p ( x ) vth
x
n / p ( x ) = n / p ( 0) e e/h
e / h = h
8 me / h e / h
where me/h and e/h are effective mass and barrier height for
electron/hole
Y. Maneglia and D. Bauza, J. Appl.
Eric Phys. 79,
M. Vogel Junepp.11-12,
4187 (1996)
2005
Slide No. 74 Electrical
F. P. Heiman and G. Warfield, Characterization of MOS
IEEE Trans. Electron Devices
Devices, 12, pp.167 (1965)
The abrupt change of F in
x direction can be used to
define the probed depth in
CP measurement.
1
0.75
F 0.5 0.5
0.25 0.25
0
0 0
5
-0.25
10
15 -0.5
20
ton=50ns, toff=500ns ton=500ns, toff=50ns
x ()
x ()
Et-Ei (eV) Et-Ei (eV)
Traps inside F=1 region have the highest probability to

be measured by CP method.
In this case, F has higher dependence on toff than ton due
to the larger value of Eric
p than n. June 11-12, 2005
M. Vogel
14
toff= 50 (ns)
13 ton= 50 (ns) xmax is defined at F
12 ton=toff equal to 0.5
When changing ton
xmax(Angstrom)
11 n=10 (cm )
-15 2
while keeping toff
10 p=10-13(cm2) constant, xmax will
be pinned.
9
The pinned xmax is
8
strongly dependent
7 on n/p.
6
10-2 10-1 100 101 102
ton/off (us)

88 11nm
nmSiO
SiO22++33nm
nmHfO
HfO22 2.4
2.4
1.5 2.2
77 1.5nm
nmSiO
SiO2 ++33nm
2 nmHfO
HfO2 2
2.2
2.0
2.0
66
cm-3))
cm-3))
1.8
-3
-3
1.8
1021 cm
1020 cm
55 1.6
1.6
21
20
1.4
1.4
NNt t((xx10
NNt t((xx10
44 1.2
1.2
33 1.0
1.0
0.8
0.8
22
0.6
0.6
11 0.4
0.4
0.2
0.2 0.4
0.4 0.6
0.6 0.8
0.8 1.0
1.0 1.2
1.2 1.4
1.4 1.6
1.6 1.8
1.8 2.0
2.0 2.2
2.2
Depth
Depth(nm)
(nm)
me/h = 0.1/0.1 m0 ,e/h = 1.3/3.3 (eV), e/h = 10-14/ 10-15 (cm2)

TUNNELING
Theory
SiO2
High-k Dielectric Stacks

Tunneling Theory
Methodologies used to calculate tunnel currents range from self-

consistent solutions of the Schroedinger and Poisson equations to
analytical formulations for potentials and transmission probability.
Self-consistent solutions are generally more accurate but require

extensive numerical computation and are time consuming.
Analytical formulations are known to be less accurate and less

physically based but are many times fit to experimental data by
choosing an insulator effective mass and/or barrier height.

Tunneling Theory - WKB
J tun = qnvPtun
2
J lr = q d kl f l ( E )(1 f r ( E ))T ( E )
3
(2 )
3

2
J rl = q d k r f r ( E )(1 f l ( E ))T ( E )
3
(2 )
3

q
J tot = J lr J rl = l
dE ( f ( E ) f ( E )) kt T ( E )
d 2
2 2 h
r

Tunneling Theory - WKB
E E fr
1 + exp
4qmt k BT k BT
J tot = ln T ( E )dE
h 3
E E fl
1 + exp k T
B
tox
T ( E ) = exp 2 k dx
k=
2m ox
(E Ec,ox ( x ))
0 h 2

WKB for SiO2
AFox2 B b3 2 (b qVox )3 2
JD = exp
qV 12 2
ox
F b
32

1 b ox

b
q3
A=
B 16 2 hs
J FN = AF exp
2
ox
ox
F
4 (2mox ) 3 2
12
B= s
3 qh
M. Depas, B. Vermeire, P. W. Mertens, R. L. Van Meirhaeghe, and M. M. Heyns, Sol. St.
Elecs. 38, 1465 (1994).

WKB for SiO2
10 8
10 8
10 7
10 7
10 6 2 nm (FN ) 2 nm - 10 nm (FN )
10 6
10 5
10 5
10 4
10 4
10 3 3 nm (FN ) 10 3
10 2 10 2 2 nm (D T)
10 1 2 nm (D T)
10 1
Jg (A/cm )
2
Jg (A/cm )
10 0
2
10 0
10 -1 10 -1
10 -2 7 nm (FN ) 10 -2
10 -3 10 -3 3 nm (D T)
10 -4 3 nm (D T) 10 -4
10 -5 10 -5
10 -6 10 -6
10 -7 10 nm (FN ) 10 -7
10 -8 10 -8
10 -9 10 -9
10 -10 10 -10
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -40 -30 -20 -10 0 10 20 30 40
V g (V ) E ox (M V /cm )
The current density is strongly dependent on thickness

when plotted as a function of voltage.
The Fowler-Nordheim current is dependent on electric field
(not thickness).

Tunneling in High-k Dielectrics
10
SiO2
9 Al2O3
Energy Gap (eV)

In general, higher 8
dielectric constant
materials have lower 7 ZrO2
bandgap. 6 Y2O3 HfO2
CeO2
5
Si3N4 Ta2O5
4 La2O3
TiO2
3
0 20 40 60 80
Relative Dielectric Constant
The tunnel current is

dependent on band
offsets not energy gap.
Although a material
may have a reasonable
energy gap, its band
offset to silicon may be
unfavorable.

10
SiO2
9 Al2O3
Energy Gap (eV)

In general, higher 8
dielectric constant
materials have lower 7 ZrO2
bandgap. 6 Y2O3 HfO2
CeO2
5
Si3N4 Ta2O5
4 La2O3
TiO2
3
0 20 40 60 80
Relative Dielectric Constant
The modeled tunneling

characteristics for ideal
dielectrics (no trap-assisted
current) provide an indication
of the trends expected when
modifying the dielectric
constant and barrier height
of a material.
E. M. Vogel et al.,
IEEE Trans. Elec. Dev. 45, 1350 (1998).
For a given EOT, the tunnel current

at low bias for a material with high
is much lower than SiO2 due to its larger
physical thickness.
However, it is more beneficial to

have a dielectric with barrier height
larger than the expected supply voltage,
than to have a larger but lower barrier
height.
E. M. Vogel et al.,
IEEE Trans.
Eric M. Vogel June 11-12, 2005 Elec. Dev. 45, 1350 (1998).
Stacked dielectrics show polarity

asymmetry due to the asymmetry of the
band diagram.
Increasing the interfacial layer

thickness results in a large increase
in the tunnel current.
The tunnel current is higher if the

electron first tunnels through the
higher barrier height material.
E. M. Vogel et al.,
Stacked dielectrics show polarity

asymmetry due to the asymmetry of
the band diagram.
Increasing the interfacial layer

thickness results in a large increase
in the tunnel current.
The tunnel current is higher if the

electron first tunnels through the
higher barrier height material.
E. M. Vogel et al.,

Electrical Characterization of MOS Devices With Advanced Gate Stacks

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Electrical Characterization of MOS Devices With Advanced Gate Stacks

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June 11-12

Semiconductor Electronics Division

Ultrathin and high- gate dielectrics present numerous

For FET Parameter Extraction see G. Ghibaudo lecture

Eric M. Vogel June 11-12, 2005

Eric M. Vogel June 11-12, 2005

Eric M. Vogel June 11-12, 2005

The ac voltage should be as small as possible

Assuming that the device capacitance is

Quasi-static C-V measurements generally

Eric M. Vogel June 11-12, 2005

spreadsheet which calculates

the relative measurement Output

Eric M. Vogel June 11-12, 2005

Capacitance Error (+/- %)

Eric M. Vogel June 11-12, 2005

Eric M. Vogel June 11-12, 2005

Eric M. Vogel June 11-12, 2005

500 F = 10 kHz 140 2

For thicker dielectrics, a simple For thinner or leakier

Series resistance alone 1000

frequency. 200 F=1MHz

Slide No. 13 Electrical Characterization of MOS Devices

Previous work provided methodologies to correct

Eric M. Vogel June 11-12, 2005

Potential and Charge Balance

Eric M. Vogel June 11-12, 2005

Potential Balance: Vg = Vsub V poly + Vox + Vbi

Charge Balance: Qsub (Vsub ) + Q poly (V poly ) + Qox = 0

To calculate C-V, we need to solve the above equations.

Vpoly is measured from the oxide-poly interface to the bulk of

Vg = Vsub V poly + Vox + Vbi Potential balance

Q poly (V poly ) = CoxVox Using Gauss Law

Eric M. Vogel June 11-12, 2005

= q ( p n + N d+ N a ) Classical Charge Density (cm-3) in

Eric M. Vogel June 11-12, 2005

To calculate Vbi set = 0 and find Ef in the bulk of the

Qsub (Vsub ) + Q poly (V poly ) + Qox = 0

To calculate Qsub(Vsub) or Qpoly(Vpoly), one must integrate from

Eric M. Vogel June 11-12, 2005

4Nv b E gap b Vsub E gap

Given: Vg, Nsub, Npoly, Cox, Qox

The above 2 equations can be solved for 2 unknowns: Vsub, Vpoly

Eric M. Vogel June 11-12, 2005

Accumulation occurs when the Ef is near the valence band.

Eric M. Vogel June 11-12, 2005

Eric M. Vogel June 11-12, 2005

Total Device Capacitance: (

Eric M. Vogel June 11-12, 2005

High frequency means that carriers can respond to the dc

The previous analysis was based on a classical description

The large band bending in the semiconductor causes the

This results in a quantization of the density of states and a

The most fundamental and computationally expensive

The splitting of energy levels and the shifting of the carriers

Quantum Mechanical 2.5

Eric M. Vogel June 11-12, 2005

Eric M. Vogel June 11-12, 2005

NCSU CVC does not 0.2 Modeled

Eric M. Vogel June 11-12, 2005

up to 20% in the calculated

This discrepancy leads to large

use of approximations for