A B C D E

1 1

Compal Confidential
2 2

Qiao Hong Schematics Document

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

3
2008-07-07 3

REV: 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 1 of 40
A B C D E
 A B C D E

Compal Confidential Diamondville SC

ZZZ1 ZZZ2 ZZZ FCBGA8
Model Name : KIZ00 437Pins
File Name : LA-4421P PCB PCB PCB 22x22mm
1
page 4,5 1
DAZ@ DAZ@

CRT Conn FSB Clock Generator

H_A#(3..31) H_D#(0..63)
400/533MHz CK505
page 19 page 12

RGB
Calistoga GSE Memory BUS(DDRII) DDRII-SO-DIMM
Thermal Sensor page 11
EMC1402 FCBGA998
1.8V DDRII 400/533
page 2 LCD Conn. LVDS
page 18 27x27mm
page 6,7,8,9,10
USB Port X1
DMI
page 28
X2 mode
USB USB Port X1
2

PCI-Express ICH7M HDA

2

page 28
BGA652
USB Port X1
31x31mm
page 28
page 15,16,17,18
New Card 10/100 Ethernet BlueTooth
JMB385 MINI Card x2 PATA
RTL8102EL page19
page 23
SSD CONTROL
page 19 page 24
SM223AC CMOS CAM
LPC BUS W/S 2G/4G/8G/16G
page22
SD/MMC/MS NAND Flash page 22
CONN page 23 Transfermer
3
page 24 3

Aralia Codec
ALC268-VB-GR
page 22
Power ON/OFF RJ45
DC/DC Interface
page 29 page 24
& LED CONN
page 26
3VALW/5VALW
page 33
ENE KBC SPI
DC IN KB926
page 31 page 25
1.5VS/0.9VS/
AMP & INT INT MIC HeadPhone &
BATT IN 2.5VS MIC Jack
page 37 page 35 Speaker
page 23
page 23
page 23
Int.KBD SPI ROM
page 27 page 25
CHARGER 1.8V/VCCP Touch Pad
page 32 page 27
4
page 34 4

CPU_CORE
page 36
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 2 of 40
A B C D E
 A B C D E

1 1

Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 100X b
EEPROM(24C16/02) 1010 000X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF

3
ICH7M SM Bus address 3

BOARD ID Table(Page 25) Device Address

ID BRD ID Ra Rb Vab Clock Generator 1101 001Xb

(SLG8SP556VTR)
0 R01 (EVT) NC 0 0V DDR DIMMA 1010 000Xb
1 R02 (DVT) 100K 8.2K 0.25V
2 R03 (PVT) 100K 18K 0.50V
3 R10A (MP) 100K NC 3.3V

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 3 of 40
A B C D E
 5 4 3 2 1

<6> H_A#[3..16]
<6> H_D#[0..15] H_D#[32..47] <6>
U5A U5B
H_A#3 P21 V19 H_ADS# +VCCP +VCCP H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# <6> D[0]# D[32]#
H_A#4 H20 Y19 H_BNR# H_BNR# <6> H_D#1 W10 R2 H_D#33
H_A#5 N20 A[4]# BNR# U21 H_BPRI# H_D#2 Y12 D[1]# D[33]# P1 H_D#34
H_BPRI# <6>

1
H_A#6 R20 A[5]# BPRI# H_D#3 AA14 D[2]# D[34]# N1 H_D#35
A[6]# D[3]# D[35]#

0
GROUP
ADDR

DATA GRP 0
H_A#7 J19 T21 H_DEFER# R201 R27 H_D#4 AA11 M2 H_D#36
H_A#8 A[7]# DEFER# H_DRDY# H_DEFER# <6> H_D#5 D[4]# D[36]# H_D#37
N19 T19 H_DRDY# <6> 56_0402_5% 330_0402_5% W12 P2
H_A#9 G20 A[8]# DRDY# Y18 H_DBSY# H_D#6 AA16 D[5]# D[37]# J3 H_D#38
A[9]# DBSY# H_DBSY# <6> D[6]# D[38]#
H_A#10 M19 H_D#7 Y10 N3 H_D#39

DATA GRP 2
2

2
H_A#11 H21 A[10]# T20 H_BR0# H_D#8 Y9 D[7]# D[39]# G3 H_D#40
A[11]# BR0# H_BR0# <6> D[8]# D[40]#
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]# D[9]# D[41]#

CONTROL
H_A#13 M20 F16 H_IERR# H_D#10 W15 N2 H_D#42
H_A#14 K19 A[13]# IERR# V16 H_INIT#_R R33 1 2 1K_0402_5% H_D#11 AA13 D[10]# D[42]# L2 H_D#43
D A[14]# INIT# H_INIT# <16> D[11]# D[43]# D
H_A#15 J20 H_D#12 Y16 M3 H_D#44
H_A#16 L21 A[15]# W20 H_LOCK# Close to CPU H_D#13 W13 D[12]# D[44]# J2 H_D#45
A[16]# LOCK# H_LOCK# <6> D[13]# D[45]#
H_ADSTB#0 K20 H_D#14 AA9 H1 H_D#46
<6> H_ADSTB#0 ADSTB[0]# D[14]# D[46]#
T5 H_AP0 D17 D15 H_RESET# H_RS#[0..2] <6> H_D#15 W9 J1 H_D#47
<6> H_REQ#[0..4] H_REQ#0 AP0 RESET# H_RS#0 H_RESET# <6> H_DSTBN#0 D[15]# D[47]# H_DSTBN#2
PAD N21 W18 Y14 K2
REQ[0]# RS[0]# <6> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <6>
H_REQ#1 J21 Y17 H_RS#1 H_DSTBP#0 Y15 K3 H_DSTBP#2
REQ[1]# RS[1]# <6> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <6>
H_REQ#2 G19 U20 H_RS#2 H_DINV#0 W16 L1 H_DINV#2
REQ[2]# RS[2]# <6> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <6>
H_REQ#3 P20 W19 H_TRDY# H_DP#0 V9 M4 H_DP#2
REQ[3]# TRDY# H_TRDY# <6> DP#0 DP#2
H_REQ#4 R19 T10 PAD PAD T15
REQ[4]# <6> H_D#[16..31] H_D#[48..63] <6>
<6> H_A#[17..31] AA17 H_HIT# H_HIT# <6> H_D#16 AA5 C2 H_D#48
H_A#17 C19 HIT# V20 H_HITM# H_D#17 Y8 D[16]# D[48]# G2 H_D#49
A[17]# HITM# H_HITM# <6> D[17]# D[49]#
H_A#18 F19 H_D#18 W3 F1 H_D#50
H_A#19 E21 A[18]# K17 H_D#19 U1 D[18]# D[50]# D3 H_D#51
H_A#20 A16 A[19]# BPM[0]# J18 H_D#20 W7 D[19]# D[51]# B4 H_D#52
A[20]# BPM[1]# D[20]# D[52]#

DATA GRP 1
H_A#21 D19 H15 H_D#21 W6 E1 H_D#53
H_A#22 C14 A[21]# BPM[2]# J15 H_D#22 Y7 D[21]# D[53]# A5 H_D#54
A[22]# BPM[3]# D[22]# D[54]#
ADDR GROUP 1
H_A#23 C18 K18 H_D#23 AA6 C3 H_D#55
H_A#24 C20 A[23]# PRDY# J16 PREQ# H_D#24 Y3 D[23]# D[55]# A6 H_D#56

DATA GRP 3
A[24]# PREQ# D[24]# D[56]#

XDP/ITP SIGNALS
H_A#25 E20 M17 ITP_TCK H_D#25 W2 F2 H_D#57
H_A#26 D20 A[25]# TCK N16 ITP_TDI H_D#26 V3 D[25]# D[57]# C6 H_D#58
H_A#27 B18 A[26]# TDI M16 ITP_TDO H_D#27 U2 D[26]# D[58]# B6 H_D#59
H_A#28 C15 A[27]# TDO L17 ITP_TMS H_D#28 T3 D[27]# D[59]# B3 H_D#60
H_A#29 B16 A[28]# TMS K16 ITP_TRST# H_D#29 AA8 D[28]# D[60]# C4 H_D#61
H_A#30 B17 A[29]# TRST# V15 H_D#30 V2 D[29]# D[61]# C7 H_D#62
H_A#31 C16 A[30]# BR1# H_D#31 W4 D[30]# D[62]# D2 H_D#63
H_A#32 A17 A[31]# G17 H_PROCHOT#_R 1 2 H_DSTBN#1 Y4 D[31]# D[63]# E2 H_DSTBN#3
A[32]# PROCHOT# H_PROCHOT# <36> <6> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <6>
H_A#33 B14 E4 H_THERMDA R202 22_0402_5% H_DSTBP#1 Y5 F3 H_DSTBP#3
THERM

A[33]# THRMDA <6> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <6>

H_A#34 B15 E5 H_THERMDC Close to CPU H_DINV#1 Y6 C5 H_DINV#3
A[34]# THRMDC <6> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <6>
H_A#35 A14 H_DP#1 R4 D4 H_DP#3
H_ADSTB#1 B19 A[35]# H17 H_THERMTRIP# T13 PAD DP#1 DP#3 PAD T12
<6> H_ADSTB#1 ADSTB[1]# THERMTRIP# H_THERMTRIP# <6,16>
H_AP1 M18 +CPU_GTLREF A7 T1 COMP0 1 R57 2 27.4_0402_1%
T7 PAD AP1 R240 1 @ 2 1K_0402_5% ACLKPH U5 GTLREF COMP[0] T2 COMP1 1 R58 2 54.9_0402_1%
C H_A20M# U18 R239 1 @ 2 1K_0402_5% DCLKPH V5 ACLKPH COMP[1] F20 COMP2 2 R208 1 27.4_0402_1% C
<16> H_A20M# A20M# DCLKPH COMP[2]
H_FERR# T16 V11 CLK_CPU_BCLK T17 F21 COMP3 2 R209 1 54.9_0402_1%
<16> H_FERR# FERR# BCLK[0] CLK_CPU_BCLK <12> BINIT# COMP[3]
H_IGNNE# J4 V12 CLK_CPU_BCLK# R6 MISC
<16> H_IGNNE# H_STPCLK# IGNNE# BCLK[1] CLK_CPU_BCLK# <12> EDM H_DPRSTP#
R16 +CPU_EXTBGREF M6 R18 H_DPRSTP# <16,36>
<16> H_STPCLK# H_INTR T15 STPCLK# N15 EXTBGREF DPRSTP# R17 H_DPSLP#
H_DPSLP# <16>
H CLK

<16> H_INTR H_NMI LINT0 FORCEPR# DPSLP# H_DPWR#

<16> H_NMI R15 N6 U4 H_DPWR# <6>
H_SMI# LINT1 HFPLL DPWR# H_PWRGOOD
U17 P17 V17 H_PWRGOOD <16>
<16> H_SMI# SMI# MCERR# PWRGOOD H_CPUSLP#
T6 N18 H_CPUSLP# <6>
D6 C21 CPU_BSEL0 J6 RSP# SLP# A13
NC1 RSVD3 <12> CPU_BSEL0 CPU_BSEL1 BSEL[0] CORE_DET
G6 C1 H5 B7 +CPU_CMREF
NC

NC2 RSVD2 <12> CPU_BSEL1 BSEL[1] CMREF[1]

H6 A3 CPU_BSEL2 G5
NC3 RSVD1 <12> CPU_BSEL2 BSEL[2]
K4
K5 NC4 AU80586GE025512_FCBGA437
M15 NC5
L16 NC6
NC7
Layout note:
AU80586GE025512_FCBGA437 COMP0,2 connect with Zo=27.4ohm +/-15%, make
. trace length shorter than 0.5"
+VCCP +VCCP +VCCP +VCCP
COMP1,3 connect with Zo=55ohm +/-15%, make
trace length shorter than0.5"
1

1
R34 1 2 1K_0402_5% H_A#32
R30 1 2 1K_0402_5% H_A#33
R31 1 2 1K_0402_5% H_A#34 R47 R234 R51
R29 1 2 1K_0402_5% H_A#35 +CPU_GTLREF 1K_0402_1% +CPU_EXTBGREF 1K_0402_1% +CPU_CMREF 1K_0402_1%
2

2
+VCCP
1

1
R28 1 2 1K_0402_5% H_A20M# 1 1 1
R32 1 2 1K_0402_5% H_IGNNE#
B B
C62 R48 C342 R238 C65 R49
0.1U_0402_16V4Z~D 2K_0402_1% 1U_0402_6.3V4Z~D 2K_0402_1% 0.1U_0402_16V4Z~D 2K_0402_1%
2 2 2
2

2
+VCCP
This shall place near CPU
R200 1 2 56_0402_5% ITP_TMS
Close to CPU pin
R198 1 2 56_0402_5% ITP_TDI within 500mils. Close to CPU pin Close to CPU pin
R206 1
R199 1
2 56_0402_5% PREQ#
ITP_TDO Zo=55ohm within 500mils. within 500mils. H_THERMDA, H_THERMDC routing together.
2 56_0402_5%
Zo=55ohm Zo=55ohm Trace width / Spacing = 10 / 10 mil
R213 1 2 56_0402_5% ITP_TCK
R218 1 2 56_0402_5% ITP_TRST#

+3VS
CPU THERMAL SENSOR
1

0.1U_0402_16V4Z~D
C352
U17
2

1 8 EC_SMB_CK2 EC_SMB_CK2 <25>

VDD SMCLK
H_THERMDA 2 7 EC_SMB_DA2
DP SMDATA EC_SMB_DA2 <25>
C351
1 2 H_THERMDC 3 6 2 R304 1
DN ALERT# +3VS
2200P_0402_50V7K 10K_0402_5%
4 5
THERM# GND
A A

EMC1402-1-ACZL-TR_MSOP8
Address:100_1100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Diamondville(1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 4 of 40
5 4 3 2 1
 5 4 3 2 1

U5D U5C +VCCP

A2 N5
A4 VSS1 VSS162 N7 C9 0.1U_0402_10V7K~D 1U_0402_6.3V6K~D
VSS2 VSS161 VTT1
A8 N9 D9 1
VSS4 VSS160 +VCCP VTT2
A15 N13 E9 1 1 1 1
VSS5 VSS159 VTT3 C295 C307 C337 C341 C57 +
A18 N17 F8
VSS6 VSS158 VTT4
A19 P3 F9
VSS7 VSS157 VTT5
A20 P4 G8
VSS8 VSS156 VTT6 2 2 2 2 2
B1 P5 V10 G14
VSS9 VSS155 VCCF VTT7
B2 P6 H8
VSS10 VSS154 VTT8 0.1U_0402_10V7K~D 1U_0402_6.3V6K~D 220U_B2_2.5VM_R35
D B5 P7 A9 H14 D
VSS11 VSS153 VCCQ1 VTT9
B8 P9 B9 J8 PLACE IN CAVITY
VSS12 VSS152 VCCQ2 VTT10
B13 P13 J14
VSS13 VSS151 VTT11
B20 P15 K8
VSS14 VSS149 VTT12
B21 P16 K14
C8 VSS15 VSS148 P18 VTT13 L8
C17 VSS16 VSS147 P19 VTT14 L14
VSS17 VSS146 VTT15
D1 R1 M8
VSS18 VSS145 +CPU_CORE VTT16
D5 R5 M14
D8 VSS19 VSS144 R7 VTT17 N8
VSS20 VSS143 VTT18
D14 R9 N14
VSS21 VSS142 VTT19
D18 R13 P8
D21 VSS22 VSS141 R21 A10 VTT20 P14
VSS23 VSS140 VCCP1 VTT21
E3 T4 A11 R8
VSS24 VSS139 VCCP2 VTT22
E6 T5 A12 R14
E7 VSS25 VSS138 T7 B10 VCCP3 VTT23 T8
VSS26 VSS137 VCCP4 VTT24
E8 T9 B11 T14
VSS27 VSS136 VCCP5 VTT25
E15 T10 B12 U8
E16 VSS28 VSS135 T11 C10 VCCP6 VTT26 U9
VSS29 VSS134 VCCP7 VTT27
E19 T12 C11 U10
VSS30 VSS133 VCCP8 VTT28
F4 T13 C12 U11
F5 VSS31 VSS132 T18 D10 VCCP9 VTT29 U12
F6 VSS32 VSS131 U3 D11 VCCP10 VTT30 U13
F7 VSS33 VSS130 U6 D12 VCCP11 VTT31 U14
VSS34 VSS129 VCCP12 VTT32
F17 U7 E10
VSS35 VSS128 VCCP13
F18 U15 E11
VSS36 VSS127 VCCP14
G1 U16 E12
VSS37 VSS126 VCCP15
G4 U19 F10 F14
VSS38 VSS125 VCCP16 VCCPC64
G7 V1 F11 F13
C VSS39 VSS124 VCCP17 VCCPC63 C
G9 V4 F12 E14
VSS41 VSS123 VCCP18 VCCPC62
G13 V6 G10 E13
VSS42 VSS122 VCCP19 VCCPC61
G21 V7 G11
H3 VSS45 VSS121 V8 G12 VCCP20
H4 VSS46 VSS120 V13 H10 VCCP21
VSS48 VSS119 VCCP22
H7 V14 H11
H9 VSS49 VSS118 V18 H12 VCCP23
H13 VSS51 VSS117 V21 J10 VCCP24
VSS52 VSS116 VCCP25
H16 W1 J11
H18 VSS53 VSS115 W5 J12 VCCP26
H19 VSS54 VSS114 W8 K10 VCCP27 +1.5VS
VSS55 VSS113 VCCP28
J5 W11 K11
J7 VSS56 VSS112 W14 K12 VCCP29
VSS57 VSS111 VCCP30 130mA
J9 W17 L10 D7 +1.5VS
VSS58 VSS110 VCCP31 VCCA
J13 W21 L11 1
VSS59 VSS109 VCCP32 C338
J17 Y1 L12
VSS60 VSS108 VCCP33 CPU_VID0 0.1U_0402_10V7K~D
K1 Y2 M10 F15
VSS61 VSS107 VCCP34 VID[0] CPU_VID1 CPU_VID0 <36>
K6 Y20 M11 D16 CPU_VID1 <36>
VSS62 VSS106 VCCP35 VID[1] CPU_VID2 2 +CPU_CORE
K7 Y21 M12 E18 CPU_VID2 <36>
VSS63 VSS105 VCCP36 VID[2] CPU_VID3
K9 AA2 N10 G15 CPU_VID3 <36>

1
VSS64 VSS104 VCCP37 VID[3] CPU_VID4
K13 AA3 N11 G16 CPU_VID4 <36>
VSS65 VSS103 VCCP38 VID[4] CPU_VID5 R221
K15 AA4 N12 E17 CPU_VID5 <36>
VSS66 VSS102 VCCP39 VID[5] CPU_VID6
K21 AA7 P10 G18 CPU_VID6 <36>
VSS67 VSS101 VCCP40 VID[6] 100_0402_1%
L3 AA10 P11
L4 VSS68 VSS100 AA12 P12 VCCP41

2
VSS69 VSS99 VCCP42 VCCSENSE
L5 AA15 R10 C13 VCCSENSE <36> Length match within 25 mils
L6 VSS70 VSS98 AA18 R11 VCCP43 VCCSENSE
VSS71 VSS97 VCCP44
L7
VSS72 VSS96
AA19 R12
VCCP45 The trace space 7 mils,
L9 AA20 D13 VSSSENSE VSSSENSE <36>
B
L13 VSS73 VSS95 VSSSENSE Zo=27.4ohm B

1
L15 VSS74 AU80586GE025512_FCBGA437
VSS75 R220
L18
L19 VSS76
VSS77 100_0402_1%
M1
VSS78
M5

2
VSS79
M7
VSS80
M9
VSS81 +CPU_CORE +CPU_CORE
M13
VSS82
M21
VSS83 PLACE IN CAVITY 2 x 330uF(9mohm/2)
N4
VSS84 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + C51 + C331
C308 C309 C310 C311 C312 C313 C314 C320 C321 C322 C323 C324 C326 C327 C325 C315
AU80586GE025512_FCBGA437 330U 2.5V Y 330U 2.5V Y
2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D

10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D

1 1 1 1 1 1 1 1 1 1 1 1
C298 C299 C300 C301 C302 C46 C304 C303 C335 C47 C328 C334

2 2 2 2 2 2 2 2 2 2 2 2
A A
10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Diamondville(2/2)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 5 of 40
5 4 3 2 1
 5 4 3 2 1

<4> H_D#[0..63] H_A#[3..31] <4>

U1A U1B
H_D#0 C4 F8 H_A#3
H_D#1 F6 H_D#_0 H_A#_3 D12 H_A#4 DMI_TXN0 Y29 C18 MCH_CLKSEL0
H_D#2 H_D#_1 H_A#_4 H_A#5 <17> DMI_TXN0 DMI_TXN1 DMI_RXN_0 CFG_0 MCH_CLKSEL1 MCH_CLKSEL0 <12>
H9 C13 <17> DMI_TXN1 Y32 E18 MCH_CLKSEL1 <12>
H_D#3 H6 H_D#_2 H_A#_5 A8 H_A#6 DMI_TXP0 Y28 DMI_RXN_1 CFG_1 G20 MCH_CLKSEL2
H_D#_3 H_A#_6 <17> DMI_TXP0 DMI_RXP_0 CFG_2 MCH_CLKSEL2 <12>
H_D#4 F7 E13 H_A#7 DMI_TXP1 Y31 G18 CFG3
H_D#_4 H_A#_7 <17> DMI_TXP1 DMI_RXP_1 CFG_3
H_D#5 E3 E12 H_A#8 J20 CFG5 1 2
D H_D#6 C2 H_D#_5 H_A#_8 J12 H_A#9 DMI_RXN0 V28 CFG_5 J18 CFG6 R181 2.2K_0402_5% D
H_D#7 H_D#_6 H_A#_9 H_A#10 <17> DMI_RXN0 DMI_RXN1 DMI_TXN_0 CFG_6
C3 B13 <17> DMI_RXN1
V31
H_D#8 K9 H_D#_7 H_A#_10 A13 H_A#11 DMI_RXP0 V29 DMI_TXN_1
H_D#_8 H_A#_11 <17> DMI_RXP0 DMI_TXP_0
H_D#9 F5 G13 H_A#12 DMI_RXP1 V32
H_D#10 H_D#_9 H_A#_12 H_A#13 <17> DMI_RXP1 DMI_TXP_1
J7 A12

DMI
H_D#11 K7 H_D#_10 H_A#_13 D14 H_A#14
H_D#12 H8 H_D#_11 H_A#_14 F14 H_A#15
H_D#13 E5 H_D#_12 H_A#_15 J13 H_A#16 M_CLK_DDR0 AF33 K32
H_D#_13 H_A#_16 <11> M_CLK_DDR0 SM_CK_0 RESERVED1
H_D#14 K8 E17 H_A#17 M_CLK_DDR1 AG1 K31
H_D#_14 H_A#_17 <11> M_CLK_DDR1 SM_CK_1 RESERVED2
H_D#15 J8 H15 H_A#18 C17
H_D#16 J2 H_D#_15 H_A#_18 G15 H_A#19 AJ1 RESERVED7 F18
H_D#17 J3 H_D#_16 H_A#_19 G14 H_A#20 AM30 SM_CK_2 RESERVED8 A3
H_D#18 N1 H_D#_17 H_A#_20 A15 H_A#21 SM_CK_3 RESERVED9

CFG/RSVD
H_D#19 M5 H_D#_18 H_A#_21 B18 H_A#22 M_CLK_DDR#0 AG33
H_D#_19 H_A#_22 <11> M_CLK_DDR#0 SM_CK#_0
H_D#20 K5 B15 H_A#23 M_CLK_DDR#1 AF1
H_D#_20 H_A#_23 <11> M_CLK_DDR#1 SM_CK#_1
H_D#21 J5 E14 H_A#24
H_D#22 H3 H_D#_21 H_A#_24 H13 H_A#25 AK1
H_D#23 J4 H_D#_22 H_A#_25 C14 H_A#26 AN30 SM_CK#_2
H_D#24 H_D#_23 H_A#_26 H_A#27 SM_CK#_3
N3 A17
H_D#_24 H_A#_27

DDR2 MUXING
H_D#25 M4 E15 H_A#28 DDR_CKE0 AN21
H_D#_25 H_A#_28 <11> DDR_CKE0 SM_CKE_0
H_D#26 M3 H17 H_A#29 DDR_CKE1 AN22
H_D#27 H_D#_26 H_A#_29 H_A#30 <11> DDR_CKE1 SM_CKE_1
N8 D17 AF26
H_D#28 N6 H_D#_27 H_A#_30 G17 H_A#31 AF25 SM_CKE_2
H_D#29 K3 H_D#_28 H_A#_31 SM_CKE_3
H_D#30 N9 H_D#_29 DDR_CS0# AG14
H_D#_30 <11> DDR_CS0# SM_CS#_0
H_D#31 M1 F10 H_ADS# DDR_CS1# AF12
H_D#32 H_D#_31 H_ADS# H_ADSTB#0 H_ADS# <4> <11> DDR_CS1# SM_CS#_1
V8 C12 H_ADSTB#0 <4> AK14
H_D#33 V9 H_D#_32 H_ADSTB#_0 H16 H_ADSTB#1 AH12 SM_CS#_2
H_D#_33 H_ADSTB#_1 H_ADSTB#1 <4> SM_CS#_3
H_D#34 R6 E2 +H_VREF
H_D#35 T8 H_D#_34 H_VREF0 B9 H_BNR# AJ21
H_D#36 H_D#_35 H_BNR# H_BPRI# H_BNR# <4> SM_OCDCOMP_0
HOST

R2 C7 H_BPRI# <4> AF11 E31 MCH_ICH_SYNC# <15>

H_D#37 N5 H_D#_36 H_BPRI# G8 H_BR0# SM_OCDCOMP_1 PM_ICHSYNC# G21
C H_D#_37 H_BREQ0# H_BR0# <4> PM_BMBUSY# PM_BMBUSY# <17> C

PM
H_D#38 N2 B10 H_RESET# M_ODT0 AE12 F26 PM_EXTTS#0
H_D#_38 H_CPURST# H_RESET# <4> +1.8V <11> M_ODT0 SM_ODT_0 PM_EXTTS#_0 PM_EXTTS#0 <11>
H_D#39 R5 E1 +H_VREF M_ODT1 AF14 H26 PM_EXTTS#1 2 1
H_D#40 H_D#_39 H_VREF1 <11> M_ODT1 SM_ODT_1 PM_EXTTS#_1 PM_DPRSLPVR <17,36>
U7 AJ14 J15 R203 0_0402_5%
H_D#41 R8 H_D#_40 AA6 CLK_MCH_BCLK# AJ12 SM_ODT_2 THRMTRIP# AB29 H_THERMTRIP#
H_D#_41 HCLKN CLK_MCH_BCLK# <12> SM_ODT_3 PWROK H_THERMTRIP# <4,16>
H_D#42 T4 AA5 CLK_MCH_BCLK W27 ICH_POK
H_D#43 H_D#_42 HCLKP H_DBSY# CLK_MCH_BCLK <12> SMRCOMPN RSTIN# PLTRST_R# 1 ICH_POK <17,25>
T7 C10 R232 1 2 80.6_0402_1% AN12 2
H_D#_43 H_DBSY# H_DBSY# <4> SM_RCOMPN PLTRST# <15,17,19,22,23,24>
H_D#44 R3 C6 H_DEFER# 1 2 SMRCOMPP AN14 R211 100_0402_5%
H_D#_44 H_DEFER# H_DEFER# <4> SM_RCOMPP
H_D#45 T5 H5 H_DINV#0 R228 80.6_0402_1% AA33
H_D#46 H_D#_45 H_DINV#_0 H_DINV#1 H_DINV#0 <4> SM_VREF_0

CLK
V6 J6 H_DINV#1 <4> +DIMM_VREF AE1 A27 CLK_MCH_DREFCLK# <12>
H_D#47 V3 H_D#_46 H_DINV#_1 T9 H_DINV#2 SM_VREF_1 D_REFCLKN A26
H_D#_47 H_DINV#_2 H_DINV#2 <4> 10uA D_REFCLKP CLK_MCH_DREFCLK <12>
H_D#48 W2 U6 H_DINV#3 1 J33
H_D#49 H_D#_48 H_DINV#_3 H_DPWR# H_DINV#3 <4> D_REFSSCLKN MCH_SSCDREFCLK# <12>
W1 G7 Layout Note: H33

0.1U_0402_16V4Z~D
H_D#_49 H_DPWR# H_DPWR# <4> D_REFSSCLKP MCH_SSCDREFCLK <12>
H_D#50 V2 E6 H_DRDY# J22

C53
H_D#51 H_D#_50 H_DRDY# H_DSTBN#0 H_DRDY# <4> +DIMM_VREF trace CLKREQ# MCH_CLKREQ# <12>
W4 F3
H_D#52 W7 H_D#_51 H_DSTBN#_0 M8 H_DSTBN#1 2 width and spacing
H_D#53 W5 H_D#_52 H_DSTBN#_1 T1 H_DSTBN#2 is 20/20. Calis toga-GSE_FCBGA998
H_D#54 H_D#_53 H_DSTBN#_2 H_DSTBN#3
V5 AA3
+VCCP H_D#55 AB4 H_D#_54 H_DSTBN#_3 F4 H_DSTBP#0
H_D#_55 H_DSTBP#_0 H_DSTBN#[0..3] <4>
H_D#56 AB8 M7 H_DSTBP#1
H_D#57 W8 H_D#_56 H_DSTBP#_1 T2 H_DSTBP#2
H_D#58 AA9 H_D#_57 H_DSTBP#_2 AB3 H_DSTBP#3
H_D#59 AA8 H_D#_58 H_DSTBP#_3
H_D#_59 H_DSTBP#[0..3] <4>
H_D#60 AB1
Strap Pin Table
1

H_D#_60
54.9_0402_1%

54.9_0402_1%

H_D#61 AB7
H_D#62 H_D#_61 H_HIT#
R6

AA2 C8
R175

H_D#63 H_D#_62 H_HIT# H_HITM# H_HIT# <4>

AB5 B4 H_HITM# <4> Low = DMI x 2 *
H_D#_63 H_HITM# H_LOCK#
C5 H_LOCK# <4> CFG5
H_LOCK# G9 H_REQ#0 High = DMI x 4
2

H_REQ#_0 E9 H_REQ#1
H_XRCOMP A10 H_REQ#_1 G12 H_REQ#2
H_XSCOMP A6 H_XRCOMP H_REQ#_2 B8 H_REQ#3
+H_SWNG0 C15 H_XSCOMP H_REQ#_3 F12 H_REQ#4
B H_YRCOMP J1 H_XSWING H_REQ#_4 A5 H_RS#0 B
H_YSCOMP H_YRCOMP H_RS#_0 H_RS#1 H_REQ#[0..4] <4>
K1 B6
+H_SWNG1 H1 H_YSCOMP H_RS#_1 G10 H_RS#2
H_YSWING H_RS#_2 E8 H_CPUSLP#
H_SLPCPU# H_RS#[0..2] <4>
E10 H_TRDY#
H_TRDY#
H_CPUSLP# <4>
H_TRDY# <4>
1

1
24.9_0402_1%

24.9_0402_1%

Calis toga-GSE_FCBGA998
R7

R182
2

+3VS
Layout Note: PM_EXTTS#0 1 2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / R187 10K_0402_5%
H_SWNG1 trace width and spacing is 10/20. PM_EXTTS#1 1 @ 2
R188 10K_0402_5%

+VCCP +VCCP

+VCCP
1

1
221_0402_1%~D

221_0402_1%~D
1
100_0402_1%

R167

R180
R176

A A
2

+H_SWNG0 +H_SWNG1
2

+H_VREF
1

1
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 1
1

100_0402_1%

100_0402_1%
0.1U_0402_16V4Z~D

R166

R178

1
200_0402_1%

C50 be placed <100mils

R174

C243

C240

C251

from GMCH pin 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2

2 2006/08/18 2007/8/18 Title

Issued Date Deciphered Date
2

Calistoga(1/5)-GTL/DMI/DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 6 of 40
5 4 3 2 1
 5 4 3 2 1

D U1C D
DDR_A_D[0..63] <11>
DDR_A_BS0 AK12 AC31 DDR_A_D0
<11> DDR_A_BS0 DDR_A_BS1 SA_BS_0 SA_DQ_0 DDR_A_D1
<11> DDR_A_BS1 AH11 AB28
DDR_A_BS2 AG17 SA_BS_1 SA_DQ_1 AE33 DDR_A_D2
<11> DDR_A_BS2 SA_BS_2 SA_DQ_2 DDR_A_D3
AF32
<11> DDR_A_DM[0..7] DDR_A_DM0 SA_DQ_3 DDR_A_D4
AB30 AC33
DDR_A_DM1 AL31 SA_DM_0 SA_DQ_4 AB32 DDR_A_D5
DDR_A_DM2 SA_DM_1 SA_DQ_5 DDR_A_D6
AF30 AB31
DDR_A_DM3 SA_DM_2 SA_DQ_6 DDR_A_D7
AK26 AE31
DDR_A_DM4 SA_DM_3 SA_DQ_7 DDR_A_D8
AL9 AH31
DDR_A_DM5 AG7 SA_DM_4 SA_DQ_8 AK31 DDR_A_D9
DDR_A_DM6 SA_DM_5 SA_DQ_9 DDR_A_D10
AK5 AL28
DDR_A_DM7 SA_DM_6 SA_DQ_10 DDR_A_D11
AH3 AK27
SA_DM_7 SA_DQ_11 AH30 DDR_A_D12
<11> DDR_A_DQS[0..7] SA_DQ_12
DDR_A_DQS0 AC28 AL32 DDR_A_D13
DDR_A_DQS1 SA_DQS_0 SA_DQ_13 DDR_A_D14
AJ30 AJ28
DDR_A_DQS2 AK33 SA_DQS_1 SA_DQ_14 AJ27 DDR_A_D15
DDR_A_DQS3 SA_DQS_2 SA_DQ_15 DDR_A_D16
AL25 AH32
DDR_A_DQS4 SA_DQS_3 SA_DQ_16 DDR_A_D17
AN9 AF31
DDR_A_DQS5 SA_DQS_4 SA_DQ_17 DDR_A_D18
AH8 AH27
DDR_A_DQS6 AM2 SA_DQS_5 SA_DQ_18 AF28 DDR_A_D19
DDR_A_DQS7 SA_DQS_6 SA_DQ_19 DDR_A_D20
AE3 AJ32
SA_DQS_7 SA_DQ_20 DDR_A_D21
<11> DDR_A_DQS#[0..7] AG31
DDR_A_DQS#0 AC29 SA_DQ_21 AG28 DDR_A_D22
DDR_A_DQS#1 SA_DQS#_0 SA_DQ_22 DDR_A_D23
AK30 AG27
DDR_A_DQS#2 SA_DQS#_1 SA_DQ_23 DDR_A_D24
AJ33 AN27
DDR_A_DQS#3 AM25 SA_DQS#_2 SA_DQ_24 AM26 DDR_A_D25

DDR2 SYSTEM MEMORY

DDR_A_DQS#4 SA_DQS#_3 SA_DQ_25 DDR_A_D26
AN8 AJ26
DDR_A_DQS#5 SA_DQS#_4 SA_DQ_26 DDR_A_D27
AJ8 AJ25
DDR_A_DQS#6 SA_DQS#_5 SA_DQ_27 DDR_A_D28
AM3 AL27
C DDR_A_DQS#7 AE2 SA_DQS#_6 SA_DQ_28 AN26 DDR_A_D29 C
SA_DQS#_7 SA_DQ_29 DDR_A_D30
AH25
<11> DDR_A_MA[0..13] DDR_A_MA0 SA_DQ_30 DDR_A_D31
AJ15 AG26
DDR_A_MA1 AM17 SA_MA_0 SA_DQ_31 AM12 DDR_A_D32
DDR_A_MA2 SA_MA_1 SA_DQ_32 DDR_A_D33
AM15 AL11
DDR_A_MA3 SA_MA_2 SA_DQ_33 DDR_A_D34
AH15 AH9
DDR_A_MA4 AK15 SA_MA_3 SA_DQ_34 AK9 DDR_A_D35
DDR_A_MA5 SA_MA_4 SA_DQ_35 DDR_A_D36
AN15 AM11
DDR_A_MA6 SA_MA_5 SA_DQ_36 DDR_A_D37
AJ18 AK11
DDR_A_MA7 SA_MA_6 SA_DQ_37 DDR_A_D38
AF19 AM8
DDR_A_MA8 AN17 SA_MA_7 SA_DQ_38 AK8 DDR_A_D39
DDR_A_MA9 SA_MA_8 SA_DQ_39 DDR_A_D40
AL17 AG9
DDR_A_MA10 SA_MA_9 SA_DQ_40 DDR_A_D41
AG16 AF9
DDR_A_MA11 AL18 SA_MA_10 SA_DQ_41 AF8 DDR_A_D42
DDR_A_MA12 SA_MA_11 SA_DQ_42 DDR_A_D43
AG18 AK6
DDR_A_MA13 SA_MA_12 SA_DQ_43 DDR_A_D44
AL14 AF7
SA_MA_13 SA_DQ_44 AG11 DDR_A_D45
DDR_A_CAS# SA_DQ_45 DDR_A_D46
AJ17 AJ6
<11> DDR_A_CAS# DDR_A_RAS# SA_CAS# SA_DQ_46 DDR_A_D47
<11> DDR_A_RAS# AK18 AH6
SA_RCVENIN# SA_RAS# SA_DQ_47 DDR_A_D48
AN28 AN6
T9 PAD SA_RCVENOUT# AM28 SA_RCVENIN# SA_DQ_48 AM6 DDR_A_D49
T8 PAD DDR_A_WE# SA_RCVENOUT# SA_DQ_49 DDR_A_D50
AH17 AK3
<11> DDR_A_WE# SA_WE# SA_DQ_50 DDR_A_D51
AL2
AH21 SA_DQ_51 AM5 DDR_A_D52
SB_BS_0 SA_DQ_52 DDR_A_D53
AJ20 AL5
SB_BS_1 SA_DQ_53 DDR_A_D54
AE27 AJ3
SB_BS_2 SA_DQ_54 AJ2 DDR_A_D55
SA_DQ_55 DDR_A_D56
AN20 AG2
SB_MA_0 SA_DQ_56 DDR_A_D57
AL21 AF3
SB_MA_1 SA_DQ_57 DDR_A_D58
AK21 AE7
AK22 SB_MA_2 SA_DQ_58 AF6 DDR_A_D59
B SB_MA_3 SA_DQ_59 B
AL22 AH5 DDR_A_D60
SB_MA_4 SA_DQ_60 DDR_A_D61
AH22 AG3
AG22 SB_MA_5 SA_DQ_61 AG5 DDR_A_D62
SB_MA_6 SA_DQ_62 DDR_A_D63
AF21 AF5
SB_MA_7 SA_DQ_63
AM21
AE21 SB_MA_8
SB_MA_9
AL20 AG19
SB_MA_10 SB_CAS#
AE22 AG21
SB_MA_11 SB_RAS#
AE26 AG20
AE20 SB_MA_12 SB_WE#
SB_MA_13

Calistoga-GSE_FCBGA998

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Calistoga(2/5)-DDR2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P 0.2

Date: Friday, August 08, 2008 Sheet 7 of 40

5 4 3 2 1
 5 4 3 2 1

D D

U1F R190 +1.5VS_PCIE

24.9_0402_1%
H27 R28 PEGCOMP 1 2
SDVO_CTRLDATA EXP_A_COMPI
J27 M28
Y26 SDVO_CTRLCLK EXP_A_ICOMPO
<12> CLK_MCH_3GPLL# G_CLKN
2 1 GMCH_CRT_R AA26 N30
<12> CLK_MCH_3GPLL G_CLKP SDVO_TVCLKIN#

MISC
R10 150_0402_1% R30
2 1 GMCH_CRT_G SDVO_INT# T29
R8 150_0402_1% SDVO_FLDSTALL#
2 1 GMCH_CRT_B
R9 150_0402_1% H20 M30
<14> GMCH_CRT_CLK CRT_DDC_CLK SDVO_TVCLKIN
<14> GMCH_CRT_DATA H22 P30
GMCH_CRT_B CRT_DDC_DATA SDVO_INT
<14> GMCH_CRT_B A24 T30
A23 CRT_BLUE SDVO_FLDSTALL
GMCH_CRT_G CRT_BLUE#
E25
<14> GMCH_CRT_G CRT_GREEN
F25
GMCH_CRT_R CRT_GREEN#

SDVO
<14> GMCH_CRT_R C25
D25 CRT_RED
Close to U4.H25

VGA
F27 CRT_RED#
<14> GMCH_CRT_VSYNC CRT_VSYNC
<14> GMCH_CRT_HSYNC D27
CRT_IREF CRT_HSYNC
2 1 H25 P28
R183 255_0402_1% CRT_IREF SDVO_RED#
N32
R171 2 SDVO_GREEN#
1 100K_0402_5% H30 P32
L_BKLTCTL SDVO_BLUE#
<25> GMCH_ENBKL G29 T32
C LCTLA_CLK L_BKLTEN SDVO_CLKN C
F28
LCTLB_DATA L_CLKCTLA
E28
LVDS_SCL L_CTLBDATA
<13> LVDS_SCL G28 N28
LVDS_SDA H28 L_DDC_CLK SDVO_RED M32
<13> LVDS_SDA L_DDC_DATA SDVO_GREEN
<13> GMCH_ENVDD
K30 P33
L_IBG L_VDDEN SDVO_BLUE
2 1 K27 R32
R184 1.5K_0402_1% J29 L_IBG SDVO_CLKP
J30 L_VBG +1.5VS
L_VREFH
K29
L_VREFL
LVDS_ACLK# D30 A21
<13> LVDS_ACLK# LA_CLKN TV_DACA
LVDS_ACLK C30 C20
<13> LVDS_ACLK LA_CLKP TV_DACB
A30 E20
LB_CLKN TV_DACC

LVDS
A29 G23
LB_CLKP TV_IREF

TV
B21 Disable TV
LVDS_A0# TV_IRTNA
<13> LVDS_A0# G31 C21
LVDS_A1# LA_DATAN_0 TV_IRTNB
<13> LVDS_A1# F32 D21
LVDS_A2# LA_DATAN_1 TV_IRTNC
<13> LVDS_A2# D31
LA_DATAN_2
LVDS_A0 H31
<13> LVDS_A0 LA_DATAP_0
LVDS_A1 G32 G26
<13> LVDS_A1 LA_DATAP_1 TV_DCONSEL0
<13> LVDS_A2 LVDS_A2 C31 J26
+3VS LA_DATAP_2 TV_DCONSEL1
F33
D33 LB_DATAN_0
LCTLA_CLK LB_DATAN_1
1 2 F30
R192 10K_0402_5% LB_DATAN_2
1 2 LCTLB_DATA E33
R191 10K_0402_5% LB_DATAP_0
D32
B
F29 LB_DATAP_1 B
LB_DATAP_2

Calistoga-GSE_FCBGA998

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga(3/5)-VGA/LVDS/TV
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 8 of 40
5 4 3 2 1
 5 4 3 2 1

+VCCP +1.5VS
U1E U1G
U1H AH33
T25 AD25 Y33 VSS_1 J16 W33 W30
R25 VCC_NCTF1 VCCAUX_NCTF1 AC25 V33 VSS_2 VSS_111 AL15 AM33 NC1 NC61 Y6
P25 VCC_NCTF2 VCCAUX_NCTF2 AB25 R33 VSS_3 VSS_112 AG15 AL33 NC2 NC62 AL1
N25 VCC_NCTF3 VCCAUX_NCTF3 AD24 G33 VSS_4 VSS_113 W15 C33 NC3 NC63 Y5
M25 VCC_NCTF4 VCCAUX_NCTF4 AC24 AK32 VSS_5 VSS_114 R15 B33 NC4 NC64 Y10
P24 VCC_NCTF5 VCCAUX_NCTF5 AD22 AG32 VSS_6 VSS_115 F15 AN32 NC5 NC65 W10
N24 VCC_NCTF6 VCCAUX_NCTF6 AD21 AE32 VSS_7 VSS_116 D15 A32 NC6 NC66 W25
M24 VCC_NCTF7 VCCAUX_NCTF7 AD20 AC32 VSS_8 VSS_117 AM14 AN31 NC7 NC67 V24
Y22 VCC_NCTF8 VCCAUX_NCTF8 AD19 AA32 VSS_9 VSS_118 AH14 W28 NC8 NC68 U24
VCC_NCTF9 VCCAUX_NCTF9 VSS_10 VSS_119 NC9 NC69
W22 AD18 U32 AE14 V27 V10
V22 VCC_NCTF10 VCCAUX_NCTF10 AD17 H32 VSS_11 VSS_120 H14 W29 NC10 NC70 U10
D
U22 VCC_NCTF11 VCCAUX_NCTF11 AD16 E32 VSS_12 VSS_121 B14 J24 NC11 NC71 K18 D

T22 VCC_NCTF12 VCCAUX_NCTF12 AD15 C32 VSS_13 VSS_122 F13 H24 NC12 NC72
R22 VCC_NCTF13 VCCAUX_NCTF13 AD14 AM31 VSS_14 VSS_123 D13 W32 NC13
P22 VCC_NCTF14 VCCAUX_NCTF14 K14 AJ31 VSS_15 VSS_124 AL12 G24 NC14
N22 VCC_NCTF15 VCCAUX_NCTF15 AD13 AA31 VSS_16 VSS_125 AG12 F24 NC15
M22 VCC_NCTF16 VCCAUX_NCTF16 Y13 U31 VSS_17 VSS_126 H12 E24 NC16
Y21 VCC_NCTF17 VCCAUX_NCTF17 W13 T31 VSS_18 VSS_127 B12 D24 NC17
W21 VCC_NCTF18 VCCAUX_NCTF18 V13 R31 VSS_19 VSS_128 AN11 K33 NC18
VCC_NCTF19 VCCAUX_NCTF19 VSS_20 VSS_129 NC19
V21 U13 P31 AJ11 A31
U21 VCC_NCTF20 VCCAUX_NCTF20 T13 N31 VSS_21 VSS_130 AE11 E21 NC20
T21 VCC_NCTF21 VCCAUX_NCTF21 R13 M31 VSS_22 VSS_131 AM9 C23 NC21
R21 VCC_NCTF22 VCCAUX_NCTF22 P13 J31 VSS_23 VSS_132 AJ9 AN19 NC22
P21 VCC_NCTF23 VCCAUX_NCTF23 N13 F31 VSS_24 VSS_133 AB9 AM19 NC23
N21 VCC_NCTF24 VCCAUX_NCTF24 M13 AL30 VSS_25 VSS_134 W9 AL19 NC24
M21 VCC_NCTF25 VCCAUX_NCTF25 AD12 AG30 VSS_26 VSS_135 R9 AK19 NC25
Y20 VCC_NCTF26 VCCAUX_NCTF26 Y12 AE30 VSS_27 VSS_136 M9 AJ19 NC26
W20 VCC_NCTF27 VCCAUX_NCTF27 W12 AC30 VSS_28 VSS_137 J9 AH19 NC27
V20 VCC_NCTF28 VCCAUX_NCTF28 V12 AA30 VSS_29 VSS_138 F9 AN3 NC28
VCC_NCTF29 VCCAUX_NCTF29 VSS_30 VSS_139 NC29

NC
U20 U12 Y30 C9 Y9
T20 VCC_NCTF30 VCCAUX_NCTF30 T12 V30 VSS_31 VSS_140 A9 J19 NC30
R20 VCC_NCTF31 VCCAUX_NCTF31 R12 U30 VSS_32 VSS_141 AL8 H19 NC31
P20 VCC_NCTF32 VCCAUX_NCTF32 P12 G30 VSS_33 VSS_142 AG8 G19 NC32
N20 VCC_NCTF33 VCCAUX_NCTF33 N12 E30 VSS_34 VSS_143 AE8 F19 NC33
M20 VCC_NCTF34 VCCAUX_NCTF34 M12 B30 VSS_35 VSS_144 U8 E19 NC34
Y19 VCC_NCTF35 VCCAUX_NCTF35 AD11 AA29 VSS_36 VSS_145 AA7 D19 NC35
P19 VCC_NCTF36 VCCAUX_NCTF36 AD10 U29 VSS_37 VSS_146 V7 C19 NC36
N19 VCC_NCTF37 VCCAUX_NCTF37 K10 R29 VSS_38 VSS_147 R7 B19 NC37
M19 VCC_NCTF38 VCCAUX_NCTF38 AN33 P29 VSS_39 VSS_148 N7 A19 NC38 Y25
VCC_NCTF39 VSS_NCTF1 VSS_40 VSS_149 NC39 RESERVED26
Y18 AA25 N29 H7 Y8 Y24
P18 VCC_NCTF40 VSS_NCTF2 V25 M29 VSS_41 VSS_150 E7 G16 NC40 RESERVED27 AB22

C
N18
M18
Y17
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
NCTF VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
U25
AA22
AA21
H29
E29
B29
VSS_42
VSS_43
VSS_44
VSS_151
VSS_152
VSS_153
B7
AL6
AG6
F16
E16
D16
NC41
NC42
NC43
RESERVED28
RESERVED29
RESERVED30
AB21
AB19
AB16 C

P17 VCC_NCTF44 VSS_NCTF6 AA20 AK28 VSS_45 VSS_154 AE6 C16 NC44 RESERVED31 AB14
N17 VCC_NCTF45 VSS_NCTF7 AA19 AH28 VSS_46 VSS_155 AB6 B16 NC45 RESERVED32 AA12
M17 VCC_NCTF46 VSS_NCTF8 AA18 AE28 VSS_47 VSS_156 W6 AN2 NC46 RESERVED33 W24
Y16 VCC_NCTF47 VSS_NCTF9 AA17 AA28 VSS_48 VSS_157 T6 A16 NC47 RESERVED34 AA24
P16 VCC_NCTF48 VSS_NCTF10 AA16 U28 VSS_49 VSS_158 M6 Y7 NC48 RESERVED35 AB24
VCC_NCTF49 VSS_NCTF11 VSS_50 VSS_159 NC49 RESERVED36
N16 AA15 T28 K6 AM4 AB20
VCC_NCTF50 VSS_NCTF12 VSS_51 VSS_160 NC50 RESERVED37

VSS
M16 AA14 J28 AN5 AF4 AB18
Y15 VCC_NCTF51 VSS_NCTF13 AA13 D28 VSS_52 VSS_161 AJ5 AD4 NC51 RESERVED38 AB15
P15 VCC_NCTF52 VSS_NCTF14 A4 AM27 VSS_53 VSS_162 B5 AL4 NC52 RESERVED39 AB13
N15 VCC_NCTF53 VSS_NCTF15 A33 AF27 VSS_54 VSS_163 AA4 AK4 NC53 RESERVED40 AB12
M15 VCC_NCTF54 VSS_NCTF16 B2 AB27 VSS_55 VSS_164 V4 W31 NC54 RESERVED41 AB17
Y14 VCC_NCTF55 VSS_NCTF17 AN1 AA27 VSS_56 VSS_165 R4 AJ4 NC55 RESERVED42
W14 VCC_NCTF56 VSS_NCTF18 C1 Y27 VSS_57 VSS_166 N4 AH4 NC56
V14 VCC_NCTF57 VSS_NCTF19 U27 VSS_58 VSS_167 K4 AG4 NC57
U14 VCC_NCTF58 K28 T27 VSS_59 VSS_168 H4 AE4 NC58
VCC_NCTF59 CFG_19 VSS_60 VSS_169 NC59
T14 R27 E4 AM1
R14 VCC_NCTF60 K25 P27 VSS_61 VSS_170 AL3 NC60
P14 VCC_NCTF61 RESERVED10 K26 N27 VSS_62 VSS_171 AD3
N14 VCC_NCTF62 RESERVED11 R24 M27 VSS_63 VSS_172 W3
+VCCP M14 VCC_NCTF63 RESERVED12 T24 G27 VSS_64 VSS_173 T3 Calis toga-GSE_FCBGA998
VCC_NCTF64 RESERVED13 K21 E27 VSS_65 VSS_174 B3
T10 RESERVED14 K19 C27 VSS_66 VSS_175 AK2
R10 VTT_NCTF1 RESERVED15 K20 B27 VSS_67 VSS_176 AH2
P10 VTT_NCTF2 RESERVED16 K24 AL26 VSS_68 VSS_177 AF2
N10 VTT_NCTF3 RESERVED17 K22 AH26 VSS_69 VSS_178 AB2
VTT_NCTF4 RESERVED18 VSS_70 VSS_179
L10 J17 W26 M2
D1 VTT_NCTF5 RESERVED19 K23 U26 VSS_71 VSS_180 K2
VTT_NCTF6 RESERVED20 K17 AN25 VSS_72 VSS_181 H2
M10 RESERVED21 K12 AK25 VSS_73 VSS_182 F2
A18 RSVD_3 RESERVED22 K13 AG25 VSS_74 VSS_183 V1
AB10 RSVD_4 RESERVED23 K16 AE25 VSS_75 VSS_184 R1
B
AA10 RSVD_5 RESERVED24 K15 J25 VSS_76 VSS_185 B
RSVD_6 RESERVED25 G25 VSS_77
Calis toga-GSE_FCBGA998 A25 VSS_78
H23 VSS_79
VSS_80
F23
B23 VSS_81
AM22 VSS_82
AJ22 VSS_83
AF22 VSS_84
G22 VSS_85
E22 VSS_86
J21 VSS_87
H21 VSS_88
F21 VSS_89
VSS_90
AM20
AK20 VSS_91
AH20 VSS_92
AF20 VSS_93
D20 VSS_94
W19 VSS_95
R19 VSS_96
AM18 VSS_97
AH18 VSS_98
AF18 VSS_99
VSS_100
U18
H18 VSS_101
D18 VSS_102
AK17 VSS_103
V17 VSS_104
T17 VSS_105
F17 VSS_106
B17 VSS_107
A
AH16 VSS_108 A

U16 VSS_109
VSS_110
Calis toga-GSE_FCBGA998

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Calistoga(4/5)-PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 9 of 40
5 4 3 2 1
 5 4 3 2 1

+VCCP +1.5VS
2940mA
U1D 144mA
T26 B20
R26
P26
VCC0
VCC1
VCCATVDACA0
VCCATVDACA1
A20
B22
PCI-E/MEM/PSB PLL decoupling
N26 VCC2 VCCATVDACB0 A22
M26 VCC3 VCCATVDACB1 D22
Disable TV
220U_B2_2.5VM_R35
VCC4 VCCATVDACC0 +1.5VS_3GPLL +1.5VS

10U_0805_10V4Z~D

10U_0805_10V4Z~D
V19 C22

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 VCC5 VCCATVDACC1
1 1 1 1 1 U19 D23 R210
+ T19 VCC6 VCCATVBG E23 +1.5VS_3GPLL 2 1 +1.5VS
C37

C41

C39

C261

C265

C266
W18 VCC7 VSSATVBG F20
VCC8 VCCDTVDAC

10U_0805_10V4Z
V18 F22 0_0603_5%

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
2 2 2 2 2 2 VCC9 VCCDQTVDAC
T18
VCC10 VCCDLVDS0
C28 20mA +1.5VS 1 1 1
R18 B28
D
W17 VCC11 VCCDLVDS1 A28 D

C277

C278

C287
U17 VCC12 VCCDLVDS2 E26 @
VCC13 VCCHV0 40mA +3VS 2 2 2

10U_0805_10V4Z~D
R17 D26

0.1U_0402_16V4Z~D
VCC14 VCCHV1 1 1
W16 C26
VCC15 VCCHV2 U4_AB33

10U_0805_10V4Z~D
V16 AB33

C24
0.1U_0402_16V4Z~D
VCC16 VCCSM0 10mil 1 1
T16 AM32 U4_AM32

C235
R16 VCC17 VCCSM1 AN29 2 2

C23
VCC18 VCCSM2 10mil
V15 AM29

C239
VCC19 VCCSM3 2 2
U15 AL29 1 1
VCC20 VCCSM4

1U_0603_10V6K~D

1U_0603_10V6K~D
T15 AK29
VCC21 VCCSM5 AJ29 45mA Max. 45mA Max.

C318

C286
AD33 VCCSM6 AH29 +1.5VS_MPLL R45 +1.5VS_HPLL R38
AD32 VCCAUX1 VCCSM7 AG29 2 2 0_0603_5% 0_0603_5%
+VCCP AD31 VCCAUX2 VCCSM8 AF29 2 1 2 1
VCCAUX3 VCCSM9 +1.5VS +1.5VS
AD30 AE29 +1.8V
AD29 VCCAUX4 VCCSM10 AN24 533 MTS=1720mA
2

+1.5VS VCCAUX5 VCCSM11

10U_0805_10V4Z~D

10U_0805_10V4Z~D
AD28 AM24

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
D15 @ AD27 VCCAUX6 VCCSM12 AL24
VCCAUX7 VCCSM13 1 1 1 1
1250mA AC27
VCCAUX8 VCCSM14
AK24

C48

C52

C43

C44
RB751V-40TE17_SOD323-2 AD26 AJ24
VCCAUX9 VCCSM15

1U_0603_10V6K~D
AC26 AH24

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V6M~D
1 1

AB26 VCCAUX10 VCCSM16 AG24 2 2 2 2

0.1U_0402_16V4Z~D

VCCAUX11 VCCSM17 1 1 1
1 AE19 AF24
R168 +2.5VS AE18 VCCAUX12 VCCSM18 AE24
C250

C288

C330

C293
@ AF17 VCCAUX13 VCCSM19 AN18
VCCAUX14 VCCSM20 10mil 2 2 2
10_0402_5% AE17 AN16
2 AF16 VCCAUX15 VCCSM21 AM16
2

AE16 VCCAUX16 VCCSM22 AL16

VCCAUX17 VCCSM23
AF15 AK16 1
AE15 VCCAUX18 VCCSM24 AJ16
J14 VCCAUX19 VCCSM25 AN13 C319
J10 VCCAUX20 VCCSM26 AM13 1U_0402_6.3V4Z~D
C
H10 VCCAUX21 VCCSM27 AL13 2 C
VCCAUX22 VCCSM28 +1.5VS_DPLLB
40mA Max. +1.5VS_DPLLA
40mA Max.
AE9 AK13
AD9 VCCAUX23 VCCSM29 AJ13 L20 L2
+VCCP U9 VCCAUX24 VCCSM30 AH13 1 2 1 2
VCCAUX25 VCCSM31 +1.5VS +1.5VS
AD8 AG13 FBM-L10-160808-301-T_0603 FBM-L10-160808-301-T_0603
VCCAUX26 VCCSM32

0.1U_0402_16V4Z~D

330U_D2E_2.5VM

0.1U_0402_16V4Z~D

330U_D2E_2.5VM
780mA AD7 AF13
C25 VCCAUX27 VCCSM33
AD6 AE13 1 1
VCCAUX28 VCCSM34 AN4
VCCSM35 10mil 1 1

C257

C249

C236

C13
1 2 10mil U4_A14 A14 AM10 + +
D10 VTT0 VCCSM36 AL10
P9 VTT1 VCCSM37 AK10
0.47U_0603_16VY5V L9 VTT2 VCCSM38 AH1 2 2 2 2
VTT3 VCCSM39 10mil 1

1U_0603_10V6K~D
D9 AH10
P8 VTT4 VCCSM40 AG10

C329
L8 VTT5 VCCSM41 AF10
D8 VTT6 VCCSM42 AE10 2
VTT7 VCCSM43 1

1U_0603_10V6K~D
P7 AN7
VTT8 VCCSM44

C54
C22 L7 AM7
D7 VTT9 VCCSM45 AL7
1 210mil U4_A7 A7 VTT10 VCCSM46 AK7 2
P6 VTT11 VCCSM47 AJ7
L6 VTT12 VCCSM48 AH7
0.47U_0603_16VY5V G6 VTT13 VCCSM49 AN10
VTT14 VCCSM50
POWER

D6 AJ10
U5 VTT15 VCCSM51 AD1
VTT16 VCCAMPLL +1.5VS_MPLL 45mA +2.5VS
P5 AD2 +1.5VS_HPLL 45mA
220U_B2_2.5VM_R35

VTT17 VCCAHPLL
L5 B26 +1.5VS_DPLLA 50mA

0.1U_0402_16V4Z~D
1 VTT18 VCCADPLLA
G5 J32 +1.5VS_DPLLB 50mA 1
+ D5 VTT19 VCCADPLLB AE5
C40

VTT20 VCCDHMPLL1 +1.5VS 150mA

Y4 AD5 Route +2.5VS from GMCH pinN33 to C267
U4 VTT21 VCCDHMPLL2 D29 +1.5VS_PCIE
2 VTT22 VCCTXLVDS0 +2.5VS 60mA decoupling cap <200mil to the edge.
2
P4 C29 R177
B
L4 VTT23 VCCTXLVDS1 U33 2 1 B
VTT24 VCC3G0 400mA +1.5VS
G4 T33 0_0805_5%
D4 VTT25 VCC3G1 V26400mA
VTT26 VCCA3GPLL +1.5VS_3GPLL 1
Y3 N33 2mA +2.5VS

220U_B2_2.5VM_R35
VTT27 VCCA3GBG +2.5VS 1 1
+

10U_0805_10V4Z~D

10U_0805_10V4Z~D
U3 M33
P3 VTT28 VSSA3GBG J23 70mA

C254

C253

C259
L3 VTT29 VCCSYNC C24 +2.5VS_CRTDAC 2 R172 1
70mA
4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

1 1 VTT30 VCCACRTDAC0 +2.5VS

G3 B24 10_0603_5% 2 2 2
VTT31 VCCACRTDAC1

10U_0805_10V4Z~D
D3 B25

0.1U_0402_16V4Z~D
C281

C276

VTT32 VSSACRTDAC 1 1

10U_0805_10V4Z~D
Y2 B31 10mA
0.022U_0402_16V7K

+2.5VS 1 1 0.1U_0402_16V4Z~D 1
2 2 U2 VTT33 VCCALVDS B32 +VCCP

C256

C245
P2 VTT34 VSSALVDS
C242

C244
L2 VTT36 P1 2 2
C241

G2 VTT35 VTT41 L1 2 2 2 CRTDAC: Route FB

VTT37 VTT42
D2 G1 within 3" of Calistoga
U4_AA1 AA1 VTT38 VTT43 U1
10mil VTT39 VTT44
U4_F1 F1 Y1
VTT40 VTT45
10mil
2 2 Calis toga-GSE_FCBGA998

C283 C248 +2.5VS +2.5VS

0.47U_0603_16VY5V 0.47U_0402_10V4Z~D
1 1 Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

0.1U_0402_16V4Z~D

0.01U_0402_25V7K~D
4.7U_0603_6.3V4Z~D
1 1 1 1

0.1U_0402_16V4Z~D
C260

C247

C237

C246
2 2 2 2
A A

close pin C29/D29 close pin B31

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
Calistoga(5/5)-PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 10 of 40
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JDIM1
<7> DDR_A_DQS#[0..7] +DIMM_VREF 1 2
3 VREF VSS 4 DDR_A_D4
+1.8V DDR_A_D0 5 VSS DQ4 6 DDR_A_D5
<7> DDR_A_D[0..63] DQ0 DQ5
DDR_A_D1 7 8
9 DQ1 VSS 10 DDR_A_DM0
<7> DDR_A_DM[0..7]

1
DDR_A_DQS#0 11 VSS DM0 12
R41 DDR_A_DQS0 13 DQS0# VSS 14 DDR_A_D6
<7> DDR_A_DQS[0..7] Layout Note: DQS0 DQ6 DDR_A_D7
15 16
Place near JDIM1 1K_0402_1% DDR_A_D2 17 VSS DQ7 18
<7> DDR_A_MA[0..13] DQ2 VSS
DDR_A_D3 19 20 DDR_A_D12

2
DQ3 DQ12 DDR_A_D13
+DIMM_VREF 21 22
DDR_A_D9 23 VSS DQ13 24

1
D DDR_A_D8 25 DQ8 VSS 26 DDR_A_DM1 D
R43 27 DQ9 DM1 28
Share +DIMM_VREF for DDR_A_DQS#1 VSS VSS M_CLK_DDR0
29 30 M_CLK_DDR0 <6>
1K_0402_1% 1.DDRII VREF DDR_A_DQS1 31 DQS1# CK0 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 <6>
+1.8V 2.GMCH SM_VREF_0 33 34

2
DDR_A_D10 35 VSS VSS 36 DDR_A_D14
SM_VREF_1 DDR_A_D11 37 DQ10 DQ14 38 DDR_A_D15
39 DQ11 DQ15 40
VSS VSS
+DIMM_VREF
2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D
2 2 2 2 2
20mils 41 42
DDR_A_D16 43 VSS VSS 44 DDR_A_D20
C91

C90

C89

C70

C71
DDR_A_D17 45 DQ16 DQ20 46 DDR_A_D21
1 1 1 1 1 47 DQ17 DQ21 48
1 1 VSS VSS
C86 C92 DDR_A_DQS#2 49 50 R54 1 2
DQS2# NC PM_EXTTS#0 <6>
DDR_A_DQS2 51 52 DDR_A_DM2 0_0402_5%
0.1U_0402_16V4Z~D 2.2U_0603_6.3V6K~D 53 DQS2 DM2 54
2 2 DDR_A_D18 55 VSS VSS 56 DDR_A_D22
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 58
59 DQ19 DQ23 60
DDR_A_D24 61 VSS VSS 62 DDR_A_D28
1 DQ24 DQ28
DDR_A_D25 63 64 DDR_A_D29
220U_B2_2.5VM_R35

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 1 1 1 DQ25 DQ29
+ 65 66
@ DDR_A_DM3 67 VSS VSS 68 DDR_A_DQS#3
C61

C69

C68

C88

C87

69 DM3 DQS3# 70 DDR_A_DQS3

2 2 2 2 2 71 NC DQS3 72
DDR_A_D26 73 VSS VSS 74 DDR_A_D30
DDR_A_D27 75 DQ26 DQ30 76 DDR_A_D31
DQ27 DQ31
77 78
DDR_CKE0 79 VSS VSS 80 DDR_CKE1
<6> DDR_CKE0 CKE0 NC/CKE1 DDR_CKE1 <6>
81 82
83 VDD VDD 84
C DDR_A_BS2 85 NC NC/A15 86 C
<7> DDR_A_BS2 BA2 NC/A14
87 88
DDR_A_MA12 89 VDD VDD 90 DDR_A_MA11
DDR_A_MA9 91 A12 A11 92 DDR_A_MA7
DDR_A_MA8 93 A9 A7 94 DDR_A_MA6
95 A8 A6 96
DDR_A_MA5 VDD VDD DDR_A_MA4
97 98
DDR_A_MA3 99 A5 A4 100 DDR_A_MA2
Layout Note: DDR_A_MA1 A3 A2 DDR_A_MA0
101 102
Place one cap close to every 2 pullup 103 A1 A0 104
DDR_A_MA10 105 VDD VDD 106 DDR_A_BS1
resistors terminated to +0.9VS DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
DDR_A_BS1 <7>
<7> DDR_A_BS0 107 108 DDR_A_RAS# <7>
DDR_A_WE# 109 BA0 RAS# 110 DDR_CS0#
<7> DDR_A_WE# WE# S0# DDR_CS0# <6>
111 112
DDR_A_CAS# 113 VDD VDD 114 M_ODT0
<7> DDR_A_CAS# CAS# ODT0 M_ODT0 <6>
DDR_CS1# 115 116 DDR_A_MA13
<6> DDR_CS1# NC/S1# NC/A13
117 118
M_ODT1 119 VDD VDD 120
<6> M_ODT1 NC/ODT1 NC
121 122
+0.9VS DDR_A_D32 123 VSS VSS 124 DDR_A_D36
DDR_A_D33 125 DQ32 DQ36 126 DDR_A_D37
127 DQ33 DQ37 128
DDR_A_DQS#4 129 VSS VSS 130 DDR_A_DM4
DDR_A_DQS4 131 DQS4# DM4 132
133 DQS4 VSS 134 DDR_A_D38
DDR_A_D34 135 VSS DQ38 136 DDR_A_D39
DDR_A_D35 DQ34 DQ39
137 138
139 DQ35 VSS 140 DDR_A_D44
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1 1 1 1 1 1 1 1 1 1 1 1 1 VSS DQ44
DDR_A_D40 141 142 DDR_A_D45
DDR_A_D41 143 DQ40 DQ45 144
C79

C84

C81

C83

C82

C99

C78

C80
C104

C103

C102

C101

C100

145 DQ41 VSS 146 DDR_A_DQS#5

2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DM5 147 VSS DQS5# 148 DDR_A_DQS5
B
149 DM5 DQS5 150 B
DDR_A_D42 151 VSS VSS 152 DDR_A_D46
DDR_A_D43 153 DQ42 DQ46 154 DDR_A_D47
155 DQ43 DQ47 156
DDR_A_D48 VSS VSS DDR_A_D52
157 158
DDR_A_D49 159 DQ48 DQ52 160 DDR_A_D53
161 DQ49 DQ53 162
163 VSS VSS 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 <6>
165 166 M_CLK_DDR#1 M_CLK_DDR#1 <6>
DDR_A_DQS#6 167 VSS CK1# 168
DDR_A_DQS6 169 DQS6# VSS 170 DDR_A_DM6
171 DQS6 DM6 172
+0.9VS DDR_A_D50 173 VSS VSS 174 DDR_A_D54
RP1 RP5 DDR_A_D51 175 DQ50 DQ54 176 DDR_A_D55
DDR_A_MA0 DDR_A_RAS# DQ51 DQ55
1 8 8 1 177 178
DDR_A_MA13 2 7 7 2 DDR_A_MA4 DDR_A_D56 179 VSS VSS 180 DDR_A_D60
DDR_CS0# 3 6 6 3 DDR_A_MA2 DDR_A_D57 181 DQ56 DQ60 182 DDR_A_D61
M_ODT0 4 5 5 4 DDR_A_BS1 183 DQ57 DQ61 184
Layout Note: DDR_A_DM7 185 VSS VSS 186 DDR_A_DQS#7
56_0804_8P4R_5% 56_0804_8P4R_5% 187 DM7 DQS7# 188 DDR_A_DQS7
Place these resistor VSS DQS7
RP2 RP6 DDR_A_D58 189 190
DDR_A_MA1 DDR_CKE1
closely DIMMA,all DDR_A_D59 DQ58 VSS DDR_A_D62
1 8 8 1 191 192
DDR_A_MA3 2 7 7 2 DDR_A_MA7 trace length<750 mil 193 DQ59 DQ62 194 DDR_A_D63
DDR_A_MA5 3 6 6 3 DDR_A_MA6 CLK_SMBDATA 195 VSS DQ63 196
+3VS <12> CLK_SMBDATA SDA VSS
DDR_A_CAS# 4 5 5 4 DDR_A_MA11 <12> CLK_SMBCLK CLK_SMBCLK 197 198 R53 1 2 10K_0402_5%
199 SCL SAO 200 R52 1 2 10K_0402_5%
+3VS VDDSPD SA1
56_0804_8P4R_5% 56_0804_8P4R_5%
RP3 RP4
DDR_A_WE# 1 8 8 1 DDR_A_MA12 @ FOX_AS0A426-N2SN-7F~D
2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

1 1
DDR_A_BS0 2 7 7 2 DDR_A_MA9 C360 C361 ME@
M_ODT1 3 6 6 3 DDR_A_MA8
DDR_CS1# 4 5 5 4 DDR_A_MA10
A
56_0804_8P4R_5% 56_0804_8P4R_5%
2 2
DIMMA A

DDR_A_BS2 1 R159 2
Layout Note:
Place these resistor
Security Classification Compal Secret Data Compal Electronics, Inc.
56_0402_5% closely DIMMA,all Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
DDR_CKE0 1 R160
56_0402_5%
2
trace length DDRII-SODIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Max=1.3" AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Docum ent Num ber Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, Augus t 08, 2008 Sheet 11 of 40
5 4 3 2 1
 5 4 3 2 1

+3VM_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB +3VS

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1
R78
2
0_0805_5% 1 1 1 1 1 1 1
C151 C181 C175 C197 C199 C155 C154 R112 R108
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 2.2K_0402_5% 2.2K_0402_5%
2 2 2 2 2 2 2 2N7002DW-T/R7_SOT363-6
0 0 1 133 100 33.3 14.318 96.0 48.0 Q10A
+1.05VM_CK505 CLK_SMBDATA
<17> ICH_SMBDATA 6 1
0 1 0 200 100 33.3 14.318 96.0 48.0
+VCCP 1 2
R131 0_0805_5% 1 1 1 1 1 1 1

2
0 1 1 166 100 33.3 14.318 96.0 48.0 C163 C198 C152 C153 C167 C189 C200 +3VS
D D

5
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
1 0 0 333 100 33.3 14.318 96.0 48.0 2 2 2 2 2 2 2
3 4 CLK_SMBCLK
<17> ICH_SMBCLK

1 0 1 100 100 33.3 14.318 96.0 48.0 Q10B

2N7002DW-T/R7_SOT363-6
1 1 0 400 100 33.3 14.318 96.0 48.0

1 1 1 Reserved SA000020K00 (Silego : SLG8SP556VTR )

SA000020H10 (ICS : ICS9LPRS387AKLFT)

+3VM_CK505 U11
9 CLK_SMBDATA
SDA CLK_SMBDATA <11>
55
VDD_SRC
SCL
10 CLK_SMBCLK
CLK_SMBCLK <11>
SRC PORT LIST
6
VDD_REF
12 71 CLK_CPU_BCLK
+VCCP VDD_PCI CPU_0 CLK_CPU_BCLK <4>
72 70 CLK_CPU_BCLK#
PORT DEVICE
VDD_CPU CPU_0# CLK_CPU_BCLK# <4>
2

CLK_MCH_BCLK
R140
19
VDD_48 CPU_1
68
CLK_MCH_BCLK <6> SRC0 MCH_DREFCLK
27 67 CLK_MCH_BCLK#
R138 56_0402_5% VDD_PLL3 CPU_1# CLK_MCH_BCLK# <6> SRC2 MCH_3GPLL
2.2K_0402_5%
SRC3
1

FSA 2 1 1 2 66 24 CLK_MCH_DREFCLK
C MCH_CLKSEL0 <6> +1.05VM_CK505 VDD_CPU_IO SRC_0/DOT_96 CLK_MCH_DREFCLK <6> C

1 @ 2 R142 31 25 CLK_MCH_DREFCLK# SRC4 PCIE_CARDREADER

<4> CPU_BSEL0 VDD_PLL3_IO SRC_0#/DOT_96# CLK_MCH_DREFCLK# <6>
R147 1K_0402_5%
0_0402_5% 62
SRC6 PCIE_WLAN
1

VDD_SRC_IO 28 MCH_SSCDREFCLK
R141 52
LCDCLK/27M MCH_SSCDREFCLK <6> SRC7
VDD_SRC_IO 29 MCH_SSCDREFCLK#
1K_0402_5% 23
LCDCLK#/27M_SS MCH_SSCDREFCLK# <6> SRC8
@ VDD_IO
SRC9 PCIE_LAN
2

38 32 CLK_MCH_3GPLL
VDD_SRC_IO SRC_2 CLK_MCH_3GPLL <8>
33 CLK_MCH_3GPLL# SRC10 PCIE_ICH
+VCCP SRC_2# CLK_MCH_3GPLL# <8>
33_0402_5% 1 2 R137 FSA 20
SRC11
<17> CLK_ICH_48M USB_0/FS_A 35
2

FSB SRC_3
2
R81 FS_B/TEST_MODE 36
33_0402_5% 1 FSC SRC_3#
2 R101 7
1K_0402_5% <17> CLK_ICH_14M REF_0/FS_C/TEST_
@ 1 2 C392 8 39 CLK_PCIE_CARD
1

FSB REF_1 SRC_4 CLK_PCIE_CARD <23>

1 2 4.7P_0402_50VNPO
MCH_CLKSEL1 <6> CLK_PCIE_CARD#
@ 40
VGATE SRC_4# CLK_PCIE_CARD# <23>
1 @ 2 R86 1
<4> CPU_BSEL1 <17,25,36> VGATE CKPWRGD/PD#
R91 1K_0402_5%
0_0402_5% 11 57 CLK_PCIE_WLAN
CLK_PCIE_WLAN <19>
1

NC SRC_6
R82 56 CLK_PCIE_WLAN#
SRC_6# CLK_PCIE_WLAN# <19>
0_0402_5% H_STP_CPU# 53
<17> H_STP_CPU# CPU_STOP# 61
2

H_STP_PCI# SRC_7
54
<17> H_STP_PCI# PCI_STOP# 60
SRC_7#
CLK_XTAL_IN 5
B +VCCP XTAL_IN 64 B
CLK_XTAL_OUT SRC_8/CPU_ITP
4
XTAL_OUT 63
2

SRC_8#/CPU_ITP# +3VS
R97
13 44 CLK_PCIE_LAN
PCI_1 SRC_9 CLK_PCIE_LAN <24>
R100 1K_0402_5%
10K_0402_5% @ PCI2_TME 14 45 CLK_PCIE_LAN# MCH_CLKREQ# R139 2 1 10K_0402_5%
1

FSC PCI_2 SRC_9# CLK_PCIE_LAN# <24> CLKREQ_LAN#

2 1 1 2 R111 2 1 10K_0402_5%
MCH_CLKSEL2 <6> WLAN_CLKREQ#
15 R84 2 1 10K_0402_5%
1 @ 2 R99 PCI_3 50 CLK_PCIE_ICH
<4> CPU_BSEL2 PCI4_SEL SRC_10 CLK_PCIE_ICH <17>
R95 1K_0402_5% 33_0402_5% 1 2 R115 16
<25> CLK_PCI_LPC PCI_4/SEL_LCDCL CLK_PCIE_ICH#
0_0402_5% 51
CLK_PCIE_ICH# <17>
1

33_0402_5% 1 ITP_EN SRC_10#

2 R121 17
<15> CLK_PCI_ICH PCIF_5/ITP_EN
R98

0_0402_5% For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# SRC_11

48
REQ PORT LIST
18 47
2

VSS_PCI SRC_11#
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
3
Pin28/29 : LCDCLK / LCDCLK# VSS_REF PORT DEVICE
1 = Pin24/25 : SRC_0 / SRC_0# 22
VSS_48 CLKREQ_3#
37
Pin28/29 : 27M/27M_SS 26 41
REQ_3#
VSS_IO CLKREQ_4#
For PCI2_TME:0=Overclocking of CPU and SRC allowed 69 58 WLAN_CLKREQ# REQ_4#
VSS_CPU CLKREQ_6# WLAN_CLKREQ# <19>
(ICS only) 1=Overclocking of CPU and SRC NOT allowed 30 65
REQ_6# PCIE_WLAN
VSS_PLL3 CLKREQ_7#
34 43 CLKREQ_LAN# REQ_7#
VSS_SRC CLKREQ_9# CLKREQ_LAN# <24>
+3VS +3VS +3VS 59 49
REQ_9# PCIE_LAN
VSS_SRC SLKREQ_10#
42 46
REQ_10#
2

VSS_SRC CLKREQ_11#
A
R129 R119 R109 73 21 MCH_CLKREQ# REQ_11# A

CLK_XTAL_IN VSS USB_1/CLKREQ_A# MCH_CLKREQ# <6>

C169 22P_0402_50V8J 10K_0402_5% 10K_0402_5% 10K_0402_5%
REQ_A# MCH_3GPLL
1

@ @ SLG8SP556VTR_QFN72_10X10
1

Y2
14.31818MHZ_16PF_DSX840GA ITP_EN PCI4_SEL PCI2_TME
2

CLK_XTAL_OUT
2

C162 22P_0402_50V8J @
R132 R117 R110
Security Classification Compal Secret Data Compal Electronics, Inc.
Routing the trace at least 10mil 10K_0402_5% 10K_0402_5% 10K_0402_5%
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
Clock Generator CK505
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
M AY BE USED BY OR DISCLOSED T O ANY T HIRD PART Y WIT HOUT PRIOR WRIT T EN CONSENT OF COM PAL ELECT RONICS, INC. Date: Friday, August 08, 2008 Sheet 12 of 40
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+3VALW +3VS
+LCDVDD
W=20mils

1
D D
1

1
R40 C59
150_0603_5% R35 @
47K_0402_5% 4.7U_0805_10V4Z~D
2

1 2

3
S
D
G
Q4 2 2 1 2 Q5
2N7002_SOT23 G R39 47K_0402_5% SI2301BDS_SOT23
S

3
2 D
C45

1
+LCDVDD
Q3 0.1U_0402_16V4Z~D W=20mils
DTC124EK_SC59 1

<8> GMCH_ENVDD 2 1 1
C58 C63

4.7U_0805_10V4Z~D 0.1U_0402_16V4Z~D
2 2

3
C C

LCD/PANEL BD. Conn.

C85
4.7U_0805_10V4Z~D 2 1 JP8

+LEDVDD 20 21
FBMA-L11-201209-221LMA30T_0805 2 L7 1 19 20 MGND1 22
400mA +5VS 19 MGND2
280mA +LCDVDD FBMA-L11-201209-221LMA30T_0805 2 L6 1 (20 MIL) +LCDVDD_L 18 23
17 18 MGND3 24
+3VS 17 MGND4 +3VS
INVT_PWM 16
For panel ADJ <25> INVT_PWM
BKOFF# 15 16
LVDS_SDA 14 15
LVDS_SCL 13 14
12 13

2
10K_0402_5%

10K_0402_5%
LVDS_A0 11 12
<8> LVDS_A0 11
LVDS_A0#

R44

R42
<8> LVDS_A0# 10
9 10
LVDS_A1 8 9
<8> LVDS_A1 8
<8> LVDS_A1# LVDS_A1# 7

1
6 7
LVDS_A2 5 6 LVDS_SCL
B <8> LVDS_A2 5 LVDS_SCL <8> B
LVDS_A2# 4
<8> LVDS_A2# 4
3 LVDS_SDA
3 LVDS_SDA <8>
LVDS_ACLK 2
<8> LVDS_ACLK LVDS_ACLK# 2
<8> LVDS_ACLK#
1
1

I-PEX_20143-020E-20F
ME@ BKOFF#
BKOFF# <25>

Coaxial LVDS Conn

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
LVDS /INVERTER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 13 of 40
5 4 3 2 1
 A B C D E

Close to CRT CONN for ESD.

2
3

2
@
@ D4
1 1

PSOT24C_SOT23-3
D3
PSOT24C_SOT23-3

1
1
Place closed to chipset L1
BK1608LL121-T 0603
1 2 RED
<8> GMCH_CRT_R
L3
BK1608LL121-T 0603
1 2 GREEN
<8> GMCH_CRT_G
L4
BK1608LL121-T 0603
1 2 BLUE
<8> GMCH_CRT_B

1
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1
R5 R13 R19 C12 C30 C35 1 1 1
C7 C20 C29
2 @ 2 @ 2 @ 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
2

2
22P_0402_50V8J @ 2 @ 2 2 @
22P_0402_50V8J 22P_0402_50V8J

+CRT_VCC 1 2 JVGA_HS
L19 FCM1608C-121T_0603
1 2
C38 0.1U_0402_16V4Z~D 1 2 JVGA_VS
L5 FCM1608C-121T_0603

1
2 2
U15
39_0402_5% 1 1

OE#
1 R282 2 2 4 CRT_HSYNC_1
<8> GMCH_CRT_HSYNC A Y C232 C31

G
10P_0402_50V8J 10P_0402_50V8J
SN74AHCT1G125DCKR_SC70-5 @ 2 2 @
3 +CRT_VCC
Place closed to chipset
1 2
C234 0.1U_0402_16V4Z~D

1
U4
@

OE#
1 R296 2 2 4 CRT_VSYNC_1
<8> GMCH_CRT_VSYNC A Y
39_0402_5%
G
SN74AHCT1G125DCKR_SC70-5
3

+3VS CRT PORT

+CRT_VCC
+CRT_VCC
1

+5VS
3 2.2K_0402_5% 3
R165 C36
+3VS D6 0.1U_0402_16V4Z~D
2.2K_0402_5% R163 W=40mils
2 1 1 2
1

1
2

R16 R164 RB491D_SC59-3 JCRT1

6
2.2K_0402_5% 2.2K_0402_5% 11
RED 1
5

7
VGA_DDC_DAT 12
4 3 VGA_DDC_DAT GREEN 2
<8> GMCH_CRT_DATA 8
JVGA_HS 13
2

Q14B BLUE 3
2N7002DW-T/R7_SOT363-6 9
1 6 VGA_DDC_CLK JVGA_VS 14 GND 16
<8> GMCH_CRT_CLK
4 GND 17
10
Q14A VGA_DDC_CLK 15
2N7002DW-T/R7_SOT363-6 5
@ 1 @ 1
SUYIN_070912FR015H236ZR
C228 C33 ME@

100P_0402_50V8J~D 2 2 68P_0402_50V8K

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
CRT PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 14 of 40
A B C D E
 5 4 3 2 1

D D

+3VS

U6B
R260 1 2 8.2K_0402_5% PCI_DEVSEL# E18 D7 PCI_REQ#0
C18 AD0 REQ0# E7
R263 1 PCI_STOP# AD1 GNT0# PCI_REQ#1
2 8.2K_0402_5% A16 PCI C16
AD2 REQ1#
F18 D16
R262 1 2 8.2K_0402_5% PCI_TRDY# E16 AD3 GNT1# C17 PCI_REQ#2
AD4 REQ2#
A18 D17 For EMI, close to ICH7
R264 1 AD5 GNT2#
2 8.2K_0402_5% PCI_FRAME# E17 E13 PCI_REQ#3
A17 AD6 REQ3# F13
R259 1 PCI_PLOCK# AD7 GNT3# PCI_REQ#4
2 8.2K_0402_5% A15 A13
AD8 REQ4# / GPIO22 PCI_RST#
C14 A14
R256 1 2 8.2K_0402_5% PCI_IRDY# E14 AD9 GNT4# / GPIO48 C8 PCI_REQ#5
D14 AD10 GPIO1 / REQ5# D8
AD11 GPIO17 / GNT5#

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
R258 1 2 8.2K_0402_5% PCI_SERR# B12 PLTRST#_R
AD12
C13 B15
R257 1 PCI_PERR# AD13 C/BE0#
2 8.2K_0402_5% G15 C12 2 2
AD14 C/BE1#
G13 D12
AD15 C/BE2#

C357

C358
E12 C15 @ @
AD16 C/BE3#
C11
C +3VS AD17 PCI_IRDY# 1 1 C
D11 A7
AD18 IRDY#
A11 E10
AD19 PAR PCI_RST#
A10 B18 PCI_RST# <25>
R254 1 2 8.2K_0402_5% PCI_PIRQA# F11 AD20 PCIRST# A12 PCI_DEVSEL#
F10 AD21 DEVSEL# C9 PCI_PERR#
R255 1 AD22 PERR#
2 8.2K_0402_5% PCI_PIRQB# E9 E11 PCI_PLOCK# 1 R244 2
D9 AD23 PLOCK# B10 PCI_SERR#
R271 1 2 8.2K_0402_5% PCI_PIRQC# B9 AD24 SERR# F15 PCI_STOP# 100K_0402_5%
AD25 STOP# PCI_TRDY#
A8
AD26 TRDY#
F14 For EC request.
R270 1 2 8.2K_0402_5% PCI_PIRQD# A6 F16 PCI_FRAME#
C7 AD27 FRAME#
R276 1 AD28
2 8.2K_0402_5% PCI_PIRQE# B6 C26 PLTRST#_R
E6 AD29 PLTRST# A9 CLK_PCI_ICH
PCI_PIRQF# AD30 PCICLK CLK_PCI_ICH <12> Place closely pin A9
R272 1 2 8.2K_0402_5% D6 B19
AD31 PME#
R275 1 2 8.2K_0402_5% PCI_PIRQG# CLK_PCI_ICH
Interrupt I/F

2
R273 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQA# A3 G8 PCI_PIRQE#
PCI_PIRQB# PIRQA# GPIO2 / PIRQE# PCI_PIRQF# @
B4 F7
R274 1 PCI_REQ#0 PCI_PIRQC# PIRQB# GPIO3 / PIRQF# PCI_PIRQG#
2 8.2K_0402_5% C5 F8 R246
PCI_PIRQD# PIRQC# GPIO4 / PIRQG# PCI_PIRQH# 10_0402_5%
B5 G7
R265 1 PIRQD# GPIO5 / PIRQH#
2 8.2K_0402_5% PCI_REQ#1

1
R266 1 2 8.2K_0402_5% PCI_REQ#2 AE5
MISC AE9
RSVD[1] RSVD[6] 1
AD5 AG8 @
R261 1 RSVD[2] RSVD[7]
2 8.2K_0402_5% PCI_REQ#3 AG4 AH8 C359
AH4 RSVD[3] RSVD[8] F21 8.2P_0402_50V8D
R277 1 2 8.2K_0402_5% PCI_REQ#4 AD9 RSVD[4] RSVD[9] AH20 2
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <6>
B PCI_REQ#5 B
R278 1 2 8.2K_0402_5%
ICH7_BGA652

+3VS
@
C297
1 2

0.1U_0402_16V4Z~D

5
U16 @
PLTRST#_R 1

P
B 4
Y PLTRST# <6,17,19,22,23,24>
2
A

1
TC7SH08FUF_SSOP5

3
R227

100K_0402_5%
1 2

2
R226 0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7M(1/4)HUB,PCI,HOST
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 15 of 40
5 4 3 2 1
 5 4 3 2 1

C49
15P_0402_50V8J
D ICH_RTCX1 D
2 1
+RTCBATT
Y1

1
10M_0402_5%
32.768K_1TJS125BJ4A421P
R214 1M_0402_5% 2 1

R37
1 2 SM_INTRUDER# NC IN
3 4
R216 332K_0402_1% NC OUT U6A
LPC_AD[0..3] <25>

2
1 2 ICH_INTVRMEN C50

RTC
15P_0402_50V8J AB1 AA6 LPC_AD0
2 1 ICH_RTCX2 AB2 RTXC1 LAD0 AB5 LPC_AD1
RTCX2 LAD1 AC4 LPC_AD2
+RTCBATT R217 1 2 ICH_RTCRST# AA3 LAD2 Y6 LPC_AD3
+RTCBATT RTCRST# LAD3

LPC
20K_0402_5%
ICH_INTVRMEN W4 AC3
@ J5 SM_INTRUDER# Y5 INTVRMEN LDRQ0# AA5
1 2 INTRUDER# LDRQ1# / GPIO23
3MM AB3 LPC_FRAME#
LFRAME# LPC_FRAME# <25>
W1
Y1 EE_CS 2 1 R204 10K_0402_5%
2 EE_SHCLK +3VS
C294 C317 EE_DOUT Y2 AE22 GATEA20
EE_DOUT A20GATE GATEA20 <25>

LAN
1U_0603_10V4Z~D W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# <4>

CPU
0.1U_0402_16V4Z~D 1 2
1 V3 AG27
LAN_CLK CPUSLP#
U3 AF24 H_DPRSTP#
LAN_RSTSYNC TP1 / DPRSTP# H_DPSLP# H_DPRSTP# <4,36>
AH25 H_DPSLP# <4>
U5 TP2 / DPSLP# 2 1 56_0402_5%
LAN_RXD0 +VCCP
V4 AG26 H_FERR# R20
LAN_RXD1 FERR# H_FERR# <4>
T5
LAN_RXD2 AG24 H_PWRGOOD
GPIO49 / CPUPWRGD H_PWRGOOD <4>
<20> HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH U7
C
R235 39_0402_5% V6 LAN_TXD0 AG22 H_IGNNE# C
LAN_TXD1 IGNNE# H_IGNNE# <4>
1 2 HDA_BITCLK_ICH V7 AG21
<20> HDA_BITCLK_AUDIO LAN_TXD2 INIT3_3V#
R230 39_0402_5% AF22 H_INIT#
HDA_RST_ICH# INIT# H_INTR H_INIT# <4>
<20> HDA_RST_AUDIO# 1 2 2 AF25 H_INTR <4>
R236 39_0402_5% C389 INTR

AC-97/AZALIA
1 2 HDA_SDOUT_ICH HDA_BITCLK_ICH U1 +VCCP
<20> HDA_SDOUT_AUDIO ACZ_BCLK
R233 39_0402_5% 39P_0402_50V8J HDA_SYNC_ICH R6 AG23 KB_RST#
1 WWAN@ ACZ_SYNC RCIN# KB_RST# <25>

1
1 HDA_RST_ICH# R5 AF23 H_SMI#
ACZ_RST# SMI# H_NMI H_SMI# <4>
C280 AH24 R194
NMI H_NMI <4>
39P_0402_50V8J <20> HDA_SDIN0 T2
WWAN@ T3 ACZ_SDIN0 AH22 H_STPCLK# 56_0402_5%
2 ACZ_SDIN1 STPCLK# H_STPCLK# <4>
T1

2
ACZ_SDIN2 AF26 THRMTRIP_ICH# 1 R196 2
HDA_SDOUT_ICH THERMTRIP# H_THERMTRIP# <4,6>
T4 24.9_0402_1%
ACZ_SDOUT
IDE_DA[0..2] <22>
AH17 IDE_DA0 Layout note: R194 needs to placed
AF18 DA0 AE17 IDE_DA1
SATALED# DA1 within 2" of ICH7, R193 must be placed
AF17 IDE_DA2
DA2 within 2" of R194 w/o stub.
AF3 AE16 IDE_DCS1# IDE_DCS1# <22>
AE3 SATA0RXN DCS1# AD16 IDE_DCS3#
SATA0RXP DCS3# IDE_DCS3# <22>
AG2
SATA0TXN

SATA
AH2 IDE_DD[0..15] <22>
SATA0TXP AB15 IDE_DD0
AF7 DD0 AE14 IDE_DD1
SATA2RXN DD1 IDE_DD2
AE7 AG13
AG6 SATA2RXP DD2 AF13 IDE_DD3
Disable SATA. SATA2TXN DD3
AH6 AD14 IDE_DD4
SATA2TXP DD4 AC13 IDE_DD5
AF1 DD5 AD12 IDE_DD6
AE1 SATA_CLKN DD6 AC12 IDE_DD7
B SATA_CLKP DD7 AE12 IDE_DD8 B

AH10 DD8 AF12 IDE_DD9

AG10 SATARBIASN DD9 AB13 IDE_DD10
+3VS SATARBIASP DD10 AC14 IDE_DD11
DD11 IDE_DD12
AF14
DD12 AH13 IDE_DD13
DD13 AH14 IDE_DD14
4.7K_0402_5% 2 1 R23 IDE_DIORDY IDE_DIORDY AG16
IDE DD14 AC15 IDE_DD15
<22> IDE_DIORDY IORDY DD15
IDE_IRQ AH16
<22> IDE_IRQ IDE_DDACK# IDEIRQ
<22> IDE_DDACK#
AF16
IDE_DIOW# AH15 DDACK# AE15 IDE_DDREQ
<22> IDE_DIOW# DIOW# DDREQ IDE_DDREQ <22>
IDE_DIOR# AF15
<22> IDE_DIOR# DIOR#

ICH7_BGA652

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
ICH7M(2/4)LAN,ATA,LPC,RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 16 of 40
5 4 3 2 1
 5 4 3 2 1

+3VS
Place closely pin B2 Place closely pin AC1

CLK_ICH_48M CLK_ICH_14M
+3VALW +3VALW

1
10K_0402_5% +3VS
R21 1 2 SERIRQ R245 R212

2
2

2
8.2K_0402_5% R55 R56 R207 @ 10_0402_5% @ 10_0402_5%
R22 1 2 PM_CLKRUN# R251 R252 8.2K_0402_5%

2
2.2K_0402_5% 2.2K_0402_5% U6C
D 10K_0402_5% 10K_0402_5% D
1 1

1
ICH_SMBCLK C22 AF19 C355 C275
<12> ICH_SMBCLK

1
ICH_SMBDATA SMBCLK GPIO21 / SATA0GP
<12> ICH_SMBDATA B22 AH18
SMBDATA GPIO19 / SATA1GP

SMB
LINKALERT#

SATA
GPIO
A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 AE19
ICH_SMLINK1 A25 SMLINK0 GPIO37 / SATA3GP
SMLINK1
+3VALW +3VALW
R59 AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M <12>

Clocks
10K_0402_5% 1 2 ICH_RI# A28 B2 CLK_ICH_48M
RI# CLK48 CLK_ICH_48M <12>
R269 1 2 LINKALERT# 8.2K_0402_5%
SB_SPKR A19
<20> SB_SPKR SPKR
10K_0402_5% PAD T4 SUS_STAT# A27 C20 ICH_SUSCLK T16 PAD
SUS_STAT# SUSCLK
R267 1 2 ITP_DBRESET# ITP_DBRESET# A22
SYS_RST#

SYS
B24 PM_SLP_S3#
PM_BMBUSY# SLP_S3# PM_SLP_S4# PM_SLP_S3# <25>
10K_0402_5% AB18 D23 PM_SLP_S4# <25>
<6> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4#
R268 1 2 OCP# F22 PM_SLP_S5#
PM_SLP_S5# <25>
OCP# B23 SLP_S5#
@ 10K_0402_5% GPIO11 / SMBALERT# ICH_POK R24
AA4 ICH_POK <6,25>
R224 1 2 SPI_MISO H_STP_PCI# AC20 PWROK 1 2 10K_0402_5%

POWER MGT
<12> H_STP_PCI# GPIO18 / STPPCI#

GPIO
H_STP_CPU# AF21 AC22 PM_DPRSLPVR
<12> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR <6,36>
@ 10K_0402_5%
R223 1 2 SB_SPI_CS# IDERST_CD# A21 C21 ICH_LOW_BAT#
<22> IDERST_CD# GPIO26 TP0 / BATLOW#
B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# <25>
E23
GPIO28 PLTRST#
1K_0402_5% C19
LAN_RST# PLTRST# <6,15,19,22,23,24>
R241 1 2 ICH_PCIE_WAKE# PM_CLKRUN# AG18
GPIO32 / CLKRUN# EC_RSMRST#
Y4 EC_RSMRST# <25>
8.2K_0402_5% AC19 RSMRST# R26 10K_0402_5%
GPIO33 / AZ_DOCK_EN#
R250 2 1 ICH_LOW_BAT# U2 1 2
GPIO34 / AZ_DOCK_RST#
C @ 10K_0402_5% ICH_PCIE_WAKE# EC_SCI# C
F20 E20
<19> ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# <25>
R222 1 2 SPI_MOSI <25> SERIRQ
SERIRQ AH21 A20 ACIN
ACIN <25,31>
EC_THERM# SERIRQ GPIO10
AF20 F19
<25> EC_THERM# THRM# GPIO12 EC_LID_OUT#
E19
VGATE GPIO13 EC_LID_OUT# <25>
<12,25,36> VGATE AD22 R4
VRMPWRGD GPIO14 E22
GPIO15
R3
AC21 GPIO24 D20 GPIO25
AC18
GPIO6 GPIO GPIO25
AD21
EC_SMI# GPIO7 GPIO35 / SATAREQ#
<25> EC_SMI# E21 AD20
GPIO8 GPIO38
AE20
GPIO39
ICH7_BGA652

U6D
PCIE_PTX_C_IRX_N1 F26 V26 DMI_RXN0
<23> PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PERn1 DMI0RXN DMI_RXP0 DMI_RXN0 <6>
F25 V25
<23> PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_RXP0 <6>
Card Reader <23> PCIE_ITX_C_PRX_N1 C73 2 1 0.1U_0402_10V7K~D PCIE_ITX_PRX_N1 E28 U28 DMI_TXN0 DMI_TXN0 <6>
PETn1 DMI0TXN

DIRECT MEDIA INTERFACE

C75 2 1 0.1U_0402_10V7K~D PCIE_ITX_PRX_P1 E27 U27 DMI_TXP0
<23> PCIE_ITX_C_PRX_P1 PETp1 DMI0TXP DMI_TXP0 <6>
PCIE_PTX_C_IRX_N2 H26 Y26 DMI_RXN1
<19> PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PERn2 DMI1RXN DMI_RXP1 DMI_RXN1 <6>
WLAN <19> PCIE_PTX_C_IRX_P2 H25
PERp2 DMI1RXP
Y25 DMI_RXP1 <6>
C66 2 1 0.1U_0402_10V7K~D PCIE_ITX_PRX_N2 G28 W28 DMI_TXN1
<19> PCIE_ITX_C_PRX_N2 PETn2 DMI1TXN DMI_TXN1 <6>
<19> PCIE_ITX_C_PRX_P2 C67 2 1 0.1U_0402_10V7K~D PCIE_ITX_PRX_P2 G27 W27 DMI_TXP1 DMI_TXP1 <6>
PETp2 DMI1TXP

PCI-EXPRESS
PCIE_PTX_C_IRX_N3 K26 AB26
<24> PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PERn3 DMI2RXN
LAN <24> PCIE_PTX_C_IRX_P3 K25
PERp3 DMI2RXP
AB25
<24> PCIE_ITX_C_PRX_N3 C60 2 1 0.1U_0402_10V7K~D PCIE_ITX_PRX_N3 J28 AA28
PCIE_ITX_PRX_P3 PETn3 DMI2TXN
<24> PCIE_ITX_C_PRX_P3 C64 2 1 0.1U_0402_10V7K~D J27 AA27
B PETp3 DMI2TXP B
M26 AD25
PERn4 DMI3RXN
M25 AD24
L28 PERp4 DMI3RXP AC28
PETn4 DMI3TXN
L27 AC27
PETp4 DMI3TXP
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# <12>
P25 AE27 CLK_PCIE_ICH <12>
PERp5 DMI_CLKP
N28
PETn5
N27
PETp5 DMI_ZCOMP
C25 R243 24.9_0402_1% Within 500 mils
D25 DMI_IRCOMP 1 2
DMI_IRCOMP +1.5VS
T25
PERn6 USB20_N0
T24 F1 USB20_N0 <28>
R28 PERp6 USBP0N F2 USB20_P0
R27
PETn6 USBP0P
G4 USB20_N1 USB20_P0 <28> USB1(Left)
PETp6 USBP1N USB20_P1 USB20_N1 <22>
G3
R2
USBP1P
H1 USB20_N2
USB20_P1 <22> CMOS
SB_SPI_CS# SPI_CLK USBP2N USB20_P2 USB20_N2 <28>
P6 H2
SPI_CS# USBP2P USB20_P2 <28> USB2(Left)
SPI

P1 J4
SPI_ARB USBP3N
J3
SPI_MOSI USBP3P USB20_N4
P5 K1 USB20_N4 <19>
+3VALW SPI_MISO P2 SPI_MOSI USBP4N K2 USB20_P4
USB_OC#6 SPI_MISO USBP4P
L4 USB20_N5
USB20_P4 <19> WiMAX
USB_OC#1 USBP5N USB20_P5 USB20_N5 <19>
L5
USB_OC#3 USB_OC#0 D3
USBP5P
M1 USB20_N6
USB20_P5 <19> WWAN
USB_OC#4 <28> USB_OC#0 USB_OC#1 OC0# USBP6N USB20_P6 USB20_N6 <19>
C4 USB M2
USB_OC#5 1 R247 2 USB_OC#2 D5
OC1# USBP6P
N4 USB20_N7 USB20_P6 <19> BT
<28> USB_OC#2 USB_OC#3 OC2# USBP7N USB20_P7 USB20_N7 <28>
10K_0402_5% D4 N3
USB_OC#4 E5
OC3# USBP7P USB20_P7 <28> USB3(Right)
USB_OC#7 1 R249 2 USB_OC#5 C3 OC4# R242 22.6_0402_1%
10K_0402_5% USB_OC#6 OC5# / GPIO29 USBRBIAS
A2 D2 1 2
USB_OC#0 USB_OC#7 B3 OC6# / GPIO30 USBRBIAS# D1
A USB_OC#2 <28> USB_OC#7 OC7# / GPIO31 USBRBIAS A
1 R248 2 Within 500 mils
10K_0402_5%
ICH7_BGA652

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
ICH7M(3/4)USB,GPIO,PCIE
T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIV ISION OF R&D
Size Docum ent Num ber Rev
Cus tom 0.2
DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, Augus t 08, 2008 Sheet 17 of 40
5 4 3 2 1
 5 4 3 2 1

U6F +VCCP U6E

0.94A A4 P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z~D A23 VSS[0] VSS[98] R1
6mA V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
L12 B1 R11
AD17 Vcc1_05[2] L14 B8 VSS[2] VSS[100] R12
V5REF[2] Vcc1_05[3] 1 VSS[3] VSS[101]
+1.5VS L16 B11 R13
Vcc1_05[4] 1 1 VSS[4] VSS[102]
10mA ICH_V5REF_SUS F6
V5REF_Sus Vcc1_05[5]
L17 C336 C316 + C252 B14
VSS[5] VSS[103]
R14
0.77A L18 B17 R15
0.1U_0402_16V4Z~D Vcc1_05[6] 220U_B2_2.5VM_R35 VSS[6] VSS[104]
AA22 M11 B20 R16
AA23 Vcc1_5_B[1] Vcc1_05[7] M18 2 2 2 B26 VSS[7] VSS[105] R17
1 Vcc1_5_B[2] Vcc1_05[8] VSS[8] VSS[106]
+5VS +3VS AB22 P11 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
C93 + C279 C305 C349 AB23 P18 C2 T6
D 220U_B2_2.5VM_R35 AC23 Vcc1_5_B[4] Vcc1_05[10] T11 1U_0603_10V4Z~D C6 VSS[10] VSS[108] T12 D
1

Vcc1_5_B[5] Vcc1_05[11] VSS[11] VSS[109]

AC24 T18 C27 T13
R237 D21 2 2 2 2 AC25 Vcc1_5_B[6] Vcc1_05[12] U11 D10 VSS[12] VSS[110] T14
Vcc1_5_B[7] Vcc1_05[13] VSS[13] VSS[111]
AC26 U18 D13 T15
100_0402_5% RB751V-40TE17_SOD323-2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D AD26 Vcc1_5_B[8] Vcc1_05[14] V11 D18 VSS[14] VSS[112] T16
AD27 Vcc1_5_B[9] Vcc1_05[15] V12 D21 VSS[15] VSS[113] T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 V14 D24 U4
ICH_V5REF_RUN D26 Vcc1_5_B[11] Vcc1_05[17] V16 E1 VSS[17] VSS[115] U12
Place closely pin Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 D27 V17 E2 U13
C343 D28,T28,AD28. D28 Vcc1_5_B[13] Vcc1_05[19] V18 E4 VSS[19] VSS[117] U14
E24 Vcc1_5_B[14] Vcc1_05[20] E8 VSS[21] VSS[118] U15
1U_0603_10V4Z~D Vcc1_5_B[15] VSS[22] VSS[119]
2
E25
Vcc1_5_B[16] Vcc3_3 / VccHDA
U6 +3VS 56mA E15
VSS[23] VSS[120]
U16
E26 1 F3 U17
Vcc1_5_B[17] C296 VSS[24] VSS[121]
F23
Vcc1_5_B[18] VccSus3_3/VccSusHDA
R7 +3VALW 10mA F4
VSS[25] VSS[122]
U24
F24 +VCCP F5 U25
G22 Vcc1_5_B[19] AE23 0.1U_0402_16V4Z~D F12 VSS[26] VSS[123] U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23
Vcc1_5_B[21] V_CPU_IO[2]
AE26 14mA F27
VSS[28] VSS[125]
V2
H22 AH26 F28 V13
+5VALW +3VALW Vcc1_5_B[22] V_CPU_IO[3] VSS[29] VSS[126]
H23 G1 V15
J22 Vcc1_5_B[23] AA7 G2 VSS[30] VSS[127] V24
+3VS 0.27A 1 1 1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D
J23 Vcc1_5_B[24] Vcc3_3[3] AB12 G5 VSS[31] VSS[128] V27
1

D11 Vcc1_5_B[25] Vcc3_3[4] VSS[32] VSS[129]

K22 AB20 G6 V28

C273

C274

C262
Vcc1_5_B[26] Vcc3_3[5] 1 VSS[33] VSS[130]
R64 @ K23 AC16 C285 G9 W6
Vcc1_5_B[27] Vcc3_3[6] 2 2 2 VSS[34] VSS[131]
L22 AD13 G14 W24
10_0402_5% RB751V-40TE17_SOD323-2 L23 Vcc1_5_B[28] Vcc3_3[7] AD18 0.1U_0402_16V4Z~D G18 VSS[35] VSS[132] W25
M22 Vcc1_5_B[29] Vcc3_3[8] AG12 2 G21 VSS[36] VSS[133] W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] VSS[37] VSS[134]

M23 AG15 G24 Y3
N22 Vcc1_5_B[31] Vcc3_3[10] AG19 G25 VSS[38] VSS[135] Y24
Vcc1_5_B[32] Vcc3_3[11] VSS[39] VSS[136]
1 N23 G26 Y27
C346 P22 Vcc1_5_B[33] A5 H3 VSS[40] VSS[137] Y28
Vcc1_5_B[34] Vcc3_3[12] +3VS VSS[41] VSS[138]
C P23 B13 H4 AA1 C
0.1U_0402_16V4Z~D Vcc1_5_B[35] Vcc3_3[13] VSS[42] VSS[139]
R22 B16 1 1 1 H5 AA24

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
2 R23 Vcc1_5_B[36] Vcc3_3[14] B7 H24 VSS[43] VSS[140] AA25
Vcc1_5_B[37] Vcc3_3[15] VSS[44] VSS[141]
R24 C10 H27 AA26

C353

C345

C354
R25 Vcc1_5_B[38] Vcc3_3[16] D15 H28 VSS[45] VSS[142] AB4
R26 Vcc1_5_B[39] Vcc3_3[17] F9 2 2 2 J1 VSS[46] VSS[143] AB6
+3VS Vcc1_5_B[40] Vcc3_3[18] VSS[47] VSS[144]
T22 G11 J2 AB11
T23 Vcc1_5_B[41] Vcc3_3[19] G12 J5 VSS[48] VSS[145] AB14
Vcc1_5_B[42] Vcc3_3[20] VSS[49] VSS[146]
T26 G16 J24 AB16
T27 Vcc1_5_B[43] Vcc3_3[21] J25 VSS[50] VSS[147] AB19
T28 Vcc1_5_B[44] W5 J26 VSS[51] VSS[148] AB21
1 Vcc1_5_B[45] VccRTC +RTCBATT VSS[52] VSS[149]
C356 U22 K24 AB24
U23 Vcc1_5_B[46] P7 K27 VSS[53] VSS[150] AB27
Vcc1_5_B[47] VccSus3_3[1] +3VALW 45mA VSS[54] VSS[151]
0.1U_0402_16V4Z~D V22 1 1 1 1 K28 AB28

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
2 V23 Vcc1_5_B[48] A24 C332 C347 L13 VSS[55] VSS[152] AC2

C289

C292
W22 Vcc1_5_B[49] VccSus3_3[2] C24 L15 VSS[56] VSS[153] AC5
Vcc1_5_B[50] VccSus3_3[3] 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D VSS[57] VSS[154]
W23 D19 L24 AC9
Y22 Vcc1_5_B[51] VccSus3_3[4] D22 2 2 2 2 L25 VSS[58] VSS[155] AC11
Vcc1_5_B[52] VccSus3_3[5] VSS[59] VSS[156]
Place closely pin AG28 within 100mlis. Y23
Vcc1_5_B[53] VccSus3_3[6]
G19 L26
VSS[60] VSS[157]
AD1
M3 AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL B27 K3 M4 VSS[61] VSS[158] AD4
R189 R186 Vcc3_3[1] VccSus3_3[7] +3VALW VSS[62] VSS[159]
50mA VccSus3_3[8]
K4 1 1 M5
VSS[63] VSS[160]
AD7
1 2 1 2 +1.5VS_DMIPLL AG28 K5 C333 C339 M12 AD8
VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
K6 M13 AD11
10U_0805_10V4Z~D

0.01U_0402_25V7K~D

0.5_0805_1% 0_0805_5% AB7 VccSus3_3[10] L1 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D M14 VSS[65] VSS[162] AD15
1 1 +1.5VS Vcc1_5_A[1] VccSus3_3[11] VSS[66] VSS[163]
0.64A AC6 L2 2 2 M15 AD19
C272

Vcc1_5_A[2] VccSus3_3[12] VSS[67] VSS[164]

AC7 L3 M16 AD23
C271

AD6 Vcc1_5_A[3] VccSus3_3[13] L6 M17 VSS[68] VSS[165] AE2

1 Vcc1_5_A[4] VccSus3_3[14] VSS[69] VSS[166]
2 2 C282 AE6 L7 M24 AE4
AF5 Vcc1_5_A[5] VccSus3_3[15] M6 M27 VSS[70] VSS[167] AE8
B 0.1U_0402_16V4Z~D AF6 Vcc1_5_A[6] VccSus3_3[16] M7 M28 VSS[71] VSS[168] AE11 B
2 Vcc1_5_A[7] VccSus3_3[17] VSS[72] VSS[169]
AG5 N7 N1 AE13
AH5 Vcc1_5_A[8] VccSus3_3[18] N2 VSS[73] VSS[170] AE18
Vcc1_5_A[9] VSS[74] VSS[171]
Connected +1.5VS directly Vcc1_5_A[19]
AB17 +1.5VS N5
VSS[75] VSS[172]
AE21
+1.5VS Place closely pin AG5. AD2 AC17 N6 AE24
when disable SATA. VccSATAPLL Vcc1_5_A[20] N11 VSS[76] VSS[173] AE25
VSS[77] VSS[174]
+3VS AH11 T7 N12 AF2
Vcc3_3[2] Vcc1_5_A[21] F17 N13 VSS[78] VSS[175] AF4
Vcc1_5_A[22] VSS[79] VSS[176]
1 AB10 G17 N14 AF8
0.1U_0402_16V4Z~D

+1.5VS Vcc1_5_A[10] Vcc1_5_A[23] VSS[80] VSS[177]

AB9 N15 AF11
AC10 Vcc1_5_A[11] AB8 1 2 N16 VSS[81] VSS[178] AF27
C263

1 Vcc1_5_A[12] Vcc1_5_A[24] VSS[82] VSS[179]

C269 AD10 AC8 N17 AF28
2 AE10 Vcc1_5_A[13] Vcc1_5_A[25] C284 0.1U_0402_16V4Z~D N18 VSS[83] VSS[180] AG1
1U_0603_10V4Z~D Vcc1_5_A[14] ICH_K7 VSS[84] VSS[181]
2
AF10
Vcc1_5_A[15] VccSus1_05[1]
K7 PAD T11 17mA N24
VSS[85] VSS[182]
AG3
AF9 N25 AG7
AG9 Vcc1_5_A[16] C28 ICH_C28 N26 VSS[86] VSS[183] AG11
Vcc1_5_A[17] VccSus1_05[2] PAD T3 VSS[87] VSS[184]
AH9 G20 ICH_G20 PAD T14 P3 AG14
Vcc1_5_A[18] VccSus1_05[3] P4 VSS[88] VSS[185] AG17
VSS[89] VSS[186]
+3VALW Place closely pin AG9. E3
VccSus3_3[19] Vcc1_5_A[26]
A1 +1.5VS P12
VSS[90] VSS[187]
AG20
1 H6 P13 AG25
C340 C1 Vcc1_5_A[27] H7 P14 VSS[91] VSS[188] AH1
+1.5VS 10mA VccUSBPLL Vcc1_5_A[28] 1 VSS[92] VSS[189]
1 J6 C344 P15 AH3
0.1U_0402_16V4Z~D C350 ICH_AA2 AA2 Vcc1_5_A[29] J7 P16 VSS[93] VSS[190] AH7
2 T2 PAD VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] VSS[94] VSS[191]
ICH_Y7 Y7 0.1U_0402_16V4Z~D P17 AH12
T6 PAD VccSus1_05/VccLAN1_05[2] 2 VSS[95] VSS[192]
0.1U_0402_16V4Z~D P24 AH23
2 V5 P27 VSS[96] VSS[193] AH27
VccSus3_3/VccLAN3_3[1] VSS[97] VSS[194]
V1
W2 VccSus3_3/VccLAN3_3[2] ICH7_BGA652
VccSus3_3/VccLAN3_3[3]
+3VS W7
VccSus3_3/VccLAN3_3[4]
A ICH7_BGA652 A
1
C291

0.1U_0402_16V4Z~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
ICH7M(4/4)POWER/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, Augus t 08, 2008 Sheet 18 of 40
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN(middle of M/B)

+3VS_WLAN +1.5VS

0.1U_0402_16V4Z~D
1 1 1 1 1
C195 C98 C121 C118 C113

4.7U_0805_10V4Z~D 0.1U_0402_16V4Z~D 4.7U_0805_10V4Z~D 0.01U_0402_25V7K~D

1 2 2 2 2 2 1

JP19
ICH_PCIE_WAKE# 1 2 +3VS_WLAN R62 1 2 0_0805_5%
<17> ICH_PCIE_WAKE# 1 2 +3VS
BT_ACTIVE R118 1 @ 2 0_0402_5% 3 4
WLAN_ACTIVE R116 1 @ 2 0_0402_5% 5 3 4 6
5 6 +1.5VS
<12> WLAN_CLKREQ# WLAN_CLKREQ# 7 8
9 7 8 10
11 9 10 12
<12> CLK_PCIE_WLAN# 11 12
<12> CLK_PCIE_WLAN
13 14
15 13 14 16
17 15 16 18
19 17 18 20 WL_OFF#
19 20 WL_OFF# <25>
21 22 PLTRST#
21 22 PLTRST# <6,15,17,22,23,24>
<17> PCIE_PTX_C_IRX_N2 23 24 1 2 +3VS
25 23 24 26 R83 0_0402_5%
<17> PCIE_PTX_C_IRX_P2 25 26
27 28 1 2 +3VALW
29 27 28 30 R348 @ 0_0402_5%
31 29 30 32
<17> PCIE_ITX_C_PRX_N2 31 32
33 34
<17> PCIE_ITX_C_PRX_P2 33 34
35 36 USB20_N4 <17>
37 35 36 38
37 38 USB20_P4 <17>
+3VS_WLAN 39 40
1 2 41 39 40 42
43 41 42 44
0.1U_0402_16V4Z~D C222 45 43 44 46
45 46
47 48
EC_TX_P80_DATA 49 47 48 50
<25,27> EC_TX_P80_DATA EC_RX_P80_CLK 49 50
<25,27> EC_RX_P80_CLK 51 52
51 52
2 2
53 54
GND1 GND2

ACES_88910-5204
ME@

+5VS

BT MODULE CONN

2
R253
Mini-Express Card for WWAN +3VS +3VS_WWAN
+3VS_WWAN
10K_0402_5%
BT@

1 1
(near by Audio Jack) J6 @
WWAN@

C191

@ C106
39P_0402_50V8J

39P_0402_50V8J

39P_0402_50V8J

39P_0402_50V8J
2 1 JOPEN @ 1 @ 1 1 2 @ 1 @ 1

10U_0805_10V4Z~D
1 2 Q21
R65 @ 0_1206_5% BT@

0.1U_0402_16V4Z~D
C165

C171

C168

C172
<25> BT_OFF#
2
JP17 2 2 2 1 2 2 +3VS +3VS_BT
1 2 BT@
3 1 2 4 DTC124EK_SC59 Q20 BT@
5 3 4 6 C348
For EMI request

3
5 6

D
7 8 +UIM_PWR 3 1 2 1
9 7 8 10 UIM_DATA AO3413_SOT23
+3VS_WWAN 11 9 10 12 UIM_CLK 0.1U_0402_16V4Z~D
@ 11 12 UIM_RST
13 14

G
2
0.1U_0402_16V4Z~D 15 13 14 16 UIM_VPP
15 16 +3VS_BT
1 WWAN@ 1 1 1 17
17 18
18
C149 WWAN@ C185 C186 19 20 WXMIT_OFF#
C105 WWAN@ 21 19 20 22
0.1U_0402_16V4Z~D 0.01U_0402_25V7K~D 23 21 22 24 1 @ 2
3 2 2 2 2 23 24 +3VS_WWAN 3
25 26 R93 0_0402_5%
10U_0805_10V4Z~D 27 25 26 28 JP10
29 27 28 30 1
31 29 30 32 2 1
+3VS_WWAN 31 32 USB20_N6 2
33 34 <17> USB20_N6 3
35 33 34 36 USB20_P6 4 3
35 36 USB20_N5 <17> <17> USB20_P6 4
37 38 BT_ACTIVE 5
37 38 USB20_P5 <17> WLAN_ACTIVE 5
10U_0805_10V4Z~D 39 40 6
1 2 41 39 40 42 7 6
@ 43 41 42 44 8 7
C226 45 43 44 46 9 8
D7 @ 47 45 46 48 10 GND1
49 47 48 50 GND2
CM1293-04SO_SOT23-6 <25,27> EC_TX_P80_DATA
51 49 50 52 MOLEX_53780-0870
<25,27> EC_RX_P80_CLK 51 52
1 4 ME@
CH1 CH4 53 54
GND1 GND2
+3VS
2 5 ACES_88910-5204
Vn Vp ME@

3 6
CH2 CH3 +3VS
@ D16
JP5 2
4 1 +UIM_PWR 1
UIM_VPP 5 GND VCC 2 UIM_RST 3
UIM_DATA 6 VPP RST 3 UIM_CLK
7 I/O CLK DAN217T146_SC59-3
DET
1U_0603_10V4Z~D

0.1U_0402_16V4Z~D

1 1
1

4 4
WWAN@
C264
10K_0402_5%

8 @
R25

C258

GND
9
@ GND 2 2
2

+UIM_PWR
TAITW_PMPAT6-06GLBS7N14N0 ME@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/05 Deciphered Date 2007/08/05 Title
Reserve for SIM card does not meet rise time Mini-Card/BT CONN
WXMIT_OFF#
and pull-up is needed. <25> WXMIT_OFF# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 19 of 40
A B C D E
 A B C D E

AC97 Codec
+VDDA
+5VS +5VAMP
(output = 150 mA)

1
FBMA-L11-201209-221LMA30T_0805 U20
R149 1 2 60mil 1 40mil
10K_0402_5% L15 IN 5
OUT +VDDA
2 4.75V
GND
1 1

1U_0603_10V6K~D
2 1 C216 C372 3 4 1
SHDN BYP

1U_0603_10V6K~D
C373
1
1U_0603_10V4Z~D +VDDA 10U_0805_10V4Z APL5151-475BC-SOT23-5 4.75V LDO

C387
C217 1
0.1U_0402_16V4Z~D @ 2 2 C385
1
R152 1 2 0.01U_0402_25V7K~D 2 1
10K_0402_5%

1
C212 1U_0603_10V4Z~D 2

2
1 2MONO_IN1 2 1 MONO_IN R148
R153 20K_0402_5% 10K_0402_5%
1 2
R155 R151 20K_0402_5%

2
C218 560_0402_5% C C213 680P_0402_50V7K~D LINE_OUTL
<25> BEEP# 2 1 1 2 2 Q13
1 B 2SC2411KT146_SOT23-3 C210 680P_0402_50V7K~D LINE_OUTR

1
C220 1U_0603_10V4Z~D E

3
@ R150
0.1U_0402_16V4Z~D 10K_0402_5%
2 R156
C219 560_0402_5% +MIC2_VREFO +MIC1_VREFO_L +AUD_VREF

2
<17> SB_SPKR 2 1 1 2
1

1
1U_0603_10V4Z~D D13
10mil 10mil 10mil
R154 1 1 1
@ @ @
@ 10K_0402_5% RB751V_SOD323 C180 C183 C178
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2

2 2 2

GNDA GNDA GNDA

HD Audio Codec
2 +AVDD_AC97 +VDDC 2
L9
L10 1 2 0.1U_0402_16V4Z~D
40mil 20mil 0.1U_0402_16V4Z~D 1 2
+VDDA +3VS
FBM-L11-160808-800LMT_0603 1 1 FBM-L11-160808-800LMT_0603
C192 C160 1 1
C173 C187

C190
C164
2 2 4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D 2 2

0.1U_0402_16V4Z~D

25

38

9
U13 1 2
C170 @ 1000P_0402_50V7K~D

DVDD
AVDD1

AVDD2

DVDD_IO
1 2
C174 @ 1000P_0402_50V7K~D

14 35 C_LINE_OUTL 21 LINE_OUTL
NC LINE_OUT_L LINE_OUTL <21>
C176 1U_0603_10V4Z~D
15 36 C_LINE_OUTR 1 2 LINE_OUTR
NC LINE_OUT_R LINE_OUTR <21>
R145 C166 1U_0603_10V4Z~D
1 2 1 2 16 39 C156 2 1 HP_L
<21> INT_MIC MIC2_L HP_OUT_L HP_L <21>
1K_0402_5% C206 2.2U_0603_6.3V6K~D 2.2U_0603_6.3V6K~D
1 2 17 41 C157 2 1 HP_R HP_R <21>
C207 2.2U_0603_6.3V6K~D MIC2_R HP_OUT_R 2.2U_0603_6.3V6K~D
23 45 X5R for audio
LINE1_L NC
performance considering
24 46
LINE1_R DMIC_CLK
18 43
CD_L NC
20 44
3 CD_R NC 3
X5R for audio
performance considering 19 HDA_BITCLK_AUDIO <16>
R146 CD_GND 6
1 2 EXT_MIC_R
2 1 C203 C_MIC 21 BIT_CLK 2 R107 1 C177 1 2
<21> EXT_MIC MIC1_L
1K_0402_5% 2.2U_0603_6.3V6K~D @ 10_0402_5% @ 10P_0402_50V8J
2 1 C204 22 8 1 2 HDA_SDIN0 <16>
2.2U_0603_6.3V6K~D MIC1_R SDATA_IN R113 39_0402_5%
MONO_IN 12 37
PCBEEP MONO_OUT
29
11 LINE1_VREFO
<16> HDA_RST_AUDIO# RESET# 31
10 GPIO1
<16> HDA_SYNC_AUDIO SYNC 28 10mil +MIC1_VREFO_L
MIC1_VREFO_L
<16> HDA_SDOUT_AUDIO 5
SDATA_OUT 32
2 MIC1_VREFO_R 10mil +AUD_VREF
3 GPIO0 30
R134 1 2 20K_0402_1% 13 GPIO3 MIC2_VREFO 10mil +MIC2_VREFO
<21> JACK_PLUG_MIC JACK_PLUG 1 2 R133 34 SENSE A 27 ACZ_VREF 10mil
<21> JACK_PLUG SENSE B VREF
1 2 39.2K_0402_1% 1 1
R79 0_0603_5% EAPD 1 2 47 40 ACZ_JDREF C184 C188
<25> EAPD EAPD JDREF
R92 0_0402_5% @
48
SPDIFO NC
33 1 10U_0805_10V4Z~D 0.1U_0402_16V4Z~D
1 2 2 2
R281 0_0603_5% 4 26 R85
7 DVSS1 AVSS1 42 20K_0402_1%
DVSS2 AVSS2
Close to codec
2

1 2 ALC268-VB-GR_LQFP48
R313 0_0603_5%
DGND AGND
4 4

DGND AGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
ALC268-VB-GR Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 20 of 40
A B C D E
 A B C D E

+3VS
APA2057A SPK/HP Amplifier +5VAMP

W=40mil Close to Speaker CONN for ESD.

1 1 1
C375 C383 C369

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

2
2 2 2 D17 D18
1 PSOT24C_SOT23-3 PSOT24C_SOT23-3 1

11

19

20
10
R312 @ 1.5K_0402_1%

1
fo=1/(2*3.14*R*C)=106Hz 1 2 U19
R=1.5K / C= 1uF R311 @ 1.5K_0402_1%

CVDD

HVDD

PVDD
PVDD

VDD
1 2

<20> LINE_OUTR 1 R306 2

0_0402_5% INR_A 3 22 SPKR+
<20> LINE_OUTL 1 R308 2 INL_A 5
INR_A
INL_A
ROUT+
ROUT-
21 SPKR- Speaker
0_0402_5%
R293 1 2 100K_0402_5% AMP_EN# 27 8 SPKL+
/AMP EN LOUT+
LOUT-
9 SPKL- Speaker
R294 1 2 100K_0402_5% HP_EN 24
+5VAMP HP EN 17 HP_ROUT JP6
<20> HP_R
HP_R 1 2 INR_H 4
INR_H
HP_R
HP_L
18 HP_LOUT Headphone ACES_87213-0400G
R307 30K_0402_5% INL_H 6 SPKL+ R225 1 2 0_0402_5% SPK_L1+ 4 6
HP_L 1 2 INL_H SPKL- R219 1 2 0_0402_5% SPK_L1- 3 4 GND 5
<20> HP_L CVSS SPKR+ SPK_R1+ 3 GND
R309 30K_0402_5% 26 15 R205 1 2 0_0402_5% 2
EC_MUTE# SET/SD CVSS SPKR- R195 0_0402_5% SPK_R1- 2
16 1 2 1
28 VSS 1
BEEP 2 ME@
20mil
1 2
AMP_CP+
AMP_CP-
12
14 CP+
GND
PGND
23
7
1
C376
Speaker Conn.
CP- PGND

@ C306

@ C290

@ C270

@ C268
C384 1U_0603_10V4Z~D 13
AMP_BIAS 25 CGND 1U_0603_10V4Z~D
BIAS 1 1 1 1
C366 2.2U_0603_6.3V6K~D 29 2
2 1 GND

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
C374 0.1U_0402_16V4Z~D
APA2057RI-TRL_TSSOP28 2 2 2 2
@

IN_A Gain = 10dB (Internal Speaker)

2 2
IN_H Gain = 0dB (Headphone)

1
R197
0_0402_5%
@

2
+5VAMP Audio Jack
1

+MIC1_VREFO_L
R291
47K_0402_5%
MIC IN

1
2

EC_MUTE# EC_MUTE# (Up side)

<25> EC_MUTE#
R87
3K_0402_5% JP13
1

2
EXT_MIC 1 2 EXT_MIC_L-2 2
<20> EXT_MIC
L8 FBM-11-160808-700T_0603 6
1 3
1
C158 C159 4
47P_0402_50V8J~D @
2GNDA 10P_0402_50V8J 1 1 GNDA 5
3 2 C130 C362 3
GNDA @ @ SINGA_2SJ-S351-012
470P_0402_50V7K~D 470P_0402_50V7K~D ME@
2 2

+MIC2_VREFO JACK_PLUG_MIC
<20> JACK_PLUG_MIC
ESD request.
1

R305 HEADPHONE
3K_0402_5% (Down side)
INT MIC
2

JP15
JMIC1 R135 47_0402_5% L11 FBM-11-160808-700T_0603 L12 FBMA-L11-160808-700LMT 1
INT_MIC 1 HP_LOUT 1 2 1 2 PL-OUT 1 2 2
<20> INT_MIC 1
GNDA 2 R143 47_0402_5% L17 FBMA-L11-160808-700LMT 6
2 HP_ROUT 1 2 1 2 PR-OUT 1 2 3
1 3 L16 FBM-11-160808-700T_0603
3

4 GND 4
C386 GND
1

47P_0402_50V8J~D D23 MOLEX_53780-0270 1 5

2 PSOT24C_SOT23-3 ME@ @ @ C211
1 1

2
GNDA R136 R144 C208 C209 @ SINGA_2SJ-S351-013
1K_0402_5% 1K_0402_5% 10P_0402_50V8J 10P_0402_50V8J ME@ R283
1

470P_0402_50V7K~D 2 0_0603_5%
2

GNDA 2 GNDA 2 GNDA

GNDA ESD request.

1
4 4
JACK_PLUG
<20> JACK_PLUG

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/05 Deciphered Date 2007/08/05 Title
AMP/VR/Audio Jack/MIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 21 of 40
A B C D E
 A B C D E F G H

1 1

LED
CMOS Camera CONN
+5VS

1
CMOS@
C3
0.1U_0402_16V4Z~D
2

JP1
1 R157 LED2 White
USB20_N1 2 1 2 1 2 1
<17> USB20_N1 2 +5VALW PWR_LED# <25>
<17> USB20_P1 USB20_P1 3 475_0402_1%
4 3 HT-F196BP5_WHITE

2
5 4
@ 5
6
D2 7 GND1 R158 LED1
PSOT24C_SOT23-3 GND2 Amber
+3VALW 2 1 2 1 CHARGE_LED1# <25>
ACES_88266-05001 300_0402_5%
2 2
ME@ HT-191UD-DT_AMBER_0603

1
SSD CONN (near by CRT)

IDE_DD[0..15]
<16> IDE_DD[0..15]

JP16
IDE_DD0 1 2 IDE_DD15
IDE_DD1 3 1 2 4
IDE_DD2 5 3 4 6 IDE_DD14
IDE_DD3 7 5 6 8 IDE_DD13
7 8 IDE_DD12
9 10
IDE_DD4 11 9 10 12 IDE_DD11
IDE_DD5 13 11 12 14 IDE_DD10
15 13 14 16 IDE_DD9
IDE_DD6 17 15 16 18
IDE_DD7 19 17 18 20 IDE_DD8 0_0402_5% @2 1 R231
3 19 20 IDERST_CD# <17> 3
21 22 33_0402_5% 2 1 R229
21 22 IDE_DIOW# PLTRST# <6,15,17,19,23,24>
23 24 IDE_DIOW# <16>
25 23 24 26
27 25 26 28 IDE_DIOR#
27 28 IDE_DIOR# <16>
29 30 IDE_DDACK#
29 30 IDE_DDACK# <16>
31 32 IDE_DDREQ
31 32 IDE_DDREQ <16>
33 34
35 33 34 36
IDE_DA0 37 35 36 38
<16> IDE_DA0 37 38
IDE_DA1 39 40
<16> IDE_DA1 39 40
IDE_DA2 41 42 IDE_DIORDY
<16> IDE_DA2 41 42 IDE_DIORDY <16>
43 44 IDE_IRQ
43 44 IDE_DCS1# IDE_IRQ <16>
45 46 IDE_DCS1# <16>
47 45 46 48 IDE_DCS3#
47 48 IDE_DCS3# <16>
49 50
51 49 50 52 +3VS
+3VS 51 52
1 1 53 54
GND1 GND2
0.1U_0402_16V4Z~D

C390 C391

4.7U_0805_10V4Z~D FOX_AS0B226-S56N-7F IDE_IRQ R36 1 2 8.2K_0402_5%

2 2 ME@
Close to connector

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SSD,CMOS CONN\LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 22 of 40
A B C D E F G H
 5 4 3 2 1

D D

+CR1_POWER

U18 1 R284 2 0_0402_5%

(20mil) @
CLK_PCIE_CARD# 3 5 +1.8VS_CARD 58mA
<12> CLK_PCIE_CARD# APCLKN APVDD
CLK_PCIE_CARD 4 10 JREAD1
<12> CLK_PCIE_CARD APCLKP APV18 MDIO6 MDIO9
30 +3VS 1mA 33 23
PCIE_ITX_C_PRX_N1 9 TAV33 MDIO3 8 xD-WP SD-DAT5 14 MDIO0
<17> PCIE_ITX_C_PRX_N1 APRXN xD-D3 SD-DAT0
PCIE_ITX_C_PRX_P1 8 19 +3VS 45mA MDIO2 9 25 MDIO4
<17> PCIE_ITX_C_PRX_P1 APRXP DV33 xD-D2 SD-CMD MDIO3
20 29
PCIE_PTX_C_IRX_N1 C367 2 1 0.1U_0402_10V7K~D PCIE_C_RXN1 11 DV33 44 MDIO3 24 SD-DAT3 12 MDIO1
<17> PCIE_PTX_C_IRX_N1 APTXN DV33 MS-DATA3 SD-DAT1
<17> PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_P1 C365 2 1 0.1U_0402_10V7K~D PCIE_C_RXP1 12 18 +1.8VS_CARD 25mA MDIO8 27
APTXP DV18 37 MDIO2 30 SD-DAT4
1 R295 2 PREXT 7 DV18 CR1_CD0N 1 SD-DAT2 26 MDIO5
+3VS 9.1K_0402_1% APREXT MDIO0 MDIO6 SD-CD MS-SCLK MDIO4
(12mil) MDIO0
48 2
SD-WP MS-BS
13
47 MDIO1 22 CR1_CD1N
38 MDIO1 46 MDIO2 MDIO0 32 MS-INS 28
T18 39 PCIES_EN MDIO2 45 MDIO3 MDIO9 6 xD-D0 MS-VCC 15 MDIO1
PAD PCIES JMB385 MDIO3
MDIO4
43 MDIO4 MDIO8 7
xD-D5
xD-D4
MS-DATA1
MS-DATA2
19 MDIO2
42 MDIO5_R 1 R303 2 MDIO5 MDIO10 5 17 MDIO0
MDIO5 41 MDIO6 22_0402_5% MDIO4 34 xD-D6 MS-DATA0
+3VS MDIO6 MDIO7 xD-WE MDIO5
40 3 20
MDIO7 29 MDIO8 MDIO11 4 xD-VCC SD-CLK 18 MDIO10
PLTRST# 1 MDIO8 28 MDIO9 MDIO5 37 xD-D7 SD-DAT6 16 MDIO11
<6,15,17,19,22,24> PLTRST# XRSTN MDIO9 xD-CE SD-DAT7
1 R286 2 4.7K_0402_5% CR1_CD0N GND 2 27 MDIO10 MDIO12 38 21
XTEST MDIO10 26 MDIO11 MDIO1 10 xD-RE SD-VCC
1 R287 2 4.7K_0402_5% CR1_CD1N MDIO11 25 MDIO12 MDIO7 36 xD-D1 31
13 MDIO12 23 MDIO13 MDIO14 35 xD-CLE 7IN1-GND 11
C T17 SEEDAT MDIO13 MDIO14 MDIO13 xD-ALE 7IN1-GND C
14 22 39
PAD SEECLK MDIO14 XDCD# 40 xD-R/B
34 xD-CD
CR1_CD1N NC
JMB385 Operation Modes 15 35 41
CR1_CD0N 16 CR1_CD1N NC 36 GND 42
CR1_CD0N NC GND
Normal
6 GND TAITW_R015-A10-LM_NR
+CR1_PCTLN 17 APGND ME@
XTEST 0 CR1_PCTLN 24
GND 31
CR1_CD0N X GND
21 32
CR1_LEDN GND D22
CR1_CD1N X 33
GND CR1_CD1N 2
1 XDCD#
CR1_CD0N 3
JMB385-LGEZ0A_LQFP48_7X7 1
C388
+CR1_POWER DAN202UT106_SC70-3
@ @ 0.1U_0402_10V7K~D
2
1 R301 2 10K_0402_5% MDIO6

1 R289 2 10K_0402_5% MDIO13

+3VS
SD,MMC,MS,XD muti-function pin define
MDIO SD Card MMC Card MS Card XD Card
1 R300 2 10K_0402_5% MDIO7
PIN Name PIN Name PIN Name PIN Name PIN Name
1 R292 2 200K_0402_5% MDIO12 +1.8VS_CARD MDIO00 SD_DAT0 MMC_DAT0 MS_DAT0 XD_DAT0
B 1 R288 2 200K_0402_5% MDIO14 B
MDIO01 SD_DAT1 MMC_DAT1 MS_DAT1 XD_DAT1
MDIO02 SD_DAT2 MMC_DAT2 MS_DAT2 XD_DAT2
1 1 @
C381 0.1U_0402_16V4Z~D MDIO03 SD_DAT3 MMC_DAT3 MS_DAT3 XD_DAT3
1 C380 1
10U_0805_10V4Z~D C368 MDIO04 SD_CMD MMC_CMD MS_BS XD_WE#
2 C364 2
0.1U_0402_16V4Z~D 1000P_0402_50V7K~D MDIO05 SDCLK1 MMCCLK MSCCLK XD_CE#
2 2
MDIO06 SD_WP# MMC_WP# XD_WP#
MDIO07 XD_CLE
MDIO08 MMC_DAT4 MS_DAT4 XD_DAT4
MDIO09 MMC_DAT5 MS_DAT5 XD_DAT5
+CR1_POWER MDIO10 MMC_DAT6 MS_DAT6 XD_DAT6
+CR1_PCTLN 1 R299 2 +CR1_POWER +1.8VS_CARD +3VS
MDIO11 MMC_DAT7 MS_DAT7 XD_DAT7
0_0805_5%
1 1 MDIO12 XD_RE#
C379
C370 MDIO13 XD_R/B#
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 1 1 1 1 @ 1
2 2 C378 C363 C371 C382 MDIO14 XD_ALE
C377 @
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 2 2 2

A A
Use 0805 type and over 0.1U_0402_16V4Z~D
20 mils trace width on Cardreader contactor not support MMC & MS
both side Bit 4~7
C377 place close to pin5 (Trace
width/length: 20mil/ <120mil).
Card Reader power circuit Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Carder JMB385
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 23 of 40
5 4 3 2 1
 A B C D E

1 2 +3V_LAN
R17 3.6K_0402_5%

U3 @
LAN_DO 4 5 2
LAN_DI DO GND
3 6 C32
LAN_SK_LAN_LINK# DI NC @
2 7
LAN_CS SK NC
1 8 +3V_LAN
CS VCC 1
AT93C46DN-SH-T_SO8 0.1U_0402_16V4Z~D

2 1
R15 10K_0402_5%
4 4
Close to Pin10,13,30,36 +LAN_VDD12
Close to Pin1,37,29
Place Close to Chip U14 +3V_LAN
0.1U_0402_16V4Z~D
<17> PCIE_PTX_C_IRX_P3 C19 2 1 0.1U_0402_10V7K~D PCIE_PTX_IRX_P3 20 33 LAN_DO 0.1U_0402_16V4Z~D
HSOP LED3/EEDO 34 LAN_DI
LED2/EEDI/AUX 2 2 2 2
<17> PCIE_PTX_C_IRX_N3 C18 2 1 0.1U_0402_10V7K~D PCIE_PTX_IRX_N3 21 35 LAN_SK_LAN_LINK# C9 C6 C27 C26 2 2 2
HSON LED1/EESK LAN_CS
32 C5 C28 C21
EECS 0.1U_0402_16V4Z~D
<17> PCIE_ITX_C_PRX_P3 15
HSIP LAN_ACTIVITY# 1 1 1 1
38
LED0 1 1 1
<17> PCIE_ITX_C_PRX_N3 16
HSIN LAN_MDI0+
RTL8102EL 2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
MDIP0 LAN_MDI0-
<12> CLK_PCIE_LAN 17 3
REFCLK_P MDIN0 LAN_MDI1+
<12> CLK_PCIE_LAN# 18 5 0.1U_0402_16V4Z~D
REFCLK_M MDIP1 LAN_MDI1-
6
25 MDIN1 8
<12> CLKREQ_LAN# CLKREQB NC
9 Close to Pin48
27 NC 11
<6,15,17,19,22,23> PLTRST# PERSTB NC
12 Close to Pin45
NC
R4 1 2 2.49K_0402_1% 46 4
RSET NC
26 48 VCTRL12 VCTRL12 0.1U_0402_16V4Z~D +LAN_VDD12
<25> LAN_WAKE# LANWAKEB VCTRL12A
ISOLATEB 28
ISOLATEB
+3V_LAN 2 1 19 +EVDD12 1 2
10K_0402_5% LAN_X1 41 VDDTX 30 @ C8
CKXTAL1 DVDD12 +LAN_VDD12
R11 LAN_X2 42 36 C227 2 1
CKXTAL2 DVDD12 13
DVDD12 2 1 C10 C14
10
DVDD12 @ 10U_0805_10V4Z~D
+3VS 39 10U_0805_10V4Z~D 1 2
NC
0.1U_0402_16V4Z~D
3 3
23 44
NC NC
1

24 45 +LAN_VDD12
NC VCTRL12D
R14
1K_0402_5% 7 29 +3V_LAN
GND VDD33
14 37 Close to Pin19
31 GND VDD33
2

ISOLATEB GND +EVDD12

47 1
GND AVDD33 40
NC
22 43
GNDTX NC
R12
15K_0402_5% RTL8102EL-GR_LQFP48_7X7 2 2
C11 C17

0.1U_0402_16V4Z~D
1 1
Y3
LAN_X1 1 2 LAN_X2 1U_0603_10V4Z~D

1 25MHZ_20P 1
C230 C229

30P_0402_50V8J 30P_0402_50V8J
2 2
For EMI.
C221 @
2 1 470P_0402_50V7K~D

T1 JRJ1
+3V_LAN 12
2 LAN_MDI1+ RJ45_MIDI1+ Yellow LED+ 2
1 16
LAN_MDI1- 2 RD+ RX+ 15 RJ45_MIDI1- LAN_ACTIVITY# R1 2 1 300_0402_5% 13
LAN_CT0 RD- RX- RJ45_CT0 Yellow LED-
C225 1 2 0.01U_0402_25V7K~D 3 14 R162 75_0402_5% 1 15
4 CT CT 13 2 1 8 SHLD1
NC NC C1 PR4-
5 12 2 1
C223 1 2 0.01U_0402_25V7K~D LAN_CT1 6 NC NC 11 RJ45_CT1 R161 75_0402_5% @ 68P_0402_50V8K 7
LAN_MDI0+ CT CT RJ45_MIDI0+ 2 PR4+
7 10 1
LAN_MDI0- TD+ TX+ RJ45_MIDI0- RJ45_MIDI1-
8 9 C224 6
TD- TX- PR2-
1000P_1206_2KV7K 5
2 PR3-
350uH_NS0013LF
4
PR3+
RJ45_MIDI1+ 3
PR2+
RJ45_MIDI0- 2
PR1-
2
RJ45_MIDI0+ 1
PR1+
@C2
@ C2 14
68P_0402_50V8K SHLD1
Layout Notice : Place as close +3V_LAN 9
COMMON+
LAN_DI 1 R2 2 1 300_0402_5% 10
chip as possible. Green LED-
LAN_SK_LAN_LINK# R46 2 1 300_0402_5% 11
Orange LED-
J4 @ 1 FOX_JM3611L-N4557-7H
2 1 JOPEN ME@
C55
SI4800BDY-T1-E3_SO8 Q18 68P_0402_50V8K
8 1 2
+3VALW @
7 2 +3V_LAN
6 3
5
4.7U_0805_10V4Z~D

1 1
4

R193
C233

ISL6237_B+ 1 2

47K_0402_5%
1
1

D C238
EN_WOL# 2 0.01U_0402_25V7K~D
<25> EN_WOL#
G
Security Classification Compal Secret Data Compal Electronics, Inc.
Q19 2 2006/08/04 2006/10/06 Title
S Issued Date Deciphered Date
3

2N7002_SOT23 RTL8102EL
T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIV ISION OF R&D
Size Docum ent Num ber Rev
Cus tom 0.2
DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 24 of 40
A B C D E
 +3VALW
+EC_AVCC
L13 1 1 1 1 1 1 +3VALW

0.1U_0402_16V4Z~D
C193

0.1U_0402_16V4Z~D
C114

0.1U_0402_16V4Z~D
C110

0.1U_0402_16V4Z~D
C119

1000P_0402_50V7K~D
C161

1000P_0402_50V7K~D
C109
+3VALW 1 2 +EC_AVCC
FCM1608C-121T_0603 +3VALW
1 2

1
C196 C194 @ C205
@ 2 2 2 2 2 2 1 2 0.1U_0402_16V4Z~D @

111
125
22
33
96

67
1000P_0402_50V7K~D 0.1U_0402_16V4Z~D R105

9
1 2 2 ECAGND 1 U8 @ 100K_0402_5%
L14 FCM1608C-121T_0603 U12

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

2
8 1
7 VCC A0 2
R67 1 2 10K_0402_5% EC_SMB_CK1 6 WP A1 3
+3VS SCL A2
1 21 INVT_PWM EC_SMB_DA1 5 4
<16> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <13> SDA GND
1 2 2 23 BEEP#
<16> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <20>
R66 0_0402_5% 3 26 AT24C16AN-10SU-2.7_SO8
<17> SERIRQ SERIRQ# FANPWM1/GPIO12 EN_WOL# <24>
For ESD. 4 27 ACOFF
<16> LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <32>
<16> LPC_AD3
5

1
LPC_AD2 LAD3
<16> LPC_AD2
7
LAD2 PWM Output
LPC_AD1 8 63 BATT_TEMP @
<16> LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP BATT_TEMP <37>
C107 R106
LAD0 LPC & MISC
<16> LPC_AD0 10 64 BATT_OVP <32>
2 1 2 1 BATT_OVP/AD1/GPIO39 65 ADP_I <32> 100K_0402_5%
R69 @ 10_0402_5% ADP_I/AD2/GPIO3A BRD_ID
<12> CLK_PCI_LPC
12 AD Input 66

2
@ 22P_0402_50V8J PCICLK AD3/GPIO3B
<15> PCI_RST# 13 75
1 2 EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76
+3VALW ECRST# SELIO2#/AD5/GPIO43
R74 47K_0402_5% EC_SCI# 20
<17> EC_SCI# SCI#/GPIO0E
2 38
C120 CLKRUN#/GPIO1D 68
DAC_BRIG/DA0/GPIO3C 70
0.1U_0402_16V4Z~D EN_DFAN1/DA1/GPIO3D IREF
1
DA Output IREF/DA2/GPIO3E
71 IREF <32>
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <32>
KSI1 56
KSI2 57 KSI1/GPIO31 +3VALW
KSI3 KSI2/GPIO32
58 83 EC_MUTE# <21>
KSI4 59 KSI3/GPIO33 PSCLK1/GPIO4A 84 USB_ON#
USB_ON# <28> Ra

2
KSI5 60 KSI4/GPIO34 PSDAT1/GPIO4B 85
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C R120
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
KSO[0..15] KSI7 62 87 TP_CLK 100K_0402_5%
<27> KSO[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <27>
KSO0 39 88 TP_DATA
KSI[0..7] KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <27>
40

1
<27> KSI[0..7] KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 BRD_ID
KSO4 43 KSO3/GPIO23 SDICS#/GPXOA00 98 WL_OFF# <19>

2
KSO5 KSO4/GPIO24 SDICLK/GPXOA01
44
KSO5/GPIO25
Int. K/B SDIDO/GPXOA02
99
KSO6 45 109 LID_SW# R126
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW# <26>
46
KSO7/GPIO27 SPI Device Interface 18K_0402_1%
KSO8 47 @
KSO9 48 KSO8/GPIO28 119 FRD#SPI_SO Rb

1
KSO10 49 KSO9/GPIO29 SPIDI/RD# 120 FWR#SPI_SI
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126
KSO12 51 128 FSEL#SPICS#
KSO13 52 KSO12/GPIO2C SPICS#
KSO14
KSO15
53 KSO13/GPIO2D
KSO14/GPIO2E
BOARD ID Table
54 73
81 KSO15/GPIO2F CIR_RX/GPIO40 74
82 KSO16/GPIO48
KSO17/GPIO49
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
89 FSTCHG <32>
ID BRD ID Ra Rb Vab
90
BATT_CHGI_LED#/GPIO52 91
EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED1#
0 R01 (EVT) NC 0 0V
<37> EC_SMB_CK1
77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 CHARGE_LED1# <22>
EC_SMB_DA1 78 93 1 R02 (DVT)
<37> EC_SMB_DA1
EC_SMB_CK2 79 SDA1/GPIO45
SM Bus SUSP_LED#/GPIO55 95 SYSON
100K 8.2K 0.25V
<4> EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 SYSON <29,34>
<4> EC_SMB_DA2
80 121 VR_ON <36> 2 R03 (PVT) 100K 18K 0.50V
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 127
AC_IN/GPIO59 ACIN <17,31>
3 R10A (MP) 100K NC 3.3V
PM_SLP_S3# 6 100
<17> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <17>
PM_SLP_S5# 14 101 EC_LID_OUT#
<17> PM_SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON EC_LID_OUT# <17>
15 102 @
<17> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <26>
16 103 D12 RB751V_SOD323
17 LID_SW#/GPIO0A EC_SWI#/GPXO06 104 ICH_POK_EC 1 2 ICH_POK
SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_POK <6,17>
18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF# <13>
19
EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09
106 BT_OFF# <19> 1 2 1 2 +3VS
25 107 R103 0_0402_5% R104 10K_0402_5%
EC_THERM#/GPIO11 GPXO10 WXMIT_OFF# <19>
28 108 @
29 FAN_SPEED1/FANFB1/GPIO14 GPXO11
EC_TX_P80_DATA 30 FANFB2/GPIO15
<19,27> EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16
<19,27> EC_RX_P80_CLK 31 110 PM_SLP_S4# <17>
32 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 112
<26> ON/OFF# ON_OFF/GPIO18 ENBKL/GPXID2 GMCH_ENBKL <8> D19
<22> PWR_LED#
34 114 EAPD <20>
PWR_LED#/GPIO19 GPXID3 EC_THERM# ICH_POK
36
NUMLED#/GPIO1A GPI GPXID4
115 EC_THERM# <17> 2 1 VGATE <12,17,36>
116 SUSP#
GPXID5 PBTN_OUT# SUSP# <29,34,35>
117 PBTN_OUT# <17>
GPXID6 118 RB751V_SOD323
XCLKI GPXID7 LAN_WAKE# <24>
122
XCLKO 123 XCLK1 124
XCLK0 V18R
20mil 1
AGND
GND
GND
GND
GND
GND

C116
4.7U_0805_10V4Z~D
KB926QFC0_LQFP128 2 +3VALW
8M SPI ROM
11
24
35
94
113

69

1 20mils
C122 U10
ECAGND

8 4
0.1U_0402_16V4Z~D VCC VSS
2 3
W
C123 7
C150 HOLD
FSEL#SPICS# 2 1 SPI_CS# 1
1

S
22P_0402_50V8J~D

R77 0_0402_5%
22P_0402_50V8J~D

X1 SPI_CLK 2 1 SPI_CLK_R 6
OUT
IN

R88 15_0402_5% C
+5VS FWR#SPI_SI 2 1 SPI_SI 5 2 SPI_SO 2 1 FRD#SPI_SO
+5VALW R89 0_0402_5% D Q R80 0_0402_5%
NC

NC

TP_CLK 1 2 SST25LF080A_SO8-200m il
1 2 EC_SMB_CK1 R127 4.7K_0402_5%
R122 4.7K_0402_5% TP_DATA 1 2
2

1 2 EC_SMB_DA1 R128 4.7K_0402_5%

R123 4.7K_0402_5% 32.768K_1TJS125BJ4A421P
C117
R76
+3VS 2 1 2 1 SPI_CLK_R
WWAN@ 10_0402_5%
1 2 EC_SMB_CK2 BATT_OVP C182 1 2 WWAN@
R124 4.7K_0402_5% 100P_0402_50V8J~D 4.7P_0402_50VNPO
1 2 EC_SMB_DA2 BATT_TEMP C179 1 2
R125 4.7K_0402_5% 100P_0402_50V8J~D
ACIN C115 1 2
100P_0402_50V8J~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
KB926/BIOS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 25 of 40
 +3VALW

2
JP2
ON/OFFBTN# 1 R347
2 1
3 2 100K_0402_5%
4 3

1
4 D14
2 ON/OFF#
E&T_6905-E04N-00R ON/OFF# <25>
ON/OFFBTN# 1
ME@ 3 51_ON#
51_ON# <31>
DAN202U_SC70

1
2
C4 D1

1000P_0402_50V7K~D RLZ20A_LL34
1

2
1
D
EC_ON 2 Q1
<25> EC_ON
G

2
S 2N7002_SOT23

3
R3

10K_0402_5%

1
LID Switch

+3VALW

2
2
R71
47K_0402_5%

VDD

1
1 3 LID_SW# <25>
C112 OUTPUT
0.1U_0402_16V4Z~D
GND

10P_0402_50V8J~D
2 C111
U9
1

A3212ELHLT-T_SOT23W-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
LID SW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 26 of 40
 5 4 3 2 1

D D

KSI[0..7]

KSO[0..15]
KSI[0..7] <25>

INT_KBD Conn. To TP/B Conn.

KSO[0..15] <25>
JP11
JP12 1
KSI1 1 +5VS TP_CLK 2 1
1 <25> TP_CLK 2
KSI7 2 TP_DATA 3
2 <25> TP_DATA 3
KSI0 C144 1 2 @ 100P_0402_50V8J~D KSO4 C145 1 2 @ 100P_0402_50V8J~D KSI6 3 4
KSO9 4 3 4
KSI1 C133 1 KSO5 KSI4 4
2 @ 100P_0402_50V8J~D C142 1 2 @ 100P_0402_50V8J~D 5
5 E&T_6905-E04N-00R
KSI5 6
KSI2 C140 1 2 @ 100P_0402_50V8J~D KSO6 C148 1 2 @ 100P_0402_50V8J~D KSO0 7 6 ME@
KSI2 7
8
KSI3 C141 1 8
2 @ 100P_0402_50V8J~D KSO7 C146 1 2 @ 100P_0402_50V8J~D KSI3 9
KSO5 10 9
KSI4 C137 1 KSO8 KSO1 10
2 @ 100P_0402_50V8J~D C147 1 2 @ 100P_0402_50V8J~D 11
KSI0 11 TP_DATA
12
KSI5 C138 1 2 @ 100P_0402_50V8J~D KSO9 C136 1 2 @ 100P_0402_50V8J~D KSO2 13 12
KSO4 14 13 TP_CLK
KSI6 C135 1 2 @ 100P_0402_50V8J~D KSO10 C129 1 2 @ 100P_0402_50V8J~D KSO7 15 14 +5VS
15

3
KSO8 16
KSI7 C134 1 KSO11 KSO6 16
2 @ 100P_0402_50V8J~D C128 1 2 @ 100P_0402_50V8J~D 17
KSO3 17 C94 D10
18
KSO0 C139 1 18
2 @ 100P_0402_50V8J~D KSO12 C126 1 2 @ 100P_0402_50V8J~D KSO12 19 @
KSO13 19 0.1U_0402_16V4Z~D PSOT24C_SOT23
20
C KSO1 C143 1 KSO13 KSO14 20 C
2 @ 100P_0402_50V8J~D C127 1 2 @ 100P_0402_50V8J~D 21

1
KSO11 21
22
KSO2 C131 1 KSO14 KSO10 22
2 @ 100P_0402_50V8J~D C124 1 2 @ 100P_0402_50V8J~D 23
KSO15 24 23
KSO3 C132 1 2 @ 100P_0402_50V8J~D KSO15 C125 1 2 @ 100P_0402_50V8J~D 24

25
GND1
26
GND2
ACES_85201-24051
ME@

EC DEBUG PORT
JP14
+3VALW 1
EC_TX_P80_DATA 2 1
<19,25> EC_TX_P80_DATA 2
EC_RX_P80_CLK 3
<19,25> EC_RX_P80_CLK 3
4
4
ACES_85205-0400
B B
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/SW/TP/LPC Debug CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 27 of 40
5 4 3 2 1
 A B C D E

USB CONN. 1
1 1

+USB_VCCA

+USB_VCCA
W=80mils
1
1
+ C231 C15
150U_Y_6.3VM
470P_0402_50V7K~D
2 2
+5VALW JP3
1
USB20_N0 2 VCC
<17> USB20_N0 USB_N
USB20_P0 3
+USB_VCCA <17> USB20_P0 USB_P
4
U2 5 GND
C34 1 8 6 GND
0.1U_0402_16V4Z~D GND VOUT GND
2 7 7
2 1 3 VIN VOUT 6 8 GND
4 VIN VOUT 5 GND
USB_OC#0 <17>

2
EN FLG SUYIN_020133MR004S536ZR
R130 RT9711PS_SO8 ME@
USB_OC#2 <17>
200K_0402_5%
1
USB_ON# C16
<25> USB_ON# 1
@ 1000P_0402_50V7K~D

2
USB20_P0 USB20_N0

2
USB CONN. 2 2

2
@ +USB_VCCA
D9
PSOT24C_SOT23-3
W=80mils
1

1
C42

470P_0402_50V7K~D
2
JP7
1
USB20_P2 USB20_N2 USB20_N2 2 VCC
<17> USB20_N2 USB_N
USB20_P2 3
<17> USB20_P2 USB_P
4
5 GND
3

6 GND
@ 7 GND
D24 8 GND
PSOT24C_SOT23-3 GND
SUYIN_020133MR004S536ZR
ME@
1

+5VALW +USB_VCCC
U7
1 8
3
2 GND VOUT 7 3

3 VIN VOUT 6
1 4 VIN VOUT
EN FLG
5 USB_OC#7 <17> USB CONN. 3
C95 RT9711PS_SO8 +USB_VCCC
0.1U_0402_16V4Z~D
2
+USB_VCCC
W=40mils
1
C77
@ 1000P_0402_50V7K~D 1 1
<25> USB_ON#
C56
2 + C72
150U_Y_6.3VM 470P_0402_50V7K~D
2
2
JP9
1
USB20_N7 2 VCC
<17> USB20_N7 USB20_P7 USB_N
<17> USB20_P7 3
4 USB_P
5 GND
3

2
6 GND
@ 7 GND
D8 8 GND
PSOT24C_SOT23-3 GND
SUYIN_020133MR004S536ZR
ME@
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
USB PORTS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 28 of 40
A B C D E
 A B C D E

1 1

+5VALW TO +5VS +3VALW TO +3VS

+5VALW +5VS +3VALW +3VS

SI4800BDY-T1-E3_SO8 Q6 SI4800BDY-T1-E3_SO8 Q12

8 1 8 1
7 2 7 2 +5VALW

2
6 3 1 1 6 3 1 1
1 1 5 C74 C76 R50 1 1 5 C201 C202 R179

2
C97 C96 C215 C214
10U_0805_10V4Z~D 470_0603_5% 10U_0805_10V4Z~D 470_0603_5% R302
4

4
10U_0805_10V4Z~D 2 2
1U_0603_10V4Z~D 10U_0805_10V4Z~D 2 2
1U_0603_10V4Z~D 100K_0402_5%

1 1
2 2
10U_0805_10V4Z~D 2 2
10U_0805_10V4Z~D
2 D 2

1
D 2 SUSP
2 SUSP G
1 2 5VS_GATE G S Q16
ISL6237_B+

3
R68 S Q9 1 2 2N7002_SOT23 SYSON#
3 B+
20K_0402_5% 1 2N7002_SOT23 R185
1

D C108 100K_0402_5% 1

1
SUSP D C255
2
Q8 G 0.01U_0402_25V7K~D SUSP 2

1
2N7002_SOT23 S
2 Q17 G 0.1U_0402_25V7K~D
3

2N7002_SOT23 S 2 Q28

3
SYSON 2
<25,34> SYSON

DTC124EK_SC59

3
RTCVREF
+5VALW

2
R298 R297
3 3
100K_0402_5% 100K_0402_5%
+1.5VS +2.5VS +VCCP +0.9VS +1.8V @

1
SUSP
<35> SUSP
2

2
R18 R169 R280 R61 R279

1
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
Q27
1

1 <25,34,35> SUSP# 2
1

D D D D D
1
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G DTC124EK_SC59
S Q2 S Q15 S Q24 S Q7 S Q23
3

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
DC INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4421P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 29 of 40
A B C D E
H23
H

@ H_5P6X3P6N

1
H15
H

@ H_3P6X5P6N

1
H7
H

@ H_9P0X6P0N

H4
H

@ H_3P6
1

H20 H19 H11 H18 H10 H8 H9 H21 H13 H12

H H H H H H H H H H
H_3P2
@ @ @ @ @ @ @ @ @ @
1

1
H3 H22 H16 H1 H28 H27 H17 H26 H14 H25 H6 H5 H2
H H H H H H H H H H H H H

@ @ @ @ @ @ @ @ @ @ @ @ @ H_2P8
1

1
FM3 FM4 FM6 FM5 FM2 FM1

@ @ @ @ @ @ FIDUCIAL_C40M80
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, Augus t 08, 2008 Sheet 30 of 40
 A B C D

Vin Detector
1
VIN 1

SP02000G100 High 18.059 17.841 17.624

PL1
Low 17.418 17.210 16.998
SMB3025500YA_2P
1 APDIN 1 2
1 2
2
3
3 4 PR1 PC5
PJP1 4 @ 10K_0402_1% @ 0.01U_0402_25V7K

1
ACES_85204-0400N PC3 1 2 1 2
PC1 PC2 100P_0402_50V8J PC4
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K PR2

2
1M_0402_1%
1 2
VIN
VS
VIN

0.01U_0402_25V7K

10K_0805_5%
82.5K_0603_0.1%
1

PC6

PR4
PR5

PR3
10K_0402_1%

2
1 2

2
PR6 ACIN <17,25>

8
22K_0603_1%
1 2 3

P
+ 1 PACIN
2 O

0.068U_0603_25V7M

G
-
VIN PU1A

19.6K_0603_0.1%
1

10K_0402_1%
RLZ4.3B_LL34
2 2
LM393DG_SO8

0.1U_0402_16V7K
PR7

4
PC7

PC8

PR8
PD1
2

2
2
PD2 PR9

2
LL4148_LL34-2 10K_0402_1%
2 1
PD3
RTCVREF 3.3V

1
LL4148_LL34-2
BATT+ 2 1

1
PR10 PR11
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR12
2

200_0603_5% 2
CHGRTCP 1 2 N1 3 1
VS
0.22U_0603_25V7K
1

PR13 PC10
PC9

100K_0402_1% 0.1U_0603_25V7K PJ1 PJ2

+3VALWP 2 1 +3VALW +1.5VSP 2 1 +1.5VS
1

PR14 2 1 2 1
2

22K_0402_1% JUMP_43X118 JUMP_43X118

1 2
<26> 51_ON#

PJ3 PJ4
2 1 2 1
+5VALWP 2 1 +5VALW +0.9VSP 2 1 +0.9VS
3 RTCVREF 3
1

JUMP_43X118 JUMP_43X79
PR15
PU2 200_0603_5%
PR16 G920AT24U_SOT89-3
0_0402_5% 3.3V
2

1 2 3 2 N2 PJ7 PJ6
OUT IN
+CHGRTC +CPU_COREP 2
2 1
1
+CPU_CORE +1.8VP 2
2 1
1 +1.8V
1

GND PC12 JUMP_43X118 JUMP_43X118

PC11 1U_0805_25V4Z
10U_0805_10V4Z 1
2

PJ8
2 1
+VCCPP 2 1 +VCCP
JUMP_43X118

PJ9
2 1
+2.5VSP 2 1 +2.5VS
JUMP_43X118

PR190 PD12
PJP2 1K_0402_5%RB751V-40TE17_SOD323-2
1 1 2 2 1 +RTCBATT
1 2
4 2 3 4

G1 PD4
4
G2 1 2 +CHGRTC
@ACES_85204-02001
RB751V-40TE17_SOD323-2

SP02000D000 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
DCIN & DETECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 31 of 39
A B C D
 A B C D

PQ2 PQ3 B+
FDS4435BZ_SO8 FDS4435BZ_SO8
8 3 3 8 PR19
VIN 7 2 2 7 0.015_1206_1%
6 1 1 6
5 5 1 4 1 2 CHG_B+

100K_0402_1%
PL11

0.01U_0402_25V7K
2

2
2 3 FBMA-L11-201209-121LMA50T_0805

PR21
4

4
CHGEN#

820P_0402_25V7
470P_0402_50V8J
PR20

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

PC13
2

2
3.3_1210_5%

1
PC22

0.01U_0402_25V7K

PC14

PC15

PC16

PC146

PC147
2

2
100K_0402_1%
PC19

0.01U_0402_25V7K
2 1

1
1 1

5
6
7
8

1
2
3
0.1U_0402_16V7K PU3 0.1U_0603_25V7K

PC17

PC18

PR23
1 2 1 28 1 2

1
PR22 CHGEN PVCC

0.1U_0603_25V7K
1

1
3.3_1210_5% PR24 /BATDRV

@ 0.1U_0603_25V7K
4

2
0_0402_5%

PC20

PC23
27 1 2 4 PQ5
1 1

2
2
BTST FDS4435BZ_SO8
PC21 PR25
2.2U_0805_25V6K 340K_0402_1% 2 26 PQ4
3 ACN HIDRV AO4466_SO8
2

3
2
1

5
6
7
8
ACP PR26

1
4 25 PL2 0.02_1206_1%
ACDET ACDRV PH 10UH_MPL73-100_3A_20%
5
ACDET BATT+
2 1 1 2 1 2 1 4
PD5

10U_1206_25V6M
PC24 2 3

REGN
2

2
LL4148_LL34-2

10U_1206_25V6M
PR28 0.1U_0603_25V7K

5
6
7
8

1
PR27 205K_0402_1%

PC26
1
PR30 54.9K_0402_1% 24751_VREF 1 2 ACSET 6 PQ6

PC25
340K_0402_1% ACSET 24 AO4466_SO8

2
REGN PR150
1

1
51K_0402_1%
PC27 4.7_1206_5%

1
1U_0603_10V6K 4

PR29

2
PC28

2
@ 0.01U_0402_25V7K

2
1 2 7

1
OVPSET PC29 ACOP 23

3
2
1
0.47U_0603_16V7K LODRV
CP setting PC140
2

2
PR31 22 680P_0603_50V8J
54.9K_0402_1% PGND PC30
8
2 OVPSET 0.1U_0402_16V7K 2

1 2
CP Point Setting 9 21 ACOFF ACOFF <25>
1

AGND LEARN

1
CP point=Iadapter*85% PR32
0_0402_5% PC31 PC32
30W adapter 24751_VREF 20 CELLS 1 2 0.1U_0603_25V7K @ 0.1U_0603_25V7K
24751_VREF

2
CELLS
Vacset=3.3*(51K/(205K+51K))=0.657V
10
VREF
CP Point=(Vacset/Vvdac)*(0.1/PR19)=1.328A PQ25 3

1
SI2301BDS-T1-E3_SOT23-3 PC33
1U_0603_10V6K
Input OVP : 22.3V PR149 19

2
100K_0402_1% RTCVREF SRP
ACIN detect : 17.26V 1 2 2 11 18
VDAC SRN
1
100K_0402_1%

Fsw : 300KHz 17
BAT
PR172

1
VADJ 12
VADJ PC34
1

24751_VREF ACSET 0.1U_0603_25V7K

2

2
29
24751_VREF 1 2 13 TP
ICHG setting
1

PC135 ACGOOD
PR169 PR33 IREF Current
0.1U_0603_25V7K
200K_0402_1% 16 2 1 IREF <25>
1

/BATDRV SRSET
14 174K_0402_1%
1

1
D BATDRV
3.0V 1.68A
2

1
PR170 2 PR35
100K_0402_1% G 15 1 2 102K_0402_1% PC35
PQ13 IADAPT @ 0.01U_0402_25V7K
S
2

2
1

D 2N7002W-T/R7_SOT323-3 BQ24751ARHDR_QFN28_5X5 PR34

2
3 3

ACOFF 1 2 2 10_0603_5%
G REGN
1

1
PC145 S PQ14
3

0.1U_0402_16V7K 2N7002W-T/R7_SOT323-3 PC36

PR171 100P_0402_50V8J 24751_VREF

2
1

340K_0402_1% ADP_I <25>

PR36
2

2
@ 0_0402_5%
VMB PR38 PR37
210K_0402_1% 100K_0402_1%
2

<25> CHGVADJ 1 2 VADJ

1

VS
340K_0402_1%

1
CHGVADJ Pre Cell
PR39

1000P_0402_50V7K

CHGEN#
1
499K_0402_1%
PR40

1
D
3.3V 4.35V
0.01U_0402_25V7K

PC37
2

<25> FSTCHG 2
2
1

PC38

G
2
1

499K_0402_1%

0V 4V S PQ7

3
2N7002W-T/R7_SOT323-3
PR41
2

"CHGVADJ" connect to EC DA pin

2
8

PR42
10K_0402_1% 3
P

+
<25> BATT_OVP 2 1 1
0 2
G

-
A/D
1

105K_0402_1%

PU4A
LI-3S :13.5V----BATT-OVP=1.5V
4

LM358DR_SO8
PR43

0.01U_0402_25V7K
PC39

4 BATT-OVP=0.1112*BATT+ 4
2
2

5
P

+
7
0 6
Security Classification Compal Secret Data Compal Electronics, Inc.
G

-
PU4B Issued Date 2007/06/22 Deciphered Date 2008/06/22 Title
4

LM358DR_SO8
CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 32 of 39
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PL12
FBMA-L11-201209-121LMA50T_0805 PR44
0_0402_5%
1 2 1 2

<BOM Structure>
2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
D D

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC40

PC41

PC42

8
7
6
5

1
PC45
VL

PC43

PC44
2

1U_0603_10V6K

2
2
PQ8 PC46

4.7U_0805_6.3V6K
AO4466_SO8 0.1U_0603_25V7K 4

1
PC47
4

PC51
1
PQ9 +5VALWP

2
AO4466_SO8

3
2
1
PL4

1
2
3
PL3 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PC48 2 1
1 2 1U_0603_10V6K

VIN

VCC

LDO
+3VALWP 33 19 1 2

5
6
7
8

1
TP PVCC PQ11

8
7
6
5
DH3 26 15 DH5 AO4712_SO8
PR151 UGATE2 UGATE1 PR152
0_0402_5%

4.7_1206_5% PQ10 2 1 BST3A 24 17 BST5A2 1 4.7_1206_5%

2

AO4712_SO8 PR45 BOOT2 BOOT1 PR46

1

@ 61.9K_0402_1%
PR47

2.2_0603_5% 2.2_0603_5% 4

2
PC49 + 4 PC50

2
150U_V_6.3VM_R18 0.1U_0603_25V7K

PR48
PC143 LX3 25 16 LX5 1
1

2 680P_0603_50V8J PHASE2 PHASE1 PC52

3
2
1
0.1U_0603_25V7K PC144 + PC53
2

1
2
3

2
C DL3 23 18 DL5 680P_0603_50V8J 150U_V_6.3VM_R18 C

1
LGATE2 LGATE1
10K_0402_1%

2
2

22

2
PGND
PR49

FB3 30
OUT2

0_0402_5%
PR50
10
32 OUT1
VL
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 2VREF_ISL6237 1
REF
+3VALWP PC54
Imax=5A 0.22U_0603_25V7K
BYP
9
8
Ipeak=6.5A PD6 LDOREFIN PR51 @ 0_0402_5%
RB751V-40TE17_SOD323-2 29 2 1
Iocp(minimum)=7.6A SKIP VL
1 2
PR52 0_0402_5%
1 2 2VREF_ISL6237
+5VALWP
PD7 PR53
20
NC POK2
28
PR191 @ 0_0402_5%
Imax=5A
VS RLZ5.1B_LL34 100K_0402_1% 1 2 Ipeak=6.5A
1 2 1 2 4 13
EN_LDO POK1 Iocp(minimum)=7.6A
2
200K_0402_5%

2
PR54

PC55 14 12 ILM1 2 1
B
0.22U_0603_25V7K EN1 ILIM1 PR55 B
301K_0402_1%
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2 PR56
PU6 301K_0402_1%

21
PD8 VL ISL6237IRZ-T_QFN32_5X5
806K_0603_1%

RB751V-40TE17_SOD323-2
2

1 2 PR57
PR58

0_0402_5%
2VREF_ISL6237 1

PR60 1U_0603_10V6K
1
PC56

@ 47K_0402_5%
PR59
1

1
2 1 1 2
2
0.047U_0402_16V7K

0_0402_5% PR61
MAINPWON <37>
@ 0.047U_0402_16V7K

0_0402_5%
1

2
PC57

PC58
2

2VREF_ISL6237
3

A 2 PQ12 A
@ TP0610K-T1-E3_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/06/22 2008/06/22 Title
Issued Date Deciphered Date 3V/5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 33 of 39
5 4 3 2 1
 A B C D

1
PC78 PC79

2
1U_0402_6.3V6K 1U_0402_6.3V6K

+5VALW 2 1 1 2 +5VALW
PR77 PR78
2.2_0603_1% 2.2_0603_1%

1 1

1
PL13 PC80
FBMA-L11-201209-121LMA50T_0805 0.1U_0603_25V7K PC81
0.1U_0603_25V7K

2
B+ 1 2 ISL6228_B+
ISL6228_B+ 2 1 2 1 ISL6228_B+
PR79 PR80
10_0603_1% 10_0603_1%

2
1000P_0402_50V7K
1

1
PC83

PC82
2

22K_0402_1%
1000P_0402_50V7K PR81

PR83
PR82 18.2K_0402_1%

2
PC84 PR85 88.7K_0402_1% +5VALW 2 1

1
1000P_0402_50V7K 2.2K_0402_5% PR84
2 1 1 2 @ 0_0402_5%

1
1 2
29

FSET1

FSET2
PGOOD1

VIN1

VCC1

VCC2

VIN2
PR86 GND_T

2
PR87 68K_0402_1%
24K_0402_1%
1 2 8 28 2 1 +5VALW PR88 PR90 PC85
FB1 PGOOD2 PR89 33.2K_0402_1% 2.2K_0402_5% 1000P_0402_50V7K
@ 0_0402_5% 1 2 1 2

1
ISL6228_B+
2 2

9 27 1 2
VO1 FB2 PR91
68K_0402_1%
8
7
6
5

PC86
1

6800P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

10 26 1 2
PC87

PC88

1 2 PQ16 OCSET1 VO2 PR92

AO4466_SO8 24K_0402_1%
2

2
2

4
PR93 VCCP_EN 11 25
24K_0402_1% EN1 PU10 OCSET2
ISL6228_B+
ISL6228HRTZ-T_QFN28_4X4 PR94
1

1
2
3

0_0402_5%
1 2 LX_VCCP 12 24 1 2 SYSON <25,29>
+VCCPP PHASE1 EN2 PC92

5
6
7
8

1
PL6 6800P_0402_25V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
PC90

PC91
8
7
6
5

2.2UH_PCMC063T-2R2MN_8A_20% PC89 1 2
1

@ 0.1U_0402_16V7K

2
4.7_1206_5%

UG_VCCP 13 23
AO4712_SO8

2
UGATE1 PHASE2
PQ17
PR148

1 4 PR95
220U_D2_4VM

24K_0402_1%
10U_0805_6.3V6M

4
2
1

+ PQ18
PC93
PC134

2 1 2 1BST_VCCP14 22 UG_1.8V AO4466_SO8

1
BOOT1 UGATE2
2

3
2
1
LGATE1

LGATE2
2 LX_1.8V
680P_0603_50V8J

PC94 PR96
PGND1

PGND2
1 2

BOOT2
PVCC1

PVCC2
PC132

+1.8VP
1
2
3

0.1U_0402_16V7K 2.2_0603_5%

5
6
7
8
PL7
2

3
2.2UH_PCMC063T-2R2MN_8A_20% 1 3

220U_D2_4VM

10U_0805_6.3V6M
15

16

17

18

19

20

21

1
+

PC95

PC133
PR147
4 4.7_1206_5%

2
BST_1.8V 1 2 1 2 2
+5VALW +5VALW

2
PR97 PC96
2

2
2.2_0603_5% 0.1U_0402_16V7K
PQ19

3
2
1

1
PR98 PC97 PC98 AO4712_SO8
1

1
0_0402_5% 1U_0402_6.3V6K 1U_0402_6.3V6K
<25,29,35> SUSP# 2 1 VCCP_EN PC131

2
680P_0603_50V8J
LG_VCCP LG_1.8V
1

PC99
+VCCPP @ 0.01U_0402_25V7K +1.8VP
2

Imax=6A Imax=6A
Ipeak=8A Ipeak=8A
Iocp(minimum)=9.2A Iocp(minimum)=9.2A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/06/22 2008/06/22 Title
Issued Date Deciphered Date VCCP/1.8V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 34 of 39
A B C D
 5 4 3 2 1

+1.8V +5VALW

1
PJ16
D D
@ JUMP_43X39 PJ12

1
JUMP_43X39

2
2

2
1

1U_0603_10V6K
PC141

PC136
10U_0805_6.3V6M

2
PU12
APL5912-KAC-TRL_SO8

6
VCNTL
5 3 +1.5VSP
PR187 9 VIN VOUT 4

1
0_0402_5% VIN VOUT

1
1 2 8

0.01U_0402_25V7K
1

PC139
<25,29,34> SUSP# EN

@220U_D2_4VM
7 2 PR188

GND

1
POK FB 2.7K_0402_1%

10U_0805_6.3V6M
+

PC138
2
1

PC142
2
PC137

2
@ 0.47U_0402_6.3V6K
2 2

1
PR189
3K_0402_1%

2
C C

+1.8V
1

PU9
PJ13 APL5508-25DC-TRL_SOT89-3 +2.5VSP
1

@ JUMP_43X39
+3VS
2 3
IN OUT
2

PU8

4.7U_0805_6.3V6K
2

1
GND

1U_0603_10V6K
1 6 +3VALW
VIN VCNTL PR74

PC73

PC74
2 5 1 @ 150_1206_5%

2
1

1
PC71 GND NC
1

4.7U_0805_6.3V6K 3 7 PC72

2
PR73 VREF NC 1U_0603_10V6K
2

2
1K_0402_1% 4 8
VOUT NC
9
2

B TP B
APL5331KAC-TRL_SO8
1

PR75
+0.9VSP
1

0_0402_5% D PR76
1 2 2 1K_0402_1% PC76
<29> SUSP
1

G 0.1U_0402_16V7K
1

S PC77
3

PC75 10U_0805_6.3V6M
PQ15
2N7002W-T/R7_SOT323-3

@ 0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/0.9V/2.5V
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 35 of 39

5 4 3 2 1
 5 4 3 2 1

+VCCP
2

D D
PR99 PR100
68_0402_5% 499_0402_1%
<6,17> PM_DPRSLPVR 1 2 +5VS

<5>

<5>

<5>

<5>

<5>

<5>

<5>
+CPU_B+

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PL8
1

PR101 FBMA-L11-201209-121LMA50T_0805

<25>
VR_ON
0_0402_5%

2
<4,16> H_DPRSTP# 1 2 1 2 B+

4700P_0402_25V7K

4.7U_0805_25V6M

4.7U_0805_25V6M

4.7U_0805_25V6M
PR103 0_0402_5% PR102
H_PROCHOT# 1 2 1_0603_5%
CLK_ENABLE#

1
PR104

1
0_0402_5%

PC100

PC101

PC102

PC103
+3VS 1 2

2
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1U_0603_10V6K
1

1
0.01U_0402_25V7K

1U_0402_6.3V6K
1

1
PR105

PC104

PC105

PC106

5
6
7
8
10K_0402_1%

2
2
PQ20

2
PR106

PR107

PR108

PR109

PR110

PR111

PR112

PR113
AO4466_SO8
<12,17,25> VGATE @ 0.1U_0402_16V7K 4

41

40

39

38

37

36

35

34

33

32

31

3
2
1
3V3

DPRSTP#

VID6

VID5

VID4

VID3
GND PAD

PGOOD

CLK_EN

DPRSLPVR

VR_ON
1

PR115 PC108 PL9

PC107

0_0603_5% 0.22U_0603_25V7K 1.5UH_PCMC063T-1R5MN_9A_20%

1 30 1 2 1 2 1 2
+CPU_COREP
2

FDE VID2
PR114
C C
1 2 2 29
PMON VID1

5
6
7
8

1
PWON
PR116 40.2K_0402_1%

1
1 2 @ 3 28
RBIAS VID0 PR117
147K_0402_1%

1
H_PROCHOT# 4 27 PQ21 @ 4.7_1206_5% PR118
<4> H_PROCHOT# VR_TT# VCCP
PH1 AO4712_SO8 11.8K_0402_1%

2
1 2 1 2 5 26 LGATE_CPU 4

2
NTC LGATE

VSUM
@ 100K_0603_1%_TH11-4H104FT PD9
PR119 1 2 6 25 B340A_SMA2

2
SOFT VSSP

1
@ 4.22K_0402_1% PC109
0.015U_0402_16V7K 7 24 PHASE_CPU

3
2
1
OCSET PHASE
PU11 PC110

2
PR120 8 ISL6261ACRZ-T_QFN40_6X6 23 UGATE_CPU @ 680P_0603_50V8J
1 2 VW UGATE
4.12K_0402_1% 9 22 BOOT_CPU
COMP BOOT
10 21
DROOP

FB NC
2

VSUM
VDIFF

VSEN

VDD
VSS
RTN

DFB
2

VIN
VO

PR121
PC111
6.81K_0402_1% 1000P_0402_50V7K
1

11

12

13

14

15

16

17

18

19

20
1

PC112 PR122
2 1 1 2

120P_0402_50V8J 332K_0402_1%
1 2 +5VS
1 2 PR123
1

10_0603_5%
B PC113 82P_0402_50V8J PC114 B

1U_0402_6.3V6K
2

PC115
1200P_0402_50V7K PR125
PR124
1 2 1 2 10_0603_5%
1.54K_0402_1% 1 2 +CPU_B+
1

PR126
1K_0402_1% PC116
1 2 0.22U_0603_25V7K
2

PC117 1000P_0402_50V7K
1 2 1 2 VSUM
<5> VCCSENSE
PR127
1

0_0402_5%
PC118 PR128
1

1000P_0402_50V7K @ 3.57K_0402_1%
2

1.82K_0402_1%
@ 0.068U_0402_10V6K

PR130

1 2
2 2
2

<5> VSSSENSE PR129

0.1U_0402_16V7K

0_0402_5% PC122 330P_0402_50V7K

PC121

PC119

2
1

1 2
1

PC120 PH2
330P_0402_50V7K 1 2 1 2 @ 10KB_0603_5%_ERTJ1VR103J
2

PR131 PR132
1K_0402_1% 1.62K_0402_1%

+CPU_COREP

A A
1

PC123
0.22U_0603_25V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/06/23 2006/10/22 Title
Issued Date Deciphered Date +CPU_CORE
T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIV ISION OF R&D
Size Docum ent Num ber Rev
DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS Cus tom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 36 of 39
5 4 3 2 1
 A B C D

PH3 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

VL
1 1
VL

2
PR133

1
47K_0402_1%
PH3 PR134
MAINPWON <33>
100K_0603_1%_TH11-4H104FT 47K_0402_1%

1
1 2
VMB

2
PL10 PR135

8
SMB3025500YA_2P 13.7K_0402_1%

1
1 1 2 1 2 5 D

P
1 BATT+ +
2 7 2
2 3 PR153 1K_0402_5% TM_REF1 6 O G

G
3 - PU1B
4 1 2 S

3
4 5 TS LM393DG_SO8

2N7002W-T/R7_SOT323-3
4
1

1
5 EC_SMDA

PQ22
6
6 7 EC_SMCA PC124 PC125
7 8 1000P_0402_50V7K 0.01U_0402_25V7K

1
8

15.4K_0402_1%
9

1000P_0402_50V7K
1

1
9 10 2 1

0.22U_0603_25V7K

PR138
VL

1
GND

100_0402_1%
11

PC126

PC127
GND 12 PR139

PR137

1
GND 13 100K_0402_1%

2
1
GND

100_0402_1%
2

3
JBATT1 PR140

PR136
@ SM05_SOT23

@ SM05_SOT23

2
SUYIN_200277MR009F516ZL 100K_0402_1%
PD10

PD11

2
EC_SMB_CK1 <25>

2
2 2

EC_SMB_DA1 <25>
1

1 2 +3VALW
PR141
1

6.49K_0402_1%
PR142
10K_0402_1%
2

A/D
BATT_TEMP <25>

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/6/22 Deciphered Date 2008/6/22 Title
BATTERY CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, Augus t 08, 2008 Sheet 37 of 39
A B C D
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Rev. PG# Modify List

1 Deleted Kill switch circuit. 0.2 P26 1.Deleted R60,C85,SW2
1 1
2 Changed to Dell PN. 0.2 -- 1.Change C308,309,310,311,312,313,314,315,320,321,322,323,324,325,326,327,337,341
from SE000000K80(0402) to SE000000K8L(0402)
2.Change C46,47,298,299,300,301,302,303,304,328,334,335 from SE000005TM8(0603) to SE00000480L(0805)
3.Change C22,25,248,283 from SE1244748K0(0402) to SE027474Z8L(0603)
4.Change C108,255,238 from SE042104K80(0603) to SE068103K8L(0402)
5.Change C11,369,376,384 from SE100105Z80(0402) to SE052105Z8L(0603)
6.Change C44,52 from SE077106M80(1206) to SE053106Z8L(0805)
7.Change C373 from SE054106Z80(1206) to SE053106Z8L(0805)
8.Change C260,276,281,293,330 from SE107475K80(0603) to SE053475Z8L(0805)
9.Change C92 from SE064225K80(0805) to SE107225K8L(0603)
9.Change C54,286,288,318,319,329 from SE100105Z80(0402) to SE080105K8L(0603)
3 Use LAN internal EEPROM and CLKREQ 0.2 P24 Unstuff U3 C32 R173 stuff R170 R111
4 LCD squence 0.2 P13 Change R35,39 to 47K ohm and C45 to 0.1u
5 Changed to Dell PN. 0.2 P28 U2,7 change from SA00001H600(Dell not approve) to SA000017B00 part
6 Add C390 and 391 for SSD 0.2 P22 Add C390 and 391 and udstuff C59 for SSD
2 2
7 Follow LAN report 0.2 P24 Short C222,226, C229,230 change from 27p to 30p
8 Follow checklist 0.2 P10 Delete C280
9 Changed to Dell PN. 0.2 P6 Change R167,180 to SD00000680L
10 Follow power squence 0.2 -- Unstuff D11 D15 R168 SW1
11 Change symbol 0.2 P11 Update DIMM termination to 8P4R
12 Remove LED function 0.2 -- Delete Q25,26,11,22,LED3,R159,JP4 Change LED2 to white
13 EC code for B phase 0.2 P25 R126 change 0ohm to 8.2k ohm and stuff R120
14 For derating report 0.2 P20 Change R148,149,150,152 to 10k ohm
15 EA test 0.2 P25 C123,150 change from 15p to 22p
16 EA test 0.2 P23 Change R295 to 9.1k ohm
17 EA test 0.2 P14 GMCH_CRT_VSYNC and GMCH_CRT_HSYNC add R282,296 39ohm
18 single part 0.2 P24 R193 change to 47k ohm
19 SPEC change 0.2 P19 Change BT pin define
20 improve power consumption 0.2 P29 Change R298 to 100K
3 3
21 0.2 P25 Unstuff C194
22 ME change 0.2 P13 Change LVDS connect to 20pin
23 Dell request 0.2 Change M/B to OSP
24 0.2 P22 Delete LPC debug connect (JP20,R102,296)
25 0.2 P13 Add C85 for +LEDVDD, Delete R46,C55
26 0.2 P21 Delete L21,C383 change to 4.7u,unstuffy C374,R291 change to 47k ohm
27 0.2 P20 Change U20 to Anpec and Delete R304,310 change C373,387 to 1u Delete L18,unstuff C372,Change C369 to 0.1u
28 Change EC susp# to 116 pin PBTN_out# to 117 pin LID_SW# to 109 pin EC_PME# to 118 pin Change EC_Therm# 25 to 115 pin BT_OFF# 98 to 106 pin WL_OFF# 106 to 98 pin
29 Delete R290,285
30 DFX request 0.3 P21 Change JP13,15 PCB footprint from SINGA_2SJ-S351-012_6P to FOX_JA6333L-B3S0-7F_6P
31 EC code for C phase 0.3 P25 R126 change 18Kohm
32 ENE request 0.3 P25 C116 change to 1u
33 0.3 Delete R215, Change netname +RTCVCC to +RTCBATT ,Add J6 D19, C191 with C185 switch,
34 EMI request 0.3 Add C389
4 35 LAN LED 0.3 Add R46 and C55 LAN LED add orange 4

36 ENE request 1.0 P25 C116 change to 4.7u

37 1.0 Delete J1,J3,SW1,JP18
38 1.0 C127 change to 1000p Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 38 of 40
A B C D E
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D D

1 Cahnge RTC battery to CR2032. To meet customer specification (3 years). R.02 31 Add PD12 (RB751) and PR190 (1K). 20080428 DVT

2 Adjust Vin detector setting. Change Vin "High==>Low" voltage from 14.355V to 17.210V. R.02 31 Change PR6 to 22K and PR7 to 19.6K. 20080428 DVT

3 Adjust VCCP OCP setting. Change VCCP OCP to 9A. R.02 34 Cahnge PR87 and PR93 to 24K and PC86 to 6800P. 20080428 DVT

4 Adjust 1.8V output voltage. Change 1.8V power rail voltage from 1.8V to 1.828V. R.02 34 Change PR88 from 34K to 33.2K. 20080428 DVT

5 Change Vin and battery discharge MOSFET. Due to SI4835BDY will EOL, so, we change to Compal standard R.02 32 Change PQ2, PQ3 and PQ5 from SI4835BDY to FDS4435BZ. 20080428 DVT
2nd source, FDS4435BZ.

6 Change battery connector. The new battery connector has screw hole. R.02 32 Change battery connector. 20080430 DVT

7 Power board-band. EMI requests to add soltion to reduce power board-band. R.02 32 Change PJ10,PJ11 and PJ14 from Jump to bead. 20080506 DVT
33 Change PR45,PR46,PR96 and PR97 from 0 ohm to 2.2 ohm.
34 Add PR151,PR152,PC143,PC144,PR147,PR148,PC131,PC132,PC146,PC147,
C
PR150 AND PC140. C

8 Modify CPU CORE OCP. Change CPU CORE OCP from 10A to 7A. R.02 36 Change PR120 from 5.9K to 4.12K. 20080514 DVT

9 Remove PR16 and PR17. Change RTC battery, so, remove PR17 and PR16. R.03 31 Delete PR17 and change PR16 to 0 Ohm. 20080605 PVT

10

11

12

13

14
B B

15

16

17

18

19

20

21
A A

22

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
<Doc>
Date: Friday, August 08, 2008 Sheet 39 of 39
5 4 3 2 1
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Rev. PG# Modify List

1
Deleted Kill switch circuit.
1 1
2 Changed to Dell PN.
0.2 P26 1.Deleted R60,C85,SW2
1.Change C308,309,310,311,312,313,314,315,320,321,322,323,324,325,326,327,337,341
0.2 -- from SE000000K80(0402) to SE000000K8L(0402)
2.Change C46,47,298,299,300,301,302,303,304,328,334,335 from SE000005TM8(0603) to SE00000480L(0805)
3.Change C22,25,248,283 from SE1244748K0(0402) to SE027474Z8L(0603)
4.Change C108,255,238 from SE042104K80(0603) to SE068103K8L(0402)
5.Change C11,369,376,384 from SE100105Z80(0402) to SE052105Z8L(0603)
6.Change C44,52 from SE077106M80(1206) to SE053106Z8L(0805)
7.Change C373 from SE054106Z80(1206) to SE053106Z8L(0805)
8.Change C260,276,281,293,330 from SE107475K80(0603) to SE053475Z8L(0805)
9.Change C92 from SE064225K80(0805) to SE107225K8L(0603)
9.Change C54,286,288,318,319,329 from SE100105Z80(0402) to SE080105K8L(0603)

3 Use LAN internal EEPROM and CLKREQ 0.2 P24 Unstuff U3 C32 R173 stuff R170 R111

4 LCD squence 0.2 P13 Change R35,39 to 47K ohm and C45 to 0.1u
2 2

5 LVDS connect 0.2 P13 LVDS connector change to 20 pins

6 Changed to Dell PN. 0.2 P28 U2,7 change from SA00001H600(Dell not approve) to SA000017B00 part

7 EA test 0.2 P23 Change R295 to 9.1k ohm

8 Follow LAN report 0.2 P24 Short C222,226, C229,230 change from 27p to 30p

9 Delete A -phase reserve 0.2 P20 Delete L18,

10 Changed to Dell PN. 0.2 P6 Change R167,180 to SD00000680L

11
0.2 Change M/B to OSP
12
3 3

13 Remove LED function 0.2 -- Delete Q25,26,11,22,LED3,R159 Change LED2 to white

14 EC code for B phase 0.2 P25 R126 change 0ohm to 8.2k ohm and stuff R120

15 For derating report 0.2 P20 Change R148,149,150,152 to 10k ohm

16 EA test 0.2 P25 C123,150 change from 15p to 22p

17 0.2 P13 Add C85 for +LEDVDD

18 0.2 P22 Delete LPC debug connect (JP20,R102,296)

19
ENE 0.2 P25 change SUSP# to U8.116 due to KB926 C0 bug
20
SSD 0.2 P22 add C390&C391 for Dell consign SSD

21 LED 0.2 P22 add white LED

4 22 0.2 4

23 0.2
24

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4421P
Date: Friday, August 08, 2008 Sheet 40 of 40
A B C D E