www.fairchildsemi.

com

AN-8027
FAN480X PFC+PWM Combination Controller Application
FAN4800A / FAN4800C / FAN4801 / FAN4802 / FAN4802L

Introduction The synchronization of the PWM with the PFC simplifies

the PWM compensation due to the controlled ripple on the
This application note describes step-by-step design PFC output capacitor (the PWM input capacitor). In
considerations for a power supply using the FAN480X addition to power factor correction, a number of protection
controller. The FAN480X combines a PFC controller and features have been built in to the FAN480X. These include
a PWM controller. The PFC controller employs average programmable soft-start, PFC over-voltage protection,
current mode control for Continuous Conduction Mode pulse-by-pulse current limiting, brownout protection, and
(CCM) boost converter in the front end. The PWM under-voltage lockout.
controller can be used in either current mode or voltage
mode for the downstream converter. In voltage mode, FAN4801/2/2L feature programmable two-level PFC
feed-forward from the PFC output bus can be used to output to improve efficiency at light-load and low-line
improve the line transient response of PWM stage. In conditions.
either mode, the PWM stage uses conventional trailing- FAN480X is pin-to-pin compatible with FAN4800 and
edge duty cycle modulation, while the PFC uses leading- ML4800, only requiring adjustment of some peripheral
edge modulation. This proprietary leading/trailing-edge components. The FAN480X series comparison is
modulation technique can significantly reduce the ripple summarized in the Appendix A.
current of the PFC output capacitor.

F1 L BOOST DBOOST VBOUT

AC L 11 L1
2
Input CBOOST R FB1 Vo1
CIF1 DR1
Q1 Q2 DR1
Drv Drv
DF1 CO11 CO12
RCS1
R RAMP

D1 D2 L22
Vo2
DR2 L 2
1
DF2 CO21 CO22
Q3
Drv DR2

RLF2
CIC2 RCS2

R IAC
RLF1
RRMS1 RIC CIC1
RD Vo
RT
1
IEA VEA
CRMS1 IAC FBPFC
RRMS2 RB RBIAS
ISENSE VREF
VD VD
VRMS D CF RF ROS1
D RVC
CLF1 CSS SS OPFC
CRMS2 R FBPWM
RMS3 OPWM
CVC2 Vo2
RT/CT GND
CT ROS2
RAMP ILIMIT CVC1
FAN480X ROS3
CRAMP RFB2

CB CFB

CLF2 CDD CREF

Figure 1. Typical Application Circuit of FAN480X

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09
AN-8027

Functional Description
However, once PFC stops switching operation, the junction
Gain Modulator capacitance of bridge diode is not discharged and VIN of
The gain modulator is the key block for PFC stage because Figure 2 is clamped at the peak of the line voltage. Then,
it provides the reference to the current control error the voltage of VRMS pin is given by:
amplifier for the input current shaping, as shown in Figure
2. The output current of gain modulator is a function of VEA, 2 RRMS 3
VRMS NS = VLINE (2)
IAC , and VRMS. The gain of the gain modulator is given in RRMS 1 + RRMS 2 + RRMS 3
the datasheet as a ratio between IMO and IAC with a given
VRMS when VEA is saturated to HIGH. The gain is inversely
proportional to VRMS2, as shown in Figure 3, to implement Therefore, the voltage divider for VRMS should be
line feed-forward. This automatically adjusts the reference designed considering the brownout protection trip point
of current control error amplifier according to the line and minimum operation line voltage.
voltage such that the input power of PFC converter is not
changed with line voltage.
VIN
PFC runs PFC stops

IL VIN

IEA
R
M
ISENS
E VRMS
R IMO = G I AC
RRMS1 M K (VEA 0.7)
RIAC = I AC
IA VRMS 2 (VEA MAX 0.7)
C
CRMS1 IAC
RRMS2 VRMS k
x
CRMS2 2

RRMS3 Figure 4. VRMS According to the PFC Operation

VEA Gain
Modulator
The rectified sinusoidal signal is obtained by the current
flowing into the IAC pin. The resistor RIAC should be large
Figure 2. Gain Modulator Block
enough to prevent saturation of the gain modulator as:
1
G 2VLINE . BO
VRMS 2 G MAX < 159 A (3)
RIAC
where VLINE.BO is the line voltage that trips brownout
protection, GMAX is the maximum modulator gain when VRMS
is 1.08V (which can be found in the datasheet), and 159A is
the maximum output current of the gain modulator.
Current and Voltage Control of Boost Stage
As shown in Figure 5, the FAN480X employs two control
loops for power factor correction: a current control loop
VRMS and a voltage control loop. The current control loop shapes
inductor current, as shown in Figure 6, based on the
VRMS-UVP reference signal obtained at the IAC pin as:
I L RCS1 = I MO RM = I AC G RM (4)
Figure 3. Modulation Gain Characteristics
To sense the RMS value of the line voltage, an averaging
circuit with two poles is typically employed, as shown in
Figure 2. The voltage of VRMS pin in normal PFC
operation is given as:

2 RRMS 3 2
VRMS = VLINE (1)
RRMS 1 + RRMS 2 + RRMS 3

where VLINE is RMS value of line voltage.

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 8/26/09 2
AN-8027

V IN VO It is typical to set the second boost output voltage as

340V~300V.
IL

RCS1
RF1
RM
IEA
ISENSE RM
RIC
RRMS1 CF1
RIAC IMO
CIC2
IAC CIC1
CRMS1 IAC VREF
RRMS2 Drive logic
VRMS +
CRMS2
RRMS3 VEA - OPFC
RFB1 Figure 7. Block of Two-Level PFC Output
RVC
FBPFC
RVC2
RVC1
2.5V RFB2 Oscillator
The internal oscillator frequency of FAN480X is
Figure 5. Gain Modulation Block determined by the timing resistor and capacitor on RT/CT
pin. The frequency of the internal oscillator is given by:
IAC
1
fOSC = (6)
0.56 RT CT + 360CT
RM
I MO
RCS1

Because the PWM stage of FAN480X generally uses a

forward converter, it is required to limit the maximum duty
IL cycle at 50%. To have a small tolerance of the maximum
duty cycle, a frequency divider with toggle flip-flops is
used, as illustrated in Figure 8. The operation frequency of
Figure 6. Inductor Current Shaping PFC and PWM stage is one quarter (1/4) of the oscillator
frequency. (For FAN4800C and FAN4802/2L, the
The voltage control loop regulates PFC output voltage operation frequencies for PFC and PWM stages are one
using internal error amplifier such that the FBPFC voltage quarter (1/4) and one half (1/2) of the oscillator frequency,
is same as internal reference of 2.5V. respectively).

Brownout Protection The dead time for the PFC gate drive signal is determined
FAN480X has a built-in internal brownout protection by the equation:
comparator monitoring the voltage of the VRMS pin. Once
the VRMS pin voltage is lower than 1.05V (0.9V for tDEAD = 360CT (7)
FAN4802L), the PFC stage is shutdown to protect the The dead time should be smaller than 2% of switching
system from over current. The FAN480X starts up the period to minimize line current distortion around line zero
boost stage once the VRMS voltage increases above 1.9V crossing.
(1.65V for FAN4802L).

Two-Level PFC Output T-FF T-FF

To improve system efficiency at low AC line voltage and VREF
T Q T Q
light load condition, FAN480X provides two-level PFC
output voltage. As shown in Figure 7, FAN480X monitors RT/
VEA and VRMS voltages to adjust the PFC output voltage. CT OPFC, OPWM
OSC
When VEA and VRMS are lower than the thresholds, an
internal current source of 20A is enabled that flows OPWM (FAN4800C, FAN4802/2L)
through RFB2, increasing the voltage of the FBPFC pin.
This causes the PFC output voltage to reduce when 20A
is enabled, calculated as: Figure 8. Oscillator Configuration

RFB1 + RFB 2
VOPFC 2 = (2.5 - 20 A RFB 2 ) (5)
RFB 2
2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 8/26/09 3
AN-8027

RT/
CT VBOUT

REF
PFC dead time RRAMP
1.5V PWM
-

OPFC CRAMP RAMP +

OPWM
FBPWM

OPWM (FAN4800C, FAN4802/2L)

Figure 9. FAN480X Timing Diagram Figure 10. PWM Ramp Generation Circuit

PWM Stage
The PWM stage is capable of current-mode or voltage-
mode operation. In current-mode applications, the PWM
ramp (RAMP) is usually derived directly from a current
sensing resistor or current transformer in the primary of the
output stage and is thereby representative of the current
flowing in the converters output stage. ILIMIT, which
provides cycle-by-cycle current limiting, is typically
connected to RAMP in such applications.
For voltage-mode operation, RAMP can be connected to a
separate RC timing network to generate a voltage ramp
against which FBPWM voltage is compared. Under these
conditions, the use of voltage feed-forward from the PFC
bus can be used for better line transient response.
No voltage error amplifier is included in the PWM stage,
as this function is generally performed by a programmable
shunt regulator, such as KA431, in the secondary-side. To
facilitate the design of opto-coupler feedback circuitry, an
offset voltage is built into the inverting input of PWM
comparator that allows FBPWM to command a zero
percent duty cycle when its pin voltage is below 1.5V.
PWM Current Limit
The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. If the input voltage at
this pin exceeds 1V, the output of the PWM is disabled
until the start of the next PWM clock cycle.
VIN OK Comparator
The VIN OK comparator monitors the output of the PFC
stage and inhibits the PWM stage if this voltage is less than
2.4V (96% of its nominal value). Once this voltage goes
above 2.4V, the PWM stage begins to soft-start.
PWM Soft-Start (SS)
PWM startup is controlled by the soft-start capacitor. A
10A current source supplies the charging current for the
soft-start capacitor. Startup of the PWM is prohibited until
the soft-start capacitor voltage reaches 1.5V.

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 4
AN-8027

Design Considerations
a design example. The design specifications are
In this section, a design procedure is presented using the
summarized in 0. The two-switch forward converter is used
schematic in Figure 11 as reference. A 300W PC power
for DC/DC converter stage.
supply application with universal input range is selected as

Design Specifications

Rated Voltage of Output 1 VOUT1 = 5V PWM Stage Efficiency PWM = 0.86

Rated Current of Output 1 IOUT1 = 9A Hold-up Time tHLD = 20ms
Rated Voltage of Output 2 Vout2 = 12V Minimum PFC Output Voltage 310V
Rated Current of Output 2 IOUT2 = 16.5A Nominal PFC output voltage VO_PFC = 387V
Rated Voltage of Output 3 VOUT3 = -12V PFC Output Voltage Ripple 12VPP
Rated Current of Output 3 IOUT3 = 0.8A PFC Inductor Ripple Current dI = 40%
Rated Voltage of Output 4 VOUT4 = 3.3V AC Input Voltage Frequency fline = 50 ~ 60Hz
Rated Current of Output 4 IOUT4 = 13.5A Switching Frequency fS = 65KHz
Rated Output Power PO = 300W Total Harmonic Distortion = 4%
Line Voltage Range 85~264VAC Magnetic Flux Density B = 0.27T
Line Frequency 50Hz Current Density Dcma = 400C-m/A
Brownout Protection Line Voltage 72VAC PWM Maximum Duty Cycle Dmax = 0.35
Overall Stage Efficiency = 0.82 5V Output Current Ripple ILo1 = 44%
12V Output Current Ripple ILo2 = 10%

F1 L BOOST DBOOST VBOUT

AC L 11 L1
2
Input CBOOST R FB1 Vo1
CIF1 DR1
Q1 Q2 DR1
Drv Drv
DF1 CO11 CO12
RCS1
R RAMP

D1 D2 L22
Vo2
DR2 L 2
1
DF2 CO21 CO22
Q3
Drv DR2

RLF2 Vo3
CIC2 RCS2 Vo4

R IAC
RLF1
RRMS1 RIC CIC1
RD
RT Vo1
IEA VEA
CRMS1 IAC FBPFC
RRMS2 RB RBIAS
ISENSE VREF
VD VD
VRMS D CF RF ROS1
D RVC
CLF1 CSS SS OPFC
CRMS2 R FBPWM
RMS3 OPWM
CVC2 Vo2
RT/CT GND
CT ROS2
RAMP ILIMIT CVC1
FAN480X ROS3
CRAMP RFB2

CB CFB

CLF2 CDD CREF

Figure 11. Reference Circuit for Design Example

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 5
AN-8027

[STEP-1] Define System Specifications
Since the overall system is comprised of two stages (PFC
and DC/DC), as shown in Figure 12, the input power and
output power of the boost stage are given as:
(Design Example) Since the switching frequency is
65kHz, CT is selected as 1nF. Then the maximum duty
cycle of PFC gate drive signal is obtained as:
DMAX . PFC = 1 360 CT f SW = 0.98

POUT The timing resistor is determined as:

PIN = (8)
1 1
RT = = 6.9k
4 0.56 f SW CT
POUT
PBOUT = (9)
PWM
where is the overall efficiency and PWM is the forward [STEP-3] Line Sensing Circuit Design
converter efficiency.
FAN480X senses the RMS value and instantaneous value of
The nominal output current of boost PFC stage is given as: line voltage using the VRMS and IAC pins, respectively, as
shown in Figure 13. The RMS value of the line voltage is
POUT obtained by an averaging circuit using low pass filter with
I BOUT = (10)
PWM VBOUT two poles. Meanwhile, the instantaneous line voltage
information is obtained by sensing the current flowing into
PBOUT
PIN IBOUT POUT IAC pin through RIAC.
VIN

Boost VBOUT Forward VOUT IL

PFC DC/DC

Figure 12. Two Stage Configuration

(Design Example)
IAC
POUT 300 RIAC
PIN = = = 366W IA
C
0.82 VRMS
RRMS1 120/100Hz
VIN
POUT 300
PBOUT = = = 349W CRMS1 RRMS2
PWM 0.86 VRMS
CRMS2

POUT 300 fp1 fp2

I BOUT = = = 0.9 A
PWM VBOUT 0.86 387 RRMS3

[STEP-2] Frequency Setting Figure 13. Line Sensing Circuits

The switching frequency is determined by the timing resistor RMS sensing circuit should be designed considering the
and capacitor (RT and CT) as: nominal operation range of line voltage and brownout
1 1 protection trip point as:
f SW (11)
4 0.56 RT CT
2 RRMS 3 2
It is typical to use a 470pF~1nF capacitor for 50~75kHz VRMS UVL = VLINE .BO (13)
RRMS 1 + RRMS 2 + RRMS 3
switching frequency operation since the timing capacitor
value determines the maximum duty cycle of PFC gate drive 2 RRMS 3
VRMS UVH < VLINE .MIN (14)
signal as: RRMS 1 + RRMS 2 + RRMS 3
TOFF .MIN where VRMS-UVL and VRMS-UVH are the brown OUT/IN
DMAX .PFC = 1 = 1 360 CT f SW (12)
TSW thresholds of VRMS.

It is typical to set RRMS2 as 10% of RRMS1. The poles of the

low pass filter are given as:
1
f P1 (15)
2 CRMS 1 RRMS 2
1
fP2 (16)
2 CRMS 2 RRMS 3

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 6
AN-8027

To properly attenuate the twice line frequency ripple in The average of boost inductor current over one switching
VRMS, it is typical to set the poles around 10~20Hz. cycle at the peak of the line voltage for low line is given as:

The resistor RIAC should be large enough to prevent 2 POUT

I L. AVG = (20)
saturation of the gain modulator as: VLINE .MIN
Therefore, with a given current ripple factor
2VLINE . BO
G MAX < 159 A (17) (KRB=IL/ILAVG), the boost inductor value is obtained as:
RIAC
where VLINE.BO is the brownout protection line voltage, VLINE .MIN 2 VBOUT 2VLINE 1
LBOOST = (21)
GMAX is the maximum modulator gain when VRMS is 1.08V K RB POUT VBOUT f SW
(which can be found in the datasheet), and 159A is the The maximum current of boost inductor is given as:
maximum output current of the gain modulator.
K RB 2 POUT K
I L PK = I L. AVG (1 + )= (1 + RB ) (22)
(Design Example) The brownout protection threshold is 2 VLINE .MIN 2
1.05V (VRMS-UVL) and 1.9V (VRMS-UVH), respectively.
Then, the scaling down factor of the voltage divider is:
RRMS 3 V (Design Example) With the ripple current
= RMS UVL specification (40%), the boost inductor is obtained as:
RRMS 1 + RRMS 2 + RRMS 3 VLINE . BO 2 2
1.05 VLINE .MIN 2 VBOUT 2VLINE 1
= = 0.0162 LBOOST =
72 2 2 K RB POUT VBOUT f SW
Then the startup of the PFC stage at the minimum line 852 0.82 387 2 85 103
= = 524 H
voltage is checked as: 0.4 300 387 65
The average of boost inductor current over one
VLINE .MIN 2 RRMS 3 switching cycle at the peak of the line voltage for low
= 85 2 0.0162 = 1.95 > 1.9V
RRMS 1 + RRMS 2 + RRMS 3 line is obtained as:

The resistors of the voltage divider network are selected 2 POUT 2 300
I L. AVG = = = 6.09 A
as RRMS1=2M, RRMS1=200k, and RRMS1=36k. VLINE .MIN 85 0.82
To place the poles of the low pass filter at 15Hz and The maximum current of the boost inductor is given as:
22Hz, the capacitors are obtained as:
1 1 2 POUT K
CRMS1 = = = 53nF I L PK = (1 + RB )
2 f P1 RRMS 2 2 15 200 103 VLINE .MIN 2
1 1 2 300 0.4
CRMS 2 = = 200nF = (1 + ) = 7.31A
2 f P 2 RRMS 3 2 22 36 103 85 0.82 2
The condition for Resistor RIAC is:
2VLINE .BO MAX 2 72 9 [STEP-5] PFC Output Capacitor Selection
RIAC > G = = 5.8M
159 106 159 106
The output voltage ripple should be considered when
Therefore, 6M resistor is selected for RIAC. selecting the PFC output capacitor. Figure 14 shows the
twice line frequency ripple on the output voltage. With a
given specification of output ripple, the condition for the
output capacitor is obtained as:
[STEP-4] PFC Inductor Design I BOUT
CBOUT > (23)
The duty cycle of boost switch at the peak of line voltage is 2 f LINE VBOUT , RIPPLE
given as: where IBOUT is nominal output current of boost PFC stage
and VBOUT,RIPPLE is the peak-to-peak output voltage ripple
VBOUT 2VLINE
DLP = (18) specification.
VBOUT
The hold-up time also should be considered when
Then, the maximum current ripple of the boost inductor at determining the output capacitor as:
the peak of line voltage for low line is given as:
PBOUT tHOLD
2VLINE .MIN VBOUT 2VLINE 1 CBOUT > (24)
I L = (19) VBOUT 2 VBOUT , MIN 2
LBOOST VBOUT f SW
where PBOUT is nominal output power of boost PFC stage,
tHOLD is the required holdup time, and VBOUT,MIN is the
allowable minimum PFC output voltage during hold-up time.

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 7
AN-8027

ID

I D , AVG

I D , AVG = I BOUT (1 cos(4 f LINE t ))

I BOUT

I BOUT
VBOUT , RIPPLE = Figure 15. Two-Level PFC Output Block
2 f LINE CBOUT
The voltage divider network for the PFC output voltage
sensing should be designed such that FBPFC voltage is
VBOUT 2.5V at nominal PFC output voltage:
RFB 2
VBOUT = 2.5V (26)
Figure 14. PFC Output Voltage Ripple RFB1 + RFB 2

(Design Example) Assuming the second level of

(Design Example) With the ripple specification of PFC output voltage is 347V:
12VPP, the capacitor should be:
VBOUT 2 2.5
RFB 2 = (1 )
CBOUT >
I BOUT
=
0.9
= 239 F
VBOUT 20 106
2 f LINE VBOUT , RIPPLE 2 50 12 347 2.5
= (1 ) = 12.9k
Since minimum allowable output voltage during one 387 20 106
cycle line (20ms) drop-outs is 310V, the capacitor 13k is selected for RFB2.
should be:
PBOUT t HOLD 2 349 20 103 VBOUT
CBOUT > = = 260 F RFB1 = ( 1) RFB 2
2
VOUT VOUT , MIN 2 2
387 310 2 2.5
387
=( 1) 13 103 = 1999k
Thus, 270F capacitor is selected for the PFC output 2.5
capacitor. 2M is selected for RFB1.

[STEP-6] PFC Output Sensing Circuit

[STEP-7] PFC Current-Sensing Circuit Design
To improve system efficiency at low line and light load
condition, FAN480X provides two-level PFC output Figure 16 shows the PFC compensation circuits. The first
voltage. As shown in Figure 15, FAN480X monitors VEA step in compensation network design is to select the current-
and VRMS voltages to adjust the PFC output voltage. sensing resistor of PFC converter considering the control
window of voltage loop. Since line feed-forward is used in
The PFC output voltage when 20A is enabled is given as: FAN480X, the output power is proportional to the voltage
control error amplifier voltage as:
20 A RFB 2
VBOUT 2 = VBOUT (1 - ) (25)
2.5 VEA 0.6
PBOUT (VEA ) = PBOUT MAX (27)
VEA SAT 0.6
It is typical second boost output voltage as 340V~300V.
where VEASAT is 5.6V and the maximum power limit of PFC
is:
VLINE . BO 2 G MAX RM
PBOUT MAX = (28)
RIAC RCS 1

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 8
AN-8027

It is typical to set the maximum power limit of PFC stage where VRAMP is the peak to peak voltage of ramp signal for
around 1.2~1.5 of its nominal power such that the VEA is current control PWM comparator, which is 2.55V.
around 4~4.5V at nominal output power. By adjusting the
The transfer function of the compensation circuit is given as:
current-sensing resistor for PFC stage, the maximum power
limit of PFC stage can be programmed. s
) 1+
To filter out the current ripple of switching frequency, an vIEA 2 f II 2 f IC
) =
s
(31)
RC filter is typically used for ISENSE pin. RLF1 should not vCS 1 s 1+
be larger than 100 and the cut-off frequency of filter 2 f IP
should be 1/2~1/6 of the switching frequency. where:
Diodes D1 and D2 are required to prevent over-voltage on GMI 1
ISENSE pin due to the inrush current that might damage f II = , f IZ = and
2 CIC1 2 RIC CIC1
the IC. A fast recovery diode or ultra fast recovery diode is (32)
recommended. 1
f IP =
2 RIC CIC 2

The procedure to design the feedback loop is as follows:

(a) Determine the crossover frequency (fIC) around
1/10~1/6 of the switching frequency. Then calculate
the gain of the transfer function of Equation (30) at
crossover frequency as:
)
vCS1 RCS1 VBOUT
) = (33)
vIEA @ f = f IC
VRAMP 2 f IC LBOOST

(b) Calculate RIC that makes the closed loop gain unity at
crossover frequency:
1
RIC = )
v (34)
GMI )CS1
vIEA @ f = f IC

Figure 16. Gain Modulation Block

(c) Since the control-to-output transfer function of power
stage has -20dB/dec slope and -90o phase at the
crossover frequency is 0dB, as shown in Figure 17; it
(Design Example) Setting the maximum power limit is necessary to place the zero of the compensation
of PFC stage as 450W, the current sensing resistor is network (fIZ) around 1/3 of the crossover frequency so
obtained as: that more than 45 phase margin is obtained. Then the
capacitor CIC1 is determined as:
VLINE .BO 2 G MAX RM 722 9 5.7 103
RCS 1 = = = 0.098
RIAC PBOUT MAX 6 106 450 1
CIC1 = (35)
RIC 2 fC / 3
Thus, 0.1 resistor is selected.

(d) Place compensator high-frequency pole (fCP) at least a

[STEP-8] PFC Current Loop Design
decade higher than fIC to ensure that it does not
The transfer function from duty cycle to the inductor interfere with the phase margin of the current loop at
current of boost power stage is given as: its crossover frequency.
)
iL V 1
) = BOUT (29) CIC 2 = (36)
d sLBOOST 2 f IP RIC

The transfer function from the output of the current control

error amplifier to the inductor current-sensing voltage is
obtained as:
)
vCS 1 RCS 1 VBOUT
) = (30)
vIEA VRAMP sLBOOST

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 9
AN-8027

60dB
Closed Loop Gain
Control-to-output
40dB

Compensation
20dB
fIP
0dB fIZ
fIC

-20dB

-40dB
10Hz 100Hz 1kHz 10kHz 100kHz 1MHz

Figure 17. Current Loop Compensation

Figure 18. Voltage Loop Compensation

(Design Example) Setting the crossover frequency

as 7kHz: The transfer function of the compensation network is
obtained as:
)
vCS 1 RCS 1 VBOUT s
) = 1+
vIEA @ f = f VRAMP 2 f IC LBOOST vCOMP 2 fVI 2 fVZ
IC
= (39)
0.1 387 vOUT s s
= = 0.66 1+
2.55 2 7 103 524 10 6 2 fVP
where:
1 1
RIC = ) = = 17 k 2.5 GMV 1
v 88 106 0.66 fVI = , fVZ = and
GMI )CS 1 VBOUT 2 CVC1 2 RVC CVC1
vIEA (40)
@ f = f IC 1
fVP =
2 RVC CVC 2
1 1
C IC1 = = = 4nF
RIC 2 fC / 3 17 103 2 7 103 / 3 The procedure to design the feedback loop is as follows:
Setting the pole of the compensator at 70kHz, (a) Determine the crossover frequency (fVC) around
1/10~1/5 of the line frequency. Since the control-to-
1 1
CIC 2 = = = 0.13nF output transfer function of power stage has -20dB/dec
2 f IP RIC 2 70 103 17 103 slope and -90o phase at the crossover frequency, as
shown in Figure 18 as 0dB; it is necessary to place the
zero of the compensation network (fVZ) around the
crossover frequency so that 45 phase margin is
[STEP-9] PFC Voltage Loop Design obtained. Then, the capacitor CVC1 is determined as:

Since FAN480X employs line feed-forward, the power GMV I BOUT K MAX 2.5
CVC1 = (41)
stage transfer function becomes independent of the line 5 C BOUT (2 fVC ) 2 VBOUT
voltage. Then, the low-frequency, small-signal, control-to- To place the compensation zero at the crossover
output transfer function is obtained as: frequency, the compensation resistor is obtained as:
vBOUT I BOUT K MAX 1 1
(37) RVC = (42)
vEA 5 sCBOUT 2 fVC CVC1
where:
vBOUT I BOUT K MAX 1
(38) (b) Place compensator high-frequency pole (fVP) at least
vEA 5 sCBOUT a decade higher than fC to ensure that it does not
interfere with the phase margin of the voltage
Proportional and integration (PI) control with high- regulation loop at its crossover frequency. It should
frequency pole is typically used for compensation. The also be sufficiently lower than the switching
compensation zero (fVZ) introduces phase boost, while the frequency of the converter so noise can be effectively
high-frequency compensation pole (fVP) attenuates the attenuated. Then, the capacitor CVC2 is determined as:
switching ripple, as shown in Figure 18. 1
CVC 2 = (43)
2 fVP RVC

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 10
AN-8027

Once the core for the transformer is determined, the

(Design Example) Setting the crossover frequency minimum number of turns for the transformer primary-side
as 22Hz: to avoid saturation is given by:
MIN
GMV I BOUT K MAX 2.5 V DMAX
CVC1 = N P MIN = BOUT (44)
5 C BOUT (2 fVC ) 2 VBOUT Ae f SW B
where Ae is the cross sectional area of the core in m2, fSW is
70 10 6 0.9 1.27 2.5
= 6
= 20nF the switching frequency, and B is the maximum flux
5 270 10 (2 22) 387
2
density swing in Tesla for normal operation. B is typically
1 1 0.2-0.3 T for most power ferrite cores in the case of a
RVC = = = 362k forward converter.
2 fVC CVC1 2 22 20 109
The turn ratio between the primary-side and secondary-side
Setting the pole of the compensator at 120Hz: winding for the first output is determined by:
MIN
1 1 N V DMAX
CVC 2 = = = 3.7 nF n = P = BOUT (45)
2 fVP RVC 2 120 362 103 N S1 (VO1 + VF 1 )
where VF is the diode forward-voltage drop.
[STEP-10] Transformer Design for PWM Next, determine the proper integer for NS1 resulting in Np
Stage larger than Npmin. Once the number of turns of the first
output is determined, the number of turns of other output
Figure 19 shows the typical secondary-side circuit of (n-th output) can be determined by:
forward converter for multi-output of PC power application.
VO ( n ) + VF ( n )
A common technique for winding multiple outputs with the N S (n) = N S1 (46)
VO1 + VF 1
same polarity sharing a common ground is to stack the
secondary windings instead of winding each output
winding separately. This approach improves the load The golden ratio between the secondary-side windings for
regulation of the stacked outputs. The winding NS1 in the best regulation of 3.3V, 5V, and 12V is known as
Figure 19 must be sized to accommodate its output current, 2:3:7.
plus the current of the output (+12V) stacked on top of it.
(Design Example) The minimum PFC output voltage
To get tight regulation of 3.3V output, magnetic amplifier
is 310V and the maximum duty cycle of PWM
(MAG-AMP) is used. The saturable core of MAG-AMP
controller is 50%. By adding 5% margin to the
prevents the diode DREC from fully conducting by
maximum duty cycle, DMAX=0.45 is used for
introducing high impedance until it is saturated. This
transformer design. Assuming ERL35 (Ae=107mm2)
allows the effective duty cycle of VREC to be controlled to
be regulated the output voltage. core is used and B=0.28, the minimum turns for the
transformer primary side is obtained as:
Additiona
l LC filter VBOUT MIN DMAX 310 0.45
N P MIN = = = 72
+12V Ae f SW B 107 10 6 65 103 0.28
NS
2
The turns ratio for 5V output is obtained as:
N P VBOUT MIN DMAX 310 0.45
n= = = = 25.6
Additiona
+5V NS (VO + VF ) (5 + 0.45)
Np NS l LC filter
1
The number of turns for the primary-side winding is
determined as:

MAG MAG AMP N p = n N S 1 = 2 25.6 = 51.2 < N P MIN

AMP Control
+3.3
V N p = n N S 1 = 3 25.6 = 76.8 > N P MIN N S 1 = 3
DREC
+ Additiona Then, the turns ratio for 12V output is obtained as:
VREC l LC filter

VO 2 + VF 2 12 + 0.7
-
NS 2 = N S1 = 3 = 6.99 7
VO1 + VF 1 5 + 0.45

Therefore, the number of turns for each winding is

Additiona
-12V obtained as:
NS
l LC filter
3 Np=78, NS1=3, NS2=7 (3+4 stack) and NS3=7.

Figure 19. Typical Secondary-Side Circuit

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 8/26/09 11
AN-8027

[STEP-11] Coupled Inductor Design for the
PWM Stage
When the forward converter has more than one output, as
shown in Figure 20, coupled inductors are usually employed
to improve the cross regulation and to reduce the ripple.
They are implemented by winding their separate coils on a
single, common core. The turns ratio should be the same as
the transformer turns ratio of the two outputs as:
NS 2 NL2
= (47)
N S 1 N L1
L2
N NL2
One way to understand the operation of coupled inductor is
to normalize the outputs to one output. Figure 21 shows
how to normalize the second output (VO2) to the first
output (VO1). The transformer and inductor turns are
divided by NS2/NS1, the voltage and current are adjusted by
NS2/NS1. It is assumed that the leakage inductances of the
coupled inductor are much smaller than the magnetizing
inductance and evenly distributed for each winding.
The inductor value of the first output can be obtained by:
VO1 (VO1 + VF 1 )
L1 = (1 DMIN )
I (48)
f SW ( PO1 + PO 2 ) SUM
I SUM
where:
V MIN

p N S2 VO2 DMIN = DMAX BOUT

VBOUT
(49)
PO1 + PO 2
I SUM =
VO1
NL1
Then, the ripple current for each output is given as:
L1 I O1 I SUM 1
= (50)
N S1 I O1 2 I O1
VO1 I O 2 I SUM N S 1 1
= (51)
IO 2 2 N S 2 IO 2

Figure 20. Coupled Inductor

(Design Example) The minimum duty cycle of
D1 L1 VO1
PWM stage at nominal input (PFC output) voltage is:
VBOUT MIN 310
VPOUT N S1
IO1
DMIN = DMAX = 0.45 = 0.36
NP VBOUT 389
0
The sum of two normalize output current is:
D2 VO2 PO1 + PO 2 243
I SUM = = = 48.6 A
L2 IO2 VO1 5
VPOUT N S 2
NP
Assuming 16% p-p ripple current in LSUM, the inductor
0 for the first output is obtained as:
VO1 (VO1 + VF 1 )
VO 2 N =
N S1
VO 2 = VO1
L1 = (1 DMIN )
I
NS 2
Normalized
f SW ( PO1 + PO 2 ) SUM
NS 2 I SUM
IO 2 N = IO 2
N S1 5(5 + 0.45)
= (1 0.36) = 6.9uH
65 103 (5 9 + 12 16.5) 0.16
ISUM LM LLK D1 VO1

IO2
VPOUT N S1 Then, the ripple current for each output is given as:
NP
I O1 I SUM 1 48.6 0.16 1
0
= = = 43%
I O1 2 I O1 2 9
D2N VO2N

LLK IO2N I O 2 I SUM N S 1 1 48.6 0.16 3 1

= = = 10%
IO 2 2 N S 2 IO 2 2 7 16.5

Figure 21. Normalized Coupled Inductor Circuit

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 12
AN-8027

[STEP-12] PWM Ramp Circuit Design [STEP-13] Feedback Compensation Design

For voltage-mode operation, the RAMP pin can be for PWM Stage
connected to a DC voltage through a resistor. When it is Figure 21 shows the typical cross regulation compensation
connected to the input of forward converter, ramp signal circuit configuration for multi-output converters. The small
slope is automatically adjusted according to the input signal characteristics of the compensation network is given as:
voltage providing line feed-forward operation. However, it )
vFBPWM
can cause more power dissipation in the resistor. For better
RB 1 + s / CZ 1 ) 1 + s / CZ 2 )
efficiency and lower standby power consumption, it is = ( vO1 + vO 2 ) (53)
recommended to connect the RAMP pin to the VREF pin. 1 + s / CP ROS 1 RD CF s ROS 2 RD CF s

where:
1
CP =
( RB1 // RB 2 )CB
1
CZ 1 = (54)
RF C F
1
CZ 2 =
( RF + ROS 2 )CF

VO2 VO1
VREF
ROS1
RB1 RD ROS2
Figure 22. Ramp Generation Circuit for PWM
FBPWM

It is typical to use 470pF~1nF capacitor on the RAMP pin

and to have the peak of the ramp signal around 2~3V. RF CF

The peak of the ram voltage is given as: RB

1 VREF 1 KA431
VRAMP PK = (52) CB ROS3
CRAMP RRAMP 2 f SW

(Design Example) Selecting CRAMP and RRAMP as

Figure 23. Feedback Compensation Circuit for
1nF and 22k, the PWM ramp voltage is obtained as:
PWM Stage
1 VREF 1 The small signal equivalent circuit for control-to-output
VRAMP PK =
CRAMP RRAMP 2 f SW transfer function of the PWM power stage can be simplified
1 7.5 1 as shown in Figure 24. The transfer function is fourth-order
= 9
= 2.6V system because additional LC filters are used to meet the
1 10 22 10 2 65 103
3
output voltage ripple specification. Therefore, it is
recommended to use engineering software, such as PSPICE
or Mathlab, to design the feedback loop.
N S1 LM
VBOUT LLK LL12 VO1
NS 2

CO11 CO12 RL1

1
VRAMP VO2N VO2

LLK L22N
VFBPWM
CO21N CO22N
RL2N

NS1:NS2

Figure 24. Simplified Small Signal Equivalent Circuit

for Control-to-Output Transfer Function

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 13
AN-8027

Design Summary
Application Output Power Input Voltage Output Voltage / Output Current
ATX Power 300W 85~264VAC 12V/16.5A5V/9A-12V/0.8A 3.3V/13.5A

Features
Meets 80+ specification
FAN4800A fully pin-to-pin compatible with ML4800 and FAN4800 (needs few parts modify)
Switch-charge technique of gain modulator can provide better PF and lower THD
Leading and trailing modulation technique for reduce output ripple
Protections: OVP (Over-Voltage Protection), UVP (Under-Voltage Protection), OLP (Open-Loop Protection), and
maximum current limit

1.8uH
F1 L BOOST DBOOST VBOUT FYPF2006DN L 11 L1
2
Vo1 12V
AC BYC10600 DR1 CO11
FDA18N50 FCP11N60 CO12
Input CBOOST R FB1
CIF1 DR1 DF1 2200uF 1000uF
Q1 2M
Q2
5 270uF FR157
RCS1 DR2 L22 2uH
10 k Vo2 5V
0.1 L2 CO21 CO22
1
D1 100 nF FCP11N60 DF2 1000uF
D2 2200uF

STPS60L45CW
FR157
10 k Q3
R RAMP DR2 SF34DG
Vo3 -12V
22k L3
1
CO31 220uF
RLF2
0.13nF CIC2 RCS2 L43 3.3V
Vo4
2M R IAC 17k 4nF L4 L 4 CO21
RLF1 6M
1 2
RRMS1 RIC CIC1 DF2 CO22
RT
53nF IEA VEA
6.9 k
CRMS1 200 K IAC FBPFC FR157 10
RRMS2 RB 7.5k
ISENSE VREF 362k
VD 1k
VD
VRMS D
200n CLF1 CSS
D RVC FR157 300
36 k SS OPFC 3.7nF 3.4 k
F
CRMS2 R FBPWM
RMS3 OPWM
10 20nF CVC2 1.2 k
RT/CT GND Vo1 1uF 10 k
CT
RAMP ILIMIT CVC1 RD 12V
1nF 5.45 k
1nF
FAN480X 32.4 k
12.9k
CRAMP RFB2 CF RF ROS1
0.47nF
100 11 k 5V
CB CFB
nF
Vo2
CLF2 CDD CREF ROS2
4.64 k
ROS3

Figure 25. Final Schematic of Design Example

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 14
AN-8027

Margin Tape Margin Tape

3mm 3mm

Mylar Tape 3T
N5
Mylar Tape 1T
N4
Mylar Tape 1T
N3
Mylar Tape 1T
N2
Mylar Tape 3T
N1
BOBBIN-ERL35
Figure 26. Forward Converter Transformer Structure

Winding Specification
No Pin(s-f) Wire Turns Winding Method
N1 3-2 0.6 37Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03mm, 3 Layers
N2 8,9-10,11,12 Copper-Foil 10mil 3Ts Copper-Foil Width 18mm
Insulation: Mylar Tape t = 0.03mm, 1 Layers
N3 13-8,9 1.0*4 4Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03mm, 1 Layers
N4 10,11,12-14 0.4 6Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03mm, 1 Layers
N5 2-6,7 0.6 37Ts Solenoid Winding
Insulation: Mylar Tape t = 0.03mm, 3 Layers
Core-ERL35
Insulation: Mylar Tape t = 0.03mm, 3 Layers
Insulation: Copper-Foil Tape t = 0.05mm-pin1 Open Loop
Insulation: Mylar Tape t = 0.03mm, 3 Layers

Core: ERL35 (Ae=107 mm2)

Bobbin: ERL35
Inductance: 13mH

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 15
AN-8027

Appendix A
FAN480X Series Comparison Table of Relevant Parameters

New New New New

FAN4800 Generation Generation Generation Generation
FAN4800A FAN4800C FAN4801 FAN4802/2L
VDD Maximum Rating 20V 30V
VDD OVP 17.9V/Clamp 28/Auto-Recover
VCC UVLO 10V/13V 9.3/11V
Two-Level PFC
NO NO YES
Output
PFC Soft-Start NO YES
Brownout NO YES
PFCPWM
11 11 12 11 12
Frequency
Frequency Range 68kHz~81kHz 50kHz~75kHz
Gate Clamp NO 16V
PFC Multiplier Traditional Switching Charge
VINOK 2.25V/1.1V 2.40V/1.15V
PWM Maximum Duty 42%~49% 49.5%~50%
Startup Current 100A 30A
Soft-Start Current 20A 10A
PWM Comparator
1.0V 1.5V
Level Shift
RAC 1~2M 5~8 M

MOSFET and Diode Reference Specification

PFC MOSFETs
Voltage Rating Part Number
FQP13N50C, FQPF13N50C, FDP18N50, FDPF18N50, FDA18N50, FDP20N50(T),
500V
FDPF20N50(T)
FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCP20N60S, FCPF20N60S, FCA20N60S,
600V
FCP20N60, FCPF20N60
Boost Diodes
600V FFP08H60S, FFPF10H60S, FFP08S60S, FPF08S60SN, BYC10600
PWM MOSFETs
FQP/PF9N50C, FQPF9N50C, FQP13N50C, FQPF13N50C, FQA13N50C, FDP18N50,
500V
FDPF18N50, FDP20N50(T), FDPF20N50(T)
FCP11N60, FCPF11N60, FCP16N60, FCPF16N60, FCA16N60, FCP20N60S, FCPF20N60S,
600V
FCA20N60S, FCP20N60, FCPF20N60, FCA20N60

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 16
AN-8027

References
FAN480X PFC/Forward PWM Controller Combo (FAN4800, FAN4801, FAN4802)
AN-6078SC FAN480X PFC+PWM Combo Controller Application
AN-6004 500W Power Factor Corrected (PFC) Design with FAN4810
AN-6032 FAN4800 Combo Controller Applications
AN-42030 Theory and Application of the ML4821 Average Current Mode PFC Controller
AN-42009 ML4824 Combo Controller Applications
ATX 300W 80+ Evaluation Board of FAN4800A+SG6520+FSQ0170

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 8/26/09 17