CMOS TECHNOLOGY

Izzani Mohd Israz 2013742633

Nurul Afiqah Abdul Rahim 2013475976
Nurul Ibtisam Mat Seman 2013707673
Nur Aiman Nabihah Ahmad Sarbini 2013383197
PHY605 / AS251 5D
 What is CMOS and what is it for?
CMOS is the term usually used to describe the small amount of memory on a computer motherboard
that stores the BIOS settings.
CMOS : Complementary-Metal-Oxide-Semiconductor

What is CMOS?
CMOS is the semiconductor technology used in
the transistors that are manufactured into most
of today's computer microchips. [1]
CMOS technology is used in microprocessors,
microcontrollers, static RAM, and other digital
logic circuits.
CMOS technology is also used for several analog
circuits such as image sensors (CMOS sensor),
data converters, and highly integrated
transceivers for many types of communication.
Figure : CMOS Battery on the motherboard [1]

[1] Photo/Source from : https://www.lifewire.com/what-is-cmos-2625826 2

CMOS
COMPLEMENTARY-METAL-OXIDE SEMICONDUCTOR
CMOS is also sometimes referred to as complementary-
symmetry metaloxidesemiconductor ( COS-MOS).

The words "complementary-symmetry" refer to the fact

that the typical design style with CMOS uses
complementary and symmetrical pairs of p-type and n-
type metal oxide semiconductor field effect transistors
(MOSFETs) for logic functions.

3
 1.
INTRODUCTION
Lets start with the first set of slides ; Introduction to CMOS, CMOS
evolution, structures, advantages and its applications

EVOLUTION ADVANTAGES

INTRODUCTION STRUCTURES APPLICATIONS

4
 CMOS circuit uses a
combination of p-type and n-type
metal-oxide-semiconductor-field-effect transistors (MOSFETs) to
implement logic gates and other digital circuits. [2]

In CMOS technology, both kinds of transistors are

used in a complementary way to form a current
gate that forms an effective means of electrical
CMOS circuitry dissipates less power
when static, and is denser than other
implementations having the same
control. functionality.

CMOS transistors use almost no power when not

needed. As the current direction changes more
rapidly, however, the transistors become hot. This
characteristic tends to limit the speed at which
microprocessors can operate.

INTRODUCTION 5
[2] Photo/Source from : https://en.wikipedia.org/wiki/Talk:CMOS
 CMOS EVOLUTION
The first working point contact transistor developed by John Bardeen, Walter Brattain and William Shockley at Bell
laboratories in 1947 initiated the rapid growth of the information technology industry.
1947

J Kilby invented the first integrated circuit flip flop at Texas

1958

Frank Wanlass at Fairchild described the first CMOS logic gate (nMOS and pMOS)
Gordon Moore predicted that as a result of continuous miniaturization, transistor count would double every 18 months. The
1963 number of components on the most complex integrated circuit chip would double each year for the next 10 years

Intel 4004 had transistors with minimum dimension of 10um and in 2003; Pentium 4 had transistors with minimum dimension of
130 nm. Having crossed 90nm, 65nm technological nodes, 32 nm and 22nm technology is in the pipeline. 53% compound annual
1971 growth rate is achieved over 45 years

Demand for digital logic devices accelerated the transition from NMOS IC to CMOS IC
1980

CMOS IC process technology developed rapidly

1990

Pentium 4 had transistors with minimum dimension of 130 nm. Having crossed 90nm, 65nm technological nodes, 32 nm and
22nm technology is in the pipeline. 53% compound annual growth rate is achieved over 45 years
2003

EVOLUTION 6
 CMOS STRUCTURE
As we know, the CMOS structure is basically from the combination of PMOS and NMOS
FeT in forming the circuit. The PMOS and NMOS structure can be seen below :

PMOS Transistor NMOS Transistor

Source Gate Drain

Polysilicon
SiO2

n+ n+

p bulk Si

STRUCTURES 7
CMOS STRUCTURE
There some things we need to aware in CMOS Structure : Well
formation in CMOS, the isolation type in CMOS, gate formation in
CMOS and the interconnection in it.

Well Isolation Gate Inter-

Formation Type Formation connection

STRUCTURES 8
 CMOS STRUCTURE
Well Formation

Well can be formed in three ways, either single well, self aligned twin well, and twin well.
Single Well Self Aligned Twin Well Twin Well

STRUCTURES 9
 CMOS STRUCTURE
Isolation Type
The isolation type in CMOS : Blanket Field Oxide, LOCOS, Shallow Trench Isolation.
Blanket Field Oxide
Used early in IC fabrication,
a simple and straight forward
process.
Can be form by growing an
oxide layer with the desired
thickness on a flat Si surface,
then patterning and etching
activation windows on the
oxide layer.
It was used until 1970.
Disadvantages :
The active window has a high
oxide step with sharp edge,
which is very difficult to cover in
the subsequently metal
deposition process.
The channel stop doping has
to be done before the oxidation,
which requires the field oxide to
align with the isolation doping
region. This requirement causes
difficulties in feature size
reduction.
LOCOS Oxide
Advantage : the SiO2 is grown after the
channel stop implantation.
The field oxide layer is self-aligned with the
isolation doping area.
LPCVD silicon nitride is used as the oxidation
mask, which allows only the thick SiO2is called
LOCOS to grow at the designated area.
Nitride is a very dense layer; it can prevent
oxidation on p-well by blocking oxygen
diffusion. Also it can prevent n-type ions from
penetrating to the p-well during ion
implantation.
STRUCTURES
STI
Since the transistor are surrounded by
isolation oxide. Fences are used to
separate neighbouring houses; in IC
fabrication, their equivalence is shallow
trench isolation.
A STI process was then developed with
CVD oxide trench fill instead of the
thermal oxidation.
Its involved many steps such as
oxidation, nitride deposition,
nitride/oxide etch, silicon etch, oxide
CVD, oxide annealing etc.
The main challenges in STI process as a
device feature size continues to shrink
are single-crystal silicon etch, oxide CVD
ad oxide CMP.
10
CMOS STRUCTURE
Gate Formation
To form the gate, the are some important characteristics :

Gate is wider than Source-Drain distance

The gate must be formed to ensure the coverage of the Source-Drain
The gate is replaced from aluminium alloy to polysilicon gate.

Why Polysilicon?
High melting point
Also attractive for the easy manufacturing of self-
aligned gates.
Same chemical composition as silicon channel beneath
the gate oxide
Can be deposited easily via chemical vapor
deposition (CVD)

STRUCTURES 11
CMOS STRUCTURE
Inter-connection

STRUCTURES 12
CMOS STRUCTURE
CMOS TECHNOLOGY LOGIC CIRCUIT STRUCTURES

Standard CMOS
Complementary Clocked CMOS
Logic CMOS logic with Bipolar Driver (BICMOS)

Pseudo-NMOS
Saturated NMOS Load
Ratio Circuit Logic Saturated PMOS Load
Depletion NMOS Load (E/D)

CMOS Domino Logic

NP Domino Logic (Zipper CMOS)
Dynamic Logic Cascade voltage Switch Logic (CVSL)
Sample-set Differential Logic (SSDL)

STRUCTURES 13
 CMOS STRUCTURE
CMOS LOGIC INVERTER

A Z

0 1

1 0

Symbol Truth table Inverter schematic

The inverter circuit as shown in the figure consist of two complimentary MOSFETs PMOS
and NMOS. The input serves as the gate voltage for both transistor.

The NMOS transistor have an input from ground and PMOS transistor have an input from
Vdd. The output serves for both NMOS and PMOS.

When the high voltage input at Vdd is given at 1, the NMOS is turn on while the PMOS is
switched off. The output is pulled-down to the ground. Similarly, when low gate voltage
input is apply, the PMOS is switch on while NMOS is switch off. The output is pulled-up to
Vdd.

STRUCTURES 14
 CMOS STRUCTURE
CMOS LOGIC NAND GATE

A B Z
0 0 1
0 1 1
1 0 1
1 1 0

Circuit schematic

The NMOS transistor have an input from ground and PMOS transistor have an input from
Vdd. The output serves for both NMOS and PMOS.

The two input NAND gate has two NMOSs and two PMOSs. The NMOSs are in series
while the PMOSs are connected in parallel. That means that for the output to be low (0)
both NMOSs must be turned on (both inputs high or 1).

STRUCTURES 15
 CMOS STRUCTURE
CMOS LOGIC NOR GATE

A B Z
0 0 1
0 1 0
1 0 0
1 1 0

Circuit schematic

The NMOS transistor have an input from ground and PMOS transistor have an input from
Vdd. The output serves for both NMOS and PMOS.

The topology of the NOR gate is the same as that of the NAND gate but turned upside
down. The output of the NOR gate is only high or 1 when both PMOSs are turned on (both
inputs are low or 0).

STRUCTURES 16
CMOS STRUCTURE
CMOS TECHNOLOGY LOGIC CIRCUIT STRUCTURES

STRUCTURES 17
CMOS ADVANTAGES
High input impedance.
The input signal is driving
electrodes with a layer of
insulation (the metal oxide)
between them and gives them a
small amount of capacitance, but
virtually infinite resistance.
Little power
CMOS logic takes very little power
when held in a fixed state. The
current consumption comes from
switching as those capacitors are
charged and discharged.
Active output
The outputs actively drive both
ways. The outputs are also
pretty much rail-to-rail.
Simple
CMOS gates are very simple.
The basic gate is a inverter,
which is only two transistors.
This together with the low
power consumption means it
lends itself well to dense
integration
ADVANTAGES 18
 CMOS APPLICATIONS

Figure : CMOS Applications [3]

[3] Photo/Source from : Yole Development 19

APPLICATIONS
 CMOS APPLICATIONS

Figure : Evolution of CMOS applications over the years[4]

[4] Photo/Source from : www.nextbigfuture.com 20

APPLICATIONS
 2.
CMOS FABRICATION
Lets see the CMOS fabrication starting from the fabrication overview, the
mask set in CMOS fabrication, the step and the design rules for fabricating
the CMOS technology.

MASK SET FABRICATION STEP

OVERVIEW DESIGN RULES

21
 FABRICATION OVERVIEW

OVERVIEW 22
MASK SET

Metal 1
oxide
n+ n+ p+ p+

N-well

p-substrate

MASK SET 23
 DETAILED MASK VIEWS

Six masks
* n-well
* Polysilicon
* n+ diffusion
* p+ diffusion
* Contact
* Metal

MASK SET 24
 MASK LAYOUT [5]

MASK SET
[5] Photo/Source from : portal.unimap.edu.my/portal/page/portal30/.../CMOS%20Fabrication.ppt
25
 FABRICATION STEPS

Step 1: Si Substrate
Start with p- type substrate

Step 2: Oxidation
Exposing to high-purity oxygen and hydrogen at approx. 1000C in oxidation furnace

FABRICATION STEPS 26
 FABRICATION STEPS
Step 3: Photoresist Coating
Photoresist is a light-sensitive organic polymer Softens when exposed to light

Step 4: Masking
Expose photoresist through n-well mask

FABRICATION STEPS 27
 FABRICATION STEPS
Step 5: Removal of Photoresist
Photoresist are removed by treating the wafer with acidic or basic solution.

Step 6: Acid Etching

SiO2 is selectively removed from areas of wafer that are not covered by photoresist by using
hydrofluoric acid.

FABRICATION STEPS 28
 FABRICATION STEPS
Step 7: Removal of Photoresist
Strip off the remaining photoresist

Step 8: Formation of n-well

n-well is formed with diffusion or ion implantation

FABRICATION STEPS 29
 FABRICATION STEPS
Step 9: Removal of SiO2
Strip off the remaining oxide using HF

Step 10: Polysilicon deposition

Deposit very thin layer of gate oxide using Chemical Vapor Deposition (CVD) process

FABRICATION STEPS 30
 FABRICATION STEPS
Step 11: N- diffusion
N-diffusion forms nMOS source, drain, and n-well contact

Dopants were diffused or ion implantated

Strip off oxide

FABRICATION STEPS 31
 FABRICATION STEPS
Step 12: P- diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

Step 13: Contact cuts

The devices are to be wired together Cover chip with thick field oxide Etch oxide where contact
cuts are needed

FABRICATION STEPS 32
 FABRICATION STEPS
Step 14: Metallization
Sputter on aluminium over whole wafer Pattern to remove excess metal, leaving wires

FABRICATION STEPS 33
 DESIGN RULES
Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
* scalable design rules: lambda parameter
* absolute dimensions (micron rules)
Intra-layer: widths, spacing
Inter-layer: enclosures, overlaps
* Transistor rules
* Contact and via rules
* Well and substrate contacts "
Special rules (sub-0.25 m)
* Area, antenna rules, density rules

DESIGN RULES34
CMOS PROCESS LAYER

DESIGN RULES35
 INTRA-LAYER DESIGN RULES [6]

[6] Photo/Source from : http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SLIDES/design_rules.pdf DESIGN RULES36

INTER LAYER : VIAS AND CONTACTS
Vias connect metal layer 1 (M1) to metal layer 2 (M2)
Contacts connect M1 to the Si.
Vias and contacts are always square (2x2 m)
For large area contact, use many contacts in an array.

DESIGN RULES37
STICK DIAGRAM

Explore your design space since it can give:
* Implications of crossovers
* Numbers of contacts
* Arrangement of devices & connections
Process Independent layout but Technology
dependent
Easy to expand to a full layout for a particular
process:
* Magic (symbolic editor)
* Tanner tools

DESIGN RULES38
STICK DIAGRAM OF CMOS INVERTER

DESIGN RULES39
 3.
CMOS OVERVIEW
Lets explore the overall overview of CMOS Technology : The future and
challenges, trends, and whats new innovation in CMOS.

CHALLENGE INNOVATION

CURRENT TREND FUTURE TREND

40
 Trends in Integrated Circuits Technology

The objective of scaling digital CMOS is to
enable smaller, faster, lower power and lower
cost logic circuits and microprocessor.
High-k gate insulator are desperately need
to maintain higher gate currents.
Ultra thin SiO can improve design.
Improvemnet in device design will dreately
increase gate current and device off current:
will reach power crisis and make the power
problem much worst.

CURRENT TREND 41
 Trends in Integrated Circuits Technology

CURRENT TREND
[7] Photo/Source from : http://www.extremetech.com/wp-content/uploads/2014/06/Cortex_A17_1.jpg
42
 CHALLENGES IN CMOS TECHNOLOGY
The challenge/limit is deferent depending on application. We are focusing on the common
challenge : TRADITIONAL-SCALING CMOS LIMITATIONS
Operation Frequency (a.u.)

Subthreshold Leakage (A/m)

CHALLENGE 43
 TRADITIONAL-SCALING CMOS LIMITATIONS
1. Minimum dimensions that can be
fabricated
Primary limitations to chip scaling
have been lithographic issues.
Lithographic technologies have been
used 193nm ultraviolet wavelength
and advance research have been done
to reduce the minimum wavelength to
13nm.
However, the real limit is the size of
the atom and molecule. Devices cannot
be fabricated smaller than the size of
one molecule. Therefore, how small
transistor can actually be fabricated?
But Wait..!
This limitation challenge has the solution. Lets check them out at our next
slide.
CHALLENGE
2. Diminishing returns in switching
performance
Physical system cannot run to
infinity. When a model approaches
infinity, some non-ideal effect will
begain to dominate and break the
model.
These effects, such as electron and
hole mobility, means that the
performance gains from each
successive generations is less than
the gain from the last generation.
Scaling all the way down to the
molecular level in traditional silicon
may not prodice devices that are
significantly better than thei larger
ancestor
3. Off-state leakage
Transistor cannot be turnedoff.
The sources that contributes to off-state
power consumption are:
-Junction leakage
-Gate induced drain leakage
-Sub-threshold channel current
-Gate tunnel currengt
These becomes more and more
significant when the dimension
decreased.
In fact, leakage current grows
exponentially as gate length decrases.
44
TRADITIONAL-SCALING CMOS INNOVATION

MOBILITY Strained SiGeS/D

HiK gate
BOOSTER: PMOS Transistor
insulator and
UNIAXIAL SiGeSiGe
Metal gate
STRAIN

INNOVATION 45
 TRADITIONAL-SCALING CMOS INNOVATION
MOBILITY BOOSTER: UNIAXIAL STRAIN

Increase the speed without decreasing the size.

Mobility enhancement through uniaxial strained silicon technology innovation introduced at 90nm
node
-Epitaxial SiGeS /D
-SiN Capping Layers

INNOVATION 46
 TRADITIONAL-SCALING CMOS INNOVATION
Strained SiGeS/D PMOS Transistor SiGeSiGe

SiGe film embedded into source/drain

SiGe film deposited by selective epitaxy
Induces large uniaxial compressive strain in channel
this strain leads to dramatic hole mobility enhancement
Strain impacts mobility through:
-energy/subb and spacing which affects scattering ()
-Valley repopulation which changes transport mass (meff)
-Band war page which changes transport mass (meff)

These transistor
structures introduced
first at Intels 90nm
CMOS node. These
structures have now
become industry
standard for strain
implementation

INNOVATION 47
 TRADITIONAL-SCALING CMOS INNOVATION
HiK gate insulator and Metal gate
HiKgate insulator introduced at 45nm CMOS node to reduce gate leakage
Metal Gate introduced at 45nm CMOS node to eliminate poly depletion
BENEFITS:
Highk gate dielectric
Reduced gate leakage
TOX(e) scaling
Metal gates
Eliminate polysilicondepletion
Resolves VTpinning and poor mobility for highk dielectrics

High-k + Metal Gate Challenges:

Highk gate dielectric
Poor mobility
Poor reliability
Metal gates
Dual band edge work functions
Thermal stability
Integration scheme
To overcome:
Key considerations
Integrate hafnium-based high-k dielectric, dual metal gate
electrodes, strained silicon
Thermal stability of metal gate electrodes
High-k First, Metal Gate Last
Metal gate deposition after high temperature anneals
Integrated with strained silicon process

MGHafnium-based high-k + metal gate transistors are the biggest advancement in transistor
technology since the late 1960s

INNOVATION 48
FUTURE TRENDS in CMOS
The future trends that will be discussed further :
Double Gate MOSFET, Double Gate Finfet

49
 FUTURE TREND : DOUBLE GATE MOSFET

Double gate is comprised of conducting channel which is usually undoped and

surrounded by gate electrodes on their sides just to ensure that no part of
channel is far away from a gate electrode. The voltage applied on the gate
terminal control the electric field determining the amount of current flow
through the channel. its advantage is that undoped channel eliminates intrinsic
parameter fluctuation and minimizes impurity scattering also it can drive higher
current..and also the reduction of drain current.

50
FUTURE TREND
FUTURE TREND : DOUBLE GATE MOSFET

51
FUTURE TREND
FUTURE TREND : DOUBLE GATE FINFET

Selfaligned gates straddle narrow silicon fin

Current flows parallel to wafer surface

52
FUTURE TREND
FUTURE TREND : DOUBLE GATE FINFET
FinFET are used to create faster and more compact circuit and computer chips.
The fins are not made from silicon but from indium-gallium-arsenide.

Tri-gate FinFET
https://www.researchgat
e.net/figure/51647791_fi
g5_Figure-5-Cross-
section-and-top-view-
layout-with-contacts-are-
shown-in-ab-for-Si

53
FUTURE TREND
FUTURE TREND : DOUBLE GATE FINFET

The evolution of transistor device.

54
FUTURE TREND
 FUTURE TREND : DOUBLE GATE FINFET

The Gate-all-around NWFET (nanowire FET) and gate-all-around NTFET (nanotube FET) might be the
future trends of transistor to overcome limitations of current transistor.

55
FUTURE TREND
 Credits
Special thanks to all other references and sources for this topic:
http://electronics.stackexchange.com/questions/26404/what-so-great-about-cmos
https://en.wikipedia.org/wiki/CMOS
http://www.engineersgarage.com/articles/what-is-cmos-technology
http://www.allaboutcircuits.com/textbook/digital/chpt-3/cmos-gate-circuitry/
http://www.awaiba.com/cmos-technology/applications/

Thanks! 56