ADC Survey Jul99

Analog-to-Digital Converter Survey & Analysis
Bob Walden
(310) 317-5895
walden@hrl.com
Update: July 16,1999
References:
1. R.H. Walden, Analog-to-digital converter survey and analysis, IEEE Journal on Selected Areas
in Communications, vol. 17, no. 4, pp. 539-550, April 1999.
2. R.H. Walden, Performance trends for analog-to-digital converters, IEEE Communications
Magazine, vol. 37, no. 2, pp. 96-101, February 1999.
1999 HRL, LLC. ALL RIGHTS RESERVED
Outline
Introduction
ADC survey
Characterization
Performance Limits
Architectures
Trends
Conclusions
Bob Walden
(310) 317-5895
1999 HRL Laboratories, LLC. All Rights Reserved walden@hrl.com
2
What Does an Analog-to-digital Converter Do?
It converts continuous-time signals to discrete-time binary-coded

form. Two purposes are (1) to enable computer analysis of the signal,
and, (2) to enable digital transmission of the signal.
Some examples of continuous-time signals:
speech, medical imaging, sonar, radar, electronic warfare,
instrumentation, consumer electronics, telecommunications,
The conversion can be thought of as a two-step process:
sampling the input signal in time, usually at regularly-spaced intervals;
fsamp = 1/T, where T = sampling interval
Example, for fsamp = 1 gigasample per second, T = 1 ns.
quantizing (or digitizing) the samples in amplitude, usually voltage. The
full-scale input voltage is divided into 2N sub-ranges where N = the
ADCs resolution (number of output leads).
Example, for N = 12 bits, a 1-Volt full-scale range is divided into 2N = 4096
levels. The size of the least-significant bit (LSB) is 1 V / 2N = 244 V.
Bob Walden
(310) 317-5895
3
Analog-to-Digital Converter Data:
Stated Resolution
Over 170 converters represented

22
20
18 HP(97) slope: -1 bit/octave

Stated Resolution (Bits)
16
14 Lucent(98)
12
10 Maxim(5/99)
module
8
hybrid
Si IC HP(97)
6
III-V IC Hypres(6/99)
4 SuperC
2 state-of-the-art
revised s-o-t-a
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Sample Rate (Samples/s)
Bob Walden
(310) 317-5895
4
ADC Basics: Quantization Noise
Sinusoidal Signal Randomized Signal

analog waveform Q/2 Q = LSB
= VFS/2N
-Q/2 N = ADC Resolution
digitized waveform T T = sampling interval
VFS t 1
e (t ) = Q ( )
T 2
T
1 t 1 2 Q
T 0
NP0 (rms ) = [Q ( )] dt =
T 2 12
time
VFS ( rms )
SNR (dB) = 20 log10 ( )
Q NP0 (rms )
VFS 1
quantization error = 20 log10 ( ) = 6.02 N + 176
.
2 2 VFS
2 N 12
Bob Walden
(310) 317-5895
5
ADC Characterization
Quasi-static tests
Differential nonlinearity, DNL
Integral nonlinearity, INL
0
Dynamic tests
signal
Collect 2bits samples "at speed" and compute fast
Fourier transform (FFT) 50
distortion
Determine signal-to-noise ratio, spurious-free dB
dynamic range, noise power ratio
noise floor
How do we count bits? 100
Stated resolution = physical number of output leads

(bits) 0 500 1000 1500 2000
Signal-to-noise ratio, SNR(dB) = 6.02beff + 1.76 frequency
beff = SNR bits = (SNR(dB)-1.76)/6.02

determined for fsig < fsamp/2
Spurious-free dynamic range, SFDR(dBc)
SFDR bits = SFDR(dBc)/6
Bob Walden
(310) 317-5895
6
Effective Resolution Bandwidth (ERBW)
Measure SNR vs fsig, fsamp
ERBW is the signal frequency where the SNR is 3 dB below

the low frequency value
If the ERBW is > fsamp/2, then we have a Nyquist converter
In this presentation:
quoted SNR values correspond to fsig << fsamp/2
ADCs in this survey have 0.25fsamp <~ ERBW <~ 0.5fsamp
Bob Walden
(310) 317-5895
7
Stated Resolution Contrasted with
SNR and SFDR
4 5
3 4
Stated Bits - SFDR Bits

Stated Bits - SNR Bits
3
2
2
1
1
0 0
-1 -1
ideal -2
-2
average difference = 1.47 bits -3
-3
-4
average difference = -0.38 bits
-4 -5
1E+4 1E+6 1E+8 1E+10 1E+4 1E+6 1E+8 1E+10

Bob Walden
(310) 317-5895
8
Spurious-Free Dynamic Range Data
SFDR-bits = SFDR(dBc) / 6.02
22
20
18
HP(97)
16
14 Lucent(98)
SFDR bits
12
Maxim(5/99)
10
6 ADC data
4 state-of-the-art
2 revised s-o-t-a
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
9
ADC Performance Limitations:
Circuit Noise
Equivalent input-referred thermal noise

<vn2> = 4kTRefffsamp/2
Reff includes contributions due to thermal noise, shot noise,
flicker noise, and input-referred noise terms
thermal noise contribution includes the signal source
resistance
maximum resolution (+/- .5 LSB)
2
Vpp 1
Bmax = log2 ( ) 2
1
6kTReff fsamp
in this presentation, Vpp = 1 V
Bob Walden
(310) 317-5895
10
Comparator Ambiguity
Comparator Signal
1
reg f T
tra
ck
r ec
ov
voltage
ery
ion
t
era
en
reg
Analog Signal
time
Sample Mode Hold Mode Sample Mode
fT
Bambiguity = 11
.
6.9fsamp
Bob Walden
(310) 317-5895
11
Aperture Uncertainty
Aperture jitter a
uncertainty in sampling time
varies from sample-to-sample
broadband noise on sampling clock
circuit noise
power-line noise
digital feedthrough noise
signal clock
phase noise on sampling clock
phase noise on input signal
system problem: on-chip & off-chip noise
sources (having a clean, stable clock may
not be enough) 2
maximum resolution (+/- .5 LSB): Baperture = log2 ( )1
3 fsamp a
Bob Walden
(310) 317-5895
12
Heisenberg Uncertainty Principal
2
LSB

2 T T
LSB/2 E = , t =
R 2 2
1 LSB T
2
E t =
T/2 R 4
1
fsamp = VFS / 2
T 2 N fsamp = 3.44 1015
LSB = VFS 2 N R
VFS = 1 V e . g ., 12 bits @ 840 GSPS
R = 50
1
R = 7.26 1017 a ,H = =.093 fs
2 fsamp
N
Bob Walden
(310) 317-5895
13
ADC Performance Limitations (updated 7/16/99)
Basis: Signal-to-Noise Ratio
22
Heisenberg
20 thermal aperture
18
16 ambiguity
14
HP(97)
SNR bits
12
ADC data Lucent(98)
10 aperture (1 ps)
aperture (0.5 ps)
8
aperture (0.2 ps) Maxim(5/99)
6 regen (50 GHz)
regen (250 GHz)
4
thermal (50 ohms)
Hypres(6/99)
2 thermal (2000 ohms)
Heisenberg (.09fs) HP(97)
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
14
ADC Power Dissipation
Power consumption varies by roughly six orders of magnitude.

50
40
Pdiss (dBm)
30
20
10
0
Pdiss (dBm)
-10
4 5 6 7 8 9 10 11
Log(fsamp)
50
40
Pdiss (dBm)
30
20
10
0
-10 Average ~ 30 dBm
0 4 8 12 16 20
SNR bits
Bob Walden
(310) 317-5895
15
ADC Figure of Merit - 1
update d 7/16/99
60
50
F = 2SNRbits x fsamp / Pdis
Number of ADCs
40
median = 1.14 x 1010 LSBs-Hz/W

30
20 mean = 7.79 x 1010 LSBs-Hz/W
10
0
0
2
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
0E
0E
9E
8E
7E
6E
5E
4E
3E
2E
1E
0E
1E
2E
1.
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
1.
1.
1.
Figure of Merit, F
Bob Walden
(310) 317-5895
16
ADC Figure of Merit - 2
p
60
50
8.8 SNRbits, F = 2SNRbits x fsamp / Pdis
15 MSPS
pipelined [28]
Number of ADCs
6 SNRbits, 1 GSPS
10.3 SNRbits,
40 15.0 SNRbits, SuperC w/o refrig.
50 MSPS
folded [25] 1.5 MSPS 15.7 SNRbits, 44 kSPS (6.6E13) [34]
w/o DF [32] w/o DF [31]
30 7.8 SNRbits, 11.3 SNRbits, 12.5 SNRbits, 40 kSPS
650 MSPS 65 MSPS 15.5 SNRbits, 50 kSPS w/o DF [30]
folded [12] AD6640 [29] w/o DF [33] 13.8 SNRbits,
20
5 MSPS
9.5 SNRbits, pipelined [26]
mean
10 20 MSPS
pipelined [27]
0
0
2
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
6E
5E
0E
9E
4E
0E
0E
8E
7E
3E
2E
1E
1E
2E
4.
5.
1.
1.
6.
9.
1.
1.
1.
2.
3.
7.
8.
1.
Figure of Merit, F
Bob Walden
(310) 317-5895
17
High Performance ADCs
High Figure of Merit:

13.8 SNRbits, 5.0 MSPS; 4-stage, calibrating; Kwak et al., et al., 97
12.5 SNRbits, 40 kSPS; , OSR = 250; Chen & Leung, 97
9.5 SNRbits, 20 MSPS; pipelined, digital correction; Cho & Gray, 95
8.8 SNRbits, 15 MSPS; pipelined, interpolating; Kusumoto et al., 93
10.3 SNRbits, 50 MSPS; folded flash , interpolating; Vorenkamp et al., 97
State-of the Art Performances (P = 2SNRbits x fsamp):
6.6 SNRbits, 4.0 GSPS; time interleaved, 40W; Schiller & Byrne, 91
6.6 SNRbits, 2.0 GSPS; folded flash; Nary et al., 95
7.5 SNRbits, 1.0 GSPS; flash; Maxim Max104, 99
6.5 SNRbits, 1.8 GSPS; flash; Wong et al., 96
3.0 SNRbits, 20.0 GSPS; superconducting folded-flash; Hypres, 99
High Spur-Free Dynamic Range
18.3 SFDRbits, 20 MSPS; dithered, HP E1437A, 97
14.2 SFDRbits, 65 MSPS; dithered, Lucent CSP1152A, 98
Flexible:
60 MHz IF, 4 GHz clock, 2nd order bandpass , Raghavan, et al., 97
7.0 SNR bits @ 63 MHz bw
14.9 SNR bits @ 366 kHz bw Bob Walden
(310) 317-5895
18
High Performance ADC Architectures
dithering improves SFDR
Example: introduce dithering by addition of pseudorandom noise to an ideal 11-bit ADC

SFDR increases
SNR decreases
optimum PRN level ~ 1/2 LSB
0 0
0 0
20
No dither 20
Dither enabled
input = -6.02 dB input = -6.02 dB
SNR = 68.0 dB SNR = 65.6 dB
40 40
SFDR = 92.5 dBc SFDR = 100.0 dBc
60 60
80 80
100 100
120 120
0 140 0 140
8 8 8 8 8
0 1 . 10 2 . 10 3 . 10 4 . 10 5 . 10 0 1 . 10
8
2 . 10
8
3 . 10
8
4 . 10
8
5 . 10
8
0 f sig f clk 0 f sig f clk
j j
2 2
Bob Walden
(310) 317-5895
19
moderate sample-rate, high resolution
Delta sigma ():

a combination of oversampling and feedback
leads to suppression of quantization noise at low-frequency end
of spectrum.
analog front-end contains a small number of low-precision
components
digital back-end contains most of the complexity
most popular configuration is a cascade of first and/or second
order modulators
requires ultra high speed IC technology for RF applications
bandpass modulators add new dimensions
tunable center frequency
tunable bandwidth
reduce number of downconversions
bandpass digital filtering replaces analog filtering functions
(better blocking of interferers)
Bob Walden
(310) 317-5895
20
Bandpass Delta Sigma Converters
e(z)
resonators
x(z) y( N
H(z) ADC z) DSP /
wideband
dB
DAC
y(z) = {z-1H(z)x(z) + e(z)} / {1 + z-1H(z)}

narrowband
tunable notch
Resonators determine modulator frequency frequencies
response and are tunable
Sample rate of modulator is sample rate of frequency (Hz)
the quantizer (ADC)
DSP is a complex digital circuit and performs
bandpass filtering and downconversion
Sample (Nyquist) rate of ADC is set by DSP
Number, N, of output leads limits ADC
resolution
Bob Walden
(310) 317-5895
21
Progress in Performance Improvement
Over Time: SNR
22
<1987 1988 1989
20
18 1990
~ 1 1/2 bits in 7 years 1991 1992
16 1993 1994 1995
14 1996 1997 1998

SNR bits
12 1999
10
4 ~ 1 1/2 bits in 9 years

2
1999
0 1990
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
22
Progress in Performance Improvement
Over Time: SFDR
22
20
18
16 ~ 2 bits in 9 years
14
SFDR bits
12
<1988 1988
10
1989 1990
8
1991 1992
6 1993 1994
4 1995 1996
1999
1997 1998
2
1999 1990
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
23
ADC Performance Trend using
Derived Aperture Jitter
1.0E-11
Derive a values from

fit log (best data)
SNR data:
1 2 SNRbits
derived aperture jitter (s)
best data a = =
1.0E-12 3 P 3 fsamp
fit log (best data), normalized to best result current best ~ 0.5 ps
trend shows very
1.0E-13 a = 112 fs (re quire d fo r 14-S NRbits @ 100 MS PS )
gradual improvement
actual progress is
sporadic
1.0E-14
1975 1980 1985 1990 1995 2000 2005 2010 2015
year
Bob Walden
(310) 317-5895
24
ADC Technology Comparison
Conclusions
ADC Survey
Over 170 converters: experimental and commercial
SNR bits: ranged from 0 to 3.5 bits below stated resolution
SFDR bits: ranged from 4 bits below to 4.5 bits above stated
resolution
Performance limitations: aperture uncertainty (?) (~ 1 ps), IC
technology speed (~ 50 - 80 GHz)
Figure of merit: F = 2(SNR bits) x fsamp / Pdiss (mean = 7.8 x 1010
LSBs-Hz/W)
High performance architectures
Time interleaved
Folded, interpolating
Pipelined
Dithered (high SFDR)
Delta sigma (including bandpass)
Relatively little improvement in ADC performance during recent
years (P = 2(SNR bits) x fsamp < 4.096 x 1011 LSBs - Hz)
Bob Walden
(310) 317-5895
25
Supplemental Charts
Bob Walden
(310) 317-5895
26
Software Radio
Next generation mobile communications will use programmable DSP

hardware to increase system programmability and functionality.
Key strategy of a software radio is the use of wideband DAC and
ADC as close to the antenna as possible.
As much functionality as possible is defined in software in order to
replace analog components.
IF, baseband and bitstream processing functions are implemented in
software.
In the canonical software radio, the hardware is simple and functions
are software defined.
Bob Walden
(310) 317-5895
27
Specifying an ADC for Receiver
Applications
Important Parameters:
Signal-to-noise ratio (SNR)
Signal-to-distortion ratio or spurious-free dynamic range
(SFDR)
Two-tone third order intermodulation products (IP3)
should be investigated for each specific application (e.g., frequency
band of interest, strength of tones, etc.)
Aperture uncertainty - rms jitter (a)
can be inferred from SNR data if not measured directly
Power dissipation (multiple-channel applications and/or
remote locations)
Minimum Goal: ADC should perform as well as the
preceding analog components
Best case scenario: ADC slightly outperforms front-end
(antenna, LNA)
Bob Walden
(310) 317-5895
28
Analog-to-Digital Converters:
COTS / non-COTS
22
20
18
16
14
12
10
6
commercial
4 experimental/military
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
29
White Noise Approximation
Input signal is random (busy)
All possible quantization errors are equally likely
Integrated noise power, Q2/12, is independent of fsamp
SNR = 6.02N + 1.76, refers to full-scale input signal
Bob Walden
(310) 317-5895
30
Signal-to-Noise Ratio Data
22
20
18
16
14
SNR bits
12 P = 4.096 x 10 11 LS Bs -Hz
10 P = 2.048 x 10 11 LS Bs -Hz
8
2 Pe rfo rmanc e , P = 2 SNRbits x fs amp

0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
31
Equivalent 1-Hz Performance
Nyquist Operation Assumed (Optimistic)
190
P = 4.096E11
180
P = 2.048E11
170 P = 1.024E11
data
160
SNR (dB/Hz)
150
140
130
120
110
100
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
SNR 1Hz = 6.02 SNRbits + 1.76 + 10 log( fsamp / 2)

Bob Walden
(310) 317-5895
32
Summary of Performance Limit Equations
numerical changes made 11/97 due to use of quantization error
representation
2
Vpp 1
Circuit noise: Bmax = log2 ( ) 2
1
6kTReff fsamp
was 16
2
Aperture uncertainty: Baperture = log2 ( ) 1
3 fsamp a
was unity
fT
Comparator ambiguity: Bambiguity = 11
.
6.9fsamp
was 6.02 was 1.4
Bob Walden
(310) 317-5895
33
ADC Performance Limitations: P = 2SNRbits x fsamp
Quantization Error Comparator Ambiguity

Q/2 Q = LSB
= VFS/2N Comparator Signal
-Q/2 N = ADC Resolution
T 1
t 1 T = sampling interval reg fT tra
ck
e (t ) = Q ( ) rec
ov
voltage
T 2 er y
n
tio
era
T
1 t 1 2 Q
[Q ( T
en
N P 0 ( rm s ) = )] d t =
reg
T 0
2 12
Analog Signal
V ( rm s )
S N R ( d B ) = 2 0 lo g 1 0 ( F S )
N P 0 ( rm s ) time
V 1 Sample Mode Hold Mode Sample Mode
= 2 0 lo g 1 0 ( F S ) = 6 .0 2 N + 1.7 6
2 2 V FS
2 N 12 fT
Bambiguity = 11
.
6.9 fsamp
Equivalent input-referred thermal noise Aperture jitter a

<vn2> = 4kTRefffsamp/2 uncertainty in sampling
time
Reff includes contributions due to varies from sample-to-
thermal noise, shot noise, flicker sample Signal Clock
noise, and input-referred noise broadband noise on
terms sampling clock
Vpp
2
2
B m ax = log 2 ( )
1
2
1 Baperture = log2 ( )1
6 kTR e ff f sa m p 3 fsamp a
Bob Walden
(310) 317-5895
34
ADC Architectures for High
Performance
Flash is fast,
2b - 1 comparators simultaneously sample the input signal
But, for high resolution,
Number of comparators increases exponentially with b
very large ICs, high power dissipation, difficulty in matching
components, and, the increasingly large input capacitance reduces
analog input bandwidth
currently available, b < 8
Alternatives:
Time-interleaved, Folded-interpolating, Pipelined (subranging, n-
stage flash)
Delta Sigma (lowpass, bandpass)
Bob Walden
(310) 317-5895
35
high sample-rate, moderate resolution
Time interleaved: a number of ADCs are operated in parallel, but with

their clocks skewed so as to increase the overall sampling rate.
example: two ADCs operating at 500 MSPS with each ADC taking turns
every 1 ns leads to 1 GSPS operation
requires narrow aperture sample and hold
appears to defy the regeneration limit
A combination of high-bandwidth, low-noise sampling circuitry and

precision digital timing is required to perform the sampling
operation.
Schiller & Byrne, J. Solid-State Circuits, vol. 26, pp. 1781-1789, Dec.
1991
Bob Walden
(310) 317-5895
36
high sample-rate, moderate resolution
Folding, interpolating: a number of folding blocks are operated in

parallel, but with their reference voltages skewed so as to increase
resolution. Resolution is further increased by using resistive
interpolation between the outputs of the folding blocks.
a folding block contains N coupled differential pairs and it forms a log2N
quantizer.
the frequency of the folding block LSB output is N times that of the analog
input signal
without interpolation, this ADC would have the same complexity as the
equivalent flash ADC
Bob Walden
(310) 317-5895
37
What is a Folding Block?
van Valberg & van de Plassche 92
coupled differential pair (CDP)

VCC example: 4 CDPs form a 2-bit ADC
1
Vout
CDP D
Vin Vlow Vin Vhigh
0.75 C + D = MSB
DC
DC
CDP C
Vin 0.50 B + D = LSB
CDP B
0.25
Vout
CDP A
0
Vin
Vlow Vhigh
Bob Walden
(310) 317-5895
38
moderate sample-rate, high resolution
Pipelined (subranging, n-stage flash): a number of ADCs are operated

in sequence with each succeeding ADC quantizing the analog residue
of the preceding stage.
an N-bit ADC followed by an M-bit ADC produces N+M-1 bits
requires track and hold for every ADC and reconstruction DAC for all but
the last stage
exception: 1-bit-at-a-time systems use only one T/H
Bob Walden
(310) 317-5895
39
Lowpass Delta Sigma Modulation
First Order Loop simulation

0
e(mT)
x(mT) u(mT) y(mT)

DELAY ADC
QUANTIZER
50
q(mT)
INTEGRATOR
F1db
j
DAC
y(mT) = x(mT - T) + e(mT) - e(mT-T) 100

{
signal
{
quantization error 150 8 8 8 8 9
0 2 10 4 10 6 10 8 10 1 10
difference f sig
j
signal band
Bob Walden
(310) 317-5895
40
Equivalent Configurations
M. Hovin, et al., J. Solid-State Circuits,
vol. 32, Jan. 1997, pp. 13-22.
e(z)
x(z) y(z)
z-1 ADC
+ +
- +
DAC
y(z) = x(z) z-1 + e(z)(1-z-1)
e(z)
x(z) y(z)
z-1 ADC
+ +
+ -
z-1
Integrate Quantize Differentiate
Bob Walden
(310) 317-5895
41
Progress in Performance Improvement Over
Time: Stated bits
22
20
18 ~ 1 1/2 bits in 7in

years
~ 2 bits 9 years
16
14
Stated bits
12
10 <1988 1988
1989 1990
8
1991 1992
6 1993 1994
4 1995 1996
1997 1998 1999
2
1999 1990
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
42
ADC Performance Trend
P = 2 SNRbits fsamp
1.0E+13 12
P = 6.5536 x 10 LS Bs - Hz (re quire d fo r 16 S NRbits @ 100 MS PS )
current best ~ 4 x 1011
LSBs - Hz
12
trend shows very
P = 1.6384 x 10 LS Bs - Hz (re quired fo r 14 S NRbits @ 100 MS PS )
gradual improvement
Performance (LSBs - Hz)
1.0E+12 actual progress is

sporadic
11
P = 4.096 x 10 LS Bs - Hz (re quire d fo r 12 S NRbits @ 100 MS PS )
best data
1.0E+11
fit log (best data)
1.0E+10
1975 1980 1985 1990 1995 2000 2005 2010 2015
year
Bob Walden
(310) 317-5895
43
Why So Little Improvement in SNR, SFDR ?
Technological / fundamental barrier?

P = 2SNRbits x fsamp < 4 x 1011 LSBs - Hz (e.g., < 12 SNRbits, 100 MSPS)
Aperture uncertainty, a very complex issue
Recent research focusing on power-efficient (high F) designs
De-emphasis on R&D ?
Lack of application drivers (cart-before-the-horse) ?
Bob Walden
(310) 317-5895
44
Analog-to-Digital Converters:
A Few Applications
Military, Commercial
22
20
consumer
18 medical imaging
16 radar
14 software radio, HDTV

EW
12
sampling
10 oscilloscopes
FPAs
8
telephony
satellite
6
4
commercial
2 experimental/military
0
1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+10 1E+11
Bob Walden
(310) 317-5895
45
Some Final Comments
ADC technological barrier (P = 2SNRbits x fsamp < 4 x 1011 LSBs - Hz)

will not be broken without considerable R&D investment
Fundamental studies of ADC limitations
Build integrated receiver systems (including the ADC) to ferret out
problems concurrently
Current work on high-performance ADCs for military apps
modified flash for >~ 2 GSPS operation
bandpass for 50 MHz <~ IF <~ 1 GHz
requires high-speed IC technologies
HBT (InP, GaAs, SiGe)
no COTs ADCs using these technologies (?)
U.S. Government is currently supporting most, if not all, of these
efforts
Other Future Possibilities
Superconducting, Optical, RTD, ??
Bob Walden
(310) 317-5895
46

ADC Survey Jul99

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ADC Survey Jul99

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Analog-to-Digital Converter Survey & Analysis

Update: July 16,1999

It converts continuous-time signals to discrete-time binary-coded

Over 170 converters represented

18 HP(97) slope: -1 bit/octave

Sinusoidal Signal Randomized Signal

Stated resolution = physical number of output leads

Signal-to-noise ratio, SNR(dB) = 6.02beff + 1.76 frequency

beff = SNR bits = (SNR(dB)-1.76)/6.02

Measure SNR vs fsig, fsamp

ERBW is the signal frequency where the SNR is 3 dB below

If the ERBW is > fsamp/2, then we have a Nyquist converter

Stated Bits - SFDR Bits

Sample Rate (Samples/s)

Equivalent input-referred thermal noise

in this presentation, Vpp = 1 V

Power consumption varies by roughly six orders of magnitude.

median = 1.14 x 1010 LSBs-Hz/W

20 mean = 7.79 x 1010 LSBs-Hz/W

High Figure of Merit:

Example: introduce dithering by addition of pseudorandom noise to an ideal 11-bit ADC

Delta sigma ():

y(z) = {z-1H(z)x(z) + e(z)} / {1 + z-1H(z)}

16 1993 1994 1995

14 1996 1997 1998

4 ~ 1 1/2 bits in 9 years

Derive a values from

Next generation mobile communications will use programmable DSP

Input signal is random (busy)

All possible quantization errors are equally likely

Integrated noise power, Q2/12, is independent of fsamp

SNR = 6.02N + 1.76, refers to full-scale input signal

2 Pe rfo rmanc e , P = 2 SNRbits x fs amp

Sample Rate (Samples/s)

SNR 1Hz = 6.02 SNRbits + 1.76 + 10 log( fsamp / 2)

Quantization Error Comparator Ambiguity

Equivalent input-referred thermal noise Aperture jitter a

Time interleaved: a number of ADCs are operated in parallel, but with

A combination of high-bandwidth, low-noise sampling circuitry and

Folding, interpolating: a number of folding blocks are operated in

coupled differential pair (CDP)

Pipelined (subranging, n-stage flash): a number of ADCs are operated

First Order Loop simulation

x(mT) u(mT) y(mT)

y(mT) = x(mT - T) + e(mT) - e(mT-T) 100

Integrate Quantize Differentiate

18 ~ 1 1/2 bits in 7in

1.0E+12 actual progress is

fit log (best data)

Technological / fundamental barrier?

Recent research focusing on power-efficient (high F) designs

Lack of application drivers (cart-before-the-horse) ?

14 software radio, HDTV

ADC technological barrier (P = 2SNRbits x fsamp < 4 x 1011 LSBs - Hz)

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