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UNIT I
Introduction: Introduction to VLSI and VLSI fabrication- Introduction to power
reduction techniques-Dynamic Power Reduction-Static Power Reduction- CMOS
inverter propagation delays power dissipation - Stick Diagram. MOS layers -
design rules and layout- choice of layers.
UNIT II
VLSI Logic Circuits, Design Process and Layout: Pass transistor and transmission
gatesinverter- NAND gates and NOR Gates for n MOS, CMOS and Bi CMOS
parity generator multiplexers- code converters PLA Clocked sequential
circuits- Memories and Registers.
UNIT III
Arithmetic Circuits: One bit adder- multibit adder Ripple carry-Carry Skip Adder-
Carry Look Ahead Adder- design of signed parallel adder-comparison of different
schemes in terms of delay - multipliers Design of serial, parallel and pipelined
multipliers- different schemes and their comparison. 2s complement array
multiplication-Booth encoding- Wallace Tree multiplier.
UNIT IV
Programmable ASICs and FPGAs: Actel, Altera and Xilinx FPGA devices.
UNIT V
Introduction to Verilog: Basics of Verilog, operators, Data Types, Continuous
assignments, Sequential and parallel statement groups. Timing control (level and
edge sensitive) and delays, tasks and functions, control statements, Blocking &
nonblocking assignments, If-else and case statements, For-while-repeat and forever
loops, Rise, fall, min, max delays, Behavioral and synthesizable coding styles for
modeling combinational logic, Behavioral & synthesizable coding styles for
modeling sequential logic, Parameters and Defines for design reuse. Verilog and
logic synthesis.
TEXT BOOKS:
1. Neil H.E. Weste and K.Eshraghian, Principles of CMOS VLSI design, Addison
Wesley Publishing Company,1985.
2. Neil He Weste,David Harris and Ayan Banerjee, Principles of CMOS VLSI
design- A circuits and Systems Perspective, Dorling Kindersley (india) Pvt Ltd,
2006.
3. Sebastian Smith, Application Specific Integrated Circuits, Pearson
Education,2001
4. J. Bhasker A Verilog HDL Primer, Star Galaxy Press,1997.
5. Wayne wolf, Modern VLSI Design: System on Chip Design, Prentice Hall of
India, 2005.
REFERENCEBOOKS:
1. E.D.Fabricious, Introduction to VLSI design, Mc Graw Hill, 1990.
2. Thomas, D . E .,Philip.R. Moorby The Verilog Hardware Description Language,
2nd ed.,Kluwer Academic Publishers,2002.
3. Jan M Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated
Circuits: A Design Perspective, Prentice Hall India, 2007.
UNIT I
Introduction
1.1. Introduction to VLSI
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This short description of CMOS inverters gives a basic understanding of the how a
CMOS inverter works. It will cover input/output characteristics, MOSFET states at
different input voltages, and power losses due to electrical current.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain
and gate terminals, a supply voltage VDD at the PMOS source terminal, and a
ground connected at the NMOS source terminal, were VIN is connected to the gate
terminals and VOUT is connected to the drain terminals.(See diagram). It is
important to notice that the CMOS does not contain any resistors, which makes it
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more power efficient that a regular resistor-MOSFET inverter.As the voltage at the
input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly. If we model each transistor as a simple switch activated
by VIN, the inverters operations can be seen very easily:
When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging
VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on:
draining the voltage at VOUT to logic low.
This model of the CMOS inverter helps to describe the inverter conceptually, but
does not accurately describe the voltage transfer characteristics to any extent. A
more full description employs more calculations and more device states.
The multiple state transistor model is a very accurate way to model the CMOS
inverter. It reduces the states of the MOSFET into three modes of operation: Cut-
Off, Linear, and Saturated: each of which have a different dependence on Vgs and
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Vds. The formulas which govern the state and the current in that given state is
given by the following tabel:
NMOS Characteristics
PMOS Characteristics
RC Delay models
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UNIT II
VLSI Logic Circuits, Design Process and Layout
The checker circuit gives an output of 0 if there is no error in the parity bit
generated. Thus it basically checks to see if the parity bit generator is error
free or not.
The design procedure is made simple by writing the truth table for the circuit.
Truth table:
Message Even parity bit Checker bit
X Y Z P C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
The circuit can now be derived by drawing the K-map for the output.
Now the parity bit generator and the checker circuit can be combined into one
circuit for simplicity. The final schematic of the circuit is shown in Figure.
Figure: Combined schematic of both parity bit generator and checker circuit
2.4. Multiplexers
2.6. PLA
Read-only memory
A read-only memory (ROM) is like a PLA with all the possible minterms
being calculated. The individual memory cells can be very compact; here is a
4 x 4 fragment of the memory array:
Diffusion tabs are run under the polysilicon word lines wherever a 0 is to be
stored, other bit positions read as 1. The 4 words stored here will read as 4, 6,
3 and 7.
Progammable read-only memories (PROMs) allow the diffusion tabs to be
switched in electrically. Erasable PROMs allow this switching to be reversed,
either by exposure to ultaviolet light (EPROMs) or under digital control
(electrically erasable PROMs or EEPROMs).
Static read/write memory
The simplest form of writeable memory (RAM) is static memory. A bit is
stored in a pair of cross-coupled invertors, with separate circuits to control
the reading and writing of the data.
The memory has two independent ports for reading; both selection lines are
opened for writing. Six transistors are required to store each bit, plus some
overheard for the control circuitry.
Dynamic RAM
Fewer transistors are needed if the bit is stored as charge on the gate of a
FET.
The bit is stored as charge under the grounded gate of a second transistor.
Again, refreshing is required and reading requires the use of subtle analogue
sense amplifiers. The tessellated layout is, however, very compact:
Really dense memory circuits use specialised processes not available for
normal digital logic.
UNIT III
Arithmetic Circuits
3.1. One bit adder
The most basic arithmetic operation is the addition of two binary digits,
i.e. bits.
A combinational circuit that adds two bits, according the scheme
outlined below, is called a half adder.
A full adder is one that adds three bits, the third produced from a
previous addition operation.
One way of implementing a full adder is to utilizes two half adders in
its implementation.
The full adder is the basic unit of addition employed in all the adders
studied here
Half Adder
A half adder is used to add two binary digits together, A and B. It
produces S, the sum of A and B, and the corresponding carry out Co.
Although by itself, a half adder is not extremely useful, it can be used
as a building block for larger adding circuits (FA).
Full Adder
A full adder is a combinational circuit that performs the arithmetic
sum of three bits: A, B and a carry in, C, from a previous addition.
Also, as in the case of the half adder, the full adder produces the
corresponding sum, S, and a carry out Co.
As mentioned previously a full adder maybe designed by two half
adders in series as shown below in Figure.
The sum of A and B are fed to a second half adder, which then adds it
to the carry in C (from a previous addition operation) to generate the
final sum S.
The carry out, Co, is the result of an OR operation taken from the carry
outs of both half adders.
Even though this is a simple adder and can be used to add unrestricted
bit length numbers, it is however not very efficient when large bit
numbers are used.
One of the most serious drawbacks of this adder is that the delay
increases linearly with the bit length.
As mentioned before, each full adder has to wait for the carry out of the
previous stage to output steady-state result.
Therefore even if the adder has a value at its output terminal, it has to
wait for the propagation of the carry before the output reaches a
correct value as shown in Fig.
where tc is the delay through the carry stage of a full adder, and ts is
the delay to compute the sum of the last stage.
The delay of ripple carry adder is linearly proportional to n, the
number of bits, therefore the performance of the RCA is limited when n
grows bigger.
The advantages of the RCA are lower power consumption as well as a
compact layout giving smaller chip area.
3.4. Carry Skip Adder
A carry-skip adder consists of a simple ripple carry-adder with a
special speed up carry chain called a skip chain.
This chain defines the distribution of ripple carry blocks, which
compose the skip adder.
Therefore, if Equation 4 is true then the carry out, Ci+1, will be one if
Ai = Bi = 1 or zero if Ai = Bi = 0.
Hence we can compute the carry out at any stage of the addition
provided equation 4 holds.
These findings would enable us to build an adder whose average time
of computation would be proportional to the longest chains of zeros and
of different digits of A and B.
Alternatively, given two binary strings of numbers, such as the
example below, it is very likely that we may encounter large chains of
consecutive bits (block 2) where Ai Bi. In order to deal with this
scenario we must reanalyze equation 3 carefully.
In the case of comparing two bits of opposite value, the carry out at
that particular stage, will simply be equivalent to the carry in.
Hence we can simply propagate the carry to the next stage without
having to wait for the sum to be calculated.
The delay of n-bit adder based on m-bit blocks of Carry Bypass Adder,
CBA rippled together can be given by:
n is the adder length and m is the length of the blocksComparing to the RCA,
the CBA has slightly improved speed for wider-bit adders (still linear to n),
but with higher active capacitance and the area overhead because of the
extra bypass circuit.
3.8. Multipliers
Both the carry and sum delay for adders appear on the critical path, so
want balanced design
Because the inputs to different columns in a row arrive at different
times, fast carry chains dont work well
Use carry-save adder and only sum carries at last stage
Can pipeline array on diagonals to improve throughput
3.11. Design of pipelined multipliers
The general architecture of the serial/parallel multiplier is shown in the
figure below. One operand is fed to the circuit in parallel while the other is
serial. N partial products are formed each cycle. On successive cycles, each
cycle does the addition of one column of the multiplication table of M*N PPs.
The final results are stored in the output register after N+M cycles. While the
area required is N-1 for M=N.
Booths algorithm permits skipping over 1s and when there are blocks of
1s
It improves performance significantly
UNIT IV
Programmable ASICs and FPGAs
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UNIT V
Introduction to Verilog
5.1. Basics of Verilog
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5.2. Operators
1. Value Set
Verilog consists of only four basic values. Almost all Verilog data types store
all these values:
0 (logic zero, or false condition)
1 (logic one, or true condition)
x (unknown logic value)
z (high impedance state)
2. Wire
A wire represents a physical wire in a circuit and is used to connect gates or
modules. The value of a wire can be read, but not assigned to, in a function or
block.
A wire does not store its value but must be driven by a continuous
assignment statement or by connecting it to the output of a gate or module.
Other specific types of wires include:
wand (wired-AND);:the value of a wand depend on logical AND of all the
drivers connected to it.
wor (wired-OR);: the value of a wor depend on logical OR of all the drivers
connected to it.
tri (three-state;): all drivers connected to a tri must be z, except one (which
determines the value of the tri).
3. Reg
A reg (register) is a data object that holds its value from one procedural
assignment to the next. They are used only in functions and procedural
blocks. A reg is a Verilog variable type and does not necessarily imply a
physical register.
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5. Integer
Integers are general-purpose variables. For synthesis they are used mainly
loops-indicies, parameters, and constants. They are of implicitly of type reg.
However they store data as signed numbers whereas explicitly declared reg
types store them as unsigned.
6. Supply0, Supply1
Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power),
respectively.
7. Time
Time is a 64-bit quantity that can be used in conjunction with the $time
system task to hold simulation time. Time is not supported for synthesis and
hence is used only for simulation purposes.
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8. Parameter
A parameter defines a constant that can be set when you instantiate a
module. This allows customization of a module during instantiation.
2. Relational Operators
Relational operators compare two operands and return a single bit 1or 0.
These operators synthesize into comparators. Wire and reg variables are
positive. Thus (-3b001) = = 3b111 and (-3d001)>3d110. However for integers
-1< 6.
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3. Bit-wise Operators
Bit-wise operators do a bit-by-bit comparison between two operands.
4. Logical Operators
Logical operators return a single bit 1 or 0. Logical operators are typically
used in conditional (if ... else) statements since they work with expressions.
5. Reduction Operators
Reduction operators operate on all the bits of an operand vector and return a
single-bit value. These are the unary (one argument) form of the bit-wise
operators above.
6. Shift Operators
Shift operators shift the first operand by the number of bits specified by the
second operand. Vacated positions are filled with zeros for both left and right
shifts (There is no sign extension).
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7. Concatenation Operator
The concatenation operator combines two or more operands to form a larger
vector.
8. Replication Operator
The replication operator makes multiple copies of an item.
9. Conditional Operator: ?
Conditional operator is like those in C/C++. They evaluate one of the two
expressions based on a condition. It will synthesize to a multiplexer (MUX).
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initial begin
a = 4; b = 3; example 1
#10 c = 18;
#5 d = 7;
end
Above, at time=0 both a and b will have 4 and 3 assigned to them respectively
and at time=10, c will equal 18 and at time=15, d will equal 7.
Non-Blocking (the <= operator)
Non-Blocking assignments tackle the procedure of assigning values to
variables in a totally different way. Instead of executing each statement as
they are found, the right-hand side variables of all non-blocking statements
are read and stored in temporary memory locations. When they have all been
read, the left-hand side variables will be determined. They are non-blocking
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because they allow the execution of other events to occur in the block even if
there are time delays set.
integer a,b,c;
initial begin
a = 67;
#10;
a <= 4; example 2
c <= #15 a;
d <= #10 9;
b <= 3;
end
This example sets a=67 then waits for a count of 10. Then the right-hand
variables are read and stored in tempory memory locations. Here this is
a=67. Then the left-hand variables are set. At time=10 a and b will be set to 4
and 3. Then at time=20 d=9. Finally at time=25, c=a which was 67, therefore
c=67.
Note that d is set before c. This is because the four statements for setting a-d
are performed at the same time. Variable d is not waiting for variable c to
complete its task. This is similar to a Parallel Block.
This example has used both blocking and non-blocking statements. The
blocking statement could be non-blocking, but this method saves on simulator
memory and will not have as large a performance drain.
Application of Non-Blocking Assignments
We have already seen that non-blocking assignments can be used to enable
variables to be set anywhere in time without worrying what the previous
statements are going to do.
Another important use of the non-blocking assignment is to prevent race
conditions. If the programmer wishes two variables to swap their values and
blocking operators are used, the output is not what is expected:
initial begin
x = 5;
y = 3;
end
example 3
always @(negedge clock) begin
x = y;
y = x;
end
This will give both x and y the same value. If the circuit was to be built a race
condition has been entered which is unstable. The compliler will give a stable
output, however this is not the output expected. The simulator assigns x the
value of 3 and then y is then assigned x. As x is now 3, y will not change its
value. If the non-blocking operator is used instead:
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5.14. Behavioral & synthesizable coding styles for modeling sequential logic
Sequential logic circuits are modeled using edge sensitive elements in the
sensitive list of always blocks. Sequential logic can be modeled only using
always blocks. Normally we use nonblocking assignments for sequential
circuits.
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Simple Flip-Flop
module flif_flop (clk,reset, q, d);
input clk, reset, d;
output q;
reg q;
always @ (posedge clk )
begin
if (reset == 1) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule
5.15. Parameters and Defines for design reuse
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