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Sensor
IA or Op
PGA ADC MCU DAC Amp PLC
Introduction
There are many physical parameters that need to be Figure 2. Resistive-bridge sensor with
pressure applied
measured and controlled in industrial automation systems.
Temperature, pressure, flow, and level are just a few of
these physical parameters. Resistive-bridge sensors are
commonly used in these applications. Figure 1 shows a
ed
St +
R ss
re R SP
R
A
tc A
A
SP
R mp
he N
process-control system. This article presents the primary
d
o
C
R mp
C
Sensor basics
re
o
ed
re R S
R ss
SP
C
St +
N
R
ed
Common-mode voltage versus output Figure 3. A VCM versus VOUT plot for the
voltage range INA826 IA
The bridges common-mode voltage (VCM) is the average
voltage present at the differential amplifiers input 5
terminals. 4.5 VS = 5 V, G = 1
R3
1
R
different IA reference voltage, or modify the bridge
common-mode voltage as shown in Figure 4. VEXT +
B D
Initial input offset voltage (VOS)
R2
The input offset voltage is the DC error voltage between
R
4
C
the differential amplifiers input terminals (for example, op
amp, IA, PGA, and so on). For a traditional IA with three
op amps, this voltage depends on the devices gain.[2] The
RBOTTOM
offset voltage contributes to the solutions overall offset
error and if not calibrated, it also shifts the common-mode
voltage. Therefore, a better choice may be a zero-drift IA
or PGA (for example, a PGA900) which has a very low
offset voltage. c alibrated at various temperatures because each system
Zero-drift is a term that applies to a chopper or devices component may drift in different directions. In some cases
with auto-zero topology that will internally correct for the error over temperature may actually increase if the
offset errors, such as initial input offset voltage, input system is calibrated at 25C without calibration at other
offset voltage drift, power supply rejection ratio (PSRR), temperatures.[3]
common-mode rejection ratio (CMRR), and some others.
Noise
Input offset voltage drift (VOS/T) An amplifiers intrinsic noise is a primary concern when
Input offset-voltage drift is the change in input offset selecting the bridge amplifier. Of particular interest is the
voltage as the temperature deviates from room tempera- amplifiers low-frequency, or 1/f, noise because industrial
ture (25C). This offset error is in addition to the initial systems are typically low-bandwidth. Noise generated by
input offset voltage. Since most industrial systems must the amplifier sums with the noise of the ADC, which ulti-
maintain accuracy over a wide temperature range, zero- mately reduces the measurements noise-fee resolution.
drift IAs or PGAs are preferred. While the initial input While zero-drift amplifiers may be preferred because the
offset voltage can be removed with a room temperature 1/f region of their noise spectral-density curve is flat, some
calibration, the offset-voltage drift requires a more non-zero-drift IAs may have better overall noise perfor-
complicated and time consuming over-temperature mance. Conduct a complete noise analysis to determine
calibration routine. Each individual system must be the amplifiers total noise contribution.
Bits
10
The decimator filter implemented in most delta-sigma
8
ADCs is a Sinc filter. This filter topology is popular
because it is inherently stable and simple to implement. 6
The order and decimation ratio of this sinc filter deter- 4
mine the performance of the ADC.[4] 2
The ADCs noise-free code resolution is defined as the
0
number of bits of resolution beyond which it is impossible 0 10 20 30 40 50 60
to resolve individual codes. The noise-free resolution of Gain (dB)
the ADC can be calculated based on the total number of
codes (2N) and the peak-to-peak noise code measurement.
Noise-free code 2N
resolution = log 2 (2) Figure 6. ADC output versus filter output
Peak-to-peak noise codes
8379200
Effective resolution can be calculated by adding log2 (6.6),
8379000
or approximately 2.7 bits to the calculated noise-free code
8378800
resolution. 8378600
Effective = Noise-free code resolution + 2.7 bits (3) 8378400
Code
resolution 8378200
For example, the delta-sigma ADC in the PGA900 has a 8378000
used. The most common 3-wire voltage output range is supply voltage, which allows the use of low-voltage op amps.
0 to 10 V, but other output ranges can be implemented The op amp input common-mode range must include
such as 10 V, 0 to 5 V, and 5 V. the negative rail. To maximize the available output voltage
The two main building blocks of the analog output stage swing, the output swing should include both rails. The
are a digital-to-analog converter (DAC) and an op amp output-current requirement is low because the op amp is
circuit configured to create the desired current or voltage only required to drive the base current of the bipolar junc-
output range. Be sure to match the performance of the tion transistor (BJT). The majority of the 4- to 20-mA
analog output stage closely to that of the sensor acquisi- current flows through the BJT from the collector to the
tion circuitry; including resolution, offset, gain error, non- emitter.
linearity and noise. Select op amp performance specifications to match the
DAC and the rest of the signal chain. The op amp must
DAC considerations have low input offset voltage and drift. High CMRR and
The DAC commonly sets the performance capabilities for PSRR will improve DC performance and noise immunity of
the analog output stage, so select it carefully. Many sensor the design. eTrim, laser trim and zero-drift (chopper/
transmitters are designed with 16-bit DACs, but systems auto-zero) CMOS op amps are typically used to meet this
with lower resolution requirements can use 12-bit DACs. circuits performance requirements.
Similar to the input stage and ADC, the DAC DC offset, As shown in the transfer function in Equation 6, resis-
gain and drift errors can be removed with calibration. tors R1, R2, and R3 set the circuits gain. Select precision
Integral non-linearity (INL) errors cannot be removed resistors with low tolerance and temperature coefficients.
with a standard gain and offset calibration and set the Ratiometric tolerance and drift-matching the resistors
post-calibration accuracy. Therefore, make sure that the greatly improves performance of the circuit over
DAC INL specification is well below the desired final temperature.
system accuracy. A differential non-linearity (DNL) speci- VDAC
fication less than 1 LSB is almost always a requirement to IOUT =
R (6)
ensure a monotonic output. R1 1 + 2
R3
2-wire, 4- to 20-mA output op amp circuit The circuit must maintain a stable output response to
A standard 2-wire, 4- to 20-mA, transmitter op amp circuit load transients and changes in the output current.
is shown in Figure 7. This circuit requires an op amp with Therefore, it is important to select the proper emitter
very-low quiescent current to minimize the impact on the resistor (RE) based on the Q-point on the V-I curve load
limited 2-wire supply-current budget of 4 mA. A linear line.[5] A properly selected value for RE results in a stable
voltage regulator is typically used to lower the +24-V loop feedback network.
2-Wire Transmitter
VREG
Voltage +
Regulator
2-Wire Analog Input
Module
V+ LOOP+
/CS VREG
VDAC R1
CLK 16-Bit
+
DIN DAC
Q1 +
10 nF VLOOP
24 V
GND
4-20 mA RTN
RE
R LOAD
250
R2 R3
2-Wire Transmitter GND
VLOOP GND
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