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Department of Computer Science and Engineering

Semester Final Examination
Trimester: Fall 2012
Course Code: CSE- 307
Course Name: Computer Architecture

1. Determine True/ False. If False, give the correct answer. 0.5*10=5

a) The time between start and completion of a task referred as response
time.
b) For division algorithm we need 33 steps for 32 bit division.
c) Single point precision floating point value is represented by 32 bit words.
d) Double precision has bias value 127.
e) Three address instruction is represented by R- format.
f) For fetching instruction in datapath we need two datapath elements.
g) Three elements needed to implement R- format ALU operation.
h) Control hazard also called branch hazard.
i) MIPS instruction classically takes 7steps.
j) Multiple instructions are overlapped in execution in pipelining process.

2. Answer the following questions (any five) 5*3=15

a) Draw and describe the first version multiplication hardware.
b) Describe the flowchart of division algorithm.
c) What is floating point? Write the difference between scientific notation
and normalized number. Define fraction and exponent.
d) Draw the two datapath units needed to implement load and store
instructions.
e) Define Amdahls law with example.
f) Draw the portion of datapath used for fetching instruction by
incrementing program counter.
g) A program runs in 10 seconds on computer A, which has 4 GHz clock.
We have to design a computer B that will run this program in 6 seconds.
If the clock rate is increased, computer B will require 1.2 times as many
clock cycles as computer A for this program. Which clock rate should we
target?
3. Answer the following questions (any five) 5*4=20

a) Add the numbers: (0.5)10 and (-0.4375)10 in binary using algorithm.

b) What is data hazard? How can we solve data hazard using forwarding
technique?
c) Draw and describe the two elements needed to implement R- format
ALU operation.
d) What are the core MIPS instruction sets? Write down the major two steps
needed for every instruction.
e) Why the single cycle datapath must have separate instruction and data
memory?
f) We have to decide between two code sequences for a particular
computer. The hardware designer has supplied the following facts:
CPI for this instruction class
A B C
CPI 1 2 3

The compiler writer is considering two code sequences that require the
following instruction counts.
Code sequence Instruction count for instruction class
A B C
1 2 1 2
2 4 1 1

i. Which code sequence executes the most instructions?

ii. Which will be faster?
iii. What is the CPI for each sequence?
g)
CPI for this instruction class
A B C
CPI 1 2 3

Consider the CPI measurement of the above table. Now measuring the
code for the same program from two different compilers and obtain the
following data.
Code sequence Instruction count (in billions) for instruction class
A B C
Compiler 1 5 1 1
Compiler 2 10 1 1

Assume the compilers clock rate is 4 GHz.

i. Which code sequence will execute faster according to MIPS?
ii. Which code sequence will execute faster according to execution
time?